JP4906052B2 - Display device - Google Patents

Description

  The present invention relates to a display device and a driving method thereof, and more particularly to a display device to which a time gray scale method is applied.

  In recent years, so-called self-luminous display devices in which pixels are formed by light-emitting elements such as light-emitting diodes (LEDs) have attracted attention. As a light-emitting element used for such a self-luminous display device, it is also called a light-emitting diode (OLED (Organic Light Emitting Diode), an organic EL element, an inorganic EL element, an electroluminescence (EL) element, or the like. ) Has been attracting attention and has been used for EL displays (organic EL displays, inorganic EL displays, or displays made of elements containing organic and inorganic). Since light-emitting elements such as OLEDs are self-luminous, there are advantages such as higher pixel visibility than a liquid crystal display, no need for a backlight, and high response speed. The luminance of the light emitting element is controlled by the value of current flowing therethrough.

  There are a digital gradation method and an analog gradation method as driving methods for controlling the light emission gradation of such a display device. In the digital gradation method, gradation is expressed by turning on and off the light emitting element by digital control. On the other hand, the analog gradation method includes a method in which the light emission intensity of the light emitting element is controlled in an analog manner and a method in which the light emission time of the light emitting element is controlled in an analog manner.

  In the digital gradation method, since there are only two states of light emission and non-light emission, only two gradations can be expressed as it is. In view of this, multi-gradation is being achieved by combining different methods. In many cases, a time gray scale method is used as a technique for multi-gradation.

The time gradation method is a method of expressing gradation by controlling the length of a light emitting period and the number of times of light emission. In other words, one frame period is divided into a plurality of subframe periods, and each subframe is weighted such as the number of times of light emission and the time of light emission. The gradation is expressed by adding a difference to. When such a time gray scale method is used, it is known that a display defect called pseudo contour (or pseudo contour) or the like is caused, and countermeasures thereof are being studied (see Patent Documents 1 to 7).
Japanese Patent No. 2903984 Japanese Patent No. 3075335 Japanese Patent No. 2639311 Japanese Patent No. 3322809 JP-A-10-307561 Japanese Patent No. 3585369 Japanese Patent No. 3489984

As described above, various methods for reducing the pseudo contour have been proposed, but the effect of the pseudo contour reduction is not yet sufficient.

  For example, it is assumed that a certain pixel A expresses the gradation number 127 and the adjacent pixel B expresses the gradation number 128. FIG. 21 shows a lighting state and a non-lighting state in each subframe in that case. If the line of sight 2101 does not move and only the pixel A or the pixel B is viewed all the time, no pseudo contour is generated (see Patent Document 2). This is because the eyes feel the brightness due to the sum of the brightness of the places where the line of sight 2101 passes. Therefore, the pixel A feels that the number of gradations is 127 (= 1 + 2 + 4 + 8 + 16 + 32 + 32 + 32), and the pixel B feels that the number of gradations is 128 (= 32 + 32 + 32 + 32). That is, the eyes feel the correct gradation.

  On the other hand, it is assumed that the line of sight moves from the pixel A to the pixel B or from the pixel B to the pixel A. Such a case is shown in FIG. In this case, depending on how the line of sight 2201 moves, in some cases, the number of gradations is felt as 96 (= 32 + 32 + 32), and in other cases, the number of gradations is felt as 159 (= 1 + 2 + 4 + 8 + 16 + 32 + 32 + 32 + 32). Originally, the number of gradations should be 127 and 128, but the number of gradations looks like 96 and 159, and a pseudo contour is generated.

  Further, it is assumed that a certain pixel A expresses the gradation number 31 and the adjacent pixel B expresses the gradation number 32. FIG. 23 shows a lighting state and a non-lighting state in each subframe in that case. If the line of sight 2301 does not move and only the pixel A or the pixel B is viewed all the time, the pseudo contour does not occur. This is because the eyes feel the brightness by the sum of the brightness of the places where the line of sight 2301 passes (see Patent Document 3). Therefore, the pixel A feels that the number of gradations is 31 (= 16 + 4 + 4 + 4 + 1 + 1 + 1), and the pixel B feels that the number of gradations is 32 (= 16 + 16). That is, the eyes feel the correct gradation.

  On the other hand, it is assumed that the line of sight moves from the pixel A to the pixel B or from the pixel B to the pixel A. This case is shown in FIG. In this case, depending on how the line of sight 2401 moves, in some cases, the number of gradations is felt as 16 (= 16), and in other cases, the number of gradations is felt as 47 (= 16 + 16 + 4 + 4 + 4 + 1 + 1 + 1). Originally, the number of gradations should be 31 and 32, but the number of gradations looks like 16 or 47, and a pseudo contour is generated.

  In view of such problems, it is an object of the present invention to provide a display device configured with a small number of subframes and capable of reducing pseudo contours, and a driving method using the display device.

  In the present invention, gradation is expressed by sequentially adding weights (lighting period, number of times of lighting, etc.) in each subframe in halftones displayed in binary. Thereby, generation | occurrence | production of a pseudo contour is suppressed.

  In order to further increase the number of gradations, other methods (area gradation method, dither diffusion method, error diffusion method) are combined.

  In addition, as a pixel configuration, a diode is used to erase a signal stored in the pixel. By simply turning on the diode, the light emitting element is in a non-light emitting state, so that power consumption can be reduced.

  The above object is achieved by expressing gradation using such a method.

  The present invention has a plurality of pixels each including a selection transistor, a driving transistor, and an erasing diode, and expresses gradation by dividing one frame into a plurality of subframes having substantially equal weights for lighting. Is. Here, weighting (with respect to lighting) refers to the length of lighting time for gradation display. Further, the “substantially equal weighting” discussed above indicates that the number of times of light emission and the light emission period weighted in each subframe may have a difference that cannot be recognized by human eyes. For example, when displaying with 64 gradations, even if there are 3 gradations in each subframe, it is considered that the weights are approximately equal.

  The present invention provides a display device that includes a plurality of pixels each including a selection transistor, a drive transistor, and an erasing diode, and divides one frame into a plurality of weighted subframes that gradually increase with respect to lighting to express gradation. The driving method is characterized in that the subframes to be lit are stacked as the number of gradations increases.

  In the above configuration, the present invention is characterized in that the weight of the subframe is controlled by the erasing diode.

  The present invention is characterized in that, in the above configuration, the display device is an EL display.

  In the present invention, there are no limitations on the types of transistors that can be used, and the transistor is formed using a thin film transistor (TFT) using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a semiconductor substrate, or an SOI substrate. A MOS transistor, a junction transistor, a bipolar transistor, a transistor using an organic semiconductor or a carbon nanotube, and other transistors can be used. There is no limitation on the kind of the substrate over which the transistor is provided, and the transistor can be provided on a single crystal substrate, an SOI substrate, a glass substrate, a plastic substrate, or the like.

  In the present invention, being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, another element (for example, another element or a switch) that enables electrical connection may be disposed therebetween.

  In the present invention, the pseudo contour can be reduced. Accordingly, the display quality is improved and a beautiful image can be seen. In addition, power consumption can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
First, here, as an example, consider the case of expressing gradation with 5 bits. That is, the case of 32 gradations will be described.

  In the present invention, gradation is expressed by sequentially adding the lighting periods (or the number of times of lighting in a certain time) in each subframe. That is, the number of subframes to be lit increases as the gray level increases. Therefore, a subframe that is lit at a small gradation is also lit at a large gradation. Such a gradation method is called an overlapping time gradation method. By using this superposition time gradation method, the entire gradation is expressed.

  Next, as a specific example, a method for selecting a subframe in each gradation, that is, whether or not each subframe is lit in each gradation will be described. FIG. 1 shows a subframe selection method in the case of 7 subframes. Thereby, 3 bits, that is, 8 gradations can be expressed. It is assumed that the lengths of the lighting periods are all 4. Here, it is assumed that the number of gradations 1 corresponds to the length of the lighting period 1.

  Note that the length of the lighting period (or the number of times of lighting in a certain time, that is, the weighting amount) in the subframe is all four, but the present invention is not limited to this. The length of the lighting period (or the number of times of lighting in a certain time, that is, the weighting amount) may be different depending on the subframe.

  Here, how to view FIG. 1 will be described. Lights up in subframes marked with ○ and turns off in subframes marked with x. Then, in each gradation number, gradation is expressed by selecting which subframe to light. For example, when the number of gradations is 0, SF1 to SF7 are not lit. At the gradation number 1, SF1 to SF7 are not lit. In the number of gradations 4, SF2 to SF7 are not lit and SF1 is lit. At the number of gradations 5, SF2 to SF7 are not lit, and SF1 is lit. At the gradation number 8, SF3 to SF7 are not lit, and SF1 and SF2 are lit.

  In this way, gradation is expressed by sequentially adding the lighting periods in each subframe. That is, the number of subframes to be lit increases as the gray level increases. Therefore, SF1 is all lit when the number of gradations is 4 or more, SF2 is all lit when the number of gradations is 8 or more, and SF3 is all lit when the number of gradations is 12 or more. The same applies to SF4 to SF7. That is, a subframe that is lit at a small gradation is also lit at a large gradation.

  By adopting such a driving method, the pseudo contour can be reduced. This is because, in a certain gradation, all subframes that are lit in a gradation lower than that are lit. Therefore, even when the line of sight moves, it can be prevented that the image is viewed with inaccurate brightness at the change of gradation.

  However, in the case of FIG. 1, since the number of subframes is 7, the number of gradations can be expressed only up to 8. Therefore, in order to increase the number of gradations, another method is combined. The main three methods are as follows.

  As a first example, an area gradation method is used. In this method, a pixel is divided into a plurality of subpixels. Then, the light emission area in the sub-pixel is changed. For example, the power of 2 is 1: 2: 4: 8:. The gradation is expressed by which of the sub-pixels emits light.

  A second example is a method using an image processing technique. For example, a dither diffusion method or an error diffusion method is used. As a result, multi-gradation can be achieved.

  As a third example, there is a method of expressing one gradation using a plurality of frames. For example, the even number frame represents the number of gradations 8, and the odd number frame represents the number of gradations 10. Then, since it is averaged and the luminance is perceived by human eyes, it can be expressed as having 9 gradations.

  Each of the first to third examples may be combined.

  Next, FIG. 2 shows a case where gradation is expressed using 10 subframes. Here, since 10 subframes are used, 11 gradations can be expressed. For multi-gradation, the methods shown as the first to third examples may be used.

  Compared with FIG. 1, in FIG. 2, since many gradations can be expressed by time gradations, gradations can be expressed more smoothly.

  Next, consider the case of expressing gradation with 6 bits. FIG. 3 shows a subframe selection method when the number of subframes is seven.

  Here, since seven subframes are used, eight gradations can be expressed. The length of the lighting period in the subframe is 8. For multi-gradation, the methods shown as the first to third examples may be used.

  Thus, when the number of subframes is N, N + 1 gradations can be expressed in the time gradation part.

  Note that when one gradation is expressed, there may be a plurality of methods for selecting a subframe. Therefore, in a certain gradation, the selection method of subframes may be changed in time or place. That is, the selection method of the subframe may be changed depending on the time, and the selection method of the subframe may be changed depending on the pixel. Further, it may be changed depending on the time and also depending on the pixel.

  For example, when a certain gradation is expressed, the selection method of subframes may be changed depending on whether the number of frames is an odd number or an even number. In addition, when expressing a certain gradation, the method of selecting a subframe may be changed depending on whether an odd-numbered row pixel is displayed or an even-numbered row pixel is displayed. In addition, when expressing a certain gradation, the method of selecting a subframe may be changed depending on whether an odd-numbered column pixel is displayed or an even-numbered column pixel is displayed.

  So far, the case where the lighting period increases linearly in proportion to the number of gradations has been described. Next, a case where gamma correction is performed will be described. The gamma correction refers to a non-linear lighting period that increases as the number of gradations increases. Even if the luminance increases linearly in proportion, the human eye does not feel that it is brighter in proportion. The higher the brightness, the less the difference in brightness is felt. Therefore, in order for the human eye to feel a difference in brightness, it is necessary to increase the lighting period as the number of gradations increases, that is, to perform gamma correction.

  The simplest method is to enable display with a larger number of bits (number of gradations) than the actual number of bits (number of gradations) to be displayed. For example, when displaying with 6 bits (64 gradations), in reality, 8 bits (256 gradations) can be displayed. And when actually displaying, it displays by 6 bits (64 gradations) so that the brightness | luminance of the number of gradations becomes nonlinear. Thereby, gamma correction can be realized.

Usually, Y = AX ^γ , where Y is the luminance, X is the number of gradations, γ is the gamma number, and A is the proportionality constant. In general, when γ = 2.2, it is considered best for the human eye. Therefore, Y = AX ^2.2 may be satisfied.

  The gamma number is not limited to 2.2. Any size that is optimal for the human eye is acceptable. Therefore, it may be 1.7 or more and 2.7 or less, but 2.2 is generally preferable.

As an example, FIG. 4 shows a correspondence table of 32 gradations after gamma correction, 64 gradations before gamma correction, and 256 gradations before gamma correction. If it is possible to display 64 gradations or 256 gradations before gamma correction, and actually 32 gradations are desired after gamma correction, they may be displayed according to the correspondence table of FIG. Let X be the number of gradations of 32 gradations after gamma correction. If γ = 2.2, X ^2.2 can be calculated. Here, X ^2.2 when the number of gradations is 31 is 1910. Therefore, by multiplying the value of each X ^2.2 by 64 and dividing 1910 which is X ^2.2 when the number of gradations is 31, the number of gradations at 64 gradations before gamma correction is obtained. It is done. Similarly, by multiplying each X ^2.2 value by 256 and dividing 1910 which is X ^2.2 when the number of gradations is 31, the number of gradations at 256 gradations before the gamma correction is obtained. Desired. Similarly, the present invention can be applied to various gradations.

  FIG. 5 shows a graph of 32 gradations after gamma correction and 64 gradations before gamma correction. As can be seen from FIG. 5, as the number of gradations at 32 gradations after gamma correction increases, the 64 gradations before gamma correction, that is, the luminance increases nonlinearly. As a result, a smooth display can be performed for human eyes.

Note that when gamma correction is performed, the length of the lighting period in each subframe is not necessarily the same. This is because the number of gradations and luminance are nonlinear. Therefore, it is desirable to select the length of the lighting period in each subframe, as shown on the equation Y = AX ^γ .

  As an example, FIG. 6 shows the length of each subframe period and the subframe selection method for 32 gradations after gamma correction and corresponding 64 gradations before gamma correction. Subframe SF1 is lighting period 1, subframe SF2 is lighting period 2, subframe SF3 is lighting period 4, subframe SF4 is lighting period 7, and subframe SF5 is lighting. It is assumed that the period is 10, the subframe SF6 is the lighting period 11, and the subframe SF7 is the lighting period 27. As described above, the length of the selected subframe increases as the number of gradations increases. Thereby, gamma correction can be performed more appropriately. Note that the length of the lighting period in each subframe is not limited to this. What is necessary is just to adjust suitably with the number of sub-frames.

  Here, the case of 32 gradations after gamma correction is shown, but the present invention is not limited to this. For other numbers of gradations, a correspondence table can be created as appropriate for cases after gamma correction and before gamma correction.

  Also, how many bits (for example, p bits, where p is an integer) can be displayed, and how many bits (for example, q bits, where q is an integer) after gamma correction is displayed. It is not limited. When displaying after gamma correction, it is desirable to increase the number of bits p as much as possible in order to express gradation smoothly. However, if it is made too large, there will be adverse effects such as an increase in the number of subframes. Therefore, it is desirable that the relationship between the number of bits q and the number of bits p is q + 2 ≦ p ≦ q + 5. As a result, it is possible to realize that the number of subframes does not increase too much while the gradation is expressed smoothly.

  The normal frame frequency is 60 Hz, but is not limited to this. The pseudo contour may be reduced by further increasing the frame frequency. For example, the operation may be performed at a frequency that is about twice that of a normal frequency of 120 Hz.

  Next, an example of a timing chart will be described. As an example, the subframe selection method shown in FIG. 1 is used. However, the subframe selection method is not limited to this, and the method can be easily applied to other subframe selection methods and other gradation numbers.

  First, a timing chart is shown in FIG. When a signal writing operation is performed in each row, the lighting period 701 starts immediately.

  In a certain row, a signal is written, and after a predetermined lighting period 701 ends, a signal writing operation in the next subframe is started. By repeating this, the length of the lighting period 701 is arranged as 4, 4, 4, 4, 4, 4, 4.

  This makes it possible to arrange many subframes in one frame even if the signal writing operation is slow.

  In addition, when adjusting the brightness | luminance of the whole screen, it may implement | achieve by adjusting duty ratio (ratio of the lighting period in 1 frame period). In such a case, it is necessary not to forcibly turn on the light. One way to do this is to erase the signal stored in the pixel.

  Accordingly, FIG. 7 shows a timing chart in the case of performing an operation for erasing the pixel signal. In each row, a signal writing operation is performed, and the pixel signal is erased before the next signal writing operation is performed. In this way, the length of the lighting period can be easily controlled. Therefore, the duty ratio can be changed freely.

  In addition, when performing the gamma correction and the length of the lighting period in each subframe is different, it is possible to control the length of the lighting period by changing the signal erasing timing for each subframe. It becomes possible.

  As an example, FIG. 8 shows a timing chart in the case of selecting the lighting period in FIG. In this manner, by changing the timing of the signal erasing operation 801 for each subframe, it is possible to appropriately control the length of the lighting period.

  FIG. 9 shows an example of a pixel configuration when the driving transistor is forcibly turned off. A selection transistor 901, a driving transistor 903, an erasing diode 911, and a display element 904 are provided. The source and drain of the selection transistor 901 are connected to the signal line 905 and the gate of the driving transistor 903, respectively. The gate of the selection transistor 901 is connected to the first gate line 907. The source and drain of the driving transistor 903 are connected to the power supply line 906 and the display element 904, respectively. The erase diode 911 is connected to the gate of the drive transistor 903 and the second gate line 917.

  The storage capacitor 902 serves to hold the gate potential of the driving transistor 903. Therefore, although it is connected between the gate of the driving transistor 903 and the power supply line 906, it is not limited to this. It is only necessary that the gate potential of the driving transistor 903 be held. In the case where the gate potential of the driving transistor 903 can be held using the gate capacitance of the driving transistor 903 or the like, the holding capacitor 902 may be omitted.

  As an operation method, the first gate line 907 is selected, the selection transistor 901 is turned on, and a signal is input from the signal line 905 to the storage capacitor 902. Then, the current of the driving transistor 903 is controlled according to the signal, and current flows from the first power supply line 906 through the display element 904 to the second power supply line 908.

  When the signal is to be erased, the second gate line 917 is selected (here, set to a high potential), the erasing diode 911 is turned on, and a current flows from the second gate line 917 to the gate of the driving transistor 903. To. As a result, the driving transistor 903 is turned off. Then, no current flows from the first power supply line 906 to the second power supply line 908 through the display element 904. As a result, a non-lighting period can be created and the length of the lighting period can be freely controlled.

  At this time, if the potential of the second gate line 917 is sufficiently high, even if the threshold voltage of the driving transistor 903 is an abnormal value (eg, the threshold voltage is a positive value in a P-channel transistor). The drive transistor 903 can be normally turned off. Further, since the non-lighting period can be created by controlling only the second gate line 917, power consumption can be reduced.

  When it is desired to hold the signal, the second gate line 917 is not selected (here, set to a low potential). Then, since the erasing diode 911 is turned off, the gate potential of the driving transistor 903 is held.

  The erasing diode 911 may be anything as long as it is a rectifying element. A PN-type diode, a PIN-type diode, a Schottky diode, or a Zener-type diode may be used.

  Further, as a diode, a transistor may be used in a diode connection (a gate and a drain are connected). A circuit diagram in that case is shown in FIG. As the erasing diode 911, a diode-connected transistor 1011 is used. Here, an N-channel type is used, but the present invention is not limited to this. A P-channel type may be used.

  In this way, when the non-lighting period is created, it is only necessary to forcibly create a non-light-emitting state, so that no current is supplied to the display element. Therefore, a switch is arranged somewhere along the path of current flowing from the first power supply line 906 to the second power supply line 908 through the display element 904, and the on / off state of the switch is controlled to set the non-lighting period. Just make it. Alternatively, the gate-source voltage of the driving transistor 903 may be controlled so that the driving transistor is forcibly turned off.

  Note that the appearance order of the subframes may change depending on the time. For example, the appearance order of subframes may change between the first frame and the second frame. Further, the appearance order of subframes may vary depending on the location. For example, the appearance order of the subframes may be changed between the pixel A and the pixel B. In addition, by combining them, the appearance order of the subframes may change with time and change with place.

  Further, the appearance order of the subframes may be arranged in order from SF1 to SF7 in FIG. 1, for example, or may be arranged in a random order.

  Note that although a lighting period, a signal writing period, and a non-lighting period are arranged in one frame period in this embodiment mode, the present invention is not limited to this. Other operation periods may be arranged. For example, a period in which the voltage applied to the display element has a polarity opposite to that of the normal voltage, that is, a so-called reverse bias period may be provided. By providing the reverse bias period, the reliability of the display element may be improved.

(Embodiment 2)
Hereinafter, in this embodiment, structures and operations of a display device, a signal line driver circuit, a gate line driver circuit, and the like will be described.

  As shown in FIG. 11, the display device includes a pixel portion 1101, a gate line driver circuit 1102, and a signal line driver circuit 1110. The gate line driver circuit 1102 sequentially outputs selection signals to the pixel portion 1101. The gate line driver circuit 1102 includes a shift register, a buffer circuit, and the like.

  In addition, the gate line driver circuit 1102 often includes a level shifter circuit, a pulse width control circuit, and the like. The shift register outputs pulses that are sequentially selected. The signal line driver circuit 1110 sequentially outputs video signals to the pixel portion 1101. The shift register 1103 outputs pulses that are sequentially selected. The pixel portion 1101 displays an image by controlling the state of light according to the video signal. A video signal input from the signal line driver circuit 1110 to the pixel portion 1101 is often a voltage. That is, the state of the display element arranged in each pixel and the element that controls the display element is changed by the video signal (voltage) input from the signal line driver circuit 1110. Examples of the display element arranged in the pixel include an EL element, an element used in an FED (field emission display), a liquid crystal, a DMD (digital micromirror device), and the like.

  Note that a plurality of gate line driver circuits 1102 and signal line driver circuits 1110 may be provided.

  The signal line driver circuit 1110 is divided into a plurality of parts. Roughly, as an example, it is divided into a shift register 1103, a first latch circuit (LAT1) 1104, a second latch circuit (LAT2) 1105, and an amplifier circuit 1106. The amplifier circuit 1106 may have a function of converting a digital signal into analog or a function of performing gamma correction.

  Further, the pixel has a display element such as an EL element. A circuit that outputs a current (video signal) to the display element, that is, a current source circuit may be provided.

  Therefore, the operation of the signal line driver circuit 1110 will be briefly described. The shift register 1103 receives a clock signal (S-CLK), a start pulse (SP), and a clock inversion signal (S-CLKb), and sequentially outputs sampling pulses according to the timing of these signals.

  The sampling pulse output from the shift register 1103 is input to the first latch circuit (LAT1) 1104. The first latch circuit (LAT1) 1104 receives a video signal from the video signal line 1108, and holds the video signal in each column in accordance with the timing at which the sampling pulse is input.

  When the first latch circuit (LAT1) 1104 completes holding the video signal up to the last column, a latch pulse (Latch Pulse) is input from the latch control line 1109 during the horizontal blanking period, and the first latch circuit (LAT1) The video signals held in 1104 are transferred to the second latch circuit (LAT2) 1105 all at once. After that, the video signal held in the second latch circuit (LAT2) 1105 is input to the amplifier circuit 1106 for one row at the same time. A signal output from the amplifier circuit 1106 is input to the pixel portion 1101.

  While the video signal held in the second latch circuit (LAT2) 1105 is input to the amplifier circuit 1106 and is input to the pixel portion 1101, the shift register 1103 outputs a sampling pulse again. That is, two operations are performed simultaneously. Thereby, line-sequential driving becomes possible. Thereafter, this operation is repeated.

  Note that the signal line driver circuit and a part thereof (such as a current source circuit and an amplifier circuit) do not exist on the same substrate as the pixel portion 1101, and may be configured using, for example, an external IC chip.

  Note that the structures of the signal line driver circuit, the gate line driver circuit, and the like are not limited to those in FIGS. For example, a signal may be supplied to the pixel by dot sequential driving. An example of the signal line driver circuit 1210 in that case is shown in FIG. A sampling pulse is output from the shift register 1203 to the sampling circuit 1204. A video signal is input from the video signal line 1208, and the video signal is output to the pixel portion 1201 in accordance with the sampling pulse. Then, signals are sequentially input to the pixels in the row selected by the gate line driver circuit 1202.

  Note that as described above, the transistor in the present invention may be any type of transistor, and may be formed on any substrate. Therefore, the circuits as shown in FIGS. 11 and 12 may all be formed on a glass substrate, may be formed on a plastic substrate, or may be formed on a single crystal substrate. It may be formed on an SOI substrate, or may be formed on any other substrate. Alternatively, a part of the circuit in FIGS. 11 and 12 may be formed on a certain substrate, and another part of the circuit in FIGS. 11 and 12 may be formed on another substrate. That is, all the circuits in FIGS. 11 and 12 may not be formed on the same substrate. For example, in FIG. 11, the pixel portion 1101 and the gate line driver circuit 1102 are formed using a TFT over a glass substrate, and the signal line driver circuit 1110 (or part thereof) is formed over a single crystal substrate. The IC chip may be connected to the glass substrate by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Auto Bonding) or a printed board.

  Note that the contents described in the present embodiment correspond to those using the contents described in the first embodiment. Therefore, the content described in Embodiment Mode 1 can be applied to this embodiment mode.

(Embodiment 3)
Next, a pixel layout in the display device of the present invention will be described. As an example, FIG. 13 shows a layout diagram of the circuit diagram shown in FIG. Similarly, a layout diagram of the circuit diagram shown in FIG. 9 is shown in FIG. Note that the circuit diagrams and layout diagrams are not limited to FIGS. 10, 9, 13, and 14.

  First, referring to FIG. A selection transistor 1301, a driving transistor 1303, a diode-connected erasing transistor 1311, and a display element electrode 1304 are provided. The source and drain of the selection transistor 1301 are connected to the signal line 1305 and the gate of the driving transistor 1303, respectively. The gate of the selection transistor 1301 is connected to the first gate line 1307. The source and drain of the driving transistor 1303 are connected to the power supply line 1306 and the electrode 1304, respectively. The diode-connected erase transistor 1311 is connected to the gate of the driving transistor 1303 and the second gate line 1317. The storage capacitor 1302 is connected between the gate of the driving transistor 1303 and the power supply line 1306.

  The signal line 1305 and the power supply line 1306 are formed by the second wiring, and the first gate line 1307 and the second gate line 1317 are formed by the first wiring.

  Reference is now made to FIG. A selection transistor 1401, a driving transistor 1403, a diode 1411, and an electrode 1404 of a display element are arranged. Here, it is assumed that the diode 1411 is a PIN diode. The source and drain of the selection transistor 1401 are connected to the signal line 1405 and the gate of the driving transistor 1403, respectively. The gate of the selection transistor 1401 is connected to the first gate line 1407. The source and drain of the driving transistor 1403 are connected to the power supply line 1406 and the electrode 1404, respectively. The diode 1411 is connected to the gate of the driving transistor 1403 and the second gate line 1417. The storage capacitor 1402 is connected between the gate of the driving transistor 1403 and the power supply line 1406.

  Note that the length of the i region in the diode 1411 may be determined in consideration of a breakdown voltage, an off-current, or the like of the diode 1411. In addition, a wiring may be arranged on the upper side or the lower side of the i region in the diode 1411. This wiring can prevent the diode from reacting to light.

  The signal line 1405 and the power supply line 1406 are formed by the second wiring, and the first gate line 1407 and the second gate line 1417 are formed by the first wiring.

  In the case of the top gate structure, the film is formed in the order of the substrate, the semiconductor layer, the gate insulating film, the first wiring, the interlayer insulating film, and the second wiring. In the case of the bottom gate structure, the film is formed in the order of the substrate, the first wiring, the gate insulating film, the semiconductor layer, the interlayer insulating film, and the second wiring.

  Note that the description in this embodiment can be implemented in free combination with the contents described in Embodiments 1 and 2.

(Embodiment 4)
In the present embodiment, hardware for controlling the driving method described in the first to sixth embodiments will be described.

  A rough block diagram is shown in FIG. A pixel portion 1504 is provided over the substrate 1501. In many cases, a signal line driver circuit 1506 and a gate line driver circuit 1505 are provided. In addition, a power supply circuit, a precharge circuit, a timing generation circuit, and the like may be arranged. In some cases, the signal line driver circuit 1506 and the gate line driver circuit 1505 are not provided. In that case, what is not arranged on the substrate 1501 is often formed in an IC. In many cases, the IC is arranged on the substrate 1501 by COG (Chip On Glass). Alternatively, an IC may be disposed on a connection board 1507 that connects the peripheral circuit board 1502 and the board 1501.

  A signal 1503 is input to the peripheral circuit board 1502. Then, the controller 1508 controls the signal to be stored in the memory 1509, the memory 1510, or the like. When the signal 1503 is an analog signal, it is often stored in the memory 1509 or the memory 1510 after analog-digital conversion. Then, the controller 1508 outputs a signal to the substrate 1501 using a signal stored in the memory 1509, the memory 1510, or the like.

  In order to realize the driving method described in Embodiment Modes 1 to 3, the controller 1508 controls the appearance order of subframes and outputs a signal to the substrate 1501.

  Note that the contents described in this embodiment mode can be freely combined with the contents described in Embodiment Modes 1 to 3.

(Embodiment 5)
An example of a structure of a mobile phone having a display device and a display device using the display method of the present invention in a display portion will be described with reference to FIGS.

  The display panel 5410 is incorporated in a housing 5400 so as to be detachable. The shape and dimensions of the housing 5400 can be changed as appropriate in accordance with the size of the display panel 5410. A housing 5400 to which the display panel 5410 is fixed is fitted into a printed board 5401 and assembled as a module.

  The display panel 5410 is connected to the printed board 5401 through the FPC 5411. A signal processing circuit 5405 including a speaker 5402, a microphone 5403, a transmission / reception circuit 5404, a CPU, a controller, and the like is formed over the printed board 5401. Such a module, the input means 5406, and the battery 5407 are combined and housed in the housings 5409 and 5412. The pixel portion of the display panel 5410 is arranged so as to be visible from an opening window formed in the housing 5412.

  In the display panel 5410, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are formed over a substrate using TFTs, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driving circuit having a high operating frequency among the circuits) may be formed over the IC chip, and the IC chip may be mounted on the display panel 5410 by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Auto Bonding) or a printed board. Note that FIG. 17A shows an example of the structure of a display panel in which some peripheral driving circuits are formed integrally with a pixel portion on a substrate and an IC chip on which other peripheral driving circuits are formed is mounted by COG or the like. is there.

  17A includes a substrate 5300, a signal line driver circuit 5301, a pixel portion 5302, scanning line driver circuits 5303 and 5304, an FPC 5305, IC chips 5306 and 5307, a sealing substrate 5308, and a sealing material. 5309.

  With such a structure, low power consumption of the display device can be achieved, and the use time by one charge of the mobile phone can be extended. In addition, the cost of the mobile phone can be reduced.

  In addition, by performing impedance conversion of a signal set to the scanning line or the signal line using a buffer, the pixel writing time for each row can be shortened. Therefore, a high-definition display device can be provided.

  In order to further reduce power consumption, as shown in FIG. 17B, a pixel portion is formed on the substrate using TFTs, and all peripheral drive circuits are formed on the IC chip. May be mounted on the display panel by COG (Chip On Glass) or the like.

  17B includes a substrate 5310, a signal line driver circuit 5311, a pixel portion 5312, scan line driver circuits 5313 and 5314, an FPC 5315, IC chips 5316 and 5317, a sealing substrate 5318, and a sealing material. 5319.

  Then, by using the display device of the present invention and its driving method, a beautiful image with reduced pseudo contour can be seen. Therefore, even an image whose gradation changes slightly like human skin can be displayed neatly.

  The structure described in this embodiment is an example of a mobile phone, and the display device of the present invention can be applied not only to the mobile phone having such a structure but also to mobile phones having various structures.

(Embodiment 6)
FIG. 18 shows an EL module in which a display panel 5701 and a circuit board 5702 are combined. A display panel 5701 includes a pixel portion 5703, a scan line driver circuit 5704, and a signal line driver circuit 5705. On the circuit board 5702, for example, a control circuit 5706, a signal dividing circuit 5707, and the like are formed. The display panel 5701 and the circuit board 5702 are connected to each other through a connection wiring 5708. An FPC or the like can be used for the connection wiring.

  The control circuit 5706 corresponds to the controller 1508, the memory 1509, the memory 1510, or the like in the fourth embodiment. The control circuit 5706 mainly controls the appearance order of subframes.

  In the display panel 5701, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among the plurality of driver circuits) are formed over the substrate using TFTs, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driver circuit having a high operating frequency among the circuits) is formed over the IC chip, and the IC chip is preferably mounted on the display panel 5701 by COG (Chip On Glass) or the like. Alternatively, the IC chip may be mounted on the display panel 5701 using TAB (Tape Auto Bonding) or a printed board. Note that FIG. 17A shows an example of a configuration in which some peripheral drive circuits are formed integrally with a pixel portion on a substrate and an IC chip on which other peripheral drive circuits are formed is mounted by COG or the like.

  In addition, by performing impedance conversion of a signal set to the scanning line or the signal line using a buffer, the pixel writing time for each row can be shortened. Therefore, a high-definition display device can be provided.

  In order to further reduce power consumption, a pixel portion is formed using a TFT on a glass substrate, all signal line driving circuits are formed on an IC chip, and the IC chip is formed by COG (Chip On Glass). It may be mounted on a display panel.

  FIG. 17B shows an example of a structure in which an IC chip in which a pixel portion is formed over a substrate and a signal line driver circuit is formed over the substrate is mounted by COG or the like.

  With this EL module, an EL television receiver can be completed. FIG. 19 is a block diagram illustrating a main configuration of an EL television receiver. A tuner 5801 receives video signals and audio signals. The video signal includes a video signal amplifying circuit 5802, a video signal processing circuit 5803 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and uses the video signal as input specifications of the drive circuit. Processing is performed by a control circuit 5706 for conversion. The control circuit 5706 outputs a signal to each of the scan line side and the signal line side. In the case of digital driving, a signal dividing circuit 5707 may be provided on the signal line side, and an input digital signal may be divided into m pieces and supplied.

  Of the signals received by the tuner 5801, the audio signal is sent to the audio signal amplifier circuit 5804, and the output is supplied to the speaker 5806 via the audio signal processing circuit 5805. The control circuit 5807 receives control information on the receiving station (reception frequency) and volume from the input unit 5808 and sends a signal to the tuner 5801 and the audio signal processing circuit 5805.

  A television receiver can be completed by incorporating an EL module into a housing. A display portion is formed by the EL module. In addition, speakers, video input terminals, and the like are provided as appropriate.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

  As described above, by using the display device of the present invention and its driving method, a beautiful image with reduced pseudo contour can be seen. Therefore, even an image whose gradation changes slightly like human skin can be displayed neatly.

(Embodiment 7)
As electronic devices using the present invention, cameras such as video cameras and digital cameras, goggle-type displays, navigation systems, sound reproduction devices (car audio, audio components, etc.), computers, game devices, portable information terminals (mobile computers, mobile phones) An image playback apparatus (specifically, a digital versatile disc (DVD)) such as a telephone, a portable game machine, or an electronic book), and an apparatus provided with a display that can display the image. ) And the like. Specific examples of these electronic devices are shown in FIGS.

  FIG. 20A illustrates a self-luminous display device which includes a housing 13001, a support base 13002, a display portion 13003, a speaker portion 13004, a video input terminal 13005, and the like. The present invention can be used for a display device included in the display portion 13003. In addition, according to the present invention, a clear image with reduced pseudo contour can be seen, and the self-luminous display device shown in FIG. 20A is completed. Since the self-luminous display device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The self-luminous display device can be used for all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

  FIG. 20B illustrates a digital camera, which includes a main body 13101, a display portion 13102, an image receiving portion 13103, operation keys 13104, an external connection port 13105, a shutter 13106, and the like. The present invention can be used for a display device included in the display portion 13102. Further, according to the present invention, a clear image with reduced pseudo contour can be seen, and the digital camera shown in FIG. 20B is completed.

  FIG. 20C illustrates a computer, which includes a main body 13201, a housing 13202, a display portion 13203, a keyboard 13204, an external connection port 13205, a pointing mouse 13206, and the like. The present invention can be used for a display device included in the display portion 13203. Further, according to the present invention, it is possible to view a beautiful image with reduced pseudo contour, and the computer shown in FIG. 20C is completed.

  FIG. 20D illustrates a mobile computer, which includes a main body 13301, a display portion 13302, a switch 13303, operation keys 13304, an infrared port 13305, and the like. The present invention can be used for a display device included in the display portion 13302. In addition, according to the present invention, it is possible to view a beautiful image with reduced pseudo contour, and the mobile computer shown in FIG. 20D is completed.

  FIG. 20E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium reading unit, which includes a main body 13401, a housing 13402, a display portion A13403, a display portion B13404, and a recording medium (DVD). Etc.) A reading unit 13405, an operation key 13406, a speaker unit 13407, and the like are included. Although the display portion A 13403 mainly displays image information and the display portion B 13404 mainly displays character information, the present invention can be used for a display device that forms the display portion A 13403 and the display portion B 13404. Note that the image reproducing device provided with the recording medium reading unit includes a home game machine and the like. Further, according to the present invention, it becomes possible to view a beautiful image with reduced pseudo contour, and the image reproducing apparatus shown in FIG. 20E is completed.

  FIG. 20F illustrates a goggle type display which includes a main body 13501, a display portion 13502, and an arm portion 13503. The present invention can be used for a display device included in the display portion 13502. Further, according to the present invention, it becomes possible to see a beautiful image with reduced pseudo contour, and the goggle type display shown in FIG. 20F is completed.

  FIG. 20G illustrates a video camera, which includes a main body 13601, a display portion 13602, a housing 13603, an external connection port 13604, a remote control reception portion 13605, an image receiving portion 13606, a battery 13607, an audio input portion 13608, operation keys 13609, an eyepiece Part 13610 and the like. The present invention can be used for a display device included in the display portion 13602. In addition, according to the present invention, it becomes possible to view a beautiful image with reduced pseudo contour, and the video camera shown in FIG. 20G is completed.

  FIG. 20H illustrates a mobile phone, which includes a main body 13701, a housing 13702, a display portion 13703, an audio input portion 13704, an audio output portion 13705, operation keys 13706, an external connection port 13707, an antenna 13708, and the like. The present invention can be used for a display device included in the display portion 13703. Note that the display portion 13703 can suppress current consumption of the mobile phone by displaying white characters on a black background. In addition, according to the present invention, it becomes possible to view a beautiful image with reduced pseudo contour, and the mobile phone shown in FIG. 20H is completed.

  Note that when a light emitting material having high light emission luminance is used, it is possible to enlarge and project the light including the output image information with a lens or the like and use it in a front type or rear type projector.

  In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the light emitting material is very high, the light emitting device is preferable for displaying moving images.

  In addition, since the light emitting device consumes electric power in the light emitting device, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light-emitting device is used for a display unit mainly including character information such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light-emitting part with a non-light-emitting part as a background. It is desirable to do.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use the display device having any structure described in Embodiments 1 to 6.

4A and 4B illustrate a structure of a driving method of a display device of the present invention. 4A and 4B illustrate a structure of a driving method of a display device of the present invention. 4A and 4B illustrate a structure of a driving method of a display device of the present invention. 4A and 4B illustrate a structure of a driving method of a display device of the present invention. 4A and 4B illustrate a structure of a driving method of a display device of the present invention. 4A and 4B illustrate a structure of a driving method of a display device of the present invention. 4A and 4B illustrate a structure of a driving method of a display device of the present invention. 4A and 4B illustrate a structure of a driving method of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 14 illustrates an electronic device to which the present invention is applied. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 14 illustrates an electronic device to which the present invention is applied. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 14 illustrates an electronic device to which the present invention is applied. 8A and 8B illustrate a structure of a conventional display device driving method. 8A and 8B illustrate a structure of a conventional display device driving method. 8A and 8B illustrate a structure of a conventional display device driving method. 8A and 8B illustrate a structure of a conventional display device driving method.

Claims (5)

The first transistor, the second transistor, the third transistor, the storage capacitor, the first wiring, the second wiring, the third wiring, the fourth wiring, and the fifth wiring And a sixth wiring and a display element,
One of a source and a drain of the first transistor is electrically connected to the first wiring;
The other of the source and the drain of the first transistor is electrically connected to the fifth wiring;
A gate of the first transistor is electrically connected to the third wiring;
One of a source and a drain of the second transistor is electrically connected to the second wiring;
The other of the source and the drain of the second transistor is electrically connected to the display element;
A gate of the second transistor is electrically connected to the fifth wiring;
One of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor and the fifth wiring;
The other of the source and the drain of the third transistor is electrically connected to the fourth wiring through the sixth wiring;
A gate of the third transistor is electrically connected to the fourth wiring;
One of the pair of electrodes of the storage capacitor is electrically connected to the gate of the second transistor,
The other of the pair of electrodes of the storage capacitor is electrically connected to one of the second wiring and the source or drain of the second transistor,
The first wiring, the second wiring, the fifth wiring, and the sixth wiring are provided in a first wiring layer;
The third wiring and the fourth wiring are provided in a second wiring layer different from the first wiring layer,
The semiconductor layer of the first transistor, the semiconductor layer of the second transistor, and the semiconductor layer of the third transistor are provided in the same layer,
The semiconductor layer of the first transistor and the semiconductor layer of the third transistor are connected to each other,
A gate electrode of the first transistor is formed by a part of the third wiring;
A gate electrode of the third transistor is formed by a part of the fourth wiring;
The display device, wherein the fifth wiring intersects with the fourth wiring and does not intersect with the third wiring. In claim 1,
One of the pair of electrodes of the storage capacitor has a portion in which the gate electrode of the second transistor extends in a direction in which the second wiring extends,
The other of the pair of electrodes of the storage capacitor has a portion in which the semiconductor layer of the second transistor extends in a direction in which the second wiring extends,
The display device is characterized in that the storage capacitor is provided so as to overlap with the second wiring. A module comprising the display device according to claim 1. The electronic device which has the said display apparatus of Claim 1 or Claim 2. An electronic book having the display device according to claim 1.

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