JP4900019B2 - Insulation transformer and power converter - Google Patents

Description

  The present invention relates to an insulation transformer and a power conversion device, and is particularly suitable for application to a method using a glass substrate for insulation between a primary side winding and a secondary side winding of an insulation transformer.

In recent vehicle equipment, in order to achieve high efficiency and energy saving measures, a step-up / down converter and an inverter are mounted on a drive system of an electric motor that generates drive force.
FIG. 9 is a block diagram showing a schematic configuration of a vehicle drive system using a conventional buck-boost converter.
In FIG. 9, the vehicle drive system includes a power source 1101 that supplies power to the buck-boost converter 1102, a buck-boost converter 1102 that performs voltage boost and boost, and an inverter that converts the voltage output from the buck-boost converter 1102 into a three-phase voltage. 1103 and an electric motor 1104 for driving the vehicle are provided. Note that the power source 1101 can be configured by a power supply voltage from an overhead wire or a battery connected in series.

  When the vehicle is driven, the step-up / down converter 1102 boosts the voltage of the power source 1101 (eg, 280 V) to a voltage suitable for driving the electric motor 1104 (eg, 750 V) and supplies the boosted voltage to the inverter 1103. Then, by turning on / off the switching element, the voltage boosted by the buck-boost converter 1102 is converted into a three-phase voltage, current is passed through each phase of the electric motor 1104, and the switching frequency is controlled to control the vehicle. The speed of the can be changed.

  On the other hand, at the time of braking of the vehicle, the inverter 1103 performs a rectifying operation by performing on / off control of the switching element in synchronization with the voltage generated in each phase of the electric motor 1104 to convert it into a DC voltage, and then the buck-boost converter. 1102. The step-up / down converter 1102 can perform a power regeneration operation by reducing the voltage (eg, 750 V) generated from the electric motor 1104 to the voltage (eg, 280 V) of the power source 1101.

FIG. 10 is a block diagram showing a schematic configuration of the buck-boost converter of FIG.
In FIG. 10, a buck-boost converter 1102 includes a reactor L for storing energy, a capacitor C for storing charge, switching elements SW1 and SW2, and switching elements SW1 and SW2 for energizing and interrupting current flowing into the inverter 1103. Control circuits 1111 and 1112 are provided for generating control signals instructing conduction and non-conduction, respectively.

  The switching elements SW1 and SW2 are connected in series, and a power source 1101 is connected to a connection point of the switching elements SW1 and SW2 via a reactor L. Here, the switching element SW1 is provided with an IGBT (Insulated Gate Bipolar Transistor) 1105 that performs a switching operation in accordance with a control signal from the control circuit 1111. The flywheel diode D1 that flows a current in a direction opposite to the current flowing in the IGBT 1105 is the IGBT 1105. Connected in parallel.

  Further, the switching element SW2 is provided with an IGBT 1106 that performs a switching operation in accordance with a control signal from the control circuit 1112, and a flywheel diode D2 that flows a current in a direction opposite to the current flowing in the IGBT 1106 is connected in parallel to the IGBT 1106. The collector of the IGBT 1106 is connected to both the capacitor C and the inverter 1103.

FIG. 11 is a diagram showing a waveform of a current flowing through reactor L in FIG. 10 during the boosting operation.
11, the step-up operation, IGBT1105 switching element SW1 Then on (conductive), a current I flows through the reactor L through the IGBT1105, energy LI ^2/2 is stored in the reactor L.
Next, when the IGBT 1105 of the switching element SW1 is turned off (non-conducting), a current flows through the flywheel diode D2 of the switching element SW2, and the energy stored in the reactor L is sent to the capacitor C.

On the other hand, in the step-down operation, IGBT1106 switching element SW2 is turned on (conducting) Then a current I flows through the reactor L through the IGBT1106, energy LI ^2/2 is stored in the reactor L.
Next, when the IGBT 1106 of the switching element SW2 is turned off (non-conducting), a current flows through the flywheel diode D1 of the switching element SW1, and the energy stored in the reactor L is regenerated to the power source 1101.

Here, the voltage of the step-up / step-down can be adjusted by changing the ON time (ON Duty) of the switching element, and the approximate voltage value can be obtained by the following equation (1).
V _L / V _H = ON Duty (%) (1)
However, V _L is the power supply voltage, V _H is the voltage after step-up / step-down, and ON Duty is the ratio of the conduction period to the switching period of the switching elements SW1 and SW2.

Here, the actual variation of the load, since there is such fluctuations in the power supply voltage V _L, monitors the voltage V _H after buck, so that the voltage V _H after buck becomes a target value, the switching element SW1 , SW2 ON time (ON Duty) is controlled.
Further, the control circuits 1111 and 1112 that are grounded to the vehicle body casing are at low pressure, and the arm side that is connected to the switching elements SW1 and SW2 is at high pressure. For this reason, in order to prevent the human body from being exposed to danger even if an accident such as destruction of the switching elements SW1 and SW2 occurs, the arm side refers to the control circuits 1111 and 1112 using a photocoupler. Signals are exchanged while being electrically insulated.

FIG. 12 is a block diagram showing a schematic configuration of a conventional intelligent power module for a buck-boost converter.
In FIG. 12, the intelligent power module for the buck-boost converter generates control signals for instructing conduction and non-conduction of switching elements SWU, SWD and switching elements SWU, SWD for energizing and interrupting the current flowing into the load, respectively. A circuit 1 is provided. Here, the control circuit 1 can be configured by a CPU 4 or a logic IC, or a system LSI on which the logic IC and the CPU are mounted.

  The switching elements SWU and SWD are connected in series so as to operate for the upper arm 2 and the lower arm 3, respectively. The switching element SWU is provided with an IGBT 6 that performs a switching operation according to the gate signal SU4, and a flywheel diode DU1 that allows a current to flow in a direction opposite to the current that flows through the IGBT 6 is connected in parallel to the IGBT 6. The chip on which the IGBT 6 is formed has a main circuit in which the emitter current of the IGBT 6 is shunted through the temperature sensor using the VF change of the diode DU2 due to the temperature change of the chip as a measurement principle and the resistors RU1 and RU2. A current sensor for detecting current is provided.

  Further, the switching element SWD is provided with an IGBT 5 that performs a switching operation in accordance with the gate signal SD4, and a flywheel diode DD1 that allows a current to flow in a direction opposite to the current that flows through the IGBT 5 is connected in parallel to the IGBT 5. The chip on which the IGBT 5 is formed includes a temperature sensor that uses the VF change of the diode DD2 due to the temperature change of the chip as a measurement principle, and the emitter current of the IGBT 5 is shunted through the resistors RD1 and RD2, and the main circuit A current sensor for detecting current is provided.

The upper arm 2 has a protection function for generating the gate signal SU4 for driving the control terminal of the IGBT 6 while monitoring the overheat detection signal SU6 from the temperature sensor and the overcurrent detection signal SU5 from the current sensor. A gate driver IC 8 is provided, and an analog PWM converter CU that generates a PWM signal corresponding to the temperature of the IGBT 6 is provided.
The lower arm 3 has a protection function for generating a gate signal SD4 for driving the control terminal of the IGBT 5 while monitoring the overheat detection signal SD6 from the temperature sensor and the overcurrent detection signal SD5 from the current sensor. A gate driver IC 7 is provided, and an analog PWM converter CD that generates a PWM signal corresponding to the temperature of the IGBT 5 is provided.

Photocouplers FU1 to FU3 and FD1 to FD3 are inserted between the control circuit 1 side grounded to the vehicle body casing and the upper arm 2 side and the lower arm 3 side, which are at high pressure, respectively. 1, signals are exchanged using the photocouplers FU1 to FU3 and FD1 to FD3 while being electrically insulated from the upper arm 2 side and the lower arm 3 side.
That is, on the upper arm 2 side, the gate drive PWM signal SU1 output from the CPU 4 is input to the gate driver IC 8 with a protective function via the photocoupler FU1. The alarm signal SU2 output from the gate driver IC 8 with a protective function is input to the CPU 4 via the photocoupler FU2. The IGBT chip temperature PWM signal SU3 output from the analog PWM converter CU is input to the CPU 4 via the photocoupler FU3.

  On the other hand, on the lower arm 3 side, the gate drive PWM signal SD1 output from the CPU 4 is input to the gate driver IC 7 with a protective function via the photocoupler FD1. The alarm signal SD2 output from the gate driver IC 7 with a protective function is input to the CPU 4 via the photocoupler FD2. The IGBT chip temperature PWM signal SD3 output from the analog PWM converter CD is input to the CPU 4 via the photocoupler FD3.

FIG. 13 is a block diagram showing a schematic configuration of a peripheral circuit of the photocoupler.
In FIG. 13, a photocoupler 2008 includes an infrared light emitting diode 2003 that emits infrared light by a forward current If, a light receiving diode 2004 that receives the emitted infrared light, and a photocurrent generated by the light receiving diode 2004 as a base current. A bipolar transistor 2005 for performing a current amplification operation is provided. The cathode of the infrared light emitting diode 2003 is connected to the field effect transistor 2001 via the resistor 2002, the collector of the bipolar transistor 2005 is connected to the power supply voltage Vcc2 via the resistor 2006, and the collector of the bipolar transistor 2005 is connected. The output signal Vout output via the signal is input to the IGBT drive IC 2007.

  When the signal SP is input to the gate of the field effect transistor 2001, the forward current If flows to the infrared light emitting diode 2003, and infrared light is emitted. Infrared light emitted from the infrared light emitting diode 2003 is received by the light receiving diode 2004, and a photocurrent corresponding to the infrared light flows to the base of the bipolar transistor 2005. When a photocurrent flows through the base of the bipolar transistor 2005, a collector current Ic flows through the bipolar transistor 2005, and the collector current Ic flows through the resistor 2006 having one end connected to the power supply voltage Vcc2, thereby causing the other end voltage of the resistor 2006 to flow. Is input to the IGBT drive IC 2007 as the output signal Vout.

  Here, the input / output characteristics of the single photocoupler 2008 can be defined by current conversion efficiency (CTR: Current Transfer Ratio), that is, Ic / If. When designing a circuit using the photocoupler 2008, (1) temperature characteristics of the current amplification factor hfe of the bipolar transistor 2005, (2) lifetime deterioration of the luminous efficiency of the infrared light emitting diode 2003, (3) CTR It is necessary to consider points such as variations in

FIG. 14 is a graph showing the temperature characteristics of the current conversion efficiency of the photocoupler.
In FIG. 14, the current conversion efficiency of the photocoupler 2008 decreases as the temperature decreases, and this factor is the temperature characteristic of the current amplification factor hfe of the bipolar transistor 2005.
FIG. 15 is a diagram showing the deterioration characteristics over time of the current conversion efficiency of the photocoupler.
In FIG. 15, the CTR of the photocoupler 2008 decreases depending on the forward current of the light emitting diode 2003, the environmental temperature, and the cumulative usage time. In particular, when the continuous usage time of the photocoupler 2008 exceeds 1000 hours, the CTR decreases. Appears remarkably.

FIG. 16 is a diagram illustrating variation in the current conversion efficiency of the photocoupler.
In FIG. 16, the current conversion efficiency of the photocoupler has a large variation, which may be a variation in the light emission efficiency of the light emitting diode 2003 or the current amplification factor hfe of the bipolar transistor 2005.
When the photocoupler is used as the insulating transmission means of the intelligent power module for the buck-boost converter shown in FIG. 12, it is necessary to design the circuit in consideration of the above points. It is difficult to satisfy continuous use for more than a year.
On the other hand, there is a method using an insulating transformer as a means for insulating a transmission signal other than the photocoupler. As such an insulating transformer, micro transformers that have been significantly reduced in size by using MEMS (Micro Electro Mechanical Systems) technology have been commercialized by several companies.

FIG. 17A is a cross-sectional view showing a schematic configuration of a conventional insulating transformer, and FIG. 17B is a plan view showing a schematic configuration of the insulating transformer of FIG.
In FIG. 17, the lead wiring layer 12 is embedded in the semiconductor substrate 11, and the primary coil pattern 14 is formed on the semiconductor substrate 11. The primary coil pattern 14 is connected to the lead wiring layer 12 via the lead portion 13. A planarizing film 15 is formed on the primary coil pattern 14, a secondary coil pattern 17 is formed on the planarizing film 15, and the secondary coil pattern 17 is covered with a protective film 18. . The protective film 18 is formed with an opening 19 that exposes the center of the secondary coil pattern 17. By connecting a bonding wire to the center of the secondary coil pattern 17 through the opening 19, the secondary coil pattern 17 is formed. Drawing from the pattern 17 can be performed.
For example, the primary coil pattern 14 and the secondary coil pattern 17 may have a winding width of 5 to 10 μm, a thickness of 4 to 5 μm, and an outermost diameter of the winding of 500 μm.

18 and 19 are cross-sectional views showing a conventional method for manufacturing an insulating transformer.
In FIG. 18A, impurities such as As, P, and B are selectively implanted into the semiconductor substrate 51 to form a lead diffusion layer 52 for leading from the center of the primary coil pattern 55a. 51. The material of the semiconductor substrate 51 can be selected from, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, or ZnSe.

Next, as shown in FIG. 18B, an insulating layer 53 is formed on the semiconductor substrate 51 on which the extraction diffusion layer 52 is formed by a method such as plasma CVD. As the material of the insulating layer 53, for example, a silicon oxide film or a silicon nitride film can be used.
Next, as shown in FIG. 18C, by using a photolithography technique, the resist pattern 54 provided with the opening 54a corresponding to the lead-out portion from the center of the primary coil pattern 55a is formed into the insulating layer 53. Form on top.
Next, as shown in FIG. 18D, the insulating layer 53 is etched using the resist pattern 54 with the opening 54a formed as a mask, thereby opening corresponding to the lead-out portion from the center of the primary coil pattern 55a. A portion 53 a is formed in the insulating layer 53.
Next, as shown in FIG. 18E, the resist pattern 54 is peeled off from the insulating layer 53 with chemicals.

Next, as shown in FIG. 18F, a conductive film 55 is formed on the insulating layer 53 by a method such as sputtering or vapor deposition. In addition, as a material of the electrically conductive film 55, metals, such as Al and Cu, can be used.
Next, as shown in FIG. 18G, a resist pattern 56 corresponding to the primary coil pattern 55a is formed by using a photolithography technique.
Next, as illustrated in FIG. 18H, the conductive coil 55 is etched using the resist pattern 56 as a mask, thereby forming a primary coil pattern 55 a on the insulating layer 153.
Next, as shown in FIG. 18I, the resist pattern 56 is peeled off from the primary coil pattern 55a with chemicals.

Next, as shown in FIG. 18J, a planarizing film 57 is formed on the insulating layer 53 on which the primary coil pattern 55a is formed by a method such as plasma CVD. As a material of the planarizing film 57, for example, a silicon oxide film or a silicon nitride film can be used.
Next, as shown in FIG. 18 (k), the planarization film 57 is planarized by a method such as oblique etching or CMP (Chemical Mechanical Polishing), and unevenness on the surface of the planarization layer 57 is removed.
Next, as shown in FIG. 18L, the resist pattern 58 provided with the opening 58a corresponding to the wiring extraction portion at the outer end of the secondary coil pattern 55a is flattened by using a photolithography technique. Formed on the film 57.

Next, as shown in FIG. 19A, the planarizing film 57 is etched using the resist pattern 58 provided with the opening 58a as a mask, thereby corresponding to the wiring extraction portion at the outer end of the secondary coil pattern 55a. The opening 57a thus formed is formed in the planarizing film 57.
Next, as shown in FIG. 19B, the resist pattern 58 is peeled off from the planarizing film 57 by chemicals.
Next, as illustrated in FIG. 19C, a separation layer 59 of the primary coil pattern 55 a and the secondary coil pattern 55 a is formed on the planarizing film 57. As a method of forming the separation layer 59, a method of forming a polyimide layer on the planarizing film 57 by spin coating or the like can be used. Alternatively, as a method of forming the separation layer 59, a silicon oxide film may be formed on the planarizing film 57 by sputtering.

Next, as shown in FIG. 19D, a conductive film 60 is formed on the separation layer 59 by a method such as sputtering or vapor deposition. In addition, as a material of the electrically conductive film 60, metals, such as Al and Cu, can be used.
Next, as shown in FIG. 19E, a resist pattern 61 corresponding to the secondary coil pattern 60a is formed by using a photolithography technique.
Next, as shown in FIG. 19 (f), the secondary coil pattern 60 a is formed on the separation layer 59 by etching the conductive film 60 using the resist pattern 61 as a mask.
Next, as shown in FIG. 19G, the resist pattern 61 is peeled off from the secondary coil pattern 60a with chemicals.

  Next, as shown in FIG. 19H, a protective film 62 is formed on the separation layer 59 on which the secondary coil pattern 60a is formed by a method such as plasma CVD. As the material of the protective film 62, for example, a silicon oxide film or a silicon nitride film can be used. Then, by patterning the protective film 62 using a photolithography technique and an etching technique, the end portion and the center portion of the secondary coil pattern 60a are exposed.

  Further, for example, in Patent Document 1, in a transformer element formed from a first wiring layer and a second wiring layer, the first wiring layer and the second wiring layer are viewed from one of the vertically upward direction and the vertically downward direction. The projected outline has a symmetrical shape with respect to a predetermined reference plane, and the projected outline is on one of the first wiring layer and the second wiring layer. A method for reducing the area occupied by the transformer element is disclosed by using the first wiring layer and the second wiring layer so as not to intersect each other at the intersection.

Further, for example, Patent Literature 2 discloses an air core transformer provided with first and second coils surrounded by a protective ring in the horizontal direction.
Further, for example, in Patent Document 3, a laminated transformer is constituted by a magnetic sheet provided with a coil conductor on the surface and a magnetic sheet provided with a glass insulating layer on the surface. A method for increasing the dielectric strength between the coils without increasing the height dimension of the components while suppressing the decrease in the coupling amount is disclosed.
Japanese Patent Laying-Open No. 2005-5585 US Patent Application Publication No. 2005/230837 JP 2005-310959 A

However, in the method of manufacturing the insulating transformer of FIGS. 18 and 19, in the method of forming a polyimide layer as the separation layer 59 by spin coating, the film thickness of the separation layer 59 is 20 μm or less in order to maintain the flatness of the surface. Limited to
Further, in the method of forming a silicon oxide film as the separation layer 59 by sputtering, the film thickness of the separation layer 59 is limited to 10 μm or less in consideration of surface non-uniformity and film formation rate due to thermal stress during film formation. Is done.

On the other hand, in applications such as vehicles and industrial equipment, ESD resistance of 15 to 30 kV corresponding to the static electricity of the human body is required, and a microtransformer as shown in FIG. 19 is combined with a primary side circuit and a secondary side circuit. As a result, the voltage of 15 to 30 kV is applied to the separation layer 59. When a voltage of 15 to 30 kV is applied to the separation layer 59, a breakdown voltage of 8 to 11 kV is applied to the polyimide layer having a thickness of 20 μm and about 7 kV is applied to the silicon oxide film having a thickness of 10 μm. There was a problem that 59 was dielectrically broken.
Accordingly, an object of the present invention is to reduce the influence of noise caused by external magnetic flux while improving reliability and environmental resistance while suppressing deterioration over time and electrically connecting the low voltage side and the high voltage side. It is an object to provide an insulating transformer and a power converter that can exchange signals while being insulated.

In order to solve the above-described problem , according to the insulating transformer of claim 1, a semiconductor substrate in which one of a primary winding and a secondary winding is formed on one surface, and the primary winding. A glass substrate or a ceramic substrate in which the other of the wire and the secondary winding is formed on one surface; and the primary winding and the secondary winding formed on the one surface of the semiconductor substrate A protective film formed on one of the lines and having a flattened surface; and an adhesive film that fixes the surface of the protective film and the other surface of the glass substrate or the ceramic substrate. Features.
As a result, the insulation transformer can be integrated on the semiconductor substrate while ensuring an interval between the primary winding and the secondary winding of the insulation transformer of several tens of μm or more, and an ESD resistance of 15 to 30 kV can be obtained. In addition, the signal transmission circuit can be reduced in size.

Further, according to the isolation transformer of claim 2, wherein said insulation transformer is characterized in that it is formed by microfabrication techniques.
Thereby, it is possible to reduce the winding diameters of the primary winding and the secondary winding, and it is possible to reduce the interval between the primary winding and the secondary winding. For this reason, while increasing the coupling coefficient between the primary winding and the secondary winding, the influence as noise can be reduced even when the external magnetic flux is linked to the primary winding and the secondary winding. The S / N ratio can be improved.

The insulating transformer according to claim 3 is characterized in that the glass substrate is made of an alkali-free component.
Thereby, even when a high voltage is applied to the glass substrate, the alkali ion component can be prevented from moving within the glass substrate, and the deterioration of the insulating properties of the glass substrate can be suppressed.

Further, according to the power conversion device of claim 4, a pair of switching elements connected in series so as to operate respectively for the upper arm and the lower arm, and for energizing and interrupting the current flowing into the load, A control circuit that generates a control signal that instructs conduction and non-conduction of the switching element, a drive circuit that drives a control terminal of the switching element based on the control signal, and the control circuit and the drive circuit are insulated. An insulating transformer in which the primary winding and the secondary winding are arranged opposite to each other , and the insulating transformer has one of the primary winding and the secondary winding on one surface. A formed semiconductor substrate, a glass substrate or a ceramic substrate in which the other of the primary winding and the secondary winding is formed on one surface, and formed on the one surface of the semiconductor substrate. A protective film formed on one of the primary winding and the secondary winding and having a flattened surface, the surface of the protective film, and the other surface of the glass substrate or the ceramic substrate And an adhesive film for adhering to each other.

  As a result, it is possible to secure an ESD resistance of 15 to 30 kV while enabling the miniaturization of the insulating transformer by a microfabrication technique, and the reliability of the insulating transformer is ensured, and this is caused by the external magnetic flux. It becomes possible to reduce the influence as noise, and it is not necessary to use a photocoupler in order to exchange signals while electrically insulating the low voltage side and the high voltage side, while suppressing deterioration over time, Environmental resistance can be improved.

  As described above, according to the present invention, the interval between the primary winding and the secondary winding of the insulation transformer can be reduced to several tens of μm while the insulation transformer can be miniaturized by a fine processing technique. As a result, the reliability and environment resistance can be improved, the influence of noise caused by external magnetic flux can be reduced, and signals can be exchanged while electrically insulating the low voltage side from the high voltage side. It becomes possible.

Hereinafter, an insulating transformer according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of an intelligent power module (IPM: Intelligent Power Module) to which a power electronic device according to an embodiment of the present invention is applied.
In FIG. 1, the intelligent power module for the buck-boost converter generates control signals for instructing conduction and non-conduction of switching elements SWU, SWD and switching elements SWU, SWD for energizing and interrupting the current flowing into the load, respectively. A circuit 1 is provided. Here, the control circuit 1 can be configured by a CPU 4 or a logic IC, or a system LSI on which the logic IC and the CPU are mounted.

  The switching elements SWU and SWD are connected in series so as to operate for the upper arm 2 and the lower arm 3, respectively. The switching element SWU is provided with an IGBT 6 that performs a switching operation based on the gate signal SU4, and a flywheel diode DU1 that allows a current to flow in a direction opposite to the current that flows in the IGBT 6 is connected in parallel to the IGBT 6. The chip on which the IGBT 6 is formed has a main circuit in which the emitter current of the IGBT 6 is shunted through the temperature sensor using the VF change of the diode DU2 due to the temperature change of the chip as a measurement principle and the resistors RU1 and RU2. A current sensor for detecting current is provided.

  Further, the switching element SWD is provided with an IGBT 5 that performs a switching operation in accordance with the gate signal SD4, and a flywheel diode DD1 that allows a current to flow in a direction opposite to the current that flows through the IGBT 5 is connected in parallel to the IGBT 5. The chip on which the IGBT 5 is formed includes a temperature sensor that uses the VF change of the diode DD2 due to the temperature change of the chip as a measurement principle, and the emitter current of the IGBT 5 is shunted through the resistors RD1 and RD2, and the main circuit A current sensor for detecting current is provided.

  The upper arm 2 has a protection function for generating the gate signal SU4 for driving the control terminal of the IGBT 6 while monitoring the overheat detection signal SU6 from the temperature sensor and the overcurrent detection signal SU5 from the current sensor. A gate driver IC 8 is provided, and an analog PWM converter CU that generates a PWM signal corresponding to the temperature of the IGBT 6 is provided. Note that the gate driver IC 8 with a protective function can be provided with a self-diagnosis circuit that generates state signals of the switching elements SWD and SWU, and the self-diagnosis circuit can generate state signals of the switching elements SWD and SWU.

The lower arm 3 has a protection function for generating a gate signal SD4 for driving the control terminal of the IGBT 5 while monitoring the overheat detection signal SD6 from the temperature sensor and the overcurrent detection signal SD5 from the current sensor. A gate driver IC 7 is provided, and an analog PWM converter CD that generates a PWM signal corresponding to the temperature of the IGBT 5 is provided.
Air-core insulating transformers TU1 to TU3 and TD1 to TD3 are inserted between the control circuit 1 side grounded to the vehicle body casing and the upper arm 2 side and the lower arm 3 side, which are at high pressure, respectively. In the control circuit 1, signals are exchanged using the air-core type insulating transformers TU1 to TU3 and TD1 to TD3 while being electrically insulated from the upper arm 2 side and the lower arm 3 side.

  That is, on the upper arm 2 side, the gate drive PWM signal SU1 output from the CPU 4 is input to the gate driver IC 8 with a protective function via the air-core type insulating transformer TU1. Further, the alarm signal SU2 output from the gate driver IC 8 with a protective function is input to the CPU 4 via the air core type insulating transformer TU2. Further, the IGBT chip temperature PWM signal SU3 output from the analog PWM converter CU is input to the CPU 4 via the air core type insulating transformer TU3.

  On the other hand, on the lower arm 3 side, the gate drive PWM signal SD1 output from the CPU 4 is input to the gate driver IC 7 with a protective function via the air-core insulating transformer TD1. The alarm signal SD2 output from the gate driver IC 7 with a protective function is input to the CPU 4 via the air core type insulating transformer TD2. The IGBT chip temperature PWM signal SD3 output from the analog PWM converter CD is input to the CPU 4 via the air-core type insulating transformer TD3.

  Here, the air-core insulating transformers TU1 to TU3 and TD1 to TD3 are respectively provided with a primary winding on the transmission side and a secondary winding on the reception side. The primary winding and the secondary winding of the air-core type insulating transformers TU1 to TU3 and TD1 to TD3 are configured to face each other. For example, the primary winding and the secondary winding of the air-core type insulating transformers TU1 to TU3 and TD1 to TD3 can be stacked on each other via an insulating layer, and the air-core type insulating transformers TU1 to TU3 and TD1 to TD3 are stacked. Can be formed by a fine processing technique such as a semiconductor process technique.

  Moreover, a glass substrate or a ceramic substrate can be used as an insulating layer that insulates and separates the primary and secondary windings of the air-core insulating transformers TU1 to TU3 and TD1 to TD3. Here, the thickness of the glass substrate or the ceramic substrate can be set so as to ensure an ESD tolerance of 15 to 30 kV, and can be set to about several tens of μm to several hundreds of μm, for example. In addition, when a glass substrate is used as an insulating layer that insulates and separates the primary and secondary windings of the air-core type insulating transformers TU1 to TU3 and TD1 to TD3, the material of the glass substrate is an alkali-free component. It is preferable. For example, alumina, zirconia, aluminum nitride, or the like can be used as the ceramic substrate for insulating and separating the primary winding and the secondary winding of the air-core type insulating transformers TU1 to TU3 and TD1 to TD3.

  Then, the CPU 4 generates the gate drive PWM signals SD1 and SU1 for instructing the conduction or non-conduction of the IGBTs 5 and 6, respectively. The gate drive PWM signals SD1 and SU1 are passed through the air-core insulated transformers TD1 and TU1, respectively. Insulated and transmitted to the gate driver ICs 7 and 8 with protective functions. Then, the gate driver ICs 7 and 8 with protective functions generate gate signals SD4 and SU4 based on the gate drive PWM signals SD1 and SU1, respectively, and drive the control terminals of the IGBTs 5 and 6, thereby switching the IGBTs 5 and 6. Make it work.

  Here, the overheat detection signals SD6 and SU6 output from the temperature sensor are input to the gate driver ICs 7 and 8 with protection function, respectively, and the overcurrent detection signals SD5 and SU5 output from the current sensor are the gate driver with protection function. Input to ICs 7 and 8, respectively. Then, the gate drivers IC 7 and 8 with protection functions transmit alarm signals SD2 and SU2 to the CPU 4 via the air-core type insulating transformers TD2 and TU2, respectively, when the threshold values that the IGBTs 5 and 6 do not break are exceeded. When the CPU 4 receives the alarm signals SD2 and SU2 from the gate driver ICs 7 and 8 with protection functions, the CPU 4 stops the generation of the gate drive PWM signals SD1 and SU1, respectively, thereby cutting off the current flowing through the IGBTs 5 and 6. .

Note that the gate driver ICs 7 and 8 with protective functions are below the threshold at which the IGBT does not break down based on the overheat detection signals SD6 and SU6 output from the temperature sensor and the overcurrent detection signals SD5 and SU5 output from the current sensor. If it is determined, the alarm signals SD2 and SU2 are canceled after a certain time has elapsed.
Further, when performing fine monitoring, the overheat detection signals SD6 and SU6 output from the temperature sensor are input to the analog PWM converters CD and CU, respectively. Then, the analog PWM converters CD and CU generate the IGBT chip temperature PWM signals SD3 and SU3, respectively, by converting the analog values of the overheat detection signals SD6 and SU6 into digital signals, respectively, and the air-core insulated transformer TD3, The IGBT chip temperature PWM signals SD3 and SU3 are transmitted to the CPU 4 via the TU3, respectively. Then, the CPU 4 calculates the chip temperatures of the IGBTs 5 and 6 from the IGBT chip temperature PWM signals SD3 and SU3, respectively, and performs a stepwise decrease in the switching frequency of the IGBTs 5 and 6 according to a predetermined number of thresholds. Or switching can be stopped.

  Here, the primary winding and the secondary are formed by fine processing technology so that the primary winding and the secondary winding of the air-core type insulating transformers TU1 to TU3 and TD1 to TD3 are arranged to face each other. It is possible to reduce the winding diameter of the winding and reduce the interval between the primary winding and the secondary winding. For this reason, while increasing the coupling coefficient between the primary winding and the secondary winding, the area where the magnetic flux interlinks with the primary winding and the secondary winding can be reduced, and noise caused by external magnetic flux It is possible to reduce the effects of noise, and it is no longer necessary to use a photocoupler to transmit and receive signals while electrically insulating the low-voltage side and high-voltage side. Can be improved.

  Further, as the insulating layer for insulating and separating the primary winding and the secondary winding of the air-core type insulating transformers TU1 to TU3 and TD1 to TD3, a glass substrate or a ceramic substrate is used so that the air-core type insulating transformer TU1. The distance between the primary and secondary windings is several tens without impairing the flatness and uniformity of the surface on which the primary and secondary windings of TU3 and TD1 to TD3 are formed. μm or more can be secured. For this reason, it becomes possible to secure the ESD tolerance of 15 to 30 kV while making it possible to miniaturize the air-core type insulating transformers TU1 to TU3 and TD1 to TD3 by the microfabrication technology, and the reliability and environmental resistance As a result, it is possible to reduce the influence of noise caused by the external magnetic flux, and to exchange signals while electrically insulating the control circuit 1 from the upper arm 2 and the lower arm 3.

FIG. 2 is a cross-sectional view showing a schematic configuration of the insulating transformer according to the first embodiment of the present invention.
In FIG. 2, a lead wiring layer 12 is embedded in a semiconductor substrate 11, and a secondary coil pattern 14 and a wiring pattern 14 ′ are formed on the semiconductor substrate 11 via an insulating layer 13. It should be noted that the semiconductor substrate 11 may be formed with integrated circuits such as gate driver ICs 7 and 8 with protective functions, analog PWM converters CU and CD shown in FIG. 1, or switching elements SWU and SWD. The material of the semiconductor substrate 11 can be selected from, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, or ZnSe. The end portion disposed at the center of the secondary coil pattern 14 is connected to the wiring pattern 14 ′ via the lead wiring layer 12. A secondary protection film 15 is formed on the secondary coil pattern 14.

  On the other hand, a primary coil pattern 18 is formed on one surface of the glass substrate 17, and the primary coil pattern 18 is covered with a protective film 19. The protective film 19 is formed with an opening exposing the start and end of the primary coil pattern 18, and bonding wires are connected to the start and end of the primary coil pattern 18 through the opening. The next coil pattern 18 can be pulled out.

For example, the winding width of the secondary coil pattern 14 and the primary coil pattern 18 may be 5 to 10 μm, the thickness may be 4 to 5 μm, and the outermost diameter of the winding may be 500 μm.
The glass substrate 17 on which the primary coil pattern 18 is formed on one surface is fixed on the semiconductor substrate 11 with the adhesive layer 16 via the other surface of the glass substrate 17. Note that an adhesive film such as an epoxy resin can be used as the adhesive layer 16.

Thereby, the distance between the secondary coil pattern 14 and the primary coil pattern 18 is several tens of μm without impairing the flatness and uniformity of the surface on which the secondary coil pattern 14 and the primary coil pattern 18 are formed. In addition to ensuring the above, the secondary coil pattern 14 and the primary coil pattern 18 can be formed by semiconductor process technology. For this reason, it is possible to integrate the insulating transformer on the semiconductor substrate 11 while ensuring an interval between the secondary coil pattern 14 and the primary coil pattern 18 of several tens of μm or more, and ensure an ESD resistance of 15 to 30 kV. In addition, the signal transmission circuit can be reduced in size.
In the above-described embodiment, the method of forming the secondary coil pattern 14 on the semiconductor substrate 11 and forming the primary coil pattern 18 on the glass substrate 17 has been described. However, the secondary coil pattern 14 is formed on the glass substrate 17. The primary coil pattern 18 may be formed on the semiconductor substrate 11.

3 and 4 are cross-sectional views showing a method for manufacturing the insulating transformer of FIG.
In FIG. 3A, impurities such as As, P, and B are selectively implanted into the semiconductor substrate 11 so that the lead wiring layer 12 for leading from the center of the secondary coil pattern 14 is formed on the semiconductor substrate. 11 to form.
Next, as shown in FIG. 3B, an insulating layer 13 is formed on the semiconductor substrate 11 on which the lead wiring layer 12 is formed by a method such as plasma CVD. As the material of the insulating layer 13, for example, a silicon oxide film or a silicon nitride film can be used.

Next, as shown in FIG. 3C, an opening H1 is provided corresponding to the lead-out portion from the center of the secondary coil pattern 14 and the connection portion with the wiring pattern 14 'by using a photolithography technique. The resist pattern R1 thus formed is formed on the insulating layer 13.
Next, as shown in FIG. 3 (d), the insulating layer 13 is etched using the resist pattern R1 in which the opening H1 is formed as a mask, whereby the lead-out portion and the wiring pattern 14 from the center of the secondary coil pattern 14 are obtained. An opening 13 a corresponding to the connection portion with ′ is formed in the insulating layer 13.
Next, as shown in FIG. 3E, the resist pattern R1 is peeled off from the insulating layer 13 with a chemical.

Next, as shown in FIG. 3F, a conductive film 14a is formed on the insulating layer 13 by a method such as sputtering or vapor deposition. In addition, as a material of the electrically conductive film 14a, metals, such as Al and Cu, can be used.
Next, as shown in FIG. 3G, a resist pattern R2 corresponding to the secondary coil pattern 14 is formed on the conductive film 14a by using a photolithography technique.
Next, as illustrated in FIG. 3H, the secondary coil pattern 14 is formed on the insulating layer 13 by etching the conductive film 14 a using the resist pattern R <b> 2 as a mask.
Next, as shown in FIG. 3I, the resist pattern R2 is peeled off from the secondary coil pattern 14 with a chemical.

  Next, as shown in FIG. 3J, a protective film 15 is formed on the insulating layer 13 on which the secondary coil pattern 14 is formed by a method such as plasma CVD. For example, a silicon oxide film or a silicon nitride film can be used as the material of the protective film 15. Then, by using a photolithography technique and an etching technique, openings corresponding to the leading end and terminal leading portions of the secondary coil pattern 14 are formed in the protective film 15.

On the other hand, in FIG. 4A, a conductive film 18a is formed on the glass substrate 17 by a method such as sputtering or vapor deposition. In addition, as a material of the electrically conductive film 18a, metals, such as Al and Cu, can be used.
Next, as shown in FIG. 4B, a resist pattern R3 corresponding to the primary coil pattern 18 is formed on the conductive film 18a by using a photolithography technique.
Next, as shown in FIG. 4C, the primary coil pattern 18 is formed on the glass substrate 17 by etching the conductive film 18a using the resist pattern R3 as a mask.
Next, as shown in FIG. 4D, the resist pattern R3 is peeled off from the primary coil pattern 18 with a chemical.

  Next, as shown in FIG. 4E, a protective film 19 is formed on the glass substrate 17 on which the primary coil pattern 18 is formed by a method such as plasma CVD. For example, a silicon oxide film or a silicon nitride film can be used as the material of the protective film 19. Then, by using a photolithography technique and an etching technique, openings corresponding to the leading and trailing lead portions of the primary coil pattern 18 are formed in the protective film 19.

Next, as shown in FIG. 4F, after the adhesive tape 16 is attached to the other surface of the glass substrate 17 on which the primary coil pattern 18 is formed on one surface, the glass substrate 17 is chipped. .
Next, as shown in FIG. 4G, the glass substrate 17 on which the primary coil pattern 18 is formed on one surface so that the secondary coil pattern 14 and the primary coil pattern 18 are arranged to face each other. Is fixed onto the semiconductor substrate 11 with an adhesive tape 16.

FIG. 5 is a cross-sectional view showing a schematic configuration of an insulating transformer according to the second embodiment of the present invention.
In FIG. 5, a recess 30 is formed in the semiconductor substrate 21. The lead-out wiring layer 22 is embedded in the semiconductor substrate 21 so as to be disposed in the recess 30, and the secondary coil pattern 24 and the wiring pattern 24 are formed on the semiconductor substrate 21 via the insulating layer 23. 'Is formed. Note that the semiconductor substrate 21 may be formed with integrated circuits such as the gate drivers ICs 7 and 8 with protection function of FIG. 1, the analog PWM converter CU and CD, or the switching elements SWU and SWD. The end portion disposed at the center of the secondary coil pattern 24 is connected to the wiring pattern 24 ′ via the lead wiring layer 22. A secondary protection film 25 is formed on the secondary coil pattern 24.

  On the other hand, a primary coil pattern 28 is formed on one surface of the glass substrate 27, and the primary coil pattern 28 is covered with a protective film 29. The protective film 29 is formed with an opening that exposes the start and end of the primary coil pattern 28, and bonding wires are connected to the start and end of the primary coil pattern 28 through the opening. The next coil pattern 28 can be pulled out.

The glass substrate 27 on which the primary coil pattern 28 is formed on one surface is fixed to the bonding surface 31 of the semiconductor substrate 21 via the other surface of the glass substrate 27 by electrostatic bonding.
In the above-described embodiment, the method of forming the secondary coil pattern 24 on the semiconductor substrate 21 and forming the primary coil pattern 28 on the glass substrate 27 has been described. However, the secondary coil pattern 24 is formed on the glass substrate 27. The primary coil pattern 28 may be formed on the semiconductor substrate 21.

6 and 7 are cross-sectional views showing a method for manufacturing the insulating transformer of FIG.
In FIG. 6A, a resist pattern R11 provided with an opening H11 corresponding to the recess 30 for arranging the secondary coil pattern 24 is formed on the semiconductor substrate 21 by using a photolithography technique.
Next, as shown in FIG. 6B, the semiconductor substrate 21 is etched using the resist pattern R11 in which the opening H11 is formed as a mask, thereby forming the recess 30 for arranging the secondary coil pattern 24 in the semiconductor substrate. 21.

Next, as illustrated in FIG. 6C, a resist pattern R <b> 12 having an opening H <b> 12 corresponding to the lead-out wiring layer 12 is formed in the recess 30 by using a photolithography technique.
Next, as shown in FIG. 6D, by using the resist pattern R12 provided with the opening H12 as a mask, impurities such as As, P, and B are selectively implanted into the semiconductor substrate 21 to obtain 2 A lead wiring layer 22 for leading from the center of the next coil pattern 24 is formed on the semiconductor substrate 21.
Next, as shown in FIG. 6E, the resist patterns R11 and R12 are peeled off from the semiconductor substrate 21 with chemicals.

Next, as shown in FIG. 6F, an insulating layer 23 is formed on the semiconductor substrate 21 on which the lead wiring layer 22 is formed by a method such as plasma CVD. As the material of the insulating layer 23, for example, a silicon oxide film or a silicon nitride film can be used.
Next, as shown in FIG. 6G, an opening H13 is provided corresponding to the lead-out portion from the center of the secondary coil pattern 24 and the connection portion with the wiring pattern 24 'by using a photolithography technique. The formed resist pattern R12 is formed on the insulating layer 23.

Next, as shown in FIG. 6 (h), the insulating layer 23 is etched using the resist pattern R13 in which the opening H13 is formed as a mask, whereby the lead-out portion from the center of the secondary coil pattern 24 and the wiring pattern 24 are obtained. An opening 23 a corresponding to the connecting portion with ′ is formed in the insulating layer 23.
Next, as shown in FIG. 6I, the resist pattern R13 is peeled off from the insulating layer 23 with a chemical.
Next, as shown in FIG. 6J, a conductive film 24a is formed on the insulating layer 23 by a method such as sputtering or vapor deposition. Note that a metal such as Al or Cu can be used as the material of the conductive film 24a.

Next, as shown in FIG. 6K, a resist pattern R14 corresponding to the secondary coil pattern 24 is formed on the conductive film 24a by using a photolithography technique.
Next, as shown in FIG. 6L, the secondary coil pattern 24 is formed on the insulating layer 23 by etching the conductive film 24a using the resist pattern R14 as a mask.
Next, as shown in FIG. 6M, the resist pattern R14 is peeled off from the secondary coil pattern 24 with a chemical.

  Next, as shown in FIG. 6 (n), a protective film 25 is formed on the insulating layer 23 on which the secondary coil pattern 24 is formed by a method such as plasma CVD. Then, the surface of the semiconductor substrate 21 outside the recess 30 is exposed by planarizing the protection film 25 by a method such as CMP so that the protection film 25 is embedded in the recess 30. For example, a silicon oxide film or a silicon nitride film can be used as the material of the protective film 25. Then, by using a photolithography technique and an etching technique, openings corresponding to the leading and trailing lead portions of the secondary coil pattern 24 are formed in the protective film 25.

On the other hand, in FIG. 7A, a conductive film 28a is formed on the glass substrate 27 by a method such as sputtering or vapor deposition. As a material for the conductive film 28a, a metal such as Al or Cu can be used.
Next, as shown in FIG. 7B, a resist pattern R15 corresponding to the primary coil pattern 28 is formed on the conductive film 28a by using a photolithography technique.
Next, as shown in FIG. 7C, the primary coil pattern 28 is formed on the glass substrate 27 by etching the conductive film 28a using the resist pattern R15 as a mask.
Next, as shown in FIG. 7D, the resist pattern R15 is peeled off from the primary coil pattern 28 with chemicals.

  Next, as shown in FIG. 7E, a protective film 29 is formed on the glass substrate 27 on which the primary coil pattern 28 has been formed by a method such as plasma CVD. As the material of the protective film 29, for example, a silicon oxide film or a silicon nitride film can be used. Then, by using a photolithography technique and an etching technique, openings corresponding to the leading and trailing lead portions of the primary coil pattern 28 are formed in the protective film 29.

  Next, as shown in FIG. 7 (f), a glass substrate 27 having the primary coil pattern 28 formed on one surface so that the secondary coil pattern 24 and the primary coil pattern 28 are arranged to face each other. Is fixed on the semiconductor substrate 21 by electrostatic bonding. When the glass substrate 27 is fixed to the semiconductor substrate 21 by electrostatic bonding, the glass substrate 27 and the semiconductor substrate 21 are electrostatically bonded while heating the glass substrate 27 and the semiconductor substrate 21 to about 400 ° C. And a negative voltage of several hundred volts can be applied to the glass substrate 27 side.

FIG. 8 is a cross-sectional view showing a schematic configuration of an insulating transformer according to the third embodiment of the present invention.
In FIG. 8, a wiring pattern 43 is formed on a semiconductor substrate 41. An insulating layer 42 is formed on the wiring pattern 43 so as to expose a connection region with the secondary coil pattern 45. Note that the semiconductor substrate 41 may be formed with integrated circuits such as gate driver ICs 7 and 8 with protection function, analog PWM converters CU and CD shown in FIG. 1 or switching elements SWU and SWD.

  On the other hand, a primary coil pattern 48 is formed on one surface of the glass substrate 47, and the primary coil pattern 48 is covered with a protective film 49. The protective film 49 is formed with an opening that exposes the start and end of the primary coil pattern 48. By connecting bonding wires to the start and end of the primary coil pattern 48 through the opening, The next coil pattern 48 can be pulled out.

A secondary coil pattern 45 is formed on the other surface of the glass substrate 47, and the primary coil pattern 48 is covered with a protective film 44. The protective film 44 is formed with an opening that exposes the start and end of the secondary coil pattern 45.
Then, the glass substrate 47 on which the primary coil pattern 48 and the secondary coil pattern 45 are formed is formed on the semiconductor substrate 41 by connecting the start and end of the secondary coil pattern 45 to the wiring pattern 43 through the protruding electrode 46. It is fixed to.

  As the protruding electrode 46, for example, a solder bump or a lead-free ball, an Au bump, a Cu bump coated with a solder material, or a Ni bump can be used. Further, a sealing resin may be injected into the gap between the glass substrate 47 and the semiconductor substrate 41. Further, for example, when the glass substrate 47 is flip-chip mounted on the semiconductor substrate 41, an ACF (Anisotropic Conductive Film), an NCF (Nonductive Conductive Paste) junction, an ACP (Anisotropic Conductive Paste) junction, an NCP (Nonconductive Bond) junction, etc. Bonding may be used, or metal bonding such as solder bonding or alloy bonding may be used.

  Accordingly, the secondary coil pattern 45 of the insulating transformer is formed on the circuit pattern formed on the semiconductor substrate 41 while ensuring the interval between the secondary coil pattern 45 of the insulating transformer 45 and the primary coil pattern 48 of several tens of μm or more. And the primary coil pattern 48 can be arranged in an overlapping manner. Therefore, the insulating transformer can be integrated on the semiconductor substrate 41 while reducing the space for forming the secondary coil pattern 45 and the primary coil pattern 48 of the insulating transformer on the semiconductor substrate 41. The signal transmission circuit can be downsized while ensuring the ESD tolerance.

1 is a block diagram illustrating a schematic configuration of an intelligent power module for a buck-boost converter to which an insulating transformer according to an embodiment of the present invention is applied. It is sectional drawing which shows schematic structure of the insulated transformer which concerns on 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the insulation transformer of FIG. It is sectional drawing which shows the manufacturing method of the insulation transformer of FIG. It is sectional drawing which shows schematic structure of the insulation transformer which concerns on 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the insulation transformer of FIG. It is sectional drawing which shows the manufacturing method of the insulation transformer of FIG. It is sectional drawing which shows schematic structure of the insulation transformer which concerns on 3rd Embodiment of this invention. It is a block diagram which shows schematic structure of the vehicle drive system using the conventional buck-boost converter. It is a block diagram which shows schematic structure of the buck-boost converter of FIG. It is a figure which shows the waveform of the electric current which flows into the reactor of FIG. 10 at the time of pressure | voltage rise operation. It is a block diagram which shows schematic structure of the conventional intelligent power module for buck-boost converters. It is a block diagram which shows schematic structure of the peripheral circuit of a photocoupler. It is a figure which shows the temperature characteristic of the current conversion efficiency of a photocoupler. It is a figure which shows the time-dependent deterioration characteristic of the current conversion efficiency of a photocoupler. It is a figure which shows the variation in the current conversion efficiency of a photocoupler. FIG. 17A is a cross-sectional view showing a schematic configuration of a conventional insulating transformer, and FIG. 17B is a plan view showing a schematic configuration of the insulating transformer of FIG. It is sectional drawing which shows the manufacturing method of the conventional insulation transformer. It is sectional drawing which shows the manufacturing method of the conventional insulation transformer.

Explanation of symbols

1 Control Circuit 2 Upper Arm 3 Lower Arm 4 CPU
5, 6 IGBT
7, 8 Gate driver IC with protection function
TU1 to TU3, TD1 to TD3 Insulating transformers DU1, DU2, DD1, DD2 Diode RU1, RU2, RD1, RD2 Resistor CU, CD Analog PWM converter 11, 21, 41 Semiconductor substrate 12, 22 Leading wiring layers 13, 23, 42 , 44, 49 Insulating layer 14, 24, 45 Secondary coil pattern 15, 25 Secondary protective film 16 Adhesive layer 17, 27, 47 Glass substrate 18, 28, 48 Primary coil pattern 19, 29 Secondary protective film R1-R3, R11-R15 Resist pattern H1, 13a, H11-H13, 23a Opening 14a, 18a, 24a, 28a Conductive film 30 Recess 31 Bonding surface 14 ', 24', 43 Wiring pattern 46 Projecting electrode

Claims (4)

A semiconductor substrate in which one of the primary winding and the secondary winding is formed on one surface;
A glass substrate or a ceramic substrate in which the other of the primary winding and the secondary winding is formed on one surface;
A protective film formed on one of the primary winding and the secondary winding formed on the one surface of the semiconductor substrate and having a planarized surface;
An insulating transformer comprising: an adhesive film that fixes the surface of the protective film and the other surface of the glass substrate or the ceramic substrate . The isolation transformer according to claim 1 Symbol placement of the isolation transformer, characterized in that it is formed by microfabrication techniques. The insulating transformer according to claim 1 or 2, wherein a material of the glass substrate is an alkali-free component. A pair of switching elements connected in series so as to operate for the upper arm and the lower arm, respectively, for energizing and interrupting the current flowing into the load;
A control circuit for generating a control signal instructing conduction and non-conduction of the switching element;
A drive circuit for driving a control terminal of the switching element based on the control signal;
An insulation transformer in which a primary winding and a secondary winding are arranged to face each other so that the control circuit and the drive circuit are insulated ;
The insulating transformer is
A semiconductor substrate in which one of the primary winding and the secondary winding is formed on one surface;
A glass substrate or a ceramic substrate in which the other of the primary winding and the secondary winding is formed on one surface;
A protective film formed on one of the primary winding and the secondary winding formed on the one surface of the semiconductor substrate and having a planarized surface;
A power conversion device comprising: an adhesive film that fixes the surface of the protective film and the other surface of the glass substrate or the ceramic substrate .

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