JP4893559B2 - Power supply voltage detection circuit - Google Patents

Description

  The present invention relates to a power supply voltage detection circuit mounted on a semiconductor device.

  The power supply voltage detection circuit outputs a power supply voltage detection signal when the power supply voltage reaches the power supply voltage detection level after the power is turned on, or outputs a power supply voltage detection signal only during a period when the power supply voltage is equal to or higher than the power supply voltage detection level. This circuit is widely mounted in semiconductor devices in order to prevent malfunction due to a low power supply voltage.

  FIG. 5 is a circuit diagram of an example of a conventional power supply voltage detection circuit. In FIG. 5, 1 is a power supply voltage detection unit, and 2 is a power supply voltage detection signal generation unit. The power supply voltage detection unit 1 detects that the power supply voltage VDD has exceeded the power supply voltage detection level after the power is turned on. When the power supply voltage detection unit 1 detects that the power supply voltage VDD exceeds the power supply voltage detection level, the power supply voltage detection signal generation unit 2 generates and outputs a power supply voltage detection signal PD having a high level.

  In the power supply voltage detector 1, 3 to 6 are power supply voltage terminals to which a power supply voltage VDD is applied, 7 to 9 are ground voltage terminals to which a ground voltage of 0 V is applied, and 10 and 11 are P-channel insulated gate field effect transistors. Certain P-channel MOS transistors (hereinafter referred to as PMOS transistors) and 12 to 15 are N-channel MOS transistors (hereinafter referred to as NMOS transistors) which are N-channel insulated gate field effect transistors.

  The PMOS transistor 10 has a source connected to the power supply voltage terminal 3, a gate connected to the ground voltage terminal 7, and a drain connected to the node N1, and functions as a resistance element. The NMOS transistor 12 has a drain connected to the node N1 and a gate connected to the power supply voltage terminal 4, and functions as a resistance element.

  The NMOS transistor 13 has a drain connected to the source of the NMOS transistor 12, a gate connected to the node N2, and a source connected to the ground voltage terminal 8, and functions as a switch element. Note that the on-resistance value of the PMOS transistor 10 is larger than the combined on-resistance value of the NMOS transistors 12 and 13.

  The PMOS transistor 11 has a source connected to the power supply voltage terminal 5 and a gate connected to the drain. The NMOS transistor 14 has a drain connected to the drain of the PMOS transistor 11, a gate connected to the power supply voltage terminal 6, and a source connected to the node N2. The NMOS transistor 15 has a drain and a gate connected to the node N2, and a source connected to the ground voltage terminal 9.

  In the power supply voltage detection signal generating unit 2, reference numerals 16 and 17 denote power supply voltage terminals, 18 denotes a ground voltage terminal, 19 denotes a power supply voltage detection signal output terminal, 20, 21 and 22 denote inverters, 23 and 24 denote PMOS transistors, 25 Is an NMOS transistor.

  Inverters 20, 21, and 22 are connected in cascade between node N 1 and power supply voltage detection signal output terminal 19. The PMOS transistor 23 has a gate connected to the input terminal of the inverter 20, a drain and a source connected to the power supply voltage terminal 16, and functions as a capacitor.

  The PMOS transistor 24 has a gate connected to the input terminal of the inverter 22 and a drain and a source connected to the power supply voltage terminal 17 and functions as a capacitor. The NMOS transistor 25 has a gate connected to the input terminal of the inverter 21 and a drain and a source connected to the ground voltage terminal 18 and functions as a capacitor.

  In this example, the PMOS transistor 11 and the NMOS transistors 14 and 15 constitute a power supply voltage follow-up voltage generation circuit, and the PMOS transistor 10, the NMOS transistors 12 and 13 and the power supply voltage detection signal generation unit 2 constitute a threshold circuit. ing.

  The NMOS transistor 26 draws out charges until the voltage at the node N2 drops to the threshold voltage of the NMOS transistor 26 when the power is turned off. The drain is connected to the power supply voltage terminal 27, and the gate and source are connected. Connected to node N2.

  In the conventional power supply voltage detection circuit configured as described above, when the power is turned on and the power supply voltage VDD starts to rise, a current flows through the PMOS transistor 11 and the NMOS transistors 14 and 15. In this case, the voltage at the node N2 is lower than the power supply voltage VDD, but rises following the power supply voltage VDD.

  In this case, the PMOS transistor 10 is also in a conductive state, but current flows through the NMOS transistor 13 while the voltage at the node N2 does not exceed the threshold voltage of the NMOS transistor 13 and the NMOS transistor 13 is in a non-conductive state. During this period, the voltage at the node N1 is substantially the same as the power supply voltage VDD, and the voltage at the power supply voltage detection signal output terminal 19 remains at the ground voltage.

  Thereafter, when the power supply voltage VDD further rises and the voltage at the node N2 exceeds the threshold voltage of the NMOS transistor 13, the NMOS transistor 13 becomes conductive, and the charge from the power supply voltage terminal 3 to the node N1 via the PMOS transistor 10 is made. Supply and charge discharge from the node N1 to the ground voltage terminal 8 through the NMOS transistors 12 and 13 occur simultaneously.

In this case, since the on-resistance value of the PMOS transistor 10 is larger than the combined on-resistance value of the NMOS transistors 12 and 13, the voltage at the node N1 decreases toward the ground voltage. As a result, the voltage of the power supply voltage detection signal output terminal 19 becomes the same as the power supply voltage VDD, and the power supply voltage detection signal PD having a high level is output.
JP 2002-109883 A

  FIG. 6 is a diagram for explaining the problems of the conventional power supply voltage detection circuit shown in FIG. 5, and shows the voltage change of the power supply voltage VDD and the voltage change of the node N1 after the power is turned on. In FIG. 6, 28 is a change in the power supply voltage VDD, 29 is a voltage change at the node N2, 30A is a voltage change at the node N1 when the operating temperature is high, and 30B is a voltage change at the node N1 when the operating temperature is low. Yes.

  In the conventional power supply voltage detection circuit shown in FIG. 5, the level of the power supply voltage VDD when the voltage of the node N2 reaches the threshold voltage of the NMOS transistor 13 becomes the power supply voltage detection level. , Changes depending on the operating temperature, lower at higher temperatures and higher at lower temperatures. On the other hand, the level of the node N2 is determined by the ratio between the combined on-resistance value of the PMOS transistor 11 and the NMOS transistor 14 and the on-resistance value of the NMOS transistor 15, so that the change due to temperature is small.

  As described above, the threshold voltage of the NMOS transistor 13 varies depending on the operating temperature. The threshold voltage decreases as the temperature increases and increases as the temperature decreases. However, since the voltage at the node N2 varies little with temperature, the power supply voltage detection level is shown in FIG. Thus, it is lower at high temperatures and higher at low temperatures, and has temperature dependence.

  However, it is desirable that the power supply voltage detection level does not have temperature dependence and is not affected by temperature changes. This is because if the power supply voltage detection level is temperature-dependent, the power supply voltage detection level must be set low so that it can operate reliably at the guaranteed operating voltage. Because it will fade.

  In view of this point, the present invention can prevent the power supply voltage detection level from being affected by temperature changes. When this is mounted on a semiconductor device, the power supply voltage detection level is set to the operation guarantee voltage of the semiconductor device. It is an object of the present invention to provide a power supply voltage detection circuit that can be set to a value close to 1 and can realize a stable operation of a semiconductor device.

  A power supply voltage detection circuit disclosed in the present application includes a power supply voltage tracking voltage generation circuit that generates a voltage that follows the power supply voltage, and an output voltage of the power supply voltage tracking voltage generation circuit, and the output voltage exceeds a threshold voltage. And a threshold voltage circuit that outputs a power supply voltage detection signal, wherein the power supply voltage follow-up voltage generation circuit has a temperature-to-output voltage characteristic that cancels a temperature change of the threshold voltage.

  According to the disclosed power supply voltage detection circuit, the power supply voltage follow-up voltage generation circuit has a temperature-to-output voltage characteristic that cancels out the temperature change of the threshold voltage of the threshold circuit, so that the power supply voltage detection level is affected by the temperature change. It can be made not to receive. Therefore, when the present invention is mounted on a semiconductor device, the power supply voltage detection level can be set to a value close to the operation guarantee voltage of the semiconductor device, and a stable operation of the semiconductor device can be realized.

(First embodiment)
FIG. 1 is a circuit diagram of a first embodiment of the present invention. The first embodiment of the present invention includes a power supply voltage detection unit 31 having a circuit configuration different from that of the power supply voltage detection unit 1 included in the conventional power supply voltage detection circuit shown in FIG. The power supply voltage detection circuit of FIG.

  The power supply voltage detector 31 provided in the first embodiment of the present invention is a paraelectric capacitor 32 and a ferroelectric capacitor instead of the PMOS transistor 11 and the NMOS transistors 14 and 15 provided in the power supply voltage detector 1 shown in FIG. The other components are the same as those of the power supply voltage detector 1 shown in FIG.

  The paraelectric capacitor 32 is configured by sandwiching a paraelectric film between metal electrodes, and the first electrode is connected to the power supply voltage terminal 5 and the second electrode is connected to the node N2. The ferroelectric capacitor 33 is configured by sandwiching a ferroelectric film between metal electrodes, and the first electrode is connected to the node N2, and the second electrode is connected to the ground voltage terminal 9.

  In the first embodiment of the present invention, a paraelectric capacitor 32 and a ferroelectric capacitor 33 constitute a power supply voltage follow-up voltage generation circuit, and a PMOS transistor 10, NMOS transistors 12 and 13, and a power supply voltage detection signal generator 2. A threshold circuit is configured.

  2A and 2B are diagrams showing the interelectrode voltage-polarization amount characteristics of the ferroelectric capacitor 33. FIG. 2A shows a case at a low temperature, and FIG. 2B shows a case at a high temperature. The ferroelectric capacitor 33 has a hysteresis characteristic as shown in FIG. 2, but in this embodiment, a characteristic part (non-inversion characteristic part) indicated by thick arrows Q1 and Q2 is used.

  That is, the ratio of the change in the polarization amount to the change in the interelectrode voltage corresponds to the capacitance of the ferroelectric capacitor 33, but the capacitance of the ferroelectric capacitor 33 tends to increase as the temperature increases and decreases as the temperature decreases. Thus, the first embodiment of the present invention uses this characteristic of the ferroelectric capacitor 33.

  In the first embodiment of the present invention thus configured, when the capacitance of the paraelectric capacitor 32 is C32 and the capacitance of the ferroelectric capacitor 33 is C33, the power is turned on and the power supply voltage VDD starts to rise. Then, the voltage of the node N2 is {C32 / (C32 + C33)} × VDD, which is lower than the power supply voltage VDD, but increases following the power supply voltage VDD.

  In this case, the PMOS transistor 10 is also in a conductive state, but current flows through the NMOS transistor 13 while the voltage at the node N2 does not exceed the threshold voltage of the NMOS transistor 13 and the NMOS transistor 13 is in a non-conductive state. During this period, the voltage at the node N1 is substantially the same as the power supply voltage VDD, and the voltage at the power supply voltage detection signal output terminal 19 remains at the ground voltage.

  Thereafter, when the power supply voltage VDD further rises and the voltage at the node N2 exceeds the threshold voltage of the NMOS transistor 13, the NMOS transistor 13 becomes conductive, and the charge from the power supply voltage terminal 3 to the node N1 via the PMOS transistor 10 is made. Supply and charge discharge from the node N1 to the ground voltage terminal 8 through the NMOS transistors 12 and 13 occur simultaneously.

  In this case, since the on-resistance value of the PMOS transistor 10 is larger than the combined on-resistance value of the NMOS transistors 12 and 13, the voltage at the node N1 decreases toward the ground voltage. As a result, the voltage of the power supply voltage detection signal output terminal 19 becomes the same as the power supply voltage VDD, and the power supply voltage detection signal PD having a high level is output.

  In the first embodiment of the present invention, when the power is turned on and the power supply voltage VDD starts to rise, the voltage at the node N2 becomes {C32 / (C32 + C33)} × VDD as described above. The capacitance C33 of the body capacitor 33 increases as the temperature increases and decreases as the temperature decreases.

  That is, when the temperature is high, the threshold voltage of the NMOS transistor 13 decreases, but the voltage at the node N2 when the power supply voltage VDD rises to the power supply voltage detection level increases the capacitance C33 of the ferroelectric capacitor 33. Lower by minutes.

  On the other hand, when the temperature is low, the threshold voltage of the NMOS transistor 13 is high, but the voltage at the node N2 when the power supply voltage VDD rises to the power supply voltage detection level is the capacitance C33 of the ferroelectric capacitor 33. It becomes higher by the smaller.

  Therefore, by setting the capacitance ratio of the paraelectric capacitor 32 and the ferroelectric capacitor 33 to a suitable value, the power supply voltage VDD rises to the power supply voltage detection level regardless of the temperature change within the guaranteed operating temperature range. In this case, the voltage of the node N2 can be set to the same voltage as the threshold voltage of the NMOS transistor 13.

  As described above, according to the first embodiment of the present invention, the threshold voltage of the NMOS transistor 13 (that is, the PMOS transistor 10 and the NMOS transistor) is added to the power supply voltage follow-up voltage generation circuit including the paraelectric capacitor 32 and the ferroelectric capacitor 33. A temperature-output voltage characteristic that cancels the temperature change of the threshold voltage of the threshold circuit including the transistors 12 and 13 and the power supply voltage detection signal generator 2 can be provided.

  Therefore, when the first embodiment of the present invention is mounted on a semiconductor device, the power supply voltage detection level can be set to a value close to the operation guarantee voltage of the semiconductor device, thereby realizing stable operation of the semiconductor device. be able to.

(Second Embodiment)
FIG. 3 is a circuit diagram of a second embodiment of the present invention. The second embodiment of the present invention is provided with a power supply voltage detection unit 34 having a circuit configuration different from that of the power supply voltage detection unit 31 provided in the first embodiment of the present invention shown in FIG. The configuration is the same as in the first embodiment of the present invention.

  The power supply voltage detection unit 34 included in the second embodiment of the present invention includes four NMOS transistors 35-1 to 35-4 instead of the NMOS transistor 13 included in the power supply voltage detection unit 31 illustrated in FIG. 1. The other configuration is the same as that of the power supply voltage detection unit 31 shown in FIG.

  The NMOS transistors 35-1 to 35-4 are connected in multiple stages (totem pole connection), the drain of the uppermost NMOS transistor 35-1 is connected to the source of the NMOS transistor 12, and the source of the lowermost NMOS transistor 35-4. Is connected to the ground voltage terminal 8, and the gates of the NMOS transistors 35-1 to 35-4 are connected to the node N2.

  In the second embodiment of the present invention, the on-resistance value of the PMOS transistor 10 is higher than the combined on-resistance value of the NMOS transistors 12 and 35-1 to 35-4. In the second embodiment of the present invention, the paraelectric capacitor 32 and the ferroelectric capacitor 33 constitute a power supply voltage follow-up voltage generation circuit. The PMOS transistor 10 and the NMOS transistors 12, 35-1 to 35-4, The power supply voltage detection signal generation unit 2 constitutes a threshold circuit.

  In the second embodiment of the present invention configured as described above, when the power is turned on and the power supply voltage VDD starts to rise, the voltage at the node N2 becomes {C32 / (C32 + C33)} × VDD, and the power supply voltage VDD Although it is lower, it rises following the power supply voltage VDD.

  In this case, the PMOS transistor 10 is also conductive, but the voltage at the node N2 is lower than the threshold voltage of the NMOS transistors 35-1 to 35-4, and the NMOS transistors 35-1 to 35-4 are nonconductive. During this period, no current flows through the NMOS transistors 35-1 to 35-4, so that during this period, the voltage at the node N 1 is substantially the power supply voltage VDD, and the voltage at the power supply voltage detection signal output terminal 19 is equal to the ground voltage. It remains.

  Thereafter, when the power supply voltage VDD further rises and the voltage at the node N2 exceeds the threshold voltage of the NMOS transistors 35-1 to 35-4, the NMOS transistors 35-1 to 35-4 are turned on, and the power supply voltage terminal 3 The charge supply to the node N1 through the PMOS transistor 10 and the discharge of the charge from the node N1 to the ground voltage terminal 8 through the NMOS transistors 12, 35-1 to 35-4 occur simultaneously.

  In this case, the voltage of the node N1 decreases toward the ground voltage because the on-resistance value of the PMOS transistor 10 is larger than the combined on-resistance value of the NMOS transistors 12, 35-1 to 35-4. As a result, the voltage of the power supply voltage detection signal output terminal 19 becomes the same as the power supply voltage VDD, and the power supply voltage detection signal PD having a high level is output.

  Here, also in the second embodiment of the present invention, by setting the capacitance ratio between the paraelectric capacitor 32 and the ferroelectric capacitor 33 to a suitable value, the temperature is within the guaranteed operating range, regardless of the temperature change. The voltage at the node N2 when the power supply voltage VDD rises to the power supply voltage detection level can be made equal to the threshold voltage of the NMOS transistors 35-1 to 35-4.

  As described above, according to the second embodiment of the present invention, the threshold voltage of the NMOS transistors 35-1 to 35-4 (that is, the threshold voltage (ie, Further, it is possible to have a temperature-output voltage characteristic that cancels the temperature change of the threshold voltage of the threshold voltage circuit including the PMOS transistor 10, the NMOS transistors 12, 35-1 to 35-4, and the power supply voltage detection signal generator 2.

  Therefore, when the second embodiment of the present invention is mounted on a semiconductor device, the power supply voltage detection level can be set to a value close to the operation guarantee voltage of the semiconductor device, thereby realizing a stable operation of the semiconductor device. be able to.

  In the second embodiment of the present invention, if the threshold voltage of any of the NMOS transistors 35-1 to 35-4 is out of the expected value due to, for example, a manufacturing process, for example, the NMOS transistor When the threshold value 35-2 deviates from the expected value, the NMOS transistor 35-1 and the drain of the NMOS transistor 35-3 are short-circuited by a jumper line 36 as shown in FIG. The transistor 35-2 can be unused.

  That is, according to the first embodiment of the present invention shown in FIG. 1, when the threshold voltage of the NMOS transistor 13 deviates from the expected value, the first embodiment of the present invention itself becomes defective. According to the second embodiment, out of the NMOS transistors 35-1 to 35-4, even if the threshold voltages of up to three NMOS transistors deviate from the expected values, the NMOS transistors deviating from the expected values are not considered. By using it, the second embodiment of the present invention can be normally operated as a power supply voltage detection circuit, so that the yield can be higher than that of the first embodiment of the present invention.

  In the second embodiment of the present invention, the case where four NMOS transistors 35-1 to 35-4 are connected in multiple stages (totem pole connection) has been described. However, the number of NMOS transistors connected in multiple stages is four. The number is not limited and can be any number.

  In the first and second embodiments of the present invention, the case where the ferroelectric capacitor 33 is provided has been described. Instead, the ferroelectric capacitor 33 is made of a pyroelectric material such as lithium titanate. An element may be provided.

It is a circuit diagram of a 1st embodiment of the present invention. It is a figure which shows the voltage-polarization amount characteristic between electrodes of the ferroelectric capacitor with which 1st Embodiment of this invention is provided. It is a circuit diagram of a 2nd embodiment of the present invention. It is a circuit diagram for demonstrating the peculiar effect which 2nd Embodiment of this invention has. It is a circuit diagram of an example of the conventional power supply voltage detection circuit. It is a figure for demonstrating the problem which the conventional power supply voltage detection circuit shown in FIG. 5 has.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Power supply voltage detection part 2 ... Power supply voltage detection signal generation part 3-6 ... Power supply voltage terminal 7-9 ... Ground voltage terminal 10, 11 ... PMOS transistor 12-15 ... NMOS transistor 16, 17 ... Power supply voltage terminal 18 ... Ground Voltage terminal 19 ... Power supply voltage detection signal output terminal 20-22 ... Inverter 23, 24 ... PMOS transistor 25, 26 ... NMOS transistor 27 ... Power supply voltage terminal 31 ... Power supply voltage detection unit 32 ... Paraelectric capacitor 33 ... Ferroelectric capacitor 34 ... Power supply voltage detector 35-1 to 35-4 ... NMOS transistor 36 ... Jumper wire

Claims (2)

A power supply voltage follow-up voltage generation circuit that generates a voltage that follows the power supply voltage;
A threshold circuit for inputting an output voltage of the power supply voltage tracking voltage generation circuit and outputting a power supply voltage detection signal when the output voltage exceeds a threshold voltage ;
Said power supply voltage track-voltage generating circuit, a temperature versus output voltage characteristic of lifting Tsu supply voltage detection circuit to cancel the temperature change of the threshold voltage,
The threshold circuit includes:
A first resistance element having one end connected to a power supply voltage terminal and the other end connected to a first node;
A second resistance element having one end connected to the first node;
An N-channel insulated gate field effect transistor having a drain connected to the other end of the second resistive element, a gate connected to the second node, and a source connected to the ground voltage terminal;
A power supply voltage detection signal generation unit that inputs the voltage of the first node and generates the power supply voltage detection signal;
The power supply voltage follow-up voltage generation circuit includes:
A paraelectric capacitor having a first electrode connected to the power supply voltage terminal and a second electrode connected to the second node;
A first electrode connected to said second node, to that supply voltage detecting circuit; and a ferroelectric capacitor connected to the second electrode to the ground voltage terminal. The first resistance element is a P-channel insulated gate field effect transistor having a source connected to the power supply voltage terminal, a gate connected to the ground voltage terminal, and a drain connected to the first node,
The second resistive element has an N-channel insulated gate field effect transistor having a drain connected to the first node, a gate connected to the power supply voltage terminal, and a source connected to the other end of the second resistive element. The power supply voltage detection circuit according to claim 1 , wherein:

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