JP2012107982A - Power supply voltage determination circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply voltage determination circuit with which the current consumption is suppressed.SOLUTION: A power supply voltage determination circuit 50 is provided between a high power source VDD and a reference power source VSS and has a first partial pressure circuit 51 in which a capacity element Cfe51 with voltage dependency that the capacity changes according to voltage applied and a capacity element Cdp51 without voltage dependency are connected in serial manner, a second partial pressure circuit 52 which is connected to the first partial pressure circuit 51 in parallel manner, and a comparator 53 for making comparison of the partial pressure P51 between the capacity elements of the first partial pressure circuit 51 with the partial pressure P52 of the second partial pressure circuit 52.

Description

  The present invention relates to a power supply voltage determination circuit.

  In recent LSIs, a system-on-chip (System On Chip) is being developed in which a CPU, digital circuit, analog circuit, memory, and the like are mounted on one chip to constitute a system. Recently, there are small memory cards and ink cartridge ICs that can be attached to and detached from the connection interface provided in the LSI body.

  By the way, if the power supply voltage supplied to the LSI from an external power supply is lowered to a voltage below the LSI operation specification standard, the LSI may malfunction. Therefore, the LSI accurately determines (detects) that the power supply voltage has fallen to a voltage lower than the operation specification standard, and executes an operation restriction such as chip reset when the power supply voltage drops to a voltage lower than the operation specification standard. It is necessary to provide a fail-safe function. Here, the voltage of the operation specification standard is, for example, 1.8V to 3.0V.

  As a method of determining that the power supply voltage has dropped to a voltage below the operating specification standard, the fact that the divided voltage of the voltage dividing circuit in which the resistance elements are connected in series is below the reference voltage corresponding to the voltage outside the operating range is indicated. There is a method of outputting the signal shown.

Japanese Patent Laid-Open No. 2005-24502

  However, since this determination method uses a resistor in the voltage dividing circuit, a current path through which a current always flows is formed in the resistor of the voltage dividing circuit, resulting in an increase in current consumption.

  Therefore, an object of the present invention is to provide a power supply voltage determination circuit that suppresses current consumption.

A first aspect of the power supply voltage determination circuit is provided between the high power supply VDD and the reference power supply VSS, and has a capacitor element having a voltage dependency characteristic whose capacitance changes according to the applied voltage and a capacitor not having the voltage dependency characteristic. A first voltage dividing circuit connected in series with the element;
A second voltage dividing circuit provided between the high power supply VDD and the reference power supply VSS and connected in parallel to the first voltage dividing circuit;
A comparator for comparing a divided voltage between the capacitive elements in the first voltage dividing circuit with a divided voltage of the second voltage dividing circuit;

  According to the first aspect, the current consumption of the power supply voltage determination circuit can be suppressed.

It is a figure explaining LSI which has a power supply voltage determination circuit relevant to this Embodiment. It is a figure which shows an example of a power supply voltage determination circuit. It is a figure explaining operation | movement of the power supply voltage determination circuit of FIG. It is a figure which shows the other example of a power supply voltage determination circuit. It is a figure explaining the power supply voltage determination circuit of 1st Embodiment. It is a figure explaining operation | movement of the power supply voltage determination circuit of FIG. It is a graph explaining the voltage dependence characteristic of a ferroelectric capacitor element and a paraelectric capacitor element. It is a figure which shows the 1st, 2nd voltage dividing circuit. It is a circuit diagram of a power supply voltage determination circuit, a bias circuit, and a buffer. It is a figure explaining the power supply voltage determination circuit of 2nd Embodiment. It is a figure explaining operation | movement of the power supply voltage determination circuit of FIG. It is a figure explaining the power supply voltage determination circuit of 3rd Embodiment. It is a figure explaining operation | movement of the power supply voltage determination circuit of FIG.

  FIG. 1 is a diagram illustrating an LSI having a power supply voltage determination circuit related to the present embodiment. The LSI 10 has a fail-safe function that determines with high accuracy that the power supply voltage has dropped to a voltage lower than the operation specification standard, and restricts the operation under a low voltage.

  The LSI 10 performs a power supply voltage determination circuit 11 that determines that the power supply voltage VDD input from the terminal VDD of the terminal T has decreased to a voltage that is less than or equal to the operation specification standard, and various processes such as image processing, transfer processing, and encryption processing. A processing circuit 12 to be executed, a memory 13, a power supply voltage determination circuit 11, a processing circuit 12, and a control circuit 14 for controlling the memory 13 are included. The processing circuit 12 includes an analog circuit. The power supply voltage determination circuit 11, the processing circuit 12, the memory 13, and the control circuit 14 are connected to a terminal VSS that is a ground terminal.

  When the power supply voltage VDD drops to a voltage below the operation specification standard, the power supply voltage determination circuit 11 outputs, for example, a low level signal VDET indicating that to the control circuit 14. The reason why the power supply voltage VDD decreases to a voltage lower than the operation specification standard is as follows. For example, the required power of the LSI 10, that is, the load on the LSI 10 becomes heavy, and the power supply cannot supply enough power to satisfy the required power. As a result, the power supply voltage VDD decreases. In addition, the internal power supply voltage VDD decreases due to poor connection between the external power supply and the terminal VDD. In addition, when the IC that controls the power supply has a specification that performs control to turn on and off the power supply, the power supply voltage VDD is lowered by turning off the power supply of the IC. Further, the operation of the power supply becomes unstable due to external noise, and the power supply voltage VDD decreases. Note that, for various other reasons, the power supply voltage VDD is lowered to a voltage lower than the operation specification standard.

  The control circuit 14 executes fail-safe processing in response to a low level signal VDET indicating that the power supply voltage VDD has dropped to a voltage equal to or lower than the operation specification standard. For example, the LSI is reset. A signal Ctr1 for notifying that the power supply voltage VDD decreases and the operation state of the LSI 10 becomes unstable is output to a host device (not shown) at an external connection destination. Note that the host device is connected to the LSI 10 via a terminal T. Further, since the control circuit 14 performs power management, it increases the frequency division ratio of the internal clock to reduce the operating current. When the processing circuit 12 is a circuit with high power consumption, for example, an encryption circuit, the control circuit 14 outputs a signal Ctr2 instructing to stop the processing to the processing circuit 12. The control circuit 14 limits the number of accesses to the memory 13.

  In order to enable such operation control (fail safe) of the control circuit 14, the power supply voltage determination circuit 11 must determine with high accuracy that the power supply voltage VDD has dropped to a voltage equal to or lower than the operation specification standard.

  Next, the power supply voltage determination circuit 11 will be described with reference to FIGS.

  FIG. 2 is a diagram illustrating an example of the power supply voltage determination circuit 11. 2 includes a BGR (Band Gap Reference) circuit 21 that outputs a reference voltage VREF, a voltage dividing circuit 22 that divides the power supply voltage VDD and outputs a divided voltage LVR, and a reference voltage VREF. A comparator 23 that compares the divided voltage LVR and outputs a signal VDET, and a bias circuit 24 that supplies a bias voltage Vbias to the BGR 21 and the comparator 23 are provided. The reference voltage VREF is input to the inverting input terminal (− terminal) of the comparator 23, and the divided voltage LVR is input to the non-inverting input terminal (+ terminal).

  FIG. 3 is a diagram for explaining the operation of the power supply voltage determination circuit 20. When the divided voltage LVR is higher than the reference voltage VREF, the comparator 23 outputs a high level signal VDET. Here, when the power supply voltage VDD decreases, the divided voltage LVR also decreases as the power supply voltage VDD decreases. When the divided voltage LVR becomes equal to or lower than the reference voltage VREF, the comparator 23 lowers the signal VDET and outputs a low level signal VDET to the control circuit 14 in FIG. This low level signal VDET indicates that the power supply voltage VDD has dropped to a voltage below the operating specification standard.

  By using the BGR circuit 21 that generates the reference voltage VREF, the power supply voltage determination circuit 20 is resistant to process variations and temperature dependence in the manufacturing process of the semiconductor device, and the power supply voltage VDD is reduced to a voltage below the operation specification standard. It can be determined with high accuracy. However, the circuit scale of the BGR circuit 21 is large, the chip size is increased, and the cost is increased. Further, since a voltage dividing circuit having a series resistance is provided between the power supply VDD and the power supply VSS (ground), a current path through which a current always flows is formed in the series resistance, and the operating current (consumption) of the power supply voltage determination circuit 20 Current) becomes large.

  FIG. 4 is a diagram for explaining another example of the power supply voltage determination circuit 11. The power supply voltage determination circuit 40 in FIG. 4 includes a voltage dividing circuit 41 formed of a series resistor that inputs the divided voltage LVR2 of the power supply voltage VDD to the gates of the transistors Tr43 to Tr45, and a voltage at a connection point N41 between the transistor Tr42 and the transistor Tr43. An inverter (INV) 46 for inverting the level and a buffer (BUF) 47 are provided. The transistor Tr42 is a PMOS transistor, and the transistors Tr43 to Tr45 are NMOS transistors. The reason why the transistors Tr43 to Tr45 are connected in series is to increase the threshold voltage Vth of the transistor Tr43. This threshold voltage Vth corresponds to the reference voltage.

  The operation of the power supply voltage determination circuit 40 will be described. Since the power supply voltage VDD is applied to the source of the PMOS transistor Tr42 and the power supply voltage VSS (ground) is applied to the gate, the transistor Tr42 is on. When the power supply voltage VDD is at an appropriate potential, the divided voltage LVR2 becomes higher than the threshold voltage Vth of the transistor Tr43, and the transistors Tr43 to Tr45 are turned on. Therefore, the voltage at the node N41 becomes the power supply voltage VSS (ground), and the high level signal VDET is output by the inverter 46. When the power supply voltage VDD decreases and the divided voltage LVR2 becomes lower than the threshold voltage Vth of the transistor Tr43, the transistors Tr43 to Tr45 are turned off. Therefore, the voltage at the connection point N41 becomes the power supply voltage VDD, and the inverter 46 outputs the low level signal VDET.

  The power supply voltage determination circuit 40 has only a transistor, a resistor, an inverter, and a buffer. The circuit configuration is simpler than that of the power supply voltage determination circuit 20 in FIG. 2, and the cost can be reduced by reducing the number of elements (reducing process steps). It is a circuit that can be expected. However, it is weak to variations in the manufacturing process of NMOS transistors and temperature dependence, and it cannot be determined with high accuracy that the power supply voltage VDD has dropped to a voltage below the operating specification standard. Further, the current during operation of the power supply voltage determination circuit 40 increases due to the current path by the voltage dividing circuit 41 and the through current due to the PMOS transistor Tr42 and the NMOS transistors Tr43 to Tr45 being simultaneously turned on.

  As described above, according to the power supply voltage determination circuit 20 of FIG. 2, it can be determined with high accuracy that the power supply voltage has dropped to a voltage lower than the operation specification standard, but the circuit scale increases and the current of the voltage divider circuit increases. There is a problem that power consumption increases due to the path. Further, according to the power supply voltage determination circuit 40 of FIG. 4, although the circuit scale is reduced, it cannot be determined with high accuracy that the power supply voltage has dropped to a voltage lower than the operation specification standard. There is a problem that the power consumption increases due to the through current. Therefore, a power supply voltage determination circuit that solves the above problems is provided.

(First embodiment)
FIG. 5 is a diagram illustrating the power supply voltage determination circuit according to the first embodiment. The power supply voltage determination circuit 50 includes a first voltage dividing circuit 51, a second voltage dividing circuit 52 connected in parallel to the first voltage dividing circuit 51, and a voltage dividing point N51 of the first voltage dividing circuit 51. The comparator 53 compares the voltage P51 with the divided voltage P52 at the connection point N52 of the second voltage dividing circuit 52.

  The first voltage dividing circuit 51 is provided between the high power supply VDD and the reference power supply VSS, and is a first capacitive element having a voltage-dependent characteristic whose capacitance changes according to the applied voltage. For example, a ferroelectric capacitive element In this configuration, Cfe51 is connected in series with, for example, a paraelectric capacitor Cdp51, which is a second capacitor having no voltage-dependent characteristics. The ferroelectric capacitor element Cfe51 is connected to the high power supply VDD side, and the paraelectric capacitor element Cdp51 is connected to the reference power supply VSS side.

  The second voltage dividing circuit 52 is provided between the high power supply VDD and the reference power supply VSS, and is a third capacitor element having no voltage dependency characteristics, for example, a paraelectric capacitor element Cdp52 and a first capacitor having voltage dependency characteristics. 4 is a configuration in which a ferroelectric capacitor Cfe52, which is a capacitor of No. 4, is connected in series. The paraelectric capacitor Cdp52 is connected to the high power supply VDD side, and the ferroelectric capacitor Cfe52 is connected to the reference power supply VSS side.

  The comparator 53 compares the voltage P51 input to the inverting input terminal (− terminal) with the voltage P52 input to the non-inverting input terminal (+ terminal). When the voltage P52 is higher than the voltage P51, the comparator 53 outputs a high level signal VDET. When the voltage P52 is lower than the voltage P51, the comparator 53 outputs a low level signal VDET. The signal VDET may be buffered by a buffer circuit described with reference to FIG.

  The bias circuit 54 supplies a bias voltage Vbias to the comparator 53, and includes a PMOS transistor Tr54 and a resistor R54. The source of the transistor Tr54 is connected to the high power supply VDD, and the drain is connected to one end of the resistor R54. The other end of the resistor R54 is connected to the reference power supply VSS.

  In the power supply voltage determination circuit 50 of FIG. 5, the voltage at which the divided voltage P51 of the first voltage dividing circuit 51 is equal to the divided voltage P52 of the second voltage dividing circuit 52 is the reference voltage VREF described in FIG. The parameters of the ferroelectric capacitor element Cfe51, the paraelectric capacitor element Cdp51, the paraelectric capacitor element Cdp52, and the ferroelectric capacitor element Cfe52 are determined. When the divided voltage P51 becomes equal to the divided voltage P52, the signal VDET indicating that the power supply voltage VDD has fallen to a non-standard voltage is output. The voltage at which the divided voltage P51 and the divided voltage P52 are equal corresponds to the reference voltage VREF generated by the BGR circuit 21 of FIG.

  FIG. 6 is a diagram for explaining the operation of the power supply voltage determination circuit 50. The power supply voltage VDD, the divided voltage P51 of the first voltage dividing circuit 51, the divided voltage P52 of the second voltage dividing circuit 52, 6 is a graph showing a signal VDET of the comparator 53. The graph of FIG. 6 shows how the power supply voltage VDD decreases and the voltages P51 and P52 decrease.

  As shown in FIG. 6, between time T0 and T1, when the voltage VDD decreases, the voltage P51 and the voltage P52 gradually decrease. However, the decrease rate of the power supply voltage VDD (voltage decrease amount per unit time) is different from the decrease rate of the voltage P51 and the decrease rate of the voltage P52. After the time T1, the rate of decrease of the voltage P52 becomes larger than the rate of decrease of the voltage P51. That is, when the voltage VDD decreases, the voltage P52 rapidly decreases, but the voltage P51 does not decrease rapidly. In other words, the voltage change amount (dv / dt) per unit time of the voltage P51 is different from the voltage change amount per unit time of the voltage P52. As a result, at time T2, the voltage P51 and the voltage P52 intersect (cross). The voltage Vc at the time of crossing at time T2 corresponds to the reference voltage VREF described above. Further, the voltage below the power supply voltage VDD0 after this time T2 corresponds to the voltage below the operation specification standard.

  As described above, the parameters of the ferroelectric capacitor Cfe51, the paraelectric capacitor Cdp51, the paraelectric capacitor Cdp52, and the ferroelectric capacitor Cfe52 are determined so that the voltage Vc at the time of crossing becomes the reference voltage VREF. ing.

  From time T0 to time T2, since voltage P52> voltage P51, the comparator 53 outputs a high level signal VDET. When the voltage P52 <the voltage P51 (when the time T2 is reached), the comparator 53 causes the high level signal to fall and outputs the low level signal VDET. This low level signal VDET is a signal indicating that the power supply voltage VDD has dropped to a voltage below the operating specification standard.

  Next, the reason why the voltage change amount (dv / dt) per unit time of the voltage P51 and the voltage change amount per unit time of the voltage P52 are different will be described with reference to FIGS.

  FIG. 7 is a graph for explaining the voltage dependence characteristics of the ferroelectric capacitor and the paraelectric capacitor. The horizontal axis represents the voltage between the electrodes of the capacitive element, and the vertical axis represents the capacitance (capacitance) of the ferroelectric capacitive element and the paraelectric capacitive element at this voltage. The capacitance of the ferroelectric capacitor increases as the voltage between the electrodes of the element decreases. However, the capacitance of the paraelectric capacitor does not change with voltage change and is constant. The voltage Va indicates a voltage at which the capacitance of the ferroelectric capacitor and the capacitance of the paraelectric capacitor match.

  FIG. 8 is a diagram for explaining a change in the voltage P51 of the first voltage dividing circuit 51 and a change in the voltage P52 of the second voltage dividing circuit 52. FIG. 8A shows the first voltage dividing circuit 51. FIG. FIG. 8B is a diagram illustrating the second voltage dividing circuit 52.

  The voltage V1 in FIG. 8A indicates the voltage between the electrode plates of the ferroelectric capacitor Cfe51, and the voltage V2 indicates the voltage between the electrode plates of the paraelectric capacitor Cdp51. The voltage V2 is the voltage P51. The voltage V3 in FIG. 8B indicates the voltage between the electrode plates of the paraelectric capacitor Cdp52, and the voltage V4 indicates the voltage between the electrode plates of the ferroelectric capacitor Cfe52. The voltage V4 is the voltage P52.

When the capacitance of the ferroelectric capacitor Cfe51 is C1, and the capacitance of the paraelectric capacitor Cdp51 is C2,
C1: C2 = V2: V1 (Formula 1)
It is. Here, assuming that the power supply voltage VDD is the voltage Va in FIG. 7, for example, C1 = C2 = 1, V2: V1 = 1: 1. When the power supply voltage VDD decreases from Va, the capacity C2 is constant, but the capacity C1 increases. Here, if the power supply voltage VDD decreases from Va and the capacity C1 becomes N times the capacity C2, then from (Equation 1),
V2: V1 = N: 1 (Expression 2) Here, N is N> 1.

If the capacitance of the paraelectric capacitor Cdp52 is C3 and the capacitor of the ferroelectric capacitor Cfe52 is C4,
C3: C4 = V4: V3 (Formula 3)
It is. Here, assuming that the power supply voltage VDD is the voltage Va in FIG. 7, for example, C3 = C4 = 1, V4: V3 = 1: 1. When the power supply voltage VDD decreases from Va, the capacitance C3 is constant, but the capacitance C4 increases. Here, when the power supply voltage VDD decreases from Va and the capacity C4 becomes N times the capacity C3, from (Equation 3),
V4: V3 = 1: N (Expression 4) N is N> 1.

  As shown in (Equation 2) and (Equation 4), the voltage change rate of the voltage V2 (voltage P51) and the voltage change rate of the voltage V4 (voltage P52) accompanying the decrease in the power supply voltage VDD are different, and the decrease rate of the voltage V2 The decrease rate of the voltage V4 is larger.

This will be described in more detail. Since the power supply voltage VDD = the voltage V1 + the voltage V2, when (Equation 1) is modified,
V2 = (C1 / (C1 + C2)) × VDD (Formula 5)
It becomes. In addition, since the power supply voltage VDD = the voltage V3 + the voltage V4,
V4 = (C3 / (C3 + C4)) × VDD (Formula 6)
It becomes.
The paraelectric capacitors C2 and C3 in (Equation 5) and (Equation 6) are constant regardless of the change in the power supply voltage VDD as described in FIG. 7, but the ferroelectric capacitors C1 and C4 are As described with reference to FIG. 7, when the power supply voltage VDD decreases, the power supply voltage VDD increases accordingly.

  When the power supply voltage VDD decreases, the capacity C1 increases. As shown in (Equation 5), the capacity C1 is in the denominator and numerator, and the change in the capacity C1 is cancelled. On the other hand, when the power supply voltage VDD decreases, the capacitance C4 increases. However, since the capacitance C4 is only in the denominator as shown in (Equation 6), (C3 / (C3 + C4)) is inversely proportional to the increase in the capacitance C4. Get smaller.

  As described in (Equation 5) and (Equation 6), it can be seen that when the power supply voltage VDD decreases, the decrease rate of the voltage V4 (voltage P52) is larger than the decrease rate of the voltage V2 (voltage P51).

  In the present embodiment, a cross point between the voltage P51 and the voltage P52 is created using the characteristics of the changes of the voltage P51 and the voltage P52. Then, the voltage Vc at the cross point becomes the reference voltage VREF, that is, at the time of the cross point (time T2 in FIG. 6), it can be considered that the power supply voltage VDD has decreased to the voltage VDD0 below the operation specification standard. In addition, parameters of the ferroelectric capacitor element Cfe51, the paraelectric capacitor element Cdp51, the ferroelectric capacitor element Cfe52, and the paraelectric capacitor element Cdp52 are adjusted.

  In the example of FIGS. 6 to 8, when the power supply voltage VDD is higher than the voltage VDD0 below the operation specification standard, that is, when the voltage P52> the voltage P51, C1: C2 = V2 (P51): V1 = N: 1, C3 : C4 = V4 (P52): V3 = Na: 1 (Na> N), and when the power supply voltage VDD is the same as the voltage VDD0 below the operation specification standard, that is, when the voltage P52 = the voltage P51 = the reference voltage VREF, The parameters of the ferroelectric capacitor Cfe51, the paraelectric capacitor Cdp51, the ferroelectric capacitor Cfe52, and the paraelectric capacitor Cdp52 are adjusted so that C1: C2 = C3: C4.

  FIG. 9 is a circuit diagram of the power supply voltage determination circuit 50, the bias circuit 54, and the buffer 81 described in FIG.

  The comparator 53 includes P-channel transistors Tr60 and Tr61 that form a current mirror circuit that generates a constant current when a bias voltage Vbias is applied to a gate, and a P-channel that receives a divided voltage P51 and a divided voltage P52, respectively. Transistors Tr62 and Tr63, N-channel transistors Tr64 and Tr65 constituting a current mirror circuit, and an N-channel transistor Tr66 having a drain connected to the gate of the transistor Tr65. The transistors Tr62 and Tr63 compare the divided voltages applied to the gates. When the divided voltage P52> the divided voltage P51, the transistor Tr66 is turned off and the connection point N53 is set to the high level. When the divided voltage P52 <the divided voltage P51, the transistor Tr63 is turned on, the transistor Tr62 is turned off, and the voltage level at the node N54 increases. As a result, the transistor Tr66 is turned on and the connection point N53 becomes low level.

  The buffer 81 includes a P-channel transistor Tr70 and an N-channel transistor 71 that constitute an inverter, and a P-channel transistor Tr72 and an N-channel transistor 73. The buffer 81 buffers the voltage at the connection point N53 and outputs a signal VDET.

  Note that the first voltage dividing circuit 51 and the second voltage dividing circuit 52 may be interchanged. For example, the ferroelectric capacitor Cfe51 connected to the high power supply VDD side of the first voltage dividing circuit 51 is connected to the reference power supply VSS side, and the paraelectric capacitor Cdp51 is connected to the high power supply VDD side. Even if the paraelectric capacitor Cdp52 connected to the high power supply VDD side of the second voltage dividing circuit 52 is connected to the reference power supply VSS side and the ferroelectric capacitor Cfe52 is connected to the high power supply VDD side. Good. If switched in this way, the comparison signal VDET of the comparator 53 becomes reverse logic. Therefore, the divided voltage P51 of the first voltage dividing circuit 51 is input to the non-inverting input terminal of the comparator 53, and the divided voltage P52 of the second voltage dividing circuit 52 is input to the inverting input terminal of the comparator 53. . In addition, the buffer 81 (see FIG. 9) at the subsequent stage of the comparator 53 may be an inverter.

  As described above, the voltage Vc corresponding to the reference voltage VREF can be generated by the first voltage dividing circuit 51 and the second voltage dividing circuit 52. The first voltage dividing circuit 51 and the second voltage dividing circuit 52 are composed of capacitive elements, and the circuit configuration is simple. Furthermore, since the capacitive elements are connected in series, there is no current path from the high power supply VDD to the reference power supply VSS, and current consumption can be reduced. Further, by setting the capacitance of the ferroelectric capacitor element Cfe51 = the capacitance of the ferroelectric capacitor element Cfe52, and the capacitance of the paraelectric capacitor element Cdp51 = the capacitance of the paraelectric capacitor element Cdp52, process variations in the manufacturing process of the capacitor element. Can be suppressed. As a result, the voltage Vc corresponding to the reference voltage can be determined with high accuracy, and it can be determined with high accuracy that the power supply voltage VDD has dropped to a voltage equal to or lower than the operating specification standard.

(Second Embodiment)
FIG. 10 is a diagram illustrating a power supply voltage determination circuit according to the second embodiment. The power supply voltage determining circuit 60 uses a second voltage dividing circuit 62 instead of the second voltage dividing circuit 52 of the power supply voltage determining circuit 50 of FIG. Other components are denoted by the same reference numerals as those in FIG.

  The second voltage dividing circuit 62 uses a paraelectric capacitive element having no voltage-dependent characteristics as a voltage dividing element, and has a paraelectric capacitive element Cdp62 and a paraelectric capacitive element Cdp62 ′ connected in series. It is.

  The comparator 53 compares the divided voltage P51 at the connection point N51 of the first voltage dividing circuit 51 with the divided voltage P62 at the connection point N62 of the second voltage dividing circuit 62.

  FIG. 11 is a diagram for explaining the operation of the power supply voltage determination circuit 60. The power supply voltage VDD, the divided voltage P51 of the first voltage dividing circuit 51, the divided voltage P62 of the second voltage dividing circuit 62, 6 is a graph showing a signal VDET of the comparator 53.

  As described with reference to FIG. 7, the paraelectric capacitor does not have voltage-dependent characteristics, so that the capacitance does not change even if the voltage between the electrodes of the capacitor changes. Therefore, the rate of decrease of the divided voltage P62 of the second voltage dividing circuit 62 composed of paraelectric capacitance elements is the same as the rate of decrease of the power supply voltage VDD. However, the reduction rate of the divided voltage P51 of the first voltage dividing circuit 51 that uses the capacitive element Cfe51 having voltage dependent characteristics as a voltage dividing element is the same as the rate of reduction of the divided voltage P62 of the second voltage dividing circuit 62. Different.

  In the present embodiment, a cross point between the voltage P51 and the voltage P62 is created by using the change characteristics of the voltage P51 and the voltage P62. Then, the ferroelectric voltage is set so that the voltage Vc at the cross point becomes the reference voltage VREF, that is, at the time of the cross point (time T10), it can be considered that the power supply voltage VDD has decreased to a voltage lower than the operation specification standard. The parameters of the body capacitive element Cfe51, paraelectric capacitive element Cdp51, paraelectric capacitive element Cdp62, and paraelectric capacitive element Cdp62 ′ are adjusted. Since a specific example of the parameter adjustment has been described in the first embodiment, a description thereof will be omitted.

  Since the first voltage dividing circuit 51 and the second voltage dividing circuit 62 have capacitive elements connected in series, there is no current path from the high power supply VDD to the reference power supply VSS, and current consumption can be reduced.

  As a modification of the second embodiment, the first voltage dividing circuit 51 and the second voltage dividing circuit 62 may be interchanged. Further, the ferroelectric capacitor Cfe51 connected to the high power supply VDD side of the first voltage dividing circuit 51 is connected to the reference power supply VSS side, and the paraelectric capacitor Cdp51 is connected to the high power supply VDD side. The ferroelectric capacitor Cfe51 and the paraelectric capacitor Cdp51 may be interchanged. When the comparison signal VDET of the comparator 53 becomes reverse logic due to this replacement, the divided voltage P51 of the first voltage dividing circuit 51 is input to the non-inverting input terminal of the comparator 53, and the second voltage dividing circuit. The divided voltage P62 of 62 is input to the inverting input terminal of the comparator 53.

(Third embodiment)
FIG. 12 is a diagram illustrating a power supply voltage determination circuit according to the third embodiment. The power supply voltage determination circuit 70 uses a second voltage dividing circuit 72 instead of the second voltage dividing circuit 52 of the power supply voltage determination circuit 50 of FIG. Other components are denoted by the same reference numerals as those in FIG.

  The second voltage dividing circuit 72 uses a resistance element as a voltage dividing element, and has a resistor R72 and a resistor R72 'connected in series.

  The comparator 53 compares the divided voltage P51 at the connection point N51 of the first voltage dividing circuit 51 with the divided voltage P72 at the connection point N72 of the second voltage dividing circuit 72.

  FIG. 13 is a diagram for explaining the operation of the power supply voltage determination circuit 70. The power supply voltage VDD, the divided voltage P51 of the first voltage dividing circuit 51, the divided voltage P72 of the second voltage dividing circuit 72, 6 is a graph showing a signal VDET of the comparator 53.

  Since the resistors R72 and R72 'have no voltage dependence characteristics, the rate of decrease of the divided voltage P72 of the second voltage dividing circuit 72 is the same as the rate of decrease of the power supply voltage VDD. However, the decreasing rate of the divided voltage P51 of the first voltage dividing circuit 51 that uses the capacitive element Cfe51 having voltage dependent characteristics as a voltage dividing element is the same as the decreasing rate of the divided voltage P72 of the second voltage dividing circuit 72. Different.

  In the present embodiment, a cross point between the voltage P51 and the voltage P72 is created by using the change characteristics of the voltage P51 and the voltage P72. Then, the ferroelectric voltage is set so that the voltage Vc at the cross point becomes the reference voltage VREF, that is, at the time of the cross point (time T20), it can be considered that the power supply voltage VDD has decreased to a voltage lower than the operation specification standard. The parameters of the body capacitance element Cfe51, the paraelectric capacitance element Cdp51, the resistor R72, and the resistor R72 ′ are adjusted. Since a specific example of the parameter adjustment has been described in the first embodiment, a description thereof will be omitted.

  When a resistor is used as the voltage dividing element of the second voltage dividing circuit 72, a current path is formed. However, since the current flowing through the second voltage dividing circuit 72 can be reduced by increasing the resistance values of the resistors R72 and R72 'that are voltage dividing elements, the influence of the current path can be reduced.

  As a modification of the third embodiment, the first voltage dividing circuit 51 and the second voltage dividing circuit 72 may be interchanged as in the modification of the second embodiment. Further, even if the ferroelectric capacitor Cfe51 connected to the high power supply VDD side of the first voltage dividing circuit 51 is connected to the reference power supply VSS side and the paraelectric capacitor Cdp51 is connected to the high power supply VDD side. Good. When the comparison signal VDET of the comparator 53 becomes reverse logic due to this replacement, the divided voltage P51 of the first voltage dividing circuit 51 is input to the non-inverting input terminal of the comparator 53, and the second voltage dividing circuit. The divided voltage P 72 of 72 is input to the inverting input terminal of the comparator 53.

  In the above description of the embodiment, a ferroelectric capacitor is illustrated as an example of a capacitor having voltage-dependent characteristics. However, a junction capacitor at the time of reverse bias of a PN diode can also be used. . The junction capacitance is an electrostatic capacitance generated when space charges are stored in a depletion layer having an insulating property at the PN junction portion of the diode when the diode is reversely biased. In addition, a MOS capacitor using a MOS transistor can be used.

  An example of a capacitive element that does not have voltage-dependent characteristics is a capacitor that uses stacked double polysilicon.

  The above embodiment is summarized as follows.

(Appendix 1)
A first voltage divider provided between the high power supply VDD and the reference power supply VSS and having a voltage-dependent characteristic whose capacitance changes according to the applied voltage and a capacitive element not having the voltage-dependent characteristic are connected in series. Circuit,
A second voltage dividing circuit provided between the high power supply VDD and the reference power supply VSS and connected in parallel to the first voltage dividing circuit;
A power supply voltage determination circuit comprising: a comparator that compares a divided voltage between the capacitive elements in the first voltage dividing circuit with a divided voltage of the second voltage dividing circuit.

(Appendix 2)
In Appendix 1,
The first voltage dividing circuit includes a first capacitive element having the voltage dependence characteristic connected to the high power supply VDD side and a second capacitive element having no voltage dependence characteristic connected to the reference power supply VSS side. Have
The second voltage dividing circuit includes a third capacitor element having no voltage dependency characteristic connected to the high power supply VDD side and a fourth capacitor element having the voltage dependency characteristic connected to the reference power supply VSS side. A power supply voltage determination circuit.

(Appendix 3)
In Appendix 1,
The second voltage dividing circuit is a power supply voltage determination circuit in which capacitive elements having no voltage dependence characteristics are connected in series.

(Appendix 4)
In Appendix 1,
The second voltage dividing circuit is a power supply voltage determination circuit in which resistance elements are connected in series.

(Appendix 5)
In any one of appendices 1 to 4,
The capacitor element having the voltage dependency characteristic is a power supply voltage determination circuit which is a ferroelectric capacitor.

(Appendix 6)
In any one of appendices 1 to 4,
The capacitor element having no voltage dependence characteristic is a power supply voltage determination circuit which is a paraelectric capacitor.

10 ... LSI
11, 20, 40, 50, 60, 70 ... power supply voltage determination circuit 51 ... first voltage divider circuit 52, 62, 72 ... second voltage divider circuit 53 ... comparator 54 ... bias circuit

Claims (5)

A first voltage dividing circuit provided between a high power supply and a reference power supply and having a voltage-dependent characteristic whose capacitance changes according to an applied voltage and a capacitive element not having the voltage-dependent characteristic are connected in series; ,
A second voltage dividing circuit provided between the high power supply and the reference power supply and connected in parallel to the first voltage dividing circuit;
A power supply voltage determination circuit comprising: a comparator that compares a divided voltage between the capacitive elements in the first voltage dividing circuit with a divided voltage of the second voltage dividing circuit. In claim 1,
The first voltage dividing circuit includes a first capacitive element having the voltage dependence characteristic connected to the high power supply side and a second capacitive element not having the voltage dependence characteristic connected to the reference power supply side. ,
The second voltage dividing circuit includes a third capacitor element having no voltage dependency characteristic connected to the high power supply side and a fourth capacitor element having the voltage dependency characteristic connected to the reference power supply side. Voltage judgment circuit. In claim 1,
The second voltage dividing circuit is a power supply voltage determination circuit in which capacitive elements having no voltage dependence characteristics are connected in series. In claim 1,
The second voltage dividing circuit is a power supply voltage determination circuit in which resistance elements are connected in series. In any of claims 1 to 4,
The capacitor element having the voltage dependency characteristic is a power supply voltage determination circuit which is a ferroelectric capacitor.

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