JP4884846B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique effective when applied to a liquid crystal display device in which a bus line is provided outside a display region.

  Conventionally, liquid crystal display devices are widely used for televisions, displays for personal computers (PCs), displays for mobile phone terminals and personal digital assistants (PDAs), and the like.

  The liquid crystal display device is a display device having a liquid crystal display panel in which a liquid crystal material is sealed between a pair of substrates. At this time, one of the pair of substrates includes, for example, a plurality of scanning signal lines, a video signal line sterically intersecting with the plurality of scanning signal lines via an insulating layer, and two lines. TFT elements and pixel electrodes arranged for a pixel region surrounded by adjacent scanning signal lines and two adjacent video signal lines. The substrate having the TFT element and the pixel electrode is generally called a TFT substrate.

  In addition, the TFT substrate may be provided with a conductive layer called a bus line outside a display area constituted by a plurality of the pixel areas (see, for example, Patent Document 1).

  When the liquid crystal display panel is of a lateral electric field driving method such as an IPS (In-Plane Switching) method, a counter electrode (also called a common electrode) is also provided on the TFT substrate. At this time, the TFT substrate has a bus line that is electrically connected to the counter electrode outside the display region.

In addition, when the liquid crystal display panel is of a vertical electric field drive system such as a TN system or a VA system, a storage capacitor line for forming a storage capacitor (also referred to as a storage capacitor) is provided on the TFT substrate. May have. At this time, the TFT substrate has a bus line that is electrically connected to the storage capacitor line outside the display region.
JP 2003-156663 A

  When a bus line is provided outside the display area of the TFT substrate, it is generally provided in an annular shape so as to surround the display area. Therefore, the scanning signal line and the video signal line three-dimensionally intersect with the bus line outside the display area.

  At this time, in each crossing region where each signal line intersects with the bus line, for example, an insulating layer such as a silicon nitride (SiN) film and a semiconductor layer formed simultaneously with the channel layer of the TFT element are interposed. And prevents short circuit of the bus line.

  However, defects may occur in the process of forming the insulating layer and the semiconductor layer, and for example, a certain video signal line and a bus line may be short-circuited.

  When a bus line is provided on a conventional TFT substrate, the width of the bus line is much wider than the width of a scanning signal line or a video signal line. Therefore, for example, when a certain video signal line and a bus line are short-circuited, there is a problem that the repair (repair) is very difficult. As a result, there is a problem that the manufacturing yield of the TFT substrate decreases.

  An object of the present invention is that when each signal line and the bus line are short-circuited on a substrate provided with a bus line that three-dimensionally intersects with a scanning signal line or a video signal line via an insulating layer outside the display area. The object is to provide a technique capable of facilitating the repair.

  Another object of the present invention is a technique capable of improving the manufacturing yield of a substrate provided with bus lines that three-dimensionally intersect with scanning signal lines and video signal lines via an insulating layer outside the display area. Is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of typical inventions among the inventions disclosed in the present application will be described as follows.

(1) A liquid crystal display device having a liquid crystal display panel in which a liquid crystal material is sealed between a pair of substrates, wherein one of the pair of substrates includes a plurality of scanning signal lines and an insulating layer. A video signal line that three-dimensionally intersects with the plurality of scanning signal lines, and a common signal line that three-dimensionally intersects the scanning signal line or the video signal line via an insulating layer. An intersection region that is disposed outside and has a bus line that supplies an electric signal to the common signal line, and the scanning signal line or the video signal line intersects the bus line in three dimensions through an insulating layer The bus line has a plurality of openings in a region other than the intersecting region when viewed in plan, and the bus line is branched into a plurality by the opening, and the scanning is performed between the intersecting regions. Signal line or video signal line A conductive film is formed through an insulating layer at a position that does not overlap and overlaps with the bus line, and the conductive film is divided into a plurality of the branched through a plurality of through holes formed in the insulating film. A liquid crystal display device electrically connected to the bus line .

(2) The liquid crystal display device according to (1), wherein the opening has a rectangular shape .

(3) In the liquid crystal display device according to (1 ), the line width of the portion where the through hole is formed out of the line width of the bus line between the openings is thicker than the line width of the other portion. Liquid crystal display device.

(4) In the liquid crystal display device of (1 ) , each of the pixel regions defined by the two adjacent scanning signal lines and the two adjacent video signal lines includes a TFT element, a pixel electrode, and a counter electrode A liquid crystal display device having electrodes, wherein the counter electrode is formed on the one substrate together with the scanning signal line and the video signal line, and the conductive film is electrically connected to the counter electrode .

(5) In the liquid crystal display device according to (1 ) , each of the pixel regions defined by two adjacent scanning signal lines and two adjacent video signal lines includes a TFT element, a pixel electrode, and a counter electrode The counter electrode is formed on a substrate different from the one substrate having the scanning signal line and the video signal line in the pair of substrates, and the one substrate has a storage capacitor A liquid crystal display device having a line, wherein the conductive film is electrically connected to the storage capacitor line .

  In the liquid crystal display device of the present invention, one of the pair of substrates of the liquid crystal display panel is provided with a bus line and a plurality of signal lines that three-dimensionally intersect the bus line via an insulating layer. It is assumed that The bus line has an opening on the outside of the intersecting region that overlaps with the signal line when viewed in plan, and the opening is provided on both sides of each intersecting region. In this way, even if the width of the bus line (distance between both ends) is wide, the portion provided with the opening is narrowed by the width of the opening. Therefore, for example, when a video signal line and a bus line are short-circuited, the bus line can be easily cut off on both sides of the intersection region of the video signal line, and can be easily repaired.

  At this time, for example, the opening of the bus line may be formed by arranging two or more openings in a region sandwiched between two adjacent intersecting regions in the extending direction of the signal line in the intersecting region. The bus line can be easily cut while maintaining the electrical characteristics of the bus line.

  When arranging two or more openings in the extending direction of the signal line in a region sandwiched between two adjacent intersecting regions of the bus line, the vicinity of one intersecting region to the other intersecting region An opening extending to the vicinity of the crossing area may be arranged, a plurality of opening parts may be arranged in the vicinity of one crossing area, and a plurality of opening parts may be arranged in the vicinity of the other crossing area.

  Further, the substrate having the bus line has a second conductive layer provided via an insulating layer in a region overlapping the bus line as viewed in plan, and the bus line and the second conductive layer are It may be electrically connected through a through hole.

  The present invention is applied to, for example, an IPS liquid crystal display panel. At this time, the substrate having the bus line includes a plurality of scanning signal lines, a video signal line three-dimensionally intersecting with the plurality of scanning signal lines through an insulating layer, and two adjacent scanning signal lines. And a TFT element and a pixel electrode arranged for a region surrounded by two adjacent video signal lines, and a counter electrode, and the first conductive layer is the counter electrode.

Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals and their repeated explanation is omitted.

1 and 2 are schematic views showing a schematic configuration of a liquid crystal display panel according to an embodiment of the present invention.
FIG. 1 is a schematic plan view of a liquid crystal display panel as viewed from the observer side. FIG. 2 is a schematic cross-sectional view taken along line AA ′ of FIG.

  According to the present invention, there is provided a display including a display panel having a bus line provided outside the display area and having a substrate in which a plurality of signal lines three-dimensionally intersect the bus line through an insulating layer. It relates to the device. One such display panel is a liquid crystal display panel. In this embodiment, a horizontal electric field drive type liquid crystal display panel such as the IPS mode is taken as an example, and a configuration and an operation effect when the present invention is applied will be described.

  For example, as shown in FIGS. 1 and 2, the liquid crystal display panel is a display panel in which a liquid crystal material 3 is sealed between a pair of substrates 1 and 2. At this time, the pair of substrates 1 and 2 are bonded to each other with a sealing material 4 arranged in an annular shape outside the display area DA, and the liquid crystal material 3 is surrounded by the pair of substrates 1 and 2 and the sealing material 4. Enclosed in space.

  Of the pair of substrates 1 and 2, the substrate 1 having a larger outer dimension as viewed from the observer side is generally called a TFT substrate. Although omitted in FIGS. 1 and 2, the TFT substrate 1 has a plurality of scanning signal lines on a surface of a transparent substrate such as a glass substrate and the plurality of scanning signal lines via an insulating layer. A plurality of video signal lines intersecting three-dimensionally are formed. A region surrounded by two adjacent scanning signal lines and two adjacent video signal lines corresponds to one pixel region, and a TFT element, a pixel electrode, or the like is arranged in each pixel region. . The other substrate 2 that forms a pair with the TFT substrate 1 is generally called a counter substrate.

  Further, when the liquid crystal display panel is a lateral electric field driving method such as an IPS method, a counter electrode (also referred to as a common electrode) facing the pixel electrode of the TFT substrate 1 is provided on the TFT substrate 1. At this time, the counter electrode is connected to, for example, a common bus line (not shown) provided in a ring shape outside the display area DA.

  Next, a configuration example of one pixel in the display area DA in the horizontal electric field drive type liquid crystal display panel will be briefly described with reference to FIGS.

  FIG. 3 is a schematic plan view showing a configuration example of one pixel in the TFT substrate of the liquid crystal display panel of this embodiment. 4 is a schematic cross-sectional view taken along line BB ′ of FIG. FIG. 5 is a schematic cross-sectional view taken along the line CC ′ of FIG.

  In the case of a horizontal electric field drive type liquid crystal display panel, the pixel electrode and the counter electrode (common electrode) are provided on the TFT substrate 1 side. At this time, the TFT substrate 1 is provided with a plurality of scanning signal lines GL extending in the x direction on the surface of the glass substrate SUB as shown in FIGS. 3 to 5, for example. There are provided a plurality of video signal lines DL extending in the y direction via the first insulating layer PAS1 and three-dimensionally intersecting with the plurality of scanning signal lines GL. A region surrounded by two adjacent scanning signal lines GL and two adjacent video signal lines DL corresponds to one pixel region.

  Further, on the surface of the glass substrate SUB, for example, a flat counter electrode CT is provided for each pixel region. At this time, the counter electrode CT of each pixel region arranged in the extending direction (x direction) of the scanning signal line GL is electrically connected by a common signal line CL parallel to the scanning signal line GL. At this time, each common signal line CL is electrically connected to the common bus line outside the display area DA. A common connection pad CP electrically connected to the counter electrode CT is provided on the side opposite to the direction in which the common signal line CL is provided when viewed from the scanning signal line GL.

  In addition to the video signal line DL, a semiconductor layer, a drain electrode SD1, and a source electrode SD2 are provided on the first insulating layer PAS1. At this time, the semiconductor layer is formed using, for example, amorphous silicon (a-Si), and has a function as the channel layer SC of the TFT element disposed for each pixel region. There is one (not shown) that prevents a short circuit between the scanning signal line GL and the video signal line DL in a region where the scanning signal line GL and the video signal line DL intersect three-dimensionally. At this time, in the semiconductor layer having a function as the channel layer SC of the TFT element, both the drain electrode SD1 and the source electrode SD2 connected to the video signal line DL are connected.

  On the surface (layer) on which the video signal line DL and the like are formed, the pixel electrode PX is provided via the second insulating layer PAS2. The pixel electrode PX is an independent electrode for each pixel region, and is electrically connected to the source electrode SD2 in an opening (through hole) TH1 provided in the second insulating layer PAS. Further, when the counter electrode CT and the pixel electrode PX are stacked via the first insulating layer PAS1 and the second insulating layer PAS2 as shown in FIGS. 3 to 5, the pixel electrode PX It is a comb-shaped electrode provided with a slit SL.

  Further, on the second insulating layer PAS2, in addition to the pixel electrode PX, for example, a bridge wiring BR for electrically connecting two counter electrodes CT arranged above and below the scanning signal line GL. Is provided. At this time, the bridge wiring BR is connected to the common signal line CL and the common connection pad CP arranged across the scanning signal line GL by the through holes TH2 and TH3.

  An alignment film ORI is provided on the second insulating layer PAS2 so as to cover the pixel electrode PX and the bridge wiring BR. Although not shown, the counter substrate 2 is disposed so as to face the surface of the TFT substrate 1 on which the alignment film ORI is provided.

  Hereinafter, a configuration and an operation effect when the present invention is applied to a liquid crystal display panel (TFT substrate) having a configuration of one pixel as shown in FIGS. 3 to 5 will be described.

  FIG. 6 is a schematic plan view showing a configuration example of the TFT substrate in the area AR1 of FIG. FIG. 7 is a schematic cross-sectional view taken along the line D-D ′ of FIG. 6. FIG. 8 is a schematic cross-sectional view taken along line E-E ′ of FIG. 6.

In the liquid crystal display panel of this embodiment, the configuration of the TFT substrate 1 in the region AR1 shown in FIG. 1 is as shown in FIGS. 6 to 8, for example. In the plan view of FIG. 6, the scanning signal lines GL ₁ is a signal line disposed on the outermost side among the plurality of scanning signal lines, corresponding to the periphery of the display area DA. And, on the outside of the scanning signal lines GL ₁ as viewed from the display area DA, the common bus line 5 connected to the counter electrode CT is provided via a common signal line CL.

  At this time, the common bus line 5 is formed simultaneously with the scanning signal line GL, for example. Therefore, the common bus line 5 intersects a plurality of video signal lines in a three-dimensional manner, for example, as shown in FIGS. At this time, the first insulating layer PAS1 and the semiconductor layer 6 are interposed in an intersecting region where the common bus line 5 and the video signal line DL intersect three-dimensionally. At this time, in the intersection region of the common bus line 5 and the video signal line DL, the common bus line 5 extends from one end 5a to the other end 5b without being missing.

  Moreover, the common bus line 5 has an opening 5c outside the intersection region with the video signal line DL as shown in FIGS. 6 and 8, for example. For example, as illustrated in FIG. 6, the opening 5 c includes two openings 5 c in the extending direction of the video signal line DL for each region sandwiched between two adjacent intersecting regions of the common bus line 5. Are provided side by side.

At this time, the conductive layer 7 is provided, for example, via a first insulating layer PAS1 and a second insulating layer PAS2 in a region sandwiched between two adjacent intersecting regions of the common bus line 5. . The conductive layer 7 is connected to a common bus line in a through hole TH4 formed by opening the first insulating layer PAS1 and the second insulating layer PAS2. Also, some of the conductive layer 7 is electrically connected to the common connection pad CP in the pixel region across the scanning signal lines GL _1. The conductive layer 7 is formed simultaneously with the pixel electrode PX, for example .

  FIG. 9 is a schematic plan view for explaining the function and effect of the TFT substrate of this embodiment.

  As in the TFT substrate of this embodiment, the common bus line 5 is provided outside the display area DA, and when the common bus line 5 and the video signal line DL intersect three-dimensionally, As shown in FIGS. 6 to 8, the first insulating layer PAS1 and the semiconductor layer 6 are interposed. Further, in the region where the common bus line 5 and the video signal line DL intersect, the common bus line 5 extends from one end 5a to the other end 5b without being chipped, and the video is displayed on a substantially flat surface. The signal lines DL intersect. Therefore, normally, the video signal line DL does not come into contact with the common bus line 5 and is short-circuited.

  However, in the process of forming the first insulating layer PAS1 and the semiconductor layer 6, the video signal line DL is brought into contact with the common bus line 5 and short-circuited due to an abnormal film thickness at the time of film formation or an etching failure at the time of patterning. There is. And in the case of the common bus line without the conventional opening part 5c, since the width | variety is wide, it was difficult to isolate | separate the part which cut | disconnected the common bus line, for example.

On the other hand, in the TFT substrate of this embodiment, the common bus line 5, for example, on both sides of the video signal line DL _n shown in FIG. 6, the opening 5c, along the extending direction of the video signal line DL _n 3 One has been separated, each of width, for example, approximately equal to the width of the scanning signal lines GL _1. Therefore, for example, if the video signal line DL _n is shorted to the common bus line 5, as shown in FIG. 9, on both sides of the video signal line DL _n, width separated are thinner by an opening 5c By cutting the location, the shorted portion of the common bus line 5 can be easily separated. When the common bus line 5 is cut, for example, a laser may be irradiated.

At this time, the common bus line 5, since provided annularly so as to surround the display area DA, in FIG. 9, the common bus line 5 on the right side of the video signal line DL _n, the common bus line on the left 5 is in an electrically connected state.

  As described above, according to the TFT substrate 1 of the present embodiment, when the common bus line 5 provided outside the display area DA and the video signal line DL are short-circuited, only the short-circuited portion of the common bus line 5 is easily obtained. Can be separated. Therefore, it becomes easy to repair a short circuit failure between the common bus line 5 and the video signal line DL. As a result, the manufacturing yield of the TFT substrate 1 (liquid crystal display panel) is improved.

  FIG. 10 is a schematic plan view for explaining a first modification of the present embodiment. FIG. 11 is a schematic plan view for explaining a second modification of the present embodiment. 10 and 11 are plan views showing only the periphery of the common bus line 5 in the area AR1 of FIG.

  In the present embodiment, an opening 5c is provided outside the crossing region that three-dimensionally intersects with the video signal line DL of the common bus line 5, so that a portion short-circuited with the video signal line DL can be easily separated. At this time, the planar shape of the opening end of the opening 5c provided in the common bus line 5 is not limited to the rectangular shape as shown in FIG. That is, the planar shape of the opening end of the opening 5c is, for example, as shown in FIG. 10, a common bus separated only in the region where the through hole TH4 connecting the conductive layer 7 and the common bus line 5 is formed and its periphery. The shape may be such that the line width is wide. In this case, since the width of each common bus line separated by the opening 5c can be reduced outside the region where the through hole TH4 is formed, it can be easily cut in a short time.

  In the example shown in FIGS. 6 and 10, an opening 5c extending from the vicinity of one video signal line to the vicinity of the other video signal line is provided between two adjacent video signal lines DL. Two are arranged in the extending direction of the line. However, the opening 5c of the common bus line 5 is not limited to such an arrangement. For example, as shown in FIG. 11, two openings 5c are arranged in the vicinity of one video signal line, and the other video signal line is arranged. Of course, another two openings 5c may be arranged in the vicinity of. In this way, the contact area between the conductive layer 7 connected to the through hole TH4 and the common bus line 5 can be increased.

  In the present embodiment, the region where the common bus line 5 and the video signal line DL intersect three-dimensionally is mentioned, but not limited to this, the common bus line 5 and the scanning signal line GL intersect three-dimensionally. It goes without saying that the same can be said for the areas that are used. In the region where the common bus line 5 and the scanning signal line GL intersect three-dimensionally, the common bus line 5 is formed at the same time as the video signal line DL and the like, and the first insulating layer PAS1 and the semiconductor layer 6 are interposed therebetween. A plurality of scanning signal lines GL intersect three-dimensionally. Therefore, even in a region where the common bus line 5 and the scanning signal line GL intersect three-dimensionally, the common bus line 5 may be provided with an opening 5c as shown in FIGS. For example, when the scanning signal line GL and the common bus line 5 are short-circuited, only the short-circuited portion of the common bus line 5 can be easily separated.

12 and 13 are schematic views for explaining another function and effect of the TFT substrate of this example.
FIG. 12 is a schematic plan view for explaining the shape of a conventional common bus line. FIG. 13 is a schematic plan view for explaining a more desirable configuration of the common bus line in the TFT substrate of this embodiment.

In the conventional TFT substrate, when the common bus line is provided outside the display region, for example, as shown in FIG. 12, the common bus line 5 is arranged in the vicinity of the scanning signal line GL ₁ arranged at the outermost side. . At this time, if the conductive film formed on the substrate is etched to form a plurality of scanning signal lines GL and the common bus line 5 at the same time, for example, the region for forming the scanning signal line GL and the common bus line An etching resist (mask) is formed in each of the regions for forming 5.

However, as shown in FIG. 12, in the vicinity of the scanning signal lines GL _1, if a very area than the scanning signal lines GL ₁ to form a wide common bus line 5, a region to be left as the scanning signal lines GL ₁ becomes difficult to form a resist pattern, there is a width of the scanning signal lines GL ₁ is narrowed.

On the other hand, in the TFT substrate of this embodiment, for example, openings as shown in FIGS. 6, 10, and 11 are formed in the common bus line 5. However, it becomes narrower than the conventional one. That, TFT substrate 1 of this embodiment is to easily form a resist pattern of a region to be left as the scanning signal lines GL _1, can be expected the effect of preventing the width of the scanning signal lines GL ₁ is narrowed.

Further, among the common bus lines 5 provided outside the display area DA, the common bus line provided near the end of the video signal line DL to which the video signal is input is common as shown in FIG. An input solid pattern 5d is provided. The solid pattern 5 d extends to the end of the TFT substrate 1. When such a huge solid pattern 5d is provided, in the vicinity thereof, further less likely to form a resist pattern of a region to be left as the scanning signal lines GL _1, the width of the scanning signal lines GL ₁ becomes narrower Sometimes. Further, when the opening 5c is formed in the common bus line 5 as in the present embodiment, it is difficult to form the opening in the resist pattern near the huge solid pattern 5d, and the shape of the opening end of the opening 5c varies. May occur.

  Therefore, in order to further increase the effect of preventing the width of the scanning signal line GL from becoming narrower in the TFT substrate 1 of the present embodiment, for example, as shown in FIG. 13, a slit SL is provided in the solid pattern 5d. Is desirable. Of course, the pattern of the slit SL provided in the solid pattern 5d is not limited to the pattern shown in FIG. 13, and various patterns can be applied.

  The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. is there.

  For example, in the above-described embodiment, the horizontal electric field driving type liquid crystal display panel (TFT substrate 1) having a configuration of one pixel as shown in FIGS. 3 to 5 is taken as an example. Of course, the present invention can also be applied to a vertical electric field drive type liquid crystal display panel such as a TN type or a VA type.

  In the case of a vertical electric field drive type liquid crystal display panel, for example, the TFT substrate 1 may be provided with a storage capacitor line parallel to the scanning signal line GL. At this time, each storage capacitor line is connected to the common bus line, for example, outside the display area DA. Therefore, the common bus line three-dimensionally intersects with the scanning signal line and the video signal line. Also in this case, for example, by forming the opening 5c as shown in FIGS. 6, 10, and 11 in the common bus line, the portion of the common bus line that is short-circuited with the signal line can be easily separated. Can do.

  In the above embodiment, the TFT substrate of the liquid crystal display panel is taken as an example. However, the present invention is not limited to this, and a bus line is provided outside the display region, and a plurality of signal lines include an insulating layer. Of course, the present invention can be applied to any display device including a display panel having a substrate that three-dimensionally intersects with the bus line.

It is the model top view which looked at the liquid crystal display panel from the observer side. It is a schematic cross section in the A-A 'line of FIG. It is a schematic plan view which shows the structural example of 1 pixel in the TFT substrate of the liquid crystal display panel of a present Example. It is a schematic cross section in the BB 'line of FIG. It is a schematic cross section in the CC 'line of FIG. FIG. 2 is a schematic plan view showing a configuration example of a TFT substrate in a region AR1 in FIG. It is a schematic cross section in the D-D 'line of FIG. It is a schematic cross section in the E-E 'line of FIG. It is a schematic plan view for demonstrating the effect of the TFT substrate of a present Example. It is a schematic plan view for demonstrating the 1st modification of a present Example. It is a schematic plan view for demonstrating the 2nd modification of a present Example. It is a schematic plan view for demonstrating the shape of the conventional common bus line. It is a schematic top view for demonstrating the more desirable structure of the common bus line in the TFT substrate of a present Example.

Explanation of symbols

1 ... TFT substrate SUB ... glass substrate GL, GL 1 _... scanning signal lines CL ... common signal line CP ... common connection pads CT ... counter electrode PAS1 ... first insulating layer DL, DL n _... video signal lines SD1 ... drain electrode SD2 ... Source electrode SC ... TFT element channel layer (semiconductor layer)
PAS2 ... second insulating layer PX ... pixel electrode SL ... slit BR ... bridge wiring ORI ... alignment film 2 ... counter substrate 3 ... liquid crystal material 4 ... sealing material 5 ... common bus line 5c ... opening 5d ... solid pattern 6 ... semiconductor Layer 7: Conductive layer TH1, TH2, TH3, TH4, TH5 ... Through hole

Claims (5)

A liquid crystal display device having a liquid crystal display panel in which a liquid crystal material is sealed between a pair of substrates,
One of the pair of substrates includes a plurality of scanning signal lines, a video signal line sterically intersecting with the plurality of scanning signal lines via an insulating layer, and the scanning via an insulating layer. signal line walking has a common signal line that intersects three-dimensionally and the video signal lines,
A bus line disposed outside the display area and supplying an electric signal to the common signal line;
The scanning signal line or the video signal line forms an intersecting region that three-dimensionally intersects with the bus line through an insulating layer,
The bus line, have a plurality of openings in a region other than the intersection region in a plan view, the bus line is branched into a plurality by the openings,
A conductive film is formed between the intersecting regions at a position that does not overlap the scanning signal line or the video signal line and overlaps the bus line via an insulating layer. A liquid crystal display device, wherein the liquid crystal display device is electrically connected to a plurality of the bus lines branched through a plurality of through holes formed in an insulating film . The liquid crystal display device according to claim 1 , wherein the opening has a rectangular shape. Of the line width of the bus line between the opening and the line width of the portion through hole is formed, the liquid crystal display according to claim 1, wherein the thicker than the line width of the other portions apparatus. Each of the pixel regions defined by two adjacent scanning signal lines and two adjacent video signal lines includes a TFT element, a pixel electrode, and a counter electrode,
The counter electrode is formed on the one substrate together with the scanning signal line and the video signal line,
The liquid crystal display device according to claim 1 , wherein the conductive film is electrically connected to the counter electrode. Each of the pixel regions defined by two adjacent scanning signal lines and two adjacent video signal lines includes a TFT element, a pixel electrode, and a counter electrode,
The counter electrode is formed on a substrate different from the one substrate having the scanning signal line and the video signal line in the pair of substrates,
The one substrate has a storage capacitor line,
The liquid crystal display device according to claim 1 , wherein the conductive film is electrically connected to the storage capacitor line.

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