JP2001290167A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable working out a countermeasure even when the short circuit at a crossing part between a counter voltage signal line and other signal line is generated. SOLUTION: This liquid crystal display device is provided with a display region which comprises the assembly of respective pixel regions where pixel electrodes and counter electrodes are formed on the liquid crystal side surface of one substrate between substrates placed opposite to each other via liquid crystal. Therein, the counter voltage signal lines connected to the counter electrodes of the respective pixel regions are extendedly prolonged outside the display regions and have the crossing parts via shielding films with other signal lines which supply signals to the respective pixel regions, and at least one slit which intersects the prolonging direction of the other signal lines is formed on the signal lines of at least one side between the counter voltage signal lines and the other signal lines on the superposition parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display called a horizontal electric field type.

[0002]

2. Description of the Related Art In a horizontal electric field type liquid crystal display device, a pixel electrode and a counter electrode are formed in each pixel region on a liquid crystal side surface of one of the substrates disposed to face each other with a liquid crystal interposed therebetween. The light transmittance of the liquid crystal is controlled by an electric field generated between the electrodes and having a component parallel to the substrate.

When the liquid crystal display device is of an active matrix type, a reference signal (voltage) is applied to a counter electrode.
And a video signal (voltage) from the drain signal line is supplied to the pixel electrode via a switching element driven by a scanning signal from the gate signal line.

In this case, the gate signal lines extend in the x-direction and are arranged in the y-direction with respect to the display area, and a scanning signal is supplied from outside the display area.
In general, video signals are supplied from outside the display area while extending in the direction and juxtaposed in the x direction.

For this reason, a counter voltage signal line for supplying a reference voltage signal to a counter electrode in each pixel region must be arranged outside the display region so as to intersect with the gate signal line or the drain signal line. Was.

[0006]

At the intersection of the drain signal line and the gate signal line or the drain signal line, an interlayer insulating film is interposed between them, but there are various reasons such as insufficient withstand voltage. It has been pointed out that there is a disadvantage that a short circuit occurs between these signal lines.

The occurrence of such a short circuit increases the number of gate signal lines or drain signal lines as the definition of a liquid crystal display device increases, and the probability of occurrence of the short circuit increases.
Early measures have been requested.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal device capable of taking measures even if a short circuit occurs at the intersection between an opposite voltage signal line and another signal line. A display device is provided.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.

That is, in the liquid crystal display device according to the present invention, basically, each of the pixel regions in which a pixel electrode and a counter electrode are formed on a liquid crystal side surface of one of the substrates disposed to face each other with the liquid crystal therebetween. And a counter voltage signal line connected to a counter electrode of each pixel region extends outside the display region, and another signal line that supplies a signal to each pixel region. And an intersecting portion with an insulating film interposed therebetween, and at the overlapping portion, intersects at least one of the counter voltage signal line and the other signal line with the extending direction of the other signal line. At least one slit is formed.

In the liquid crystal display device configured as described above, when a short circuit occurs between the opposite voltage signal line and another signal line in the superimposed portion, one of the plurality of signal lines branched by the slit is used. In some cases, this is normal.

For this reason, the signal line at the short-circuited portion is cut off from the original signal line by cutting two portions between the short-circuited portions so that the function of the original signal line is not impaired. Short circuit with the signal line can be avoided.

[0013]

[Example 1]

<< Overall Configuration >> FIG. 2 is a plan view showing a configuration of a liquid crystal side surface of one of the transparent substrates disposed opposite to each other via a liquid crystal in the in-plane switching mode liquid crystal display device according to the present invention. is there.

On the surface of the transparent substrate SUB1, gate signal lines GL and counter voltage signal lines CL extending in the x direction in the figure are alternately arranged in the y direction.

In this embodiment, the counter voltage signal line CL is arranged substantially at the center of the gate signal lines GL arranged in parallel.

A drain signal line DL is provided which is insulated from the gate signal line GL and the counter voltage signal line CL, extends in the y direction in the drawing, and is juxtaposed in the x direction.

The insulation between the gate signal line GL and the drain signal line DL with respect to the counter voltage signal line CL is provided by an interlayer insulating film formed over the entire area of the transparent substrate SUB1.

Here, each pixel region is provided with a counter voltage signal line C
A region surrounded by a gate signal line GL adjacent to L and a drain signal line DL adjacent to each other (shown by a dotted frame A in the figure) is configured. In addition,
The detailed configuration of this pixel region will be described later.

A set of these pixel regions constitutes a display region (shown by a dotted frame B in the figure).

Note that this display area is defined as
The transparent substrate SUB1 is fixed to the other transparent substrate facing the transparent substrate SUB1 and is distinguished from a sealing material forming region (shown by a dotted frame C in the figure) defining a liquid crystal sealing region.

Each of the drain signal lines DL has one end (upper side in the drawing) extending beyond the sealing material, and the extending end is formed with a terminal for inputting a video signal.

Similarly, each of the gate signal lines GL has one end (the left side in the figure) extending beyond the sealing material, and the extended end is formed with a terminal to which a scanning signal is input.

On the other hand, each of the opposed voltage signal lines CL has one end (the left side in the figure) at a location beyond the display area, and has an opposed voltage signal line CLB extending in the y direction in the figure (opposed in the following description). Voltage signal baseline).
One end of the counter voltage signal base line CLB extends beyond the sealing material, and the extending end is formed with a terminal to which a counter voltage is input.

Since the counter voltage signal base line CLB is arranged to cross each gate signal line GL,
An interlayer insulating film is interposed between each gate signal line GL.

In some cases, the gate signal line GL is formed in the same layer as the counter voltage signal line CL. In this case, the counter voltage signal base line CLB is formed, for example, simultaneously with the formation of the drain signal line DL to form the interlayer insulating film. Each of the counter voltage signal lines CL is connected through a contact hole.

Each of the gate signal lines GL has, for example, a Futamata shape at the intersection with the counter voltage signal base line CLB, so that two branched signal lines are formed.

The reason for this is that the gate signal line GL and the counter voltage signal base line CLB due to a defect in the interlayer insulating film or the like.
If there is a short circuit between the two (there is a high probability that a short circuit will occur in one of the branch signal lines), the branch signal line on the side where the short circuit has occurred is cut at the two places between the short circuits, and Is separated from the gate signal line GL to avoid a short circuit with the counter voltage signal base line CLB without impairing the function of the original gate signal line GL.

<< Configuration of Pixel >> FIG. 3 is a plan view showing one embodiment of each pixel, and shows a view in a region within a dotted frame A in FIG.

First, a gate signal line GL extending in the x direction in the drawing is formed of, for example, a chromium layer. The gate signal line GL is formed, for example, below the pixel region, as shown in the drawing, so that a region which substantially functions as a pixel is made as large as possible.

The gate signal line GL is supplied with a scanning signal from outside the display unit, and drives a thin film transistor TFT described later.

At substantially the center of the pixel region, a counter voltage signal line CL extending in the x direction in the figure is formed of, for example, the same material as the gate signal line GL.

The common electrode CT is formed integrally with the common voltage signal line GL, and the common electrode CT is formed in a substantially “H” -shaped pattern together with the common voltage signal line CL in the pixel area.

The counter electrode CT is connected to a pixel electrode P described later.
A signal serving as a reference for a video signal supplied to X is supplied via the counter voltage signal line CL, and an electric field having an intensity corresponding to the video signal is provided between the pixel electrode PX and the pixel electrode PX. Is caused to occur.

This electric field has a component parallel to the surface of the transparent substrate SUB1, and the light transmittance of the liquid crystal is controlled by the electric field composed of this component. This is the reason why the liquid crystal display device described in this embodiment is called a so-called horizontal electric field method. Note that a reference signal is supplied to the counter voltage signal line CL from outside the display unit.

The surface of the transparent substrate SUB1 on which the gate signal lines GL and the counter voltage signal lines CL are formed is made of, for example, a silicon nitride film including the gate signal lines GL and the counter voltage signal lines CL. An insulating film (not shown) is formed.

This insulating film is formed of a thin film transistor T described later.
In the region where the FT is formed, it functions as a gate insulating film. In the region where a drain signal line DL described later is formed, it functions as an interlayer insulating film for the gate signal line GL and the counter voltage signal line CL. The region has a function as a dielectric film.

In such an insulating film, a thin film transistor TFT is formed so as to overlap the gate signal line GL, and a semiconductor layer AS made of, for example, amorphous Si is formed in that portion.

Then, by forming the drain electrode SD2 and the source electrode SD1 on the upper surface of the semiconductor layer AS, a so-called inverted staggered thin film transistor having a part of the gate signal line GL as a gate electrode is formed.

Here, the drain electrode S on the semiconductor layer AS
D2 and the source electrode SD1 are formed simultaneously with the pixel electrode PX, for example, when the drain signal line DL is formed.

That is, a drain signal line DL extending in the y direction in the drawing is formed, and a drain electrode SD2 integrally formed with the drain signal line DL is formed on the semiconductor layer AS.

Here, as shown in the figure, the drain signal line DL is formed, for example, on the left side of the pixel region, and has a region which substantially functions as a pixel as large as possible.

The source electrode SD1 is formed simultaneously with the drain signal line DL, and at this time, is formed integrally with the pixel electrode PX.

The pixel electrode PX is connected to the counter electrode C described above.
It is formed so as to run between T and extend in the y direction in the figure. In other words, the counter electrodes CT are arranged at substantially equal intervals on both sides of the pixel electrode PX, and an electric field is generated between the pixel electrode PX and the counter electrode CT.

Here, as will be apparent from the figure,
The pixel electrode PX is formed in, for example, an inverted 'C'-shaped pattern bent at the counter voltage signal line CL, and accordingly, each counter electrode CT facing the pixel electrode PX is formed.
Also, the width is changed so as to be separated in parallel with the pixel electrode PX.

That is, when the bent pixel electrode PX has a uniform width in the longitudinal direction as shown in the figure, the counter electrodes CT located on both sides of the bent pixel electrode PX are:
The side on the drain signal line DL side is formed in parallel with the drain signal line DL, and the side on the pixel electrode PX side is formed in parallel with the pixel electrode PX.

As a result, the pixel electrode PX and the counter electrode CT
The direction of the electric field E generated between the counter voltage common line CL
In the figure, (−) θ is provided for the counter voltage common line CL in the lower pixel region, and (+) is provided for the counter voltage common line CL in the upper pixel region. ) Θ.

As described above, the direction of the electric field E is different in the area of one pixel (not necessarily in the area of one pixel, but may be in relation to other pixels).
The object is to change the light transmittance by rotating liquid crystal molecules in opposite directions with respect to a certain initial alignment direction.

In this manner, the inconvenience due to the viewing angle dependency of the liquid crystal display panel, which causes the luminance to be inverted when the viewpoint is inclined at an angle to the main viewing angle direction of the liquid crystal display panel, is eliminated. .

The initial alignment direction of the liquid crystal molecules (having a positive dielectric anisotropy) is substantially coincident with, for example, the direction in which the drain signal line DL extends. This is performed along the line DL.

For this reason, the electric field direction θ is set to an appropriate value in relation to the initial orientation direction. In general, θ is the gate signal line G of the electric field E.
The absolute value of the angle with respect to L is the drain signal line DL of the electric field E.
Is smaller than the absolute value of the angle with respect to.

In the pixel electrode PX, a portion overlapping the counter voltage signal line CL is formed so as to increase the area thereof, and a capacitor Cadd is formed between the pixel electrode PX and the counter voltage signal line CL. I have. The dielectric film in this case is the above-mentioned insulating film.

The capacitive element Cadd is formed to accumulate a video signal supplied to the pixel electrode PX for a relatively long time, for example. That is, when the scanning signal is supplied from the gate signal line GL, the thin film transistor TFT is turned on, and the video signal from the drain signal line DL is supplied to the pixel electrode PX via the thin film transistor TFT. Thereafter, even when the thin film transistor TFT is turned off, the video signal supplied to the pixel electrode PX is accumulated by the capacitor Cadd.

Then, the thus formed transparent substrate S
A protective film (not shown) made of, for example, a silicon nitride film is formed on the entire surface of the UB1 so that, for example, direct contact of the thin film transistor TFT with the liquid crystal can be avoided.

Further, an alignment film (not shown) for determining the initial alignment direction of the liquid crystal is formed on the upper surface of the protective film. This alignment film is coated, for example, with a synthetic resin film,
As described above, the surface is formed by performing a rubbing process along the extending direction of the drain line.

<< Intersection of Counter Voltage Signal Line with Other Signal Lines >> FIG. 1 is an enlarged view of a portion of the counter voltage signal line CL that intersects with the gate signal line (referred to as CLB in the figure). It is a top view.

In the figure, there is a counter voltage signal base line CLB extending in the y direction in the figure. This counter voltage signal line CLB
Is formed, for example, integrally with each of the opposed voltage signal lines CL running in the display area, and supplies a reference voltage signal to each of the opposed voltage signal lines CL through the opposed voltage signal base line CLB.

The common voltage signal base line CLB is formed to have a larger width than each of the common voltage signal lines CL.
Thus, the overall resistance value of the common voltage signal line is reduced, and the waveform distortion of the supplied reference voltage signal is reduced.

Since the counter voltage signal base line CLB is formed outside the display area (defined as the outline outside the group of pixels), there is a margin in space unlike the display area, and The width is formed to be extremely large as compared with each counter voltage signal line CL in the region.

In the counter voltage signal base line CLB, a slit SL is formed at a portion crossing the gate signal line GL so as to cross the gate signal line GL.

By providing this slit SL, the counter voltage signal base line CLB has two paths at a portion intersecting with the gate signal line GL. For example, as shown in FIG. Even if a short circuit occurs with the signal line GL (indicated by an arrow x in the figure), by dividing the path, the function can be maintained as the counter voltage signal base line CLB on the other path.

As shown in the figure, the path is cut by cutting the path of the short-circuited portion at two places between the short-circuited parts by, for example, scanning with a laser beam (indicated by LR in the figure). To separate from the original counter voltage signal base line CLB.

Here, in this embodiment, the slit S
L is formed on the counter voltage signal base line CLB side. As described above, since the opposed voltage signal base line CLB is formed to have a relatively large width, the formation of the slit SL described above causes a small increase in the resistance value as a whole.

However, the present invention is not limited to the counter voltage signal base line CLB, and it goes without saying that the slit SL may be provided on the gate signal line GL side.

In the above-described embodiment, the number of slits SL formed in the counter voltage signal base line CLB is one. However, as shown in FIG. 5, for example, three or more (two or more) slits are provided. It may be provided.

As described above, since the counter voltage signal base line CLB has a relatively large width, a large number of slits SL can be formed within a certain range.
Also, this is because the increase in the resistance value seen from the whole of the counter voltage signal line is small.

By forming a plurality of slits SL in this manner, there are many other remaining paths with respect to the path divided by the short circuit, in other words, the width of the path to be separated is the other remaining path. The width of the path can be made smaller than the entire width of the path, and the effect of suppressing an increase in the resistance value of the counter voltage signal base line CLB is obtained.

[Embodiment 2] FIG. 6 shows a counter voltage signal base line C.
FIG. 13 is a plan view showing another embodiment of the intersection between the LB and the gate signal line GL, and corresponds to FIG. 1.

In the figure, a slit is provided on the gate signal line GL side. In this case, the slit Sl
Are formed so as to have a sufficient width from one branch point to the other branch point.

Since the gate signal line GL is formed to have a smaller width than the counter voltage signal base line CLB crossing the gate signal line GL, an increase in the resistance of the gate signal line GL is suppressed by the above configuration. Let me.

As shown in FIG. 7, the original gate signal line G
If the width of L is W ₃ , the width of each path branched by the slit SL is W ₁ , and the width from the original gate signal line GL to each path is W ₂ , W ₂ ≧ W
By having the relationship of ₃ , 2W ₁ ≒ W ₃ , an increase in the resistance of the gate signal line GL can be suppressed.

In this case, the gate signal line GL has to be configured so as to be wider at the intersection with the counter voltage signal base line CLB in the extending direction of the counter voltage signal base line CLB.

However, since this portion is a region outside the display region, the width can be made sufficiently large in a range where it does not come into contact with another adjacent gate signal line GL.

In the above-described embodiment, one slit SL is provided, but it goes without saying that a plurality of slits, such as two or three, may be provided as shown in FIG.

Also in this case, by setting the width of each path branched by the slit SL and the width from the original gate signal line GL to each path as described above, the gate signal It is not necessary to increase the resistance of the line GL.

By forming a plurality of slits SL, the width of the path to be separated can be made smaller than the entire width of other remaining paths, and the effect of suppressing an increase in the resistance value of the counter voltage signal line can be suppressed. Play.

Therefore, a portion of the gate signal line GL that intersects the counter voltage signal base line CLB is formed wider than the other portion, and a slit that intersects the counter voltage signal base line CLB in this wide portion is formed by one slit. One or a plurality of the gate signal lines GL may be provided so that the width of the portion intersecting the counter voltage signal base line CLB and the number of slits SL can be set within the range of the allowable resistance value of the entire gate signal line GL. Become.

[Embodiment 3] In each of the above-described embodiments, each of them has the counter voltage signal base line CLB and the gate signal line GL.
3 shows the configuration at the intersection with.

However, as shown in FIG. 9, the counter voltage signal line CL of each pixel region may extend in the y direction in the drawing, that is, in parallel with the drain signal line DL.

In this case, the counter voltage signal base line CLB for connecting the respective counter voltage signal lines CL in common is configured to cross each drain signal line DL.

Therefore, in such a case, it goes without saying that each of the above-described configurations can be applied to the intersection between the counter voltage signal base line CLB and each drain signal line DL.

[0081]

As is apparent from the above description,
According to the liquid crystal display device of the present invention, even if a short circuit occurs at the intersection of the opposite voltage signal line and another signal line, the countermeasure can be taken.

[Brief description of the drawings]

FIG. 1 is a plan view of an essential part showing one embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is an overall plan view showing one embodiment of a liquid crystal display device according to the present invention.

FIG. 3 is a plan view showing one embodiment of a pixel of the liquid crystal display device according to the present invention.

FIG. 4 is an explanatory diagram showing an effect of the liquid crystal display device according to the present invention.

FIG. 5 is a main part plan view showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 6 is a main part plan view showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 7 is a main part plan view showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 8 is a main part plan view showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 9 is an overall plan view showing another embodiment of the liquid crystal display device according to the present invention.

[Explanation of symbols]

CLB: Counter voltage signal base line, CL: Counter voltage signal line, GL: Gate signal line, DL: Drain signal line,
SL ... Slit.

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[Procedure amendment]

[Submission date] April 20, 2000 (200.4.2
0)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 7

[Correction method] Change

[Correction contents]

FIG. 7

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Takanori Nakayama 3300 Hayano Mobara-shi, Chiba Prefecture Hitachi Display Group, Inc. Term (reference) 2H092 GA14 JA26 JA28 JB31 JB35 JB38 KA05 NA16 5C094 AA31 AA32 AA41 AA42 AA43 BA03 BA43 CA19 DA15 DB04 EA03 EA04 EA07 EA10 FA04 5G435 AA19 BB12 CC09 KK10

Claims (5)

[Claims] 1. A display area comprising a set of pixel areas in which a pixel electrode and a counter electrode are formed on a liquid crystal side surface of one of substrates opposed to each other with a liquid crystal interposed therebetween. A common voltage signal line connected to the common electrode extends outside the display area, and has an intersection with another signal line for supplying a signal to each pixel area via an insulating film. And that at least one slit intersecting with the extending direction of the other signal line is formed in at least one of the counter voltage signal line and the other signal line in the superimposed portion. Characteristic liquid crystal display device. 2. A display area comprising a set of pixel areas each having a pixel electrode and a counter electrode formed on a liquid crystal side surface of one of the substrates opposed to each other with a liquid crystal interposed therebetween. A common voltage signal line connected to the common electrode extends outside the display area, and has an intersection with another signal line for supplying a signal to each pixel area via an insulating film. A liquid crystal display device, wherein at least one slit that intersects the extending direction of the other signal line is formed in the counter voltage signal line in the overlapping portion. 3. A display area comprising a set of pixel areas each having a pixel electrode and a counter electrode formed on a liquid crystal side surface of one of the substrates opposed to each other with a liquid crystal interposed therebetween. A common voltage signal line connected to the common electrode extends outside the display area, and has an intersection with another signal line for supplying a signal to each pixel area via an insulating film. A portion of the other signal line that intersects the opposing voltage signal line is formed wider than the other portion, and at least one slit that intersects the opposing voltage signal line is formed in the wide portion. A liquid crystal display device characterized by the above-mentioned. 4. The switching device according to claim 1, wherein a switching element is formed in the pixel region, and the other signal line is a gate signal line for driving the switching element. Liquid crystal display. 5. A switching element is formed in a pixel area, and the other signal line is a drain signal line for supplying a signal to the pixel area through the switching element. The liquid crystal display device according to any one of the above.