JP4884723B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a field effect transistor characterized by the configuration of an electric field relaxation electrode for improving the breakdown voltage in a small-sized high-frequency field effect transistor and a method for manufacturing the same. It is about.

  Considering high-frequency circuit applications of transistors, naturally, transistors require high-speed operation, but at the same time, withstand voltage is often required as in power amplifiers, etc. And withstand voltage are in a trade-off relationship.

  In order to improve the high speed, the distance between the source and the drain is usually shortened as much as possible. However, this causes an increase in the electric field between the gate and the drain, and the withstand voltage is lowered. I will explain.

See FIG.
The upper diagram of FIG. 8 is a schematic perspective view of the carbon nanotube FET, the middle diagram is a sectional view along the channel length direction, and the lower diagram is an electric field distribution diagram between the gate and the drain. In such a carbon nanotube FET, as shown in the middle and lower diagrams, the electric field between the gate and the drain is usually concentrated on the end portion of the gate electrode 66, and the breakdown voltage is determined at this portion.

  As a means for relaxing the electric field between the gate and the drain, there is a method in which an electrode for electric field relaxation is provided between the gate and the drain, and a voltage having the same potential as the gate is applied to the electrode (for example, see Patent Document 1). ).

See FIG.
The upper diagram of FIG. 9 is a schematic perspective view of a high breakdown voltage type carbon nanotube FET provided with an electric field relaxation electrode, the middle diagram is a cross-sectional view along the channel length direction, and the lower diagram is between the gate and the drain. FIG.
As shown in the middle and lower diagrams, by providing the electric field relaxation electrode 67, the electric field distribution shown by the broken line is changed to the electric field distribution shown by the solid line, and the electric field between the gate and the drain is relaxed, so that the breakdown voltage is improved. Will do.

In order to reduce the size or increase the speed of the transistor, the gate electrode is composed of metallic carbon nanotubes (for example, see Patent Document 2), or the channel is composed of semiconducting carbon nanotubes (for example, patents). Reference 3) has also been proposed.
JP 2001-237250 A JP 2003-109974 A JP 2005-116618 A

However, when an electric field relaxation electrode that can be said to be a second gate electrode is newly provided, the interelectrode capacitances C _gs and C _gd increase, and there is a problem that high-speed performance is impaired.

  In addition, since a high-speed FET has a gate-drain distance of the order of submicron, it is difficult to form a new electric field relaxation electrode between the gate and the drain in terms of manufacturing technology.

  In addition, if an electric field relaxation electrode is provided between the gate and the drain on the order of submicrons, the width of the electric field relaxation electrode becomes very thin, and thus inevitably has a high resistance. There is a problem.

  Therefore, an object of the present invention is to provide a fine electric field relaxation electrode having a low resistance between the gate and the drain without causing an increase in capacitance.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
In order to solve the above problem, the present invention is a field effect transistor in which the distance between the gate electrode 6 and the drain electrode (3) is metallic between the gate and the drain of the field effect transistor having a submicron order. An electric field relaxation electrode 8 made of carbon nanotubes exhibiting properties is provided.

  Since the diameter of the carbon nanotube is as thin as about 10 nm, it can be easily provided between the gate and the drain on the order of submicron, and the capacity between the carbon nanotube and the channel is hardly increased, so the distance between the source and the drain is shortened. It is possible to simultaneously realize a high speed by using a carbon nanotube electrode and an electric field relaxation and a high breakdown voltage.

For example, the current gain cutoff frequency f _T , which is an index of the high speed of the transistor, is
f _T -g _m / {2π (C _gs + C _gd )}
Therefore, the breakdown voltage can be improved without causing a decrease in the current gain cutoff frequency f _T by reducing C _gs and C _gd caused by the electric field relaxation electrode 8.

  In addition, since the carbon nanotube has a very low resistance in the major axis direction, the resistance of the electric field relaxation electrode 8 can be reduced, thereby realizing a uniform electric field relaxation in the plane.

  In this case, it is desirable that the gate electrode 6 is also composed of carbon nanotubes exhibiting metallic properties, whereby the resistance of the gate electrode 6 of the microstructure transistor can be reduced, resulting in higher device gain and lower noise. It becomes possible.

  Further, at least one of the gate electrode 6 and the electric field relaxation electrode 8 may be embedded between the substrate 1 and the channel 4 to form an embedded structure.

  As a growth starting point of such carbon nanotubes exhibiting metallic properties, an Fe / Ta laminated thin film 7 in which an Fe film is provided on a Ta film is desirable, and carbon nanotubes exhibiting metallic properties are independent of manufacturing conditions. It becomes possible to form with good reproducibility.

Further, the channel 4 may be made of carbon nanotubes having semiconducting properties, whereby the operation speed of the transistor can be further improved.
In this case, the growth starting point of carbon nanotubes that exhibit semiconducting properties is preferably an Fe / Al laminated thin film in which an Fe film is provided on an Al layer, and carbon nanotubes that exhibit semiconducting properties are reproducible without depending on manufacturing conditions. It becomes possible to form well.

  Alternatively, the channel 4 may be formed of a single crystal semiconductor, and thereby the electric field relaxation electrode 8 with good reproducibility even when the gate-drain distance of the compound semiconductor FET for which manufacturing technology has been established is 1 μm or less. Can be formed

In the case of manufacturing the above-described field effect transistor, the first electrode 2 having a catalytic action composed of an Fe / Al laminated thin film in which an Fe film is provided on an Al layer on an insulating substrate 1 is provided, A second electrode 3 having no catalytic action is provided opposite to the first electrode 2 at a distance, and carbon nanotubes exhibiting semiconducting properties reaching the second electrode 3 are grown from the first electrode 2 as a growth starting point. Then, the channel 4 is formed, and after the gate insulating film 5 is deposited on the channel 4 , the distance between the first electrode 2 or one of the second electrodes 3 serving as the drain electrode on the gate insulating film 5 Is formed at a position on the order of submicron , and then Ta is formed at the end portion between the first electrode 2 or the second electrode 3 serving as the drain electrode and the gate electrode 6. Fe film on the film The Fe / Ta laminated film 7 digits provided may be an electric field relaxation electrodes 8 by growing carbon nanotubes exhibit metallic properties which extend in the channel 4 the width direction of Fe / Ta laminated film 7 as the growth starting point.

  In this case, in the step of forming the gate electrode 6, an Fe / Ta laminated thin film for gate electrode growth in which an Fe film is provided on the Ta film is provided at the channel end, and the gate electrode growth is performed simultaneously with the step of forming the electric field relaxation electrode 8. Carbon nanotubes exhibiting metallic properties extending in the channel width direction using the Fe / Ta laminated thin film for growth as a starting point may be grown as the gate electrode 6, thereby simplifying the manufacturing process. it can.

  In the present invention, both high speed and high breakdown voltage can be achieved by using carbon nanotubes exhibiting metallic properties as the electric field relaxation electrode.

In the present invention, a catalyst electrode made of an Fe / Al laminated thin film in which an Fe film is provided on an Al layer is provided on an insulating substrate, and a non-catalyst electrode facing the catalyst electrode at a distance is provided so that a direct current is applied in the growth direction. Single-walled carbon nanotubes exhibiting semiconducting properties that reach the non-catalytic electrode with the Fe film as a growth starting point with the boundary applied are grown into a channel, and then a gate insulating film is deposited on the channel and then the gate insulating film is formed on the channel. A gate electrode is formed at a position where the distance from one of the catalyst electrodes or non-catalyst electrodes that is the drain electrode is on the order of submicron , and then one of the catalyst electrodes or non-catalyst electrodes that is to be the drain electrode Fe / Ta laminated thin film with Fe / Ta laminated thin film provided with Fe film on Ta film at the edge between electrode and gate electrode, with DC electric field applied in the growth direction Film is grown multiwall carbon nanotubes exhibit metallic properties extending in the channel width direction as the growth starting point is to form an electric field relaxation electrodes.

Here, with reference to FIG. 2 thru | or FIG. 4, the manufacturing process of carbon nanotube FET of Example 1 of this invention is demonstrated.
See Figure 2
First, an Al film 13 having a thickness of, for example, 5 nm and an Fe film 14 having a thickness of, for example, 1 nm having a catalytic action are sequentially deposited on the sapphire substrate 11 by a sputtering method using a resist pattern as a mask. The source electrode 12 is formed by removing the pattern.

  Next, an Al film having a thickness of, for example, 6 nm is deposited again by sputtering using the resist pattern as a mask so as to face the source electrode 12 with a gap of, for example, 5 μm, and the drain is removed by removing the resist pattern. The electrode 15 is used.

See Figure 3
Next, using plasma CVD, acetylene gas is used as a process gas, Ar gas or hydrogen gas is used as a carrier gas, and a DC electric field is applied between the source electrode 12 and the drain electrode 15, for example, 100 Pa The carbon nanotubes 16 are formed by applying RF power at a growth temperature of 600 ° C. under pressure.
In this case, although not shown, the carbon nanotubes 16 actually grow from the entire upper surface of the source electrode 12 toward the drain electrode 15.

  At this time, for example, the Fe film 14 constituting the surface of the source electrode 12 at a growth temperature of 600 ° C. becomes particulate due to the influence of the temperature. The diameter of the particle reflects the wettability with the underlying Al. Thus, the growing carbon nanotubes 16 become single-walled carbon nanotubes having semiconducting properties, and thus constitute a channel.

In addition, since a DC electric field is applied between the source electrode 12 and the drain electrode 15 in the growth state, the carbon nanotubes 16 grow toward the drain electrode 15 using the Fe film 14 on the source electrode 12 as a growth starting point, and the drain The growth is terminated when the electrode 15 is sufficiently reached.
For example, the growth time is 40 minutes.

Next, a SiO ₂ film 17 having a thickness of, for example, 10 nm is deposited by CVD to fill the gaps between the carbon nanotubes 16, and the portion deposited on the carbon nanotubes 16 is used as a gate insulating film.

  Next, the gate electrode 18 is formed by sequentially depositing a Ti film 19 having a thickness of, for example, 10 nm and a Pt layer 20 having a thickness of, for example, 100 nm by sputtering using the resist pattern as a mask, and then removing the resist pattern. Form.

  Next, a Ta film 22 having a thickness of, for example, 5 nm and an Fe film 23 having a catalytic action of, for example, 1 nm in thickness are sequentially deposited by sputtering using a resist pattern having an opening of 100 nm × 100 nm as a mask. After that, the growth pattern 21 is obtained by removing the resist pattern.

  Next, using plasma CVD, acetylene gas is used as a process gas, Ar gas or hydrogen gas is used as a carrier gas, and a direct current electric field is applied in a direction along the gate electrode 18, for example, a pressure of 100 Pa Then, by applying RF power at a growth temperature of 600 ° C., the electric field relaxation electrode 24 made of carbon nanotubes is formed, thereby completing the basic structure of the carbon nanotube FET of Example 1 of the present invention.

  At this time, for example, the Fe film 14 constituting the surface of the source electrode 12 at the growth temperature of 600 ° C. becomes particulate due to the influence of temperature. The diameter of the particle reflects the wettability with the underlying Ta. Therefore, the carbon nanotubes to be grown are multi-walled carbon nanotubes having a metallic property and having a diameter of about 10 nm, for example.

  In addition, since a direct current electric field is applied in a direction along the gate electrode 18 in the growth state, the carbon nanotubes grow in a direction parallel to the gate electrode 18.

See Figure 4
The upper diagram of FIG. 4 is a schematic perspective view of the carbon nanotube FET of Example 1 of the present invention, the middle diagram is a sectional view along the channel length direction, and the lower diagram is the electric field distribution between the gate and the drain. FIG.
In the carbon nanotube FET of Example 1 of the present invention, as shown in the middle and lower diagrams, the electric field between the gate and the drain is relaxed by the electric field relaxation electrode 24 and the breakdown voltage is improved.

  In Example 1 of the present invention, since the electric field relaxation electrode 24 is composed of carbon nanotubes having a diameter of about 10 nm, there is almost no increase in capacitance between the electric field relaxation electrode and the channel, and between the source and drain. High speed by shortening the distance and electric field relaxation and high breakdown voltage by the electric field relaxation electrode 24 can be realized at the same time.

  In addition, since the diameter of the carbon nanotube is as small as about 10 nm, it is easy to form an electric field relaxation electrode on a fine transistor having a gate-drain distance of submicron order.

  Furthermore, since carbon nanotubes having metallic properties have a very low resistance in the major axis direction, even in the case of the thin electric field relaxation electrode 24, a signal delay due to the high resistance does not occur.

Next, the carbon nanotube FET of Example 2 of the present invention will be described with reference to FIG. 5. Since the basic manufacturing process is the same as that of Example 1, only the final device configuration diagram is shown. Show.
See Figure 5
The upper diagram of FIG. 5 is a schematic perspective view of the carbon nanotube FET of Example 2 of the present invention, and the lower diagram is a cross-sectional view along the channel length direction.
First, in the same manner as in the first embodiment, after forming the source electrode 12 composed of the Al film 13 and the Fe film 14 on the sapphire substrate 11, the drain electrode 15 is formed so as to face the source electrode 12.

Next, carbon nanotubes 16 having semiconducting properties are formed between the source electrode 12 and the drain electrode 15 to form channels, and an SiO ₂ film 17 is deposited to fill the gaps between the carbon nanotubes 16 and on the carbon nanotubes 16. The deposited portion is used as a gate insulating film.

  Next, a Ta film 22 having a thickness of, for example, 5 nm and a catalytic action having a thickness of, for example, 1 nm are formed by sputtering using a resist pattern having an opening of 100 nm × 100 nm and an opening of 1000 nm × 2000 nm as a mask. After sequentially depositing the Fe film 23, the resist pattern is removed to form growth electrodes 21 and 25.

Next, using plasma CVD, acetylene gas is used as a process gas, Ar gas or hydrogen gas is used as a carrier gas, and a DC electric field is applied in a direction along the channel width, for example, at a pressure of 100 Pa The basic structure of the carbon nanotube FET of Example 2 of the present invention is completed by forming the electric field relaxation electrode 24 and the gate electrode 26 made of carbon nanotubes by applying RF power at a growth temperature of 600 ° C. .
Here, for convenience of illustration, the gate electrode 26 is formed of two carbon nanotubes, but the number of carbon nanotubes constituting the gate electrode 26 is arbitrary.

  In the second embodiment of the present invention, since the gate electrode 26 is also composed of carbon nanotubes having a very low resistance, it is possible to simultaneously realize a reduction in gate resistance, a reduction in gate-drain capacitance, and a reduction in gate-source capacitance, By using this carbon nanotube FET for an amplifier, it is possible to reduce noise and increase gain.

Next, a carbon nanotube FET of Example 3 of the present invention will be described with reference to FIG. 6. Since the basic manufacturing process is the same as that of Example 1, only the final device configuration diagram is shown. Show.
See FIG.
The upper part of FIG. 6 is a schematic perspective view of the carbon nanotube FET of Example 3 of the present invention, and the lower part is a cross-sectional view along the channel length direction.
First, a Ta film 29 having a thickness of, for example, 5 nm and a thickness of, for example, 1 nm are formed on the sapphire substrate 11 by sputtering using a resist pattern having an opening of 100 nm × 100 nm and an opening of 1000 nm × 2000 nm as a mask. After sequentially depositing the Fe film 30 having the catalytic action, the resist pattern is removed to form the growth electrodes 27 and 28.

  Next, using plasma CVD, acetylene gas is used as a process gas, Ar gas or hydrogen gas is used as a carrier gas, and a DC electric field is applied in a direction along the channel width, for example, at a pressure of 100 Pa By applying RF power at a growth temperature of 600 ° C., the gate electrode 31 made of metallic carbon nanotubes and the electric field relaxation electrode 32 are formed using the growth electrodes 27 and 28 as growth starting points.

Next, the gap between the gate electrode 31 and the electric field relaxation electrode 32 formed by depositing the SiO ₂ film 33 and the periphery thereof are filled, and the portion deposited on the gate electrode 31 is used as a gate insulating film.

Next, after forming the source electrode 34 composed of the Al film 35 and the Fe film 36 on the SiO ₂ film 33, the drain electrode 37 is formed so as to face the source electrode 34.

Next, after forming a carbon nanotube 38 having semiconductor properties between the source electrode 34 and the drain electrode 37 to form a channel, an SiO ₂ film 39 is deposited to fill the gap between the carbon nanotubes 38. The basic structure of the carbon nanotube FET of Example 3 is completed.

  In the third embodiment of the present invention, a carbon nanotube having metallic properties is used as the gate electrode and the electric field relaxation electrode, and a carbon nanotube having semiconductor properties is used as the channel, thereby providing a high breakdown voltage buried gate structure. The FET can be configured with good reproducibility.

Next, with reference to FIG. 7, the high voltage | pressure-resistant MESFET of Example 4 of this invention is demonstrated.
See FIG.
First, after sequentially growing an i-type GaAs operation layer 41 and an n ⁺ -type GaAs layer on the semi-insulating GaAs substrate 41 by using the MBE method, the source contact region 43 is formed by patterning the n ⁺ -type GaAs layer. The drain contact region 44 is formed.

Next, a SiO ₂ film 45 having a thickness of, for example, 0.4 μm is formed on the entire surface by plasma CVD, and then an opening for gate contact is provided, and then a W silicide layer 47 and an Au layer 48 are sequentially deposited. After that, the gate electrode 46 is formed by patterning the laminated film by ion milling.

  Next, a Ta film 50 having a thickness of, for example, 5 nm and a thickness of, for example, 1 nm are formed by sputtering using a resist pattern having an opening of 100 nm × 100 nm in the vicinity of the drain contact region 44 side of the gate electrode 46 as a mask. After sequentially depositing the Fe film 51 having the catalytic action, the resist pattern is removed to obtain the growth electrode 49.

  Next, using plasma CVD, acetylene gas is used as a process gas, Ar gas or hydrogen gas is used as a carrier gas, and a DC electric field is applied in a direction along the gate electrode 46, for example, a pressure of 100 Pa In FIG. 5, the basic structure of the high voltage MESFET of Example 4 of the present invention is formed by forming the electric field relaxation electrode 52 made of multi-walled carbon nanotubes having metallic properties by applying RF power at a growth temperature of 600 ° C. Is completed.

  Thus, by using a small-diameter carbon nanotube as the electric field relaxation electrode, both high speed and high breakdown voltage can be achieved even in a MESFET using a single crystal semiconductor layer as a channel.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made. For example, it is necessary for the growth of carbon nanotubes. The source gas is not limited to acetylene gas, and hydrocarbon gas such as methane or ethylene or alcohol gas such as methanol may be used, and the growth method is not limited to the CVD method, but arc discharge. Alternatively, other growth methods such as a laser ablation method may be used.

  In the above embodiment, Fe that can control the conductive properties of the carbon nanotubes grown on the substrate is used as a catalyst. However, the present invention is not limited to Fe, and Co, Ni, Pt, Rh, An alloy of one or more types of catalyst and one or more types of Ti, Mo, Al, Ta, etc. may be used. The shape of the catalyst is not limited to a thin film, and the diameter is controlled by a differential electrostatic classifier or the like. In such a case, if the growth conditions such as the source gas, the growth temperature, and the underlying metal are suitable for the process of growing the metallic carbon nanotube and the semiconducting carbon nanotube, good.

In the above-described Examples 1 to 3, sapphire is used as the substrate. However, the substrate is not limited to sapphire, and any insulating substrate that can withstand the growth temperature of carbon nanotubes may be used. A heat-resistant glass such as (registered trademark) may be used, or a substrate in which an insulating film such as a SiO ₂ film is provided on the surface of a silicon substrate or the like may be used.

  In the third embodiment, both the gate electrode and the electric field relaxation electrode have a buried structure, but only one of them may be buried and the other may be provided on the surface side. .

  In the first and second embodiments, the gate electrode and the electric field relaxation electrode are provided at the same height. For example, the region of the insulating film that becomes the gate insulating film is lightly etched to form the recess. The gate electrode is formed in this recess, and the thickness of the other region of the insulating film to be the passivation film is increased, and the influence of the electric field applied to the channel by the gate electrode and the electric field applied to the channel by the electric field relaxation electrode is affected. It may be different.

In the second and third embodiments, the channel, the gate electrode, and the electric field relaxation electrode are formed in separate steps, but may be formed in a single growth step.
In this case, the thickness of the Al film that is the base of the source electrode for growing the channel and the thickness of the Ta film that is the base of the growth electrode that is the growth starting point of the gate electrode and the electric field relaxation electrode is about the diameter of the carbon nanotube. What is necessary is just to grow so that a difference may be provided and each carbon nanotube may cross | intersect through space.

  In this case, in order to control the growth direction of the carbon nanotubes, it is desirable to apply an electric field from an oblique direction such as 45 ° with respect to a line connecting the source and drain during growth. Further, SOG (Spin On Glass) may be spin-coated after the growth of the carbon nanotubes to form a gate insulating film between the channel, the gate electrode, and the electric field relaxation electrode, and fill the space between the carbon nanotubes. .

  In Example 4, the basic structure is a compound semiconductor such as GaAs. However, the basic structure is not limited to a compound semiconductor, but is applied to a MOSFET having a silicon substrate or a SiGe layer provided on the silicon substrate as an active region. In the case of a MOSFET, metallic carbon nanotubes may be employed as the gate electrode.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Again see Figure 1
(Additional remark 1) The electric field relaxation electrode 8 which consists of a carbon nanotube which shows a metallic property was provided between the gate-drain of the field effect transistor whose space | interval of the gate electrode 6 and the drain electrode (3) is a submicron order. A characteristic field-effect transistor.
(Supplementary note 2) The field effect transistor according to supplementary note 1 , wherein the gate electrode 6 is made of carbon nanotubes exhibiting metallic properties.
(Supplementary Note 3) at least one of the gate electrode 6 and the field relaxation electrodes 8, according to Appendix 1 or Appendix 2, characterized in that a buried structure embedded between the substrate 1 and the channel 4 Field effect transistor.
As (Supplementary Note 4) growth origin of the carbon nanotubes showing the metallic properties, to any one of Appendices 1 to Appendix 3, characterized in that using the Fe / Ta laminated film 7 having a Fe film on the Ta film The field effect transistor described.
(Supplementary note 5) The field effect transistor according to any one of supplementary notes 1 to 4, wherein the channel 4 is made of a carbon nanotube exhibiting semiconducting properties.
(Supplementary Note 6) as a growth starting point of carbon nanotubes showing the semiconductor property, the field-effect transistor according to Note 5, characterized in that using the Fe / Al laminated film in which a Fe film on the Al film.
(Supplementary note 7) The field effect transistor according to any one of supplementary notes 1 to 4, wherein the channel 4 is made of a single crystal semiconductor.
(Additional remark 8) While providing the 1st electrode 2 which has the catalytic action which consists of an Fe / Al laminated thin film which provided the Fe film | membrane on the Al film | membrane on the insulating board | substrate 1, the said 1st electrode 2 is spaced apart from the said 1st electrode 2. The second electrode 3 having no opposing catalytic action is provided, and a carbon nanotube exhibiting semiconducting properties reaching the second electrode 3 is grown from the first electrode 2 as a growth starting point to form a channel 4. A step of depositing a gate insulating film 5 on the channel 4, and a distance between the first electrode 2 or one of the second electrodes 3 serving as a drain electrode on the gate insulating film 5 is submicron. A step of forming the gate electrode 6 at the position to be ordered, and Ta at one end of the first electrode 2 or the second electrode 3 between the one electrode serving as the drain electrode and the gate electrode 6. Fe film was provided on the film a step of providing an electric field relaxation electrode 8 by providing an e / Ta multilayer thin film 7 and growing carbon nanotubes having metallic properties extending in the width direction of the channel 4 using the Fe / Ta multilayer thin film 7 as a growth start A method of manufacturing a field effect transistor.
In (Supplementary Note 9) the step of forming the gate electrode 6, the channel 4 an end provided with a gate electrode growth for Fe / Ta laminated film having a Fe film on the Ta film, and the step of forming the field relaxation electrode 8 at the same time 9. The field effect according to appendix 8 , wherein a carbon nanotube exhibiting metallic properties extending in the width direction of the channel 4 is grown from the Fe / Ta laminated thin film for gate electrode growth as a growth starting point to form a gate electrode 6. Type transistor manufacturing method.
(Additional remark 10) While providing the 1st electrode 2 which has the catalytic action which consists of a Fe / Al laminated thin film which provided Fe film | membrane on the Al film | membrane on the insulating board | substrate 1, the said 1st electrode 2 is spaced apart from the said 1st electrode 2. And providing a second electrode 3 having no opposing catalytic action, a first opening on the insulating substrate 1 and larger than the first opening and the first electrode 2 or the second electrode. The Fe / Ta laminated thin film having a catalytic action is deposited by using a resist pattern having a second opening as a mask at a position where the distance from one of the electrodes 3 serving as the drain electrode is in the submicron order. Forming a third electrode in the first opening, forming a fourth electrode in the second opening, and reaching the second electrode 3 using the first electrode 2 as a growth starting point; A car that is a channel that exhibits semiconducting properties Nanotubes, carbon nanotubes serving as electric field relaxation electrodes 8 exhibiting metallic properties extending in the channel width direction from the third electrode as a growth starting point, and extending in the channel width direction from the fourth electrode as a growth starting point A step of forming a carbon nanotube to be a gate electrode 6 exhibiting existing metallic properties by a single growth, the channel, the gate electrode 6, the electric field relaxation electrode 8 and between the channel and the gate electrode 6, and the channel and the electric field. A method of manufacturing a field effect transistor, comprising a step of forming an insulating film between the relaxation electrodes 8.

  As an application example of the present invention, a transistor for a high-frequency circuit and a manufacturing method thereof are typical, but it is not limited to a high-frequency circuit, and as a manufacturing method, an Fe base serving as a catalyst is made of Al. By selectively providing growth electrodes made of Si and Ta, it becomes possible to simultaneously grow semiconducting carbon nanotubes and metallic carbon nanotubes at arbitrary positions.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of carbon nanotube FET of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 2 of carbon nanotube FET of Example 1 of this invention. It is explanatory drawing of carbon nanotube FET of Example 1 of this invention. It is explanatory drawing of carbon nanotube FET of Example 2 of this invention. It is explanatory drawing of carbon nanotube FET of Example 3 of this invention. It is explanatory drawing of the high voltage | pressure-resistant MESFET of Example 4 of this invention. It is explanatory drawing of the conventional carbon nanotube FET. It is explanatory drawing of the conventional high voltage | pressure-resistant carbon nanotube FET.

DESCRIPTION OF SYMBOLS 1 Substrate 2 First electrode 3 Second electrode 4 Channel 5 Gate insulating film 6 Gate electrode 7 Fe / Ta laminated thin film 8 Electric field relaxation electrode 11 Sapphire substrate 12 Source electrode 13 Al film 14 Fe film 15 Drain electrode 16 Carbon nanotube 17 SiO ₂ film 18 Gate electrode 19 Ti film 20 Pt layer 21 Growth electrode 22 Ta film 23 Fe film 24 Electric field relaxation electrode 25 Growth electrode 26 Gate electrode 27 Growth electrode 28 Growth electrode 29 Ta film 30 Fe film 31 Gate electrode 32 Electric field relaxation electrode 33 SiO ₂ film 34 Source electrode 35 Al film 36 Fe film 37 Drain electrode 38 Carbon nanotube 39 SiO ₂ film 41 Semi-insulating GaAs substrate 42 i-type GaAs operation layer 43 Source contact region 44 Drain contact region 45 SiO ₂ film 46 Gate electrode 47 W silissa Id layer 48 Au layer 49 Growth electrode 50 Ta film 51 Fe film 52 Electric field relaxation electrode 61 Sapphire substrate 62 Source electrode 63 Drain electrode 64 Carbon nanotube 65 SiO ₂ film 66 Gate electrode 67 Electric field relaxation electrode

Claims (5)

A field effect transistor comprising a field relaxation electrode made of carbon nanotubes exhibiting metallic properties between a gate and a drain of a field effect transistor having a distance between a gate electrode and a drain electrode of submicron order . 2. The field effect transistor according to claim 1 , wherein the gate electrode is made of carbon nanotubes exhibiting metallic properties. Wherein at least one of the gate electrode and the electric field relaxation electrodes, field-effect transistor according to claim 1 or claim 2, characterized in that a buried structure embedded between the substrate and the channel. The field effect transistor according to any one of claims 1 to 3, characterized in that the channel consists of carbon nanotubes having semiconductor properties. A first electrode having a catalytic action composed of an Fe / Al laminated thin film in which an Fe film is provided on an Al film is provided on an insulating substrate, and has a catalytic action facing the first electrode with an interval. A step of providing a second electrode not to be grown and growing a carbon nanotube exhibiting semiconducting properties reaching the second electrode with the first electrode as a growth starting point to form a channel; A step of forming a gate electrode on the gate insulating film at a position where an interval between the first electrode or the second electrode serving as a drain electrode of the first electrode or the second electrode is on the order of submicron , and An Fe / Ta laminated thin film in which an Fe film is provided on a Ta film is provided at an end portion between one electrode serving as a drain electrode of the first electrode or the second electrode and the gate electrode, and the Fe / Ta T FET manufacturing method of a transistor characterized by having a step of carbon nanotubes exhibit metallic properties extending in the channel width direction of the laminated film as the growth starting point is grown to form an electric field relaxation electrodes.

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