JP3963686B2 - Carbon nanotube gate high electron mobility transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a transistor, and more particularly to a field effect transistor using a carbon nanotube exhibiting metallic properties as a gate material.
The present invention also relates to a fine pattern forming method using carbon nanotubes as a mask material for dry etching.
[0002]
[Prior art]
Increasing the density of semiconductor LSIs has been promoted by microfabrication technology of semiconductor elements and wirings as constituent elements. The fine processing of a semiconductor LSI is performed by first etching a base using a resist patterned in a lithography process as a mask. Therefore, both the resolution and the etching resistance are characteristics required for the resist. However, the conventional organic polymer resist cannot resolve a pattern of 10 nm class smaller than the polymer size, and the dry etching resistance is not sufficient. Therefore, the pattern transfer to another film is necessary for the etching.
[0003]
[Problems to be solved by the invention]
Currently, the shortest gate length of a transistor is reported to be 8 nm in a MOS structure transistor manufactured by electron beam exposure. In this case, since the resolution of the resist has almost reached its limit, the formed gate has a large dimensional fluctuation and poor linearity, which is not suitable for practical use. In general, gate miniaturization is most effective for improving the high-speed and high-frequency performance of a single transistor. Therefore, a technique for reducing fluctuations in place of using a resist is desired as a gate processing technique with a size of 10 nm or less.
[0004]
A HEMT (High Electron Mobility Transistor) fabricated on an InP substrate is known as one having the highest performance as a high-frequency transistor. The highest performance HEMT reported by Endo et al. Has a gate length of 25 nm and a cutoff frequency f. _T Has reached about 400 GHz (A. Endoh et al., IPRM'01, pp 448-51 (2001)). On the other hand, for the high-speed optical communication network, a communication speed of 40 Gbps is in the development stage in the TDM system, but in the future, it is desired to realize 80 and 160 Gbps (FIG. 1). In that case, as an electronic device characteristic required for communication in the light modulation system, f _T In general, a frequency that is 4 to 5 times the communication speed is required, so for example, if the communication speed is 160 Gbps, the frequency f is 640 to 800 GHz. _T Is expected to be needed. F of electronic devices _T It is known that there is a certain degree of correlation between the gate length and the gate length, and FIG. 2 is a graph of this, which corresponds to the gate length realized so far in this figure f _T Extrapolating the relationship with (indicated by the solid line in the figure) f of about 800 GHz _T It can be seen that the gate length must be less than 10 nm in order to obtain Thus, in order to meet the demand for high-speed communication in the near future, further miniaturization of the gate is considered essential.
[0005]
An object of the present invention is to respond to a demand for miniaturization of a gate more than ever, and an object of the present invention is to provide a field effect transistor having a fine gate with no dimensional fluctuation.
It is also an object of the present invention to provide a fine pattern forming method that enables formation of a fine structure including such a fine gate.
[0006]
[Means for Solving the Problems]
The field effect transistor of the present invention uses metallic carbon nanotubes as a material that enables realization of a fine gate. Specifically, the field effect transistor of the present invention includes a source that supplies carriers, that is, electrons or holes that contribute to electrical conduction in a semiconductor device such as a transistor, a drain that receives carriers, and a current between them. A field effect transistor including a gate as a current control electrode for controlling a current flowing through a channel by changing a conductivity of the channel as a passage, wherein the gate is made of metallic carbon nanotubes It is a field effect transistor.
[0007]
In the method for forming a fine pattern according to the present invention, it is possible to form a fine pattern free from dimensional fluctuations by using carbon nanotubes as an etching mask. Specifically, in the fine pattern forming method of the present invention, carbon nanotubes are arranged on an underlayer, and the shape of the nanotubes is transferred to the underlayer by performing dry etching using the carbon nanotubes as a mask. It is a fine pattern forming method characterized by patterning a formation.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, as a gate material of a field effect transistor or as a mask material for pattern formation by dry etching, a self-organized nanostructure is a cylindrical structure composed of carbon elements, Generally known carbon nanotubes are used.
[0009]
Carbon nanotubes are a new carbon material that has recently attracted attention due to its unique properties. The carbon nanotube has a tube structure in which a graphite sheet formed by connecting carbon atoms in a hexagonal shape with the strongest bond called sp2 bond is wound in a cylindrical shape. The diameter of the tube reaches a minimum of 0.4 nm and the length reaches several hundred μm. Further, since the carbon nanotube is a nanostructure formed by carbon atoms growing in a self-organized manner, there is a feature that the dimensional fluctuation is extremely small. Furthermore, it is known that carbon nanotubes vary widely in electrical conductivity from semiconducting to metallic due to differences in chirality. In the case of metallic carbon nanotubes with metallic electrical conductivity, if there are no lattice defects, the charge exhibits non-scattering (ballistic) conduction in the nanotubes, and the resistance is a quantum resistance value (6 .5Ω) is known.
[0010]
Conventionally, arc discharge and laser ablation have been used for the production of carbon nanotubes, but recent studies have reported that they can also be produced by plasma CVD or thermal CVD. A method using arc discharge or the like is a method that enables production of high-purity nanotubes, but is not suitable for manufacturing semiconductor devices, whereas a method using CVD can be said to be effective for application to semiconductor devices.
[0011]
The present invention provides a field effect transistor having a fine gate with no dimensional fluctuation by applying a carbon nanotube having a diameter of 10 nm or less to a gate electrode of a transistor or a processing technique thereof. A processing technique for forming a fine pattern using a carbon nanotube as a mask is applicable not only to the gate of a transistor but also to a case where a particularly fine pattern is required in a semiconductor device or the like.
[0012]
FIG. 3 shows a first embodiment of a field effect transistor according to the present invention. For comparison, FIG. 4 shows a conventional field effect transistor.
Referring to FIGS. 3 and 4, the substrate 11 is made of InP in both the conventional field effect transistor (FIG. 4) and the present invention (FIG. 3), and the HEMT (High Electron Transfer) is formed thereon. Heterojunction structure is formed. Specifically, an InAlAs buffer layer 12, an InGaAs channel layer 13, an InAlAs electron supply layer 15 with Si donor δ-doping 14, an InP cap layer 16, n ⁺ The InGaAs ohmic layer 17 is sequentially crystal-grown by MBE (molecular beam epitaxy) or MOCVD (metal organic chemical vapor deposition). The source 21 and the drain 22 are made of AuGe / Ni / Au as an ohmic electrode, and are subjected to an alloying treatment for reducing resistance at a temperature of about 450 ° C. The difference between the field effect transistor of the present invention (FIG. 3) and the conventional field effect transistor (FIG. 4) is that the material of the gate electrodes 23 (present invention, FIG. 3) and 23 ′ (prior art, FIG. 4) In contrast to the use of WSi or the like, the former uses carbon nanotubes having metallic properties. The shape of the gate electrode 23 reflects the difference in material for the structure of the gate electrode. Are different. As will be described below, the carbon nanotubes in the present invention are disposed in the active layer portion of the transistor to form a so-called “finger” portion of the gate, while the portion for electrical connection between the gate and the outside ( That is, the lead-out portion of the gate electrode is formed in the same manner as the conventional transistors, and thus has the same shape as the conventional transistors. Therefore, the gate 23 of FIG. 3 showing the transistor of the present invention is connected to such a gate electrode lead-out portion (indicated by an imaginary line in the figure) behind the gate 23. The surface of portions other than the source 21, drain 22, and gates 23, 23 ′ is made of SiO as a surface passivation film. ₂ Insulating film coatings 25 and 26 are applied.
[0013]
The gate electrode 23 'in the conventional field effect transistor is manufactured as follows. FIG. 5A shows a source 21, drain 22, SiO 2 on an InP substrate 11 on which the various layers 12, 13, 15, 16, 17 mentioned above are formed. ₂ The place where the film 25 is provided is shown. Next, as shown in FIG. 5B, a resist pattern 31 is formed on the surface of the substrate, and SiO 2 is used as a mask. ₂ Membrane 25 and n ⁺ The InGaAs layer 17 is etched to form an opening 32 for forming a gate. After the resist pattern 31 is removed, the entire surface of the substrate is SiO. ₂ A film 26 is formed (FIG. 5C). Next, as shown in FIG. 6A, a resist pattern 34 for forming a gate is formed, and this is used as a mask for SiO. ₂ The film 26 is etched to form an opening 35. After removing the resist pattern 34, as shown in FIG. ₂ Another resist pattern 36 is formed so that a part of the film 26 is exposed, and the exposed SiO 2 is exposed. ₂ The InP layer 16 is etched using the film 26 as a mask to form a hole 37. Next, a gate electrode material is deposited, and a gate electrode 23 ′ is formed using a lift-off method as shown in FIG. Subsequently, SiO ₂ A part of the film 26 is removed to partially expose the source 21 and the drain 22 to obtain the field effect transistor according to the prior art described with reference to FIG. As described above, the lithography technique and the lift-off method are used to manufacture the gate electrode 23 ′ of the conventional field effect transistor, and a practical gate electrode can only have a minimum thickness of 25 nm.
[0014]
FIG. 8 is a schematic top view of a conventional field effect transistor. In this figure and a similar top view of the transistor referred to below, the source, drain, gate, and active region (indicated by 40 in the figure) that are the basic components of the transistor are schematically shown. I will show it in
[0015]
FIG. 7 corresponds to the cross section taken along the line AA of FIG. 8, and the SiO shown in FIG. ₂ The portion of the hole 37 provided in the film 26 and the underlying InP layer 16 (where the transistor current control gate electrode is located) corresponds to the portion indicated by 37x in FIG. As is apparent from the figure, this portion is formed so as to cross the active layer 40 of the field effect transistor. In FIG. 8, a portion 23a ′ of a region where the portion 37x does not exist (region above the imaginary line 39 in the drawing) corresponds to a lead portion of the gate electrode.
[0016]
A gate portion, which is a feature of the field effect transistor of the present invention described with reference to FIG. 3, is taken out and shown in a perspective view of FIG. The gate 23 is made of SiO ₂ A carbon nanotube located in the opening 35 (FIG. 6A) of the film 26 and the hole 37 (FIG. 6B) formed in the underlying InP layer 16 (for simplicity, this figure and the following) In the figure referred to in FIG. One end of the carbon nanotube is connected to the gate electrode lead portion 23a formed in the same manner as the production of the lead portion 23a ′ of the gate 23 ′ of the conventional transistor described above. Thus, the carbon nanotube corresponding to the gate metal has a structure extending from the base of the gate electrode lead portion 23a.
[0017]
The manufacture of the field effect transistor according to the embodiment of the present invention shown in FIG. 3 will be described with reference to FIGS. After the gate electrode is formed in the same manner as described with reference to FIGS. 5A to 5C, FIGS. 6A, 6B, and 7, the carbon nanotube gate 23 (“ The gate metal in the region to be formed (also referred to as “gate finger”) (FIG. 9) is removed by patterning to leave the gate electrode lead portion 23a, and then the resist (not shown) used therefor is removed (FIG. 10A). )). The groove indicated by 41 in FIG. 10A corresponds to the hole 37 in FIG. 6B, and the gate of the carbon nanotube is formed in this groove. Next, another resist pattern 43 is formed as shown in FIG. 10B, and Ni, Co, Fe or the like serving as a catalyst for producing carbon nanotubes is formed in the opening 44 that communicates with the root of the gate electrode lead portion 23a. The transition metal fine particles, or the fine particles of such transition metal alloys are deposited. The resist pattern 43 is removed, and as shown in FIG. 11, the carbon nanotubes 46 serving as gate fingers are grown while the direction is controlled by the CVD method using the deposited transition metal catalyst 45. Control of this growth direction can be achieved by performing thermal CVD growth while applying an electric field in the direction in which the carbon nanotubes are to be grown. The electric field used here is a DC electric field.
[0018]
Another method for growing the carbon nanotube of the gate finger will be described with reference to FIGS. 12 (a) and 12 (b). As shown in FIG. 12 (a), SiO is treated in the same manner as described above. ₂ A groove 51 for growing carbon nanotubes is formed in the film 26 and the underlying InP layer 16 (FIG. 3), a transition metal catalyst 52 is deposited on both ends of the groove 51, and CVD is performed while applying an electric field. The carbon nanotubes 53 are grown by the method. In this case, by using an AC electric field, the carbon nanotube 53 grows from both ends of the groove 51 toward the center of the groove 51, and finally connects at the center to form one tube 54. (FIG. 12B).
[0019]
In another embodiment of the field effect transistor of the present invention, a carbon nanotube housed in a V-shaped groove formed on a semiconductor substrate is used as a gate. In this case, the position and direction controllability of the carbon nanotube can be improved by growing the carbon nanotube in a V-shaped groove provided in the semiconductor substrate. By using an InP substrate and etching the substrate with HCl gas using an insulating film as a mask, highly selective etching is possible due to the difference in plane orientation, and a nanometer-level sharp groove can be formed. Furthermore, by utilizing the fact that carbon can be plated with a metal such as Ni, it is possible to bury such a metal in a V-shaped groove where carbon nanotubes exist, thereby reducing the resistance of the gate.
[0020]
This aspect will be described with reference to the drawings.
First, in the manner described above with reference to FIGS. 5A to 5C and FIG. 6A, the source 21, the drain 22, and the insulating film 26 are provided. ₂ A substrate in which an opening 35 (FIG. 6A) is provided in the insulating film 26 is prepared. Next, as shown in FIG. 13A, a resist pattern 61 for forming a gate is formed, and the InP layer 16 is dry etched at high temperature using HCl gas. The etching mask at this time is not the resist pattern 61 but the SiO exposed at the opening. ₂ This is the insulating film 26. The longitudinal direction of the opening pattern of the insulating film 26 (the direction in which carbon nanotubes are grown later) is previously aligned with the (110) direction of the InP layer 16. When the InP layer 16 is dry etched at such a high temperature, a groove having a V-shaped cross section and a very sharp V-shaped bottom can be automatically formed, and an InP crystal is formed on the side surface of the V-shaped groove. It was found that the (111) B plane of
[0021]
Subsequently, when an InP growth source gas (trimethylindium, phosphine, etc.) is supplied and InP MOCVD is performed, crystals do not grow on the (111) B surface of the side wall of the V-shaped groove, and the bottom part of the groove You can only selectively grow and fill the pointed bottom. The width W of the bottom surface of the V-shaped groove thus formed _L As shown in FIG. 17, it can be controlled by the growth temperature. By using this technique, it is possible to obtain a groove 62 (FIG. 13B) having a bottom surface width necessary for stably growing carbon nanotubes on the bottom surface of the V-shaped groove later.
[0022]
After forming a predetermined V-shaped groove 62 (FIG. 13B) in the InP layer 16, a gate metal material is deposited using the resist pattern 61 as a mask, and the lift-off method is used as described with reference to FIG. A gate 63 is formed. Subsequently, SiO ₂ A part of the film 26 is removed by etching to partially expose the source 21 and the drain 22. Next, in the example described above with reference to FIGS. 10A and 10B, the cross section of the groove 41 for growing the carbon nanotubes was rectangular, but here the V-shaped groove 62 (FIG. 13B). In the same manner as in the previous case, the carbon nanotube 67 is grown in the V-shaped groove 62 using the Ni metal catalyst 66 (FIG. 14). Before preparing the Ni metal catalyst 66, the gate metal is removed leaving a portion that becomes the gate electrode lead portion 63a (FIG. 14). The controllability of the growth direction of the carbon nanotubes at this time is further enhanced by growing along the V-shaped groove in addition to the action of the applied electric field.
[0023]
FIG. 15 corresponds to the BB cross section of FIG. 14, and in this figure, a resist pattern 68 serving as a mask for plating in which Ni metal is embedded in the V-shaped groove where the carbon nanotubes 67 are present is shown. Has been. Ni electrolytic plating is performed using the resist pattern 68 as a mask, Ni metal 69 is embedded in the V-shaped groove as shown in FIG. 16, and then the resist pattern 68 is removed.
[0024]
Since the minimum diameter of the carbon nanotube used in the present invention is 0.4 nm, the present invention makes it possible to realize a gate length of 10 nm or less, which is essential for future high-speed / high-frequency transistors.
[0025]
Thus, carbon nanotubes having a small diameter can be used not only as a transistor gate itself but also as a mask in the fabrication of the gate, which also makes it possible to realize a gate length of 10 nm or less. When a fine gate is manufactured using a resist pattern as a mask as in the prior art, such a fine pattern cannot be obtained satisfactorily because the dimensional fluctuation of the resist pattern itself is large. On the other hand, the fluctuation accompanying the transfer of the mask pattern to the underlying layer by etching is not so great even now. Therefore, if a carbon nanotube with extremely small size or shape fluctuation is used as a mask, a fine gate with extremely small size or shape fluctuation can be obtained accordingly. In order to fabricate a gate using a carbon nanotube as a mask, a gate metal film is first grown on a semiconductor substrate or a gate insulating film, and then a fluorine-based gas such as SF is used. ₆ , CF _Four The gate metal film is dry-etched with, for example, and then the carbon nanotube mask is removed using an oxygen-based dry etch gas.
[0026]
Hereinafter, fabrication of a field effect transistor using a carbon nanotube as a mask according to the present invention will be described with reference to the drawings.
First, in the manner described with reference to FIGS. 5A to 5C and FIGS. 6A to 6B, the source 21, the drain 22, and the insulating film 26 are provided. A substrate in which a gate metal hole 37 (FIG. 6B) is provided in the lower InP layer 16 is prepared. Next, as shown in FIG. 18A, a gate metal layer 81 is formed, and a Ni catalyst 82 for carbon nanotube growth is prepared thereon. Subsequently, thermal CVD is performed while applying a DC electric field to grow carbon nanotubes 83 (FIG. 18B). Using the obtained carbon nanotube 83 as a mask, for example, SF ₆ Is used to dry-etch the gate metal layer 81, and the carbon nanotubes are removed by oxygen dry etching to obtain a gate 84 with a fine pattern formed of metal (FIG. 19A). Next, a gate lead portion 85 is formed at one end of the gate 84 (FIG. 19B).
[0027]
By making full use of this method, even when the thickness is 10 nm or less, it is possible to avoid a dimensional fluctuation that becomes a problem in the case of lithography using a resist and to realize a high-speed / high-frequency transistor.
[0028]
Here, the present invention is described by taking HEMT as an example, but it goes without saying that the present invention can be applied to various other transistors. For example, in the field effect transistor of the present invention employing a carbon nanotube gate, the number of gates is not limited to one, and may be plural. The growth of the carbon nanotube serving as the gate can be performed by plasma CVD in addition to the thermal CVD mentioned in the above description. In the case of thermal CVD, the catalyst remains at the starting point of growth, whereas in the case of plasma CVD, the catalyst is located at the tip of the growing tube and moves with the growth of the tube. In addition, a method of forming a fine pattern using a carbon nanotube as a mask is not only a method for producing a gate, but also, for example, SiO ₂ It can be easily understood that it can be applied to patterning of an insulating film. In any case, an appropriate etching gas may be selected in accordance with the carbon nanotube as a mask and the material to be patterned. For example, when etching a metal film, SF is used. ₆ , CF _Four Etc., CHF for silicon oxide film _Three Etc. can be used.
[0029]
The present invention is as described above. The features of the present invention will be described as follows together with various aspects.
(Appendix 1) An electric field including a source that supplies carriers, a drain that receives carriers, and a gate as a current control electrode that controls the current flowing through the channel by changing the conductivity of the channel that is a current path therebetween. A field effect transistor, wherein the gate is made of metallic carbon nanotubes.
(Supplementary note 2) The field effect transistor according to supplementary note 1, wherein a gate of the carbon nanotube is connected to a gate lead portion of a metal material.
(Supplementary note 3) The field effect transistor according to supplementary note 2, wherein the gate lead-out portion is manufactured by a lithography technique.
(Additional remark 4) The field effect transistor of Additional remark 2 or 3 with which the gate of the said carbon nanotube and the gate drawer | drawing-out part of the said metal material are connected via the catalyst metal for CVD growth of the said carbon nanotube.
(Supplementary note 5) The field effect transistor according to supplementary note 4, wherein the catalyst metal is a transition metal or an alloy thereof.
(Supplementary note 6) The field effect transistor according to supplementary note 5, wherein the transition metal is Ni, Co, or Fe.
(Supplementary note 7) The field effect transistor according to any one of supplementary notes 1 to 6, wherein the carbon nanotube of the gate is located in a groove formed across the channel in the substrate including the channel portion.
(Additional remark 8) The field effect transistor of Additional remark 7 whose cross-sectional shape of the said groove | channel is a rectangle.
(Additional remark 9) The field effect transistor of Additional remark 7 whose cross-sectional shape of the said groove | channel is V type.
(Supplementary note 10) The field effect transistor according to supplementary note 9, wherein a metal material filling the groove is located on the carbon nanotube in the groove.
(Supplementary Note 11) An electric field including a source that supplies carriers, a drain that receives carriers, and a gate as a current control electrode that controls current flowing through the channel by changing the conductivity of the channel that is a current path between them A field effect transistor manufacturing method, wherein the gate is made of metallic carbon nanotubes, wherein the gate of the carbon nanotubes is grown by a CVD method under electric field application conditions. A method of manufacturing a field effect transistor.
(Additional remark 12) The method of Additional remark 11 which performs the gate growth of the said carbon nanotube using the catalyst attached to a part of gate drawing part of the metal material which should be connected to the gate of the said carbon nanotube.
(Supplementary note 13) The method according to supplementary note 12, wherein a DC electric field is applied to grow the carbon nanotube gate in one direction from the gate lead-out portion.
(Supplementary Note 14) In addition to the catalyst attached to a part of the gate lead-out portion, a catalyst is disposed at a position where the tip of the carbon nanotube opposite to the gate lead-out portion is connected, and an AC electric field is generated. 13. The method according to appendix 12, wherein the carbon nanotubes are grown and connected in a direction facing each other starting from the positions of both catalysts.
(Supplementary note 15) The method according to any one of Supplementary notes 11 to 14, wherein the carbon nanotube gate is grown in a groove formed across the channel on a substrate including a channel portion.
(Supplementary note 16) The method according to supplementary note 15, wherein the groove has a rectangular cross-sectional shape.
(Supplementary note 17) The method according to supplementary note 16, wherein a cross-sectional shape of the groove is V-shaped.
(Appendix 18) A fine structure characterized in that carbon nanotubes are arranged on an underlayer, and the shape of the nanotube is transferred to the underlayer by performing dry etching using the carbon nanotube as a mask, thereby patterning the underlayer. Pattern forming method.
(Supplementary note 19) The method according to supplementary note 18, wherein the underlayer is a metal layer.
(Supplementary note 20) The method according to supplementary note 19, wherein the metal layer is for forming a gate of a transistor.
(Supplementary note 21) The method according to supplementary note 19, wherein the underlayer is an insulating layer.
[0030]
【The invention's effect】
As described above, the present invention can contribute to the provision of a field effect transistor provided with a fine gate with no dimensional fluctuation. Further, according to the present invention, it is possible to use a fine pattern forming method that enables formation of a fine structure including such a fine gate.
[Brief description of the drawings]
FIG. 1 is a graph for explaining prediction of future optical communication speed.
FIG. 2 shows the gate length and cutoff frequency f of an electronic device. _T It is a graph explaining the relationship.
FIG. 3 is a diagram illustrating one embodiment of a field effect transistor according to the present invention having a HEMT structure.
FIG. 4 is a diagram illustrating a field effect transistor having a conventional HEMT structure.
FIG. 5 is a first diagram illustrating the manufacture of a conventional field effect transistor.
FIG. 6 is a second diagram illustrating the manufacture of a conventional field effect transistor.
FIG. 7 is a third diagram illustrating the manufacture of a conventional field effect transistor.
FIG. 8 is a schematic top view of a conventional field effect transistor.
FIG. 9 is a perspective view illustrating a gate portion of a field effect transistor according to the present invention.
FIG. 10 is a first diagram illustrating a method for manufacturing a gate of a field effect transistor according to the present invention.
FIG. 11 is a second diagram illustrating a method for manufacturing the gate of the field effect transistor of the present invention.
FIG. 12 is a diagram illustrating another method for manufacturing the gate of the field effect transistor of the present invention.
FIG. 13 is a first diagram illustrating the manufacture of another embodiment of a field effect transistor according to the present invention having a HEMT structure.
FIG. 14 is a second diagram illustrating the manufacture of another embodiment of a field effect transistor according to the present invention having a HEMT structure.
FIG. 15 is a third diagram illustrating the manufacture of another embodiment of a field effect transistor according to the present invention having a HEMT structure.
FIG. 16 is a fourth view illustrating the manufacture of another embodiment of a field effect transistor according to the present invention having a HEMT structure.
FIG. 17 is a graph showing the relationship between the temperature observed when a material is embedded in the V-shaped groove by MOCVD and the width of the bottom surface of the V-shaped groove.
FIG. 18 is a first diagram illustrating a fine pattern forming method according to the present invention.
FIG. 19 is a second view illustrating the fine pattern forming method according to the present invention.
[Explanation of symbols]
11 ... Board
16 ... Cap layer
17 ... Ohmic layer
21 ... Source
22 ... Drain
23, 23 ', 63 ... Gate
25, 26 ... Insulating film
23a, 23a '... Gate electrode lead-out portion
40 ... Active layer
41, 51 ... groove
45, 52, 66 ... metal catalyst
46, 53, 54, 67 ... carbon nanotubes
62 ... V-shaped groove
81 ... Gate metal layer
82 ... Metal catalyst
83 ... carbon nanotube
84 ... Gate
85 ... Gate drawer

Claims (11)

A high electron mobility transistor in which a channel layer and an electron supply layer are stacked, and a source, a gate, and a drain are arranged above the electron supply layer ,
A high electron mobility transistor, wherein the gate is made of metallic carbon nanotubes. The high electron mobility transistor according to claim 1, wherein a gate of the carbon nanotube is connected to a gate lead portion made of a metal material. The gate of the carbon nanotube and the gate lead-out portion of the metal material, the catalytic metal through are connected, the high electron mobility transistor according to claim 2, wherein for the CVD growth of the carbon nanotubes. 4. The high electron mobility transistor according to claim 1, wherein the gate made of the carbon nanotube is located in a groove formed across the source and the drain. 5. 4. The height according to claim 1, wherein the carbon nanotube of the gate has a cross-sectional shape formed across the channel in the substrate including the channel portion, and is located in the V-shaped groove. 5. Electron mobility transistor. The high electron mobility transistor according to claim 4 or 5 , wherein a metal material filling the groove is located on the carbon nanotube in the groove. A method of manufacturing a high electron mobility transistor in which a channel layer and an electron supply layer are stacked, and a source, a gate, and a drain are disposed above the electron supply layer ,
The method of manufacturing a high electron mobility transistor, wherein the gate is formed by growing a carbon nanotube by a CVD method while applying an electric field in a growth direction . The gate growth of carbon nanotubes is carried out using a catalyst deposited on a portion of the gate lead portion of the metallic material to be connected to the gate of the carbon nanotubes, the method of claim 7 wherein. 9. The method of claim 8 , wherein a direct current electric field is applied to grow the carbon nanotube gate in one direction from the gate lead-out. In addition to the catalyst attached to a part of the gate lead-out part, a catalyst is disposed at a position where the tip of the carbon nanotube opposite to the gate lead-out part is connected, and an alternating electric field is applied, 9. The method according to claim 8 , wherein the carbon nanotubes are grown and connected in directions facing each other starting from the positions of both catalysts. A method of manufacturing a high electron mobility transistor in which a channel layer and an electron supply layer are stacked, and a source, a gate, and a drain are disposed above the electron supply layer,
A gate metal layer is grown at the gate formation position,
Carbon nanotubes are grown on the gate metal layer,
Using the carbon nanotubes as a mask to dry-etch the gate metal layer to form a gate pattern;
A method for producing a high electron mobility transistor .

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