JP4225716B2 - Semiconductor device with cylindrical multilayer structure - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a new type of semiconductor device using a cylindrical multilayer structure represented by a new material, carbon nanotube.
[0002]
[Prior art]
Since the invention, the transistor has been improved with various improvements. Speaking of a field effect transistor that uses a channel region located between two regions of a source and a drain as a current path through which carriers flow and changes its electric resistance according to the voltage of the gate electrode, thereby controlling the current flowing through the channel region. For higher speed and higher frequency operation, miniaturization of the gate (gate length) and higher carrier mobility of the channel material have been attempted. As gate miniaturization has already reached the 10 nm level, many problems have emerged, such as processing accuracy problems due to lithography fluctuations, increased transistor off-current (short channel effect), on-current saturation, and increased gate leakage current. It is becoming. Increasing the dielectric constant of the gate insulating film has been studied as an effective means for solving some of these. On the other hand, an approach to increase the current control capability of the gate by changing the transistor gate structure itself from a current planar type to a three-dimensional structure (for example, a so-called surround gate structure) has been considered.
[0003]
As shown in FIG. 1, the surround gate structure is a structure in which a semiconductor channel layer (in this example, a p-type semiconductor layer) 1 is surrounded by a gate electrode 2 from the outside like a coaxial cable, and electric lines of force extending from the gate. Does not escape out of the channel, the current control efficiency is better than that of the planar type, and the suppression of the short channel effect can be expected. In the semiconductor device of FIG. 1, 3 is a source electrode, 4 is a drain electrode, 5 is a high-concentration n-type semiconductor layer embedded in a semiconductor substrate 9 for connecting the source electrode 3 and the channel 1, 6 Is a high-concentration n-type semiconductor layer for connecting the drain electrode 4 and the channel 1, and 7 is an insulating material.
[0004]
[Problems to be solved by the invention]
However, the surround gate structure requires a cylindrical semiconductor layer extending upward from the substrate surface, and its processing is difficult. Therefore, the threshold voltage of the transistor (the gate voltage for turning off the current flowing through the transistor) is There are many remaining problems such as fluctuation easily by individual transistors and difficulty in controlling impurity concentration by doping.
[0005]
Starting with this example, a conventional field effect transistor that has been particularly miniaturized has various problems, and has not yet been realized with excellent characteristics.
[0006]
Accordingly, the present invention provides a new type of semiconductor device that has never been provided, and in particular, provides a semiconductor device that is effective in suppressing the short channel effect and that enables high-speed operation, high-frequency operation, high current drive capability, and the like. It is intended.
[0007]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a cylindrical multilayer structure composed of carbon elements, the inner cylinder having semiconducting properties and the outer cylinder having metallic properties, And it has the conductor connected to an outer cylinder directly or through an insulator, and the outer cylinder is divided in two or more places. This is a semiconductor device.
[0008]
More specifically, the semiconductor device of the present invention is a cylindrical multilayer structure composed of carbon elements, in which the inner cylinder has semiconducting properties and the outer cylinder has metallic properties. A multilayer structure having At both ends of the inner cylinder Conductor to be connected and outer cylinder Conductor connected directly or via an insulator A semiconductor device characterized by comprising:
[0009]
The basic configuration of the semiconductor device of the present invention is as described above, and various modes can be considered as described in detail below.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, as at least a part of the semiconductor material and the metal material in the semiconductor device, a self-organized nanostructure which is a cylindrical structure composed of carbon element is used. Examples of such a structure include those generally known as carbon nanotubes. A cylindrical structure composed of carbon elements that can be used in the present invention (which will be described as “carbon nanotubes” below) has a cylindrical body or tube having semiconducting properties on the inside, and an outer side. It is a multilayer structure having a cylindrical body or tube having metallic properties.
[0011]
Carbon nanotubes are a new carbon-based material that has recently attracted attention due to its unique properties. A carbon nanotube has a structure in which a graphite sheet in which carbon atoms are assembled into a 6-membered ring with the strongest bond of sp2 is rolled up into a cylindrical shape, and the tip of the tube is closed by several 6-membered rings including a 5-membered ring. ing. The diameter of the tube can be miniaturized to the order of sub-nanometers, with a minimum of 0.4 nanometers. The length of the tube can be manufactured up to several tens of μm at present.
[0012]
Some carbon nanotubes have a band structure that satisfies the conditions for exhibiting metallic properties, and others have a band structure that satisfies the conditions for exhibiting semiconducting (semi-metallic) properties. The carbon nanotube chirality (how to twist the tube or how to wind the graphite sheet) is involved in whether the carbon nanotube exhibits metallic or semiconducting properties. FIG. 2 (a) shows the chirality of nanotubes (referred to as armchair type) showing metallic properties, and FIG. 2 (b) shows those showing semiconducting properties (called zigzag types). . The structure shown in FIG. 2C is known as a chiral type, and in this case, it may exhibit metallic properties and semiconductor properties depending on conditions. The chirality of carbon nanotubes depends on the production method and production conditions.
[0013]
Since the structure of a carbon nanotube is formed by self-organization, the diameter of one tube is usually constant. In addition, multi-walled nanotubes with other tubes in the tube can also be obtained, and the chirality of each tube is often different. By utilizing this characteristic, it is possible to obtain a multilayer structure in which the inner tube has semiconducting properties and the outer tube has metallic properties.
[0014]
The physical properties of this material are now being researched. However, as described above, the electrical conductivity becomes semiconductive and metallic due to chirality, and the thermal conductivity and current density are already 1 square centimeter. 10 per hit ⁶ It has been reported that it has attractive physical properties such as being able to flow to amperes, having a high Young's modulus, and possibly having a high storage efficiency for hydrogen and the like.
[0015]
Conventionally, arc discharge and laser ablation have been used for the production of carbon nanotubes, but recent studies have reported that they can also be produced by plasma CVD or thermal CVD. The arc discharge method is a method that enables the production of high-purity nanotubes, but is not suitable for the manufacture of semiconductor devices, whereas the CVD method is effective for application to semiconductor devices.
[0016]
The present invention is characterized in that this carbon nanotube is applied to the channel and gate of a fine transistor.
FIG. 3 shows the basic configuration. The semiconductor device 10 in this figure includes a multi-layered structure 12 of carbon nanotubes, which is composed of an inner tube 14 and an outer tube 16, the inner tube 14 having semiconducting properties, and the outer tube 16 being metallic. Has properties. Each of the inner tube 14 and the outer tube 16 may have a multilayer structure including a plurality of tubes having the same property (semiconductor property or metal property). Each of these tubes is formed of a carbon element stitch structure as illustrated in FIG. 2, but in FIG. 3 (and the figures referenced in the following description), it is represented as a simple cylinder for simplicity. Has been.
[0017]
The semiconductor device 10 of FIG. 3 further includes conductors 18 and 20 connected to the tips 14a and 14b of the inner tube 14, and means 22 for applying a voltage to the outer tube. In this semiconductor device 10, the inner tube 14 exhibiting semiconducting properties and the outer tube 16 exhibiting metallic properties form a semiconductor-metal junction, so that the inner tube 14 serves as the channel of the transistor, and the outer tube 16. Can work as a gate. In this case, for example, the current flowing from the conductor 18 to the conductor 20 through the inner tube 14 having a semiconducting property can be controlled in accordance with the voltage applied by the voltage applying means 22 from the outside. Although the tips 14a and 14b of the inner tube 14 extend from both ends 16a and 16b of the outer tube 16 in FIG. 3, the outer tubes 16 are made of metallic materials for joining with the conductors 18 and 20. As long as they do not contact with each other, they may be positioned on the same plane as the both ends 16a and 16b of the outer tube.
[0018]
In this semiconductor device 10, the inner tube 14 corresponding to the channel is surrounded by the outer tube 16 corresponding to the gate, and it can be seen that this structure is the surround gate structure shown in FIG. In this semiconductor device 10, by applying a positive voltage to the outer nanotube 16, the hole density in the inner nanotube 14 is reduced, and the current flowing through the channel is reduced. This structure is particularly effective in suppressing the short channel effect because electric lines of force extending from the gate do not escape out of the channel, and can provide good off characteristics.
[0019]
The conductors 18 and 20 may be made of any material as long as they can be electrically connected to the inner tube 14. For example, the metal processed into a probe shape may be sufficient, or the carbon nanotube which shows a metallic property may be sufficient. The manner of connection with the inner tube 14 is not limited to the joining of the distal ends 14a and 14b of the inner tube and the distal ends of the conductors 18 and 20 as shown in FIG. For example, you may connect the conductors 18 and 20 to the side surface of the inner tube 14 extended and exposed to the outer side of the both ends 16a and 16b of an outer tube. As in the embodiment described later, it is also possible to divide the outer tube of the multi-walled carbon nanotube and use the divided outer tube that does not directly contact the gate tube as the conductors 18 and 20.
[0020]
The means 22 for applying a voltage to the outer tube 16 may generally be a conductor. The voltage applying means 22 may be directly connected to the outer tube 16 as schematically shown in FIG. 3, or via an insulator (not shown) inserted between the outer tube 16 and the voltage applying means 22. The voltage may be applied to the outer tube 16.
[0021]
Next, a semiconductor device according to another aspect of the present invention will be described. As shown in the plan view of FIG. 4A and the cross-sectional view of FIG. 4B, the semiconductor device of this embodiment has an outer tube having electrical properties at two locations of the carbon nanotubes 32 having a multilayer structure. In other words, there is a portion in which only the inner tube 34 having a semiconductor property exists, whereby the semiconductor device is electrically insulated and separated into the source region S, the drain region D, and the channel region C. In the source region S, a source electrode 38 serving as an ohmic electrode is ohmically connected to the outer tube 36S having a metallic property. In the drain region D, a drain electrode 40 serving as an ohmic electrode is also ohmically connected to the outer tube 36D. ing. On the other hand, in the channel region C, a gate electrode 42 as a rectifying electrode is connected to the outer tube 36C having a metallic property (this connection itself is ohmic connection), thereby forming a gate. The current passing through the inner tube 34 in the channel region C is controlled by rectifying contact with the inner tube 36C. As described above, this semiconductor device also has a surround gate structure, and therefore has excellent off characteristics. Further, this semiconductor device corresponds to a field effect transistor using a Schottky junction between a metal and a semiconductor as a gate, and therefore is particularly suitable for use as a semiconductor device for high-frequency operation.
[0022]
In general, the source electrode 38 and the drain electrode 40 can be formed of a metal material such as Ni, Ti, Pt, or Pt—Au alloy in order to obtain a low contact resistance. On the other hand, the gate electrode 42 can be formed of a metal material such as Al or W, or polycrystalline silicon. The source electrode 38, the drain electrode 40, and the gate electrode 42 are drawn so as to be in contact with the entire length of the side surfaces of the outer tubes 36S, 36D, and 36C of the carbon nanotube 32 in FIGS. 4 (a) and 4 (b). Can also be in contact with some of them.
[0023]
As clearly shown in FIG. 4 (b), the carbon nanotubes 32 are generally disposed on an optional insulator layer 44. The insulator layer 44 may be a single substrate of an insulating material, or may be an insulating material layer provided on a substrate 46 of another material. Alternatively, a semiconductor layer with low conductivity may be used.
[0024]
A semiconductor device according to still another embodiment of the present invention will be described with reference to FIG. 5 which is a cross-sectional view similar to FIG. In FIG. 5, the same members as those described in FIGS. 4A and 4B are denoted by the same reference numerals, and description thereof will be omitted to avoid duplication.
[0025]
In the semiconductor device shown in FIG. 5, the insulator 52 is disposed between the gate electrode 42 and the outer tube 36 </ b> C of the channel region C and along the side surface of the gate electrode 42. Except this, this semiconductor device is the same as that described in FIGS. 4 (a) and 4 (b). In the semiconductor device having this structure, since the insulator 52 is inserted between the source and the gate and between the gate and the drain, the gate capacitance can be reduced. Therefore, this semiconductor device is particularly suitable for high-speed switching operation and high integration.
[0026]
Another embodiment of the present invention is shown in the plan view of FIG. 6A and the cross-sectional view of FIG. In any of the embodiments described above, the longitudinal axis of the carbon nanotube 32 is parallel to the surface of the substrate 46, whereas in the embodiment described below, the longitudinal axis of the carbon nanotube is perpendicular to the substrate surface. Thus, the semiconductor device of this aspect is a saddle type semiconductor device.
[0027]
6A and 6B, a plurality of carbon nanotubes 66 are arranged in the vertical direction between the lower source electrode 62 and the upper drain electrode 64. These carbon nanotubes 66 have the multi-layer structure described above, and the outer tube 68 having metallic properties is cut and separated at two locations to expose the inner tube 70 having semiconducting properties. A gate electrode 72 is disposed adjacent to the remaining portion (corresponding to the channel region) of the central outer tube. The other portions shown in FIGS. 6A and 6B are made of an insulating material. In the semiconductor device shown in the figure, an insulating material exists between the nanotube 66 and the gate electrode 72. However, as described above, the gate electrode 72 is in contact with the outer tube of the nanotube having a multilayer structure. You can also.
[0028]
The semiconductor device shown in FIGS. 6A and 6B includes a plurality of carbon nanotubes 66 having a multi-layer structure, and a bundle 76 schematically shown in FIG. 6A is formed. ing. The number of the multi-layered carbon nanotubes in this semiconductor device may be one, but a special advantage described below can be obtained by using a bundle of a plurality of tubes as shown in the figure. In a semiconductor device having a bundle of carbon nanotubes, the nanotube 68 of the outer metallic properties is left even in the bundle of the plurality of multi-walled nanotubes in the channel portion. It is maintained at a potential. Normally, when the channel diameter is increased, the threshold voltage increases. However, in this semiconductor device, the gate (metal outer tube) is wound around each tube, so if the tube diameter is uniform, The threshold voltage has the feature that it does not change regardless of the number of tubes. Accordingly, by bundling a plurality of nanotubes serving as channels, a larger amount of current can flow, and the current driving capability is further enhanced.
[0029]
Next, the manufacture of the semiconductor device described above will be described.
The semiconductor device described in FIGS. 4A and 4B can be manufactured as follows, for example. As shown in FIG. 7A, a silicon oxide film 104 having a thickness of 100 nm is deposited on the surface of an n-type silicon substrate 102, and carbon nanotubes are disposed thereon, and a resist pattern (not shown) is used for carbon. The exposed both ends of the nanotube are subjected to oxygen plasma ashing, the resist pattern is removed, and a carbon nanotube 106 having a required length is prepared. Next, as shown in FIG. 7B, the nanotube 106 on the substrate 102 is exposed to a fullerene (C60) -containing atmosphere, and the fullerene 108 is injected into the inside by a strong suction force of the nanotube 106 to form a so-called peapod. Make it. The peapod-structured carbon nanotube 106 (FIG. 7B) is annealed at 1200 ° C. to produce a multi-walled carbon nanotube 110 (FIG. 7C).
[0030]
Next, a resist pattern (not shown) having openings for the source / drain electrodes is formed so as to cover the multi-walled nanotube 110 and the underlying oxide film 104, and Pt—Au is used as a metal for the source / drain electrodes. After vapor deposition of the alloy, the metal other than the resist pattern opening is removed by lift-off to form the source electrode 112 and the drain electrode 114 (FIG. 8A). A gate metal (W) is deposited by using a resist pattern (not shown) having an opening in the central portion of the nanotube 110, and a gate electrode 116 (FIG. 8B) is similarly formed by lift-off. Next, oxygen plasma etching is performed for a predetermined time using the metal electrodes 112, 114, and 116 as a mask to remove only the exposed outer tube of the multi-walled nanotube 110, referring to FIGS. 4 (a) and 4 (b). The semiconductor device 100 having the structure described above is obtained (FIG. 8C).
[0031]
The removal of the outer tube can also be performed by a method other than the method using the oxygen plasma etching described above. For example, when the source, drain, and gate electrodes 112, 114, and 116 are formed as shown in FIG. 8B, current is passed between the gate and the source and between the gate and the drain, respectively. It is possible to remove. In this case, since the outer tube showing metallic properties is more likely to flow current than the inner tube having semiconducting properties and high resistance, the carbon constituting the outer tube of the portion not covered with the electrode metal is first. It can disappear and leave only the inner tube.
[0032]
After the multilayer nanotube 110 described with reference to FIG. 7C is formed, an insulating film (silicon nitride film or oxide film) (not shown) that covers the multilayer nanotube 110 and the oxide film 104 under the multilayer nanotube 110 is formed. In the semiconductor device 100 of (c), it is possible to manufacture a semiconductor device provided with an insulating film between the gate electrode 116 and the nanotube 110 below it. The manufacturing method is as follows.
[0033]
As shown in FIG. 9A, a silicon nitride film 122 (or a silicon oxide film) covering the multi-walled nanotube 110 and the underlying oxide film 104 is formed to 2 nm. Next, a resist pattern (not shown) is formed on the nitride film 122, and the nitride film 122 is etched to form an insulating film 124 so that both ends of the nanotube 110 are exposed as shown in FIG. 9B. leave. Subsequently, as described with reference to FIGS. 8A to 8C, the source electrode 112 and the drain electrode 114 are formed, and the gate electrode 116 is further formed on the insulating film 124. (FIG. 9C), and after etching the exposed insulating film 124, the outer tube of the nanotube 110 was removed by oxygen plasma ashing to provide a gate insulating film 126 as shown in FIG. 9D. A semiconductor device 100 ′ is obtained.
[0034]
The semiconductor device provided with the side wall of the insulating material on the side surface of the gate electrode shown in FIG. 5 can be manufactured as follows.
After the process up to the formation of the gate electrode 116 on the insulating film 124 shown in FIG. 9C is completed, the formation and etching of a 100 nm silicon nitride film (not shown) are performed, so that FIG. As shown in FIG. 9, a nitride side wall 132 is formed on the side surface of the gate electrode 116 (at this time, the exposed nitride film 124 (FIG. 9C) on the nanotube 110 is also etched). Subsequently, oxygen plasma etching is performed for a predetermined time using the metal electrodes 112, 114, and 116 and the nitride side wall 132 as a mask, and only the exposed outer tube of the multi-walled nanotube 110 is removed. The semiconductor device 100 ″ having the structure as described above is obtained (FIG. 10B).
[0035]
Next, the manufacture of the semiconductor device having the saddle type structure described above with reference to FIGS. 6A and 6B will be described.
As shown in FIG. 11 (a), As ions are implanted and p. ⁺ On the n-type silicon substrate 202 on which the region 204 is formed, a silicon nitride film (50 nm) 206, a silicon oxide film (50 nm) 208, a polysilicon gate metal film (20 nm) 210, a silicon oxide film (50 nm) 212, and silicon nitride A film (50 nm) 214 is sequentially formed. Next, after forming a resist pattern (not shown), the respective films 214, 212, 210, 208 and 206 are sequentially selectively etched using the resist pattern as a mask to form the bottom portion as shown in FIG. p ⁺ An exposed opening 216 of the region 204 is formed, and subsequently Ni (or Fe or Co) is deposited on the entire surface, and then a 1-10 nm metal film (not shown) is left only at the bottom of the opening 216 by a lift-off method. . Using the metal film Ni as a catalyst, carbon nanotubes 220 (FIG. 11C) are grown vertically in the openings 216 by CVD, and the tips of the nanotubes 220 are removed by oxygen plasma treatment. When plasma CVD is used as the CVD growth method, the catalyst metal is removed by Ar sputtering. In the case of thermal CVD, since the catalyst remains at the bottom of the film 210, this step is unnecessary. Next, as described above, a peapod is produced by injecting fullerene (not shown) into the nanotube by treatment in a fullerene-containing atmosphere, and annealing is performed to form a plurality of multi-walled nanotubes 220a (FIG. 12 (a)). Form. Next, a metal film (not shown) for the drain electrode is formed of TiSi, and this is etched using a resist pattern (not shown) to form the drain electrode 222 shown in FIG. .
[0036]
Subsequently, as shown in FIG. 12B, the nitride film 214 (FIG. 12A) is anisotropically etched using the drain electrode 222 as a mask, and the oxide film under the etched nitride film 214 ′ is further etched. Is removed by isotropic etching. Next, as shown in FIG. 12C, the gate metal film 210 (FIG. 12B) is anisotropically dry-etched to form the gate electrode 224, and the oxide film under the gate electrode 224 is formed on the oxide film. It is removed by isotropic etching. The multi-walled carbon nanotube 220a (FIG. 12C) exposed by the removal of the oxide film is subjected to oxygen plasma treatment to remove only the outer tube of the exposed portion, and as shown in FIG. The inner nanotube 226 is exposed.
[0037]
Subsequently, as shown in FIG. 13B, a silicon oxide film 228 having a thickness of 200 nm is formed on the entire surface. Next, as shown in FIG. 14A, a resist pattern 230 is formed, and using this as a mask, the oxide film 228 and the nitride film 206 are etched to form electrode contact holes 232 and 234. A Pt—Au alloy is deposited as the source / drain metal, and the source 236 and the drain 238 are formed by leaving the metal only in the contact holes 232 and 234 by lift-off (FIG. 14B). In this way, a semiconductor device having a saddle type structure similar to that described with reference to FIGS. 6A and 6B is obtained.
[0038]
FIG. 15 is a plan view of a semiconductor device manufactured through the steps of FIG. 11A to FIG. 14B. In this semiconductor device, a part of the source 236 and the drain 238 is exposed in the opening of the oxide insulating film 228, and the multi-walled carbon nanotube 220a serving as a channel below the drain 238 (FIG. 14A). ) Bundle 240 is located. A gate electrode 224 is positioned surrounding the nanotube bundle 240 and a portion thereof is exposed to another opening of the insulating film 228. The opening for exposing the gate electrode 224 can be formed, for example, after the oxide film 228 is formed in FIG.
[0039]
A semiconductor device using a bundle that is an aggregate of a plurality of multi-walled carbon nanotubes is not limited to the vertical structure described above, but has a horizontal structure in which the longitudinal axis of the nanotube is parallel to the substrate surface. Needless to say, it is good.
[0040]
One of the characteristics of carbon nanotubes is that electrons as carriers travel in the nanotubes without scattering (in a coherent state). In such electron conduction, the electric resistance is constant regardless of the length of the current path. Such a phenomenon is recognized when the length of the current path is less than the mean free path of electrons. Accordingly, the length of the channel portion that controls the current flowing through the gate in the semiconductor device of the present invention, in other words, the length of the continuous outer tube in which the gate electrode is in direct contact or indirectly through the insulating layer, In the case where the average free path is below the electron, the semiconductor device of the present invention is particularly capable of high-speed / high-frequency operation and high-current drive, and obtains low noise characteristics.
[0041]
In addition, since the structure of the carbon nanotube is formed by self-organization, its structural fluctuation (variation) is extremely small. Also, in the carbon nanotube having a multilayer structure used in the present invention, the interval between the outer and inner nanotubes is 0.34 nm and is extremely uniform. Therefore, if a semiconductor device is configured using carbon nanotubes, miniaturization beyond the limits of lithography is possible.
[0042]
Up to now, the gate electrode has been described as one. However, like the so-called “double gate” type semiconductor device, the semiconductor device of the present invention can have two or more gate electrodes. In this case, there are independent outer tubes separated from each other corresponding to the number of gates in the carbon nanotube portion between the source and the drain. More specifically, in the semiconductor device having the simplest structure described with reference to FIG. 3, if the number of gates is one, the outer tube may be one continuous body, and the number of gates is two. Then, the outer tube becomes a discontinuous parted at one place. On the other hand, in the case of a semiconductor device having an outer tube having a divided portion between the gate and the source electrode and between the gate and the drain as described with reference to FIGS. 4A and 4B, for example, If the number of gates is one, it is divided at two places, and if the number of gates is two, it is divided at three places.
[0043]
The present invention is as described above. The features of the present invention are described as follows along with various aspects.
(Additional remark 1) It is the cylindrical multilayer structure comprised from a carbon element, Comprising: The inner cylinder body has a semiconducting property, and the outer cylinder body contains the multilayer structure which has a metallic property, This multilayer structure A semiconductor device characterized in that the electrical conductivity of an inner cylindrical body of a body is controlled by a voltage applied to the outer cylindrical body.
(Appendix 2) A cylindrical multilayer structure composed of carbon elements, the inner cylinder having semiconducting properties and the outer cylinder having metallic properties, and the inner cylinder The semiconductor device according to appendix 1, characterized by having conductors respectively connected to opposite sides across the outer cylindrical body and means for applying a voltage to the outer cylindrical body.
(Supplementary note 3) The semiconductor device according to Supplementary note 1 or 2, wherein the outer cylindrical body is a continuous structure without division, and the inner cylindrical body is a continuous structure without division.
(Supplementary note 4) The semiconductor device according to Supplementary note 1 or 2, wherein the outer cylindrical body is a discontinuous structure divided and the inner cylindrical body is a continuous structure without division.
(Supplementary note 5) The semiconductor device according to supplementary note 3, wherein a rectifying electrode is in direct contact with the outer cylindrical body.
(Supplementary note 6) The semiconductor device according to supplementary note 3, wherein a rectifying electrode is indirectly in contact with the outer cylindrical body through an insulating material.
(Supplementary note 7) The semiconductor device according to supplementary note 4, wherein the outer cylindrical body is divided at one place, and a rectifying electrode is in direct contact with each divided outer cylindrical body.
(Supplementary note 8) The semiconductor device according to supplementary note 4, wherein the outer cylindrical body is divided at one place, and a rectifying electrode is indirectly in contact with each divided outer cylindrical body via an insulating material.
(Supplementary Note 9) The outer cylindrical body is divided at two or more locations, the ohmic electrodes are in contact with the outer cylindrical bodies at both ends, and the divided intermediate outer cylindrical body has a rectifying electrode. The semiconductor device according to appendix 4, wherein
(Supplementary note 10) The semiconductor device according to supplementary note 9, wherein the rectifying electrode is in direct contact with the outer cylindrical body.
(Supplementary note 11) The semiconductor device according to supplementary note 9, wherein the rectifying electrode is indirectly in contact with the outer cylindrical body through an insulating material.
(Supplementary note 12) The semiconductor device according to supplementary note 11, wherein a side wall of the rectifying electrode facing the outer cylindrical body at both divided ends is provided with a side wall made of an insulating material.
(Supplementary note 13) The semiconductor device according to any one of supplementary notes 5 to 12, wherein a length of the continuous outer cylindrical body in contact with the rectifying electrode is equal to or less than an electron mean free path.
(Supplementary note 14) The semiconductor device according to any one of supplementary notes 1 to 13, wherein a longitudinal axis of the multilayer structure is parallel to a substrate surface on which the multilayer structure is disposed.
(Supplementary note 15) The semiconductor device according to any one of supplementary notes 1 to 13, wherein a longitudinal axis of the multilayer structure is perpendicular to a substrate surface on which the multilayer structure is disposed.
(Supplementary note 16) The semiconductor device according to any one of supplementary notes 1 to 15, wherein the semiconductor device includes a plurality of the multilayer structures, and the bundles are formed by contact between the outer cylindrical bodies.
(Supplementary note 17) The semiconductor device according to any one of supplementary notes 1 to 16, wherein the multilayer structure is formed of a plurality of carbon nanotubes.
[0044]
【The invention's effect】
As described above, the semiconductor device of the present invention in which carbon nanotubes are applied to the gate and channel of a transistor can have a surround gate structure that is particularly effective for suppressing the short channel effect, and thus can operate at high speed. . Further, according to the present invention, it is possible to use a semiconductor device capable of high-frequency operation or a semiconductor device having a high current driving capability.
[0045]
By making the length of the nanotube in the part where the undivided outer tube is in contact with the gate electrode directly or indirectly through the insulating layer equal to or less than the mean free path of electrons, the semiconductor device of the present invention Especially, it has a low noise characteristic of high speed operation, high frequency operation, or high current drive.
[0046]
Furthermore, the use of carbon nanotubes makes it possible to provide a fine semiconductor device that exceeds the limits of lithography.
[Brief description of the drawings]
FIG. 1 illustrates a semiconductor device having a surround gate structure.
FIG. 2 is a diagram illustrating the chirality of carbon nanotubes.
FIG. 3 is a diagram illustrating a basic configuration aspect of a semiconductor device of the present invention;
FIG. 4 is a diagram illustrating another embodiment of a semiconductor device of the present invention.
FIG. 5 is a diagram illustrating still another embodiment of the semiconductor device of the present invention.
FIG. 6 is a diagram illustrating another embodiment of the semiconductor device of the present invention.
7 is a diagram for explaining the first half of the manufacture of the semiconductor device shown in FIG. 4; FIG.
8 is a diagram for explaining the second half of the manufacture of the semiconductor device shown in FIG. 4; FIG.
FIG. 9 is a diagram illustrating the manufacture of a semiconductor device in which an insulating film is interposed between a gate electrode and a carbon nanotube.
10 is a diagram for explaining the manufacture of the semiconductor device having a side wall of the insulating material on the side surface of the gate electrode shown in FIG. 5;
11 is a first view for explaining the manufacture of the semiconductor device shown in FIG. 6; FIG.
12 is a second view for explaining the manufacture of the semiconductor device shown in FIG. 6; FIG.
13 is a third diagram for explaining the manufacture of the semiconductor device shown in FIG. 6; FIG.
14 is a fourth diagram for explaining the manufacture of the semiconductor device shown in FIG. 6; FIG.
FIG. 15 is a plan view of the semiconductor device manufactured through the processes of FIGS.
[Explanation of symbols]
1 ... Channel
2 ... Gate electrode
3 ... Source electrode
4 ... Drain electrode
10, 100, 100 ′, 100 ″... Semiconductor device
12, 32, 66, 110, 220a ... multi-layered carbon nanotube
14, 34, 70, 226 ... inner tube
16, 36C, 36D, 36S, 68 ... outer tube
18, 20 ... Conductor
22: Voltage application means
38, 62, 112, 236 ... Source electrode
40, 64, 114, 222, 238... Drain electrode
42, 72, 116, 224 ... gate electrodes
52, 124, 228 ... insulator
76, 240 ... Bundle of nanotubes
132 ... side wall

Claims (10)

A cylindrical multilayer structure composed of carbon elements, the inner cylinder having semiconducting properties and the outer cylinder having metallic properties, and directly on the outer cylinder Alternatively , a semiconductor device having a conductor connected through an insulator and the outer cylindrical body being divided at two or more locations . A cylindrical multilayer structure composed of carbon elements, in which the inner cylinder has semiconducting properties and the outer cylinder has metallic properties, and is connected to both ends of the inner cylinder. The semiconductor device according to claim 1, comprising a conductor and a conductor connected to the outer cylindrical body directly or via an insulator . Ohmic electrodes on the outer cylinder of the partial cross-sectional been both ends contact respectively, and, in the outer cylindrical body of the shed intermediate contacts rectifying electrode, the semiconductor device according to claim 1 or 2, wherein .   The semiconductor device according to claim 3, wherein the rectifying electrode is in direct contact with the outer cylindrical body.   The semiconductor device according to claim 3, wherein the rectifying electrode is in indirect contact with the outer cylindrical body through an insulating material.   6. The semiconductor device according to claim 5, wherein a side wall of the rectifying electrode facing the outer cylindrical body at both divided ends is provided with a side wall made of an insulating material.   The semiconductor device according to any one of claims 3 to 6, wherein a length of a continuous outer cylindrical body in contact with the rectifying electrode is equal to or less than an electron mean free path.   The semiconductor device according to claim 1, wherein a longitudinal axis of the multilayer structure is parallel to a substrate surface on which the multilayer structure is disposed.   The semiconductor device according to claim 1, wherein a longitudinal axis of the multilayer structure is perpendicular to a substrate surface on which the multilayer structure is disposed.   10. The semiconductor device according to claim 1, wherein the semiconductor device includes a plurality of the multilayer structures, and these form a bundle by contact between the outer cylindrical bodies.

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