JP4882303B2 - Signal processing circuit - Google Patents

Description

The present invention relates to a signal processing circuit using a control signal generating circuits for generating a control signal at a predetermined timing, to reduce and control the circuit operating power holds the particular control signal when deactivated.

Conventionally, in order to suppress a rush current at the time of activation of a Power Gate (power gate) application block (signal processing circuit), control such as shifting the timing of opening a Power (power) switch has been performed. (Patent Document 1), they activate the entire minimum unit circuit block at once. For this reason, the following two signals propagate through the entire signal processing circuit, and when activated, the switching rate in the signal processing circuit increases and wasteful power is consumed.
One signal is an input signal, which always propagates from input to output when activated, and stabilizes the internal node.
Other signals are glitches that occur naturally at unspecified locations in the signal processing circuit, and the more they are generated, the more wasteful switching sources in the signal processing circuit become.
As described above, this wasteful power consumption generated when the signal processing circuit is activated increases the OFF period of the minimum unit circuit for obtaining the effect of reducing the leakage.
Moreover, the technique which paid attention to suppression of the switching rate at the time of activation is not yet known.

When Power Gate is applied to these signal processing circuits, a control signal generating circuit that generates a control signal for controlling Power Gate, an indefinite value propagation blocking circuit that constitutes a part thereof, a circuit that transmits a control signal, etc. Since the circuit itself is not a Power Gate application circuit, it becomes a leakage current generation source and suppresses the leakage current reduction effect.
Furthermore, when the Power Gate application circuit is activated, it is difficult for the circuit to determine whether the circuit has been activated, that is, whether the internal state is stable, and it has been necessary to predict from the estimation. However, a specific circuit example for determining whether or not it is activated is not known.
JP 2003-289245 A

As described above, the conventional power gate application block is required to suppress the rush current, the generation of glitches, and the unnecessary switching operation due to the propagation.

The signal processing circuit according to the first aspect of the present invention includes a circuit block that processes a signal while propagating the signal, a power supply line that supplies power for activating the circuit block, and the signal propagation timing of the circuit block is early. A plurality of virtual power supply lines provided in each domain when divided into a plurality of domains in order, and connected between each of the virtual power supply lines and the power supply lines, and the virtual power supply lines with respect to the power supply lines A plurality of switching means for connecting or disconnecting, and a control signal generating circuit for outputting a control signal to the plurality of switching means and activating a domain corresponding to the switching means supplied with the control signal, The control signal generating circuit is provided to the plurality of switching means so as to sequentially activate the plurality of domains in the order of propagation timing of the signals. When the control signal corresponding to the domain activated second or later in the order of the propagation timing of the signal is output, the control signal of the individual timing is already activated according to the order of the propagation timing of the signal. A plurality of stages in which an enable signal that is a basis of the control signal for continuously outputting a control signal for maintaining each activated domain in an active state is input to the first stage for each switching means of the domain The plurality of inverters propagate the delay while inverting the enable signal, and output the control signal for activating the next domain from the inverter corresponding to the operation completion time of each domain Of the plurality of inverters, the inverter that outputs the control signal is connected to the power supply line, Inverter other than that is connected to the virtual power line connection between the power supply line is connected or cut off by the switching unit based on the control signal.
A signal processing circuit according to a second aspect of the present invention includes a circuit block that processes a signal while propagating the signal, a power supply line that supplies power for activating the circuit block, and the signal propagation timing of the circuit block is early. A plurality of virtual power supply lines provided in each domain when divided into a plurality of domains in order, and connected between each of the virtual power supply lines and the power supply lines, and the virtual power supply lines with respect to the power supply lines A plurality of switching means for connecting or disconnecting, and a control signal generating circuit for outputting a control signal to the plurality of switching means and activating a domain corresponding to the switching means supplied with the control signal, The control signal generating circuit is provided to the plurality of switching means so as to sequentially activate the plurality of domains in the order of propagation timing of the signals. When the control signal corresponding to the domain activated second or later in the order of the propagation timing of the signal is output, the control signal of the individual timing is already activated according to the order of the propagation timing of the signal. A plurality of stages in which an enable signal that is a basis of the control signal for continuously outputting a control signal for maintaining each activated domain in an active state is input to the first stage for each switching means of the domain The plurality of inverters propagate the delay while inverting the enable signal, and output the control signal for activating the next domain from the inverter corresponding to the operation completion time of each domain And a plurality of transistors provided in one-to-one correspondence with each inverter that outputs the control signal. The Star, holds the values of each inverter.
A signal processing circuit according to a third aspect of the present invention includes a circuit block that processes a signal while propagating the signal, a power supply line that supplies power for activating the circuit block, and the signal propagation timing of the circuit block is early. A plurality of virtual power supply lines provided in each domain when divided into a plurality of domains in order, and connected between each of the virtual power supply lines and the power supply lines, and the virtual power supply lines with respect to the power supply lines A plurality of switching means for connecting or disconnecting, and a control signal generating circuit for outputting a control signal to the plurality of switching means and activating a domain corresponding to the switching means supplied with the control signal, The control signal generating circuit is provided to the plurality of switching means so as to sequentially activate the plurality of domains in the order of propagation timing of the signals. When the control signal corresponding to the domain activated second or later in the order of the propagation timing of the signal is output, the control signal of the individual timing is already activated according to the order of the propagation timing of the signal. A minimum unit circuit block in which a control signal for maintaining each activated domain in an active state is continuously output to each switching means in the domain, and a signal is input from the final domain of the circuit block An indefinite value propagation cut-off circuit for forming the circuit, wherein the indefinite value propagation cut-off circuit is in an inactive state in which all domains from the first stage to the last stage of the circuit block are not activated. A constant value is output so as not to propagate the block indefinite signal .
A signal processing circuit according to a fourth aspect of the present invention includes a circuit block that processes a signal while propagating the signal, a power supply line that supplies power for activating the circuit block, and the signal propagation timing of the circuit block is early. A plurality of virtual power supply lines provided in each domain when divided into a plurality of domains in order, and connected between each of the virtual power supply lines and the power supply lines, and the virtual power supply lines with respect to the power supply lines A plurality of switching means for connecting or disconnecting, and a control signal generating circuit for outputting a control signal to the plurality of switching means and activating a domain corresponding to the switching means supplied with the control signal, The control signal generating circuit is provided to the plurality of switching means so as to sequentially activate the plurality of domains in the order of propagation timing of the signals. When the control signal corresponding to the domain activated second or later in the order of the propagation timing of the signal is output, the control signal of the individual timing is already activated according to the order of the propagation timing of the signal. The control signal generation circuit for continuously outputting a control signal for maintaining each activated domain in an active state to each switching means of the domain is provided with an enable signal based on the control signal. A plurality of inverters input to the first stage have a plurality of inverters, and the plurality of inverters propagate the delay while inverting the enable signal, and activate the next domain from the inverter corresponding to the operation completion time of each domain. The minimum unit circuit block that outputs the control signal for and receives the signal from the final domain of the circuit block An indeterminate value propagation cut-off circuit for forming the indeterminate value propagation cut-off circuit connected to the virtual power supply line connected to or cut off from the power supply line by the switching means, and the control signal Activation is controlled by the output signal of the inverter at the final stage of the generation circuit.

In the present invention, it is possible to suppress a rush current in a power gate application block and suppress a useless switching operation due to generation or propagation of glitches.

FIG. 1 is a block diagram of a signal processing circuit 10 having a power gate block (Power Gate Block) as an embodiment.
The signal processing circuit 10 includes: a control signal generation circuit 20; power gate transistors 21 to 23; and domains 31 to 33 in which the power gate block 30 is divided based on operation timing; Circuit; Fence Circuit) 34 and the like.
The control signal generation circuit 20 includes a plurality of signal inverting circuits such as buffer amplifiers or INVs (inverters) connected in cascade, and further a circuit and a keeper (circuit) for holding the state between the signal inverting circuits. Details will be described later.
When a control (enable) signal is supplied to the control signal generation circuit 20, the buffer (inverter) is propagated with a predetermined delay time, the data is held in the keeper circuit, and the propagated control signal is transmitted. Are sequentially output to the power gate transistors (21 to 23).
The power gate transistors (21 to 23) are composed of, for example, MOS transistors and function as SW (switches). Corresponding to the operation time of each domain, control signal (Enable) 1 to control signal N delayed from the control signal generation circuit 20 at a predetermined interval are supplied to the power gate transistors (21 to 23), and the power gates are sequentially turned on. The transistor is turned on to switch between the virtual GND (ground) 1 (41) to the virtual GNDN (43) and GND of each domain (domain 1 (31) to domain N (33)) of the power gate block 30.

The power gate block 30 is a block minimum block that is established as one function of the circuit, and further includes domains 1 to N. Each of these domains corresponds to a virtual GND 1 (41) to a virtual GND N (43) is provided.
Here, the domain 1 to the domain N are obtained by appropriately dividing the power gate block 30 at the timing of signal propagation.
For example, in FIG. 1, when the power gate transistors 21 to 23 are sequentially turned ON, the virtual GND1 to the virtual GNDN are sequentially connected to the ground in accordance with the operation of the domain 1 to the domain N. The operation is sequentially performed at a predetermined delayed timing.
As a result, the input signal (data) (Input) input from the input terminal is propagated to the subsequent domain while being activated or signal-processed in each domain, domain 2,..., Domain N. .
The indeterminate value signal propagation cutoff circuit (fence circuit) 34 shown in FIG. 1 is a circuit for preventing the indefinite value (signal) from the signal processing circuit 10 from propagating to the circuit block in the subsequent stage. The indeterminate value signal propagation cutoff circuit 34 is one of the guidelines for defining it as a minimum unit circuit block.

Next, the operation of the signal processing circuit 10 will be described with reference to FIG.
As shown in FIG. 1, the minimum unit circuit blocks are domainized in order from the earliest signal propagation timing. For example, the order is defined as domain 1, domain 2,.
The signal propagation timing for propagating in this domain is obtained from STA (Static Timing Analysis) results and the like.
As described above, virtual power lines (lines) in each domain are assumed to be virtual ground (GND) 1, virtual GND 2,..., Virtual GND. Thus, in the case of FIG. 1, the virtual power supply line is on the GND side.
During normal operation, the input signal propagates in the order of domain 1, domain 2,..., Domain N from the input (input terminal) side, and finally passes through the indefinite value signal propagation cutoff circuit 34 to the output (output terminal) side. Is output.
The virtual power supply line in each domain is connected to the original power supply (supply) line through the power gate transistors 21 to 23.

Further, each of the power gate transistors 21 to 23 is controlled by the control signal generation circuit 20, and is turned on sequentially from the power gate transistor connected to the domain close to the input (Input) at the timing of time t0 to tN. Timing constraints are as follows.
Here, the time from when the activation signal is input to the i-th domain (domain i) to when the activation signal is input to the (i + 1) -th domain is such that signal propagation ends within the i-th domain, i The time is sufficient for the signal corresponding to the output of the th domain to be determined.

At time t0, the control signal generation circuit 20 supplies the “H” level voltage of the control signal 1 to the gate of the power gate transistor (NMOS transistor 21). Then, the NMOS transistor 21 becomes conductive, and the virtual GND 1 connected to the drain is connected to the original power supply line, here the ground (GND).
As a result, the domain 1 is activated and starts signal processing (arithmetic processing). However, at time t0, the other power gate transistors 22 to 23 are non-conductive, and the corresponding domains 2 to N are also non-operating (inactive).

At time t1, the control signal 1 maintains the “H” level voltage and the domain 1 continues to operate. However, the control signal 2 that has further transitioned to the “H” level receives the power gate transistor (NMOS transistor 22). ) Is supplied to the gate.
Then, the NMOS transistor 22 becomes conductive, the virtual GND 2 of the domain 2 is connected to the original ground, the domain 2 becomes an operating state, and signal processing is started.
At time t1, the signal processing result of domain 1 that started operation at time t0 is propagated to domain 2, and signal processing is newly performed using the propagated signal (data) and other signals.

Thereafter, the same operation is repeated.
At time tN, the control signal N is supplied from the control signal generation circuit 20 to the gate of the power gate transistor (NMOS transistor 23), the NMOS transistor 23 is turned on, and the virtual GNDN of the domain N is connected to the original ground. Start operation.
Then, data output from the domain N according to the control signal from the control signal generation circuit 20 is output via the indefinite value signal propagation blocking circuit 34.

  In this way, each domain is divided into operation blocks, and each block is operated in the order of operation, so that the operation of the subsequent domain is stopped until the previous domain is activated or the operation ends, and the number of switching operations is performed on the input side of each domain. As a result, the switching rate of the entire circuit can be reduced and power consumption can be reduced.

FIG. 2 shows a circuit configuration of the control signal generation circuit 20 (100) shown in FIG. 1, which is another embodiment.
In the control signal generation circuit 100, a keeper circuit (also referred to as a keeper) includes a normal inverter (INV) that is not a power gate target and a pull-up PMOS transistor. This pull-up PMOS transistor is provided to reliably hold (keep) the value. The keeper circuit that holds data can be modified.
The other part of the circuit includes a power gate target inverter (INV) and an indeterminate value signal propagation cutoff circuit.
Here, the indeterminate value signal propagation cutoff circuit is for preventing the indefinite value signal in the circuit from propagating to other blocks when the power gate application circuit (signal processing circuit) is in the inactive state. It is a circuit and keeps outputting a certain value when it is in an inactive state.
The keeper is mounted as a set with a power switch or an indeterminate value signal propagation cutoff circuit (area surrounded by a broken line in the figure). An odd number of power gate target inverters are arranged between the input and the keeper, or between the two keepers, and the output value of the keeper is adjusted to be equal to the enable signal.
By mounting in this way, it becomes possible to keep the same value as the external power switch control signal at the input node of the power switch even in the inactive state. Therefore, the control signal propagation circuit and the indeterminate value signal propagation cutoff circuit can also be the target of the power gate, and the power supply may be shut off when inactive.

Next, a specific circuit configuration as an embodiment of the control signal generation circuit shown in FIG. 2 will be described.
A terminal to which a power gate enable (PGEN; Enable) signal is input is connected to a commonly connected gate of the PMOS transistor 105 and the NMOS transistor 106 and a gate of the NMOS transistor 107.
The source of the PMOS transistor 105 is connected to the power supply VDD 101, and the drain is connected to the drain of the NMOS transistor 106 and the commonly connected gates of the PMOS transistor 108 and the NMOS transistor 109.
The source of the NMOS transistor 106 is connected to a virtual power supply (or virtual GND (ground)) 102, the virtual GND 102 is connected to the drain of the NMOS transistor 107, and the source of the NMOS transistor 107 is connected to the GND 103.

The source of the PMOS transistor 108 constituting the PG (power gate) target INV (inverter) is connected to the power supply 101, and the drain is connected to the drain of the NMOS transistor 109 and the commonly connected gate of the PMOS transistor 110 and NMOS transistor 111. Yes. The source of the NMOS transistor 109 is connected to the virtual GND 102.
The source of the PMOS transistor 110 is connected to the power supply 101, the drain is connected to the drain of the NMOS transistor 111, the gate of the PMOS transistor 112 and the NMOS transistor 113 are connected in common, and the drain of the PMOS transistor 114. The source of the NMOS transistor 111 is connected to the virtual GND 102.
The source of the PMOS transistor 112, which normally constitutes INV and PG (power gate) -SW (switch), is connected to the power supply 101, the drain is connected to the drain of the NMOS transistor 113, and the source of the NMOS transistor 113 is connected to the GND 103. Has been. The source of the PMOS transistor 114 is connected to the power supply 110, and the gate is connected to the drain of the PMOS transistor 112 and the NMOS transistor 113 that are connected in common.
Further, the drain of the NMOS transistor 115 is connected to the virtual GND 102, the gate is connected to the drain connected to the PMOS transistor 112 and the NMOS transistor 113 in common, and the source is connected to the GND 103.

Similarly, PG target INV, normal INV and PG-SW, PG target INV,... Are repeated, and the output is connected to the commonly connected gates of the PMOS transistor 124 and the NMOS transistor 125.
The source of the PMOS transistor 124 is connected to the power supply 101, and the drain is connected to the drain of the NMOS transistor 125 and the gate of the PMOS transistor 126.
The source of the NMOS transistor 125 is connected to the GND 103. Further, the source of the PMOS transistor 126 is connected to the power supply 101, and the drain is connected to the commonly connected gates of the PMOS transistor 124 and the NMOS transistor 125.
The commonly connected drains of the PMOS transistor 124 and the NMOS transistor 125 are connected to the gate of the PMOS transistor 128 and the gate of the NMOS transistor 130, and further to the gate of the NMOS transistor 127.
The source of the PMOS transistor 128 is connected to the power supply 101, and the drain is connected to the drain of the NMOS transistor 130 and the drain of the PMOS transistor 129.
The source of the NMOS transistor 130 is connected to the drain of the NMOS transistor 131, the source of the NMOS transistor 131 is connected to the virtual GND 102, and LOGIC OUT (logic output signal) is supplied to the gate.
The source of the PMOS transistor 129 is connected to the power supply 101, the gate is connected to the gate of the NMOS transistor 131, and the LOGIC OUT signal is supplied.
The drain of the NMOS transistor 127 is connected to the virtual GND 102, the gate is connected to the commonly connected gate of the PMOS transistor 124 and the NMOS transistor 125, and the source is connected to the GND 103.

Next, the operation (activation, deactivation) of the control signal generation circuit 100 shown in FIG. 2 will be described with reference to FIG.
First, the operation when transitioning from OFF to ON operation will be described.
In the control signal generation circuit 100, the internal circuit is charged up by a leakage current during the OFF period. At that time, the logical values of the main nodes in the control signal generation circuit (100) are as shown in the table of FIG. 3, and all the power switches (NMOS transistors 107, 115, 121, 127) are OFF.
(1) When the enable (PGEN) signal becomes “H” level, the leading power switch is turned on to start activating the circuit. Here, the power switch includes a PMOS transistor 105 and NMOS transistors 106 and 107.
(2) The propagation circuit configured by the Power Gate target INV starts to operate and propagates the enable signal to the keeper.
Here, the Power Gate target INV includes a PMOS transistor 108 and an NMOS transistor 109, a PMOS transistor 110 and an NMOS transistor 111, a PMOS transistor 116 and an NMOS transistor 117, a PMOS transistor 122 and an NMOS transistor 123, and the like. The input signal is inverted by these INVs, and the inverted signal is output to the next INV or keeper.
The keeper includes PMOS transistors 112 and 114, an NMOS transistor 113, PMOS transistors 118 and 120, and an NMOS transistor 119.
(3) When the enable signal propagates to the keeper, the next power switch is turned on, and the activation of the signal processing circuit (domain) is further promoted. The keeper holds the “H” level.
For example, in a keeper composed of PMOS transistors 112 and 114 and an NMOS transistor 113, when a “L” level voltage is supplied to the input terminal, the drain connected to the PMOS transistor 112 and the NMOS transistor 113 in common is “H” level. Thus, this “H” level voltage is input to the gate of the positive feedback PMOS transistor 114 and is turned off, so that the commonly connected gates of the PMOS transistor 112 and the NMOS transistor 113 are at the “L” level. As a result, the output is maintained at the “H” level.
In addition, since this “H” level voltage is supplied to the gate of the NMOS transistor 115 of the power gate transistor, it becomes conductive and the virtual GND 102 is connected to the original ground 103.
Here, the power gate (switch) includes NMOS transistors 115, 121, 127, and the like.
(4) Thereafter, the operations of (2) and (3) are repeated, and the activation of the circuit and the ON operation of the power switch are performed in parallel.
(5) When the enable (PGEN) signal propagates to the indefinite value signal propagation cutoff circuit, a signal corresponding to the output of the logic is inverted and output.
The indeterminate value signal propagation cutoff circuit is composed of PMOS transistors 124 and 126 and an NMOS transistor 125.
The circuit that inverts the output signal of the logic includes PMOS transistors 128 and 129 and NMOS transistors 130 and 131.
Since the drain outputs of the PMOS transistor 124 and the NMOS transistor 125 are at “H” level, the PMOS transistor 128 is OFF and the NMOS transistor 130 is ON.
Under this condition, if Logic Out is at “H” level, a voltage of “H” level is supplied to the gate of the PMOS transistor 129 and the gate of the NMOS transistor 131, so that the PMOS transistor 129 is turned off and the NMOS transistor 131 is turned off. Becomes an ON operation state. As a result, the output terminal Out becomes “L” level.
On the other hand, when Logic Out is at “L” level, the PMOS transistor 129 is turned on, and the NMOS transistor 131 is turned off.
As a result, the Out output terminal becomes “H” level.
(6) The activation of the circuit is completed.

Next, circuit operation when the control signal generating circuit 100 is turned off from on will be described.
(1) When the enable (PGEN) signal becomes “L” level, the head power switch is turned off and the signal processing circuit starts to be deactivated. However, since the power switch at the subsequent stage remains ON, the propagation circuit itself can operate.
(2) The propagation circuit constituted by the Power Gate target INV propagates the enable signal to the keeper.
For example, when the “L” level of the enable signal is propagated to INV composed of the PMOS transistor 110 and the NMOS transistor 111, the PMOS transistor 110 is turned on and the NMOS transistor 111 is turned off, and the outputs are connected in common. The drain becomes “H” level.
(3) When the enable signal propagates to the keeper, the next power switch is turned OFF, and the inactivation of the circuit is further promoted. Here, it is important that the “L” level is kept in the keeper.
In FIG. 2, the “H” level of the drain output of the PMOS transistor 110 and NMOS transistor 111 of the Power Gate target INV is supplied to the PMOS transistors 112 and 114 and the NMOS transistor 113 constituting the keeper.
As a result, the commonly connected drains of the PMOS transistor 112 and the NMOS transistor 113 are at the “L” level. Then, this “L” level voltage is supplied to the gate of the positive feedback PMOS transistor 114, becomes ON, and becomes conductive, and the “H” level voltage is supplied to the common gate of the PMOS transistor 112 and NMOS transistor 113. The keeper output is maintained at the “L” level.
At the same time, the “L” level of the drain outputs of the PMOS transistor 112 and the NMOS transistor 113 is supplied to the gate of the NMOS transistor 115 of the power switch, so that the NMOS transistor (115) changes from the ON operation state to the OFF operation state. Transition.
(4) Thereafter, (2) and (3) are repeated, and the circuit deactivation and the power switch OFF operation are performed in parallel. Since the last power switch (for example, NMOS transistor 121) is turned off after the signal has propagated to the end of the propagation circuit, the signal will not stop propagating as the circuit is deactivated.
(5) When the enable signal propagates to the indefinite value signal propagation cutoff circuit, the “H” level is output. This indeterminate value signal propagation cutoff circuit corresponds to the Fence circuit of FIG.
(6) Deactivation of the circuit is completed.

Next, charge-up during the OFF period of the control signal generation circuit 100 will be described with reference to FIG.
During the OFF period, the circuit is charged up by a leak current, and each node changes from "L" level to "H" level and from "H" level to "H" level. The nodes N2 and N4 in this circuit are originally at the “H” level and are not affected by the charge-up, so that the value held in the keeper does not change. As a result, the power switch can be accurately kept OFF even during charge-up.
The above is the description of the operation of the control signal generation circuit 100.

Next, the monitoring operation in the activated state will be described by taking a logic circuit as an example with this circuit configuration.
When the logic circuit of the Power Gate application circuit has been activated, it is at least necessary that the input signal has propagated through the circuit at the time of activation and all internal nodes have been stabilized. Here, if the virtual power supply line of the propagation circuit and the logic circuit is common, the activation state of the logic circuit can be reflected.
The signal propagation speed of the logic circuit at the time of activation dynamically changes depending on the potential of the virtual power supply line, and the propagation speed increases as the potential of the virtual power supply line approaches. If the virtual power supply lines are shared and the delay times of each other are set in advance, the change in the signal propagation speed of the logic circuit is reflected in the propagation circuit as it is.
Therefore, it is possible to monitor whether the signal has been propagated even in the logic circuit only by monitoring whether the signal has completely propagated through the propagation circuit.
If a signal indicating that the internal state is stable in the logic circuit can be generated in the signal processing circuit, the control signal for the indefinite value signal propagation blocking circuit and the control signal for the next Power Gate application block can be automatically generated.

The circuit configuration of a control signal generation circuit which is another embodiment will be described below.
In FIG. 2, a pull-up PMOS transistor is mounted on the keeper. However, a keeper having no pull-up PMOS transistor is also possible. If the feedback structure is eliminated by removing the pull-up PMOS transistor, the keeper output value is held by the parasitic capacitance.
The node corresponding to the input of the keeper transitions to the “H” level when deactivated, and continues to be charged by the leak current even during the inactive state, so that the “H” level can be maintained. Thereby, the output value of the keeper can continue to hold the same “L” as the power switch control signal even in the inactive state.

FIG. 4 shows a control signal generation circuit 200 that transmits a tree-like control signal using a keeper without a pull-up PMOS transistor according to another embodiment.
The input terminal is connected to the input of the inverter 201 and the gate of the NMOS transistor 211 of the power switch. The output of the inverter 201 is connected to the input of the subsequent inverter 202.
The grounding terminal (ground) of the inverter 201 is connected to the drain of the NMOS transistor 211 and the virtual power supply (virtual GND) 220, and the source of the NMOS transistor 211 is connected to the original ground (GND).
The output of the inverter 202 is connected to the input of the inverter 203 and the input of the inverter 203B.
In the case of a grounding terminal of the inverter 202, for example, a CMOS configuration, the source of the NMOS transistor is connected to the virtual GND 220.
In the following, the same circuit connection configuration is used, but the output of the inverter 205 is that of a keeper (206, 206A to 206C, 208, 208A to 208C in FIG. 4) composed of a normal inverter connected to the subsequent stage and a pull-up PMOS. The output is connected to the gate of the power switch NMOS transistor 212 and the input of the normal inverter 207. The grounding terminal of the inverter 207 is connected to the virtual GND 220.
The output of the inverter 207 is connected to the input of the keeper (208), and the output of the keeper (208) is connected to the gate of the NMOS transistor 213 of the power switch.
The drains of the NMOS transistors 211, 212, and 213 of these power switches are commonly connected to the virtual GND 220, and the sources are connected to the original ground (GND).

The output of the inverter 203 is connected to the input of the first-stage inverter 204A of another tree, and the ground output terminal is connected to the virtual GND 220A. The virtual GND 220A is connected to the virtual GNDs 220, 220B, and 220C at one end.
The connection configuration between the inverter connected to the virtual GND 220A and the keeper is the same as the circuit configuration after the inverter 204 connected to the virtual GND 220B.

The connection configuration between the inverter connected to the virtual GND 220 </ b> B and the keeper is the same as the circuit configuration after the inverter 203 connected to the virtual GND 220.
Furthermore, the connection configuration between the inverter connected to the virtual GND 220C and the keeper is the same as the circuit configuration after the inverter 204B connected to the virtual GND 220B.

Next, the operation of the control signal generation circuit 200 will be described.
When the “H” level voltage of the control signal (Enable signal) is input to the input of the inverter 201 and the gate of the NMOS transistor 211 of the power (power) switch, the NMOS transistor 211 is turned on, and the virtual GND 220 is Connected to ground. Then, the input signal is inverted by the inverter 201 to output an “H” level voltage.
The inverter operation is repeated, and an “L” level voltage is supplied to the input of the keeper 206, where it is inverted and an “H” level voltage is output. This “H” level voltage is supplied to the input of the inverter 207 in the next stage and the gate of the NMOS transistor 212 of the power switch. Then, the NMOS transistor 212 is turned on, and the virtual ground 220 (a power switch is provided in the middle of the wiring in consideration of the wiring length) and the original ground are connected via a power switch arranged in the middle of the wiring. The
The “L” level voltage inverted by the inverter 207 is input to the keeper 208, where it is inverted and the “H” level voltage is output, supplied to the gate of the NMOS transistor 213 of the power switch, and the wiring of the virtual GND 220 One end of is connected to the original ground.
These keeper output voltages are output as control voltages to the power gate transistors that drive the domains of the power gate block.
The circuit operation connected to the tree of the virtual GNDs 220A, 220B, and 220C is the same as that described above.

When the input signal is at “L” level, this “L” level signal propagates, and the NMOS transistors 211, 212, 212A, 212B, 212C, 213, 213A, 213B, and 213C of the power switch are sequentially shifted to the OFF state. The inverters and keepers constituting each tree stop operating.
However, the values of the keepers (206, 206A to 206C, 208, 208A to 208C) are held by the parasitic capacitance as described above.
Since the input terminal of the keeper becomes “H” level when inactivated, the keeper output is held at “L” level.

The control signal generation circuit 200 having the tree configuration shown in FIG. 4 shows an example in which an NMOS transistor is used as a power switch, but when a PMOS transistor is used as a power switch as shown in FIG. Is also applicable. At that time, the only change in the structure of the keeper is that the pull-up PMOS transistor becomes a pull-down NMOS transistor, and there is no change in the normal inverter.
Further, the keeper can hold data without using a positive feedback transistor, for example, using a parasitic capacitance.

FIG. 5 shows a circuit configuration of a keeper (circuit) 250 constituting the control signal generating circuit. The source of the PMOS transistor 251 is connected to the power supply VDD 254, the drain is connected to the drain of the NMOS transistor 252, and the gate is connected to the gate of the NMOS transistor 252 and the drain of the NMOS transistor 253.
The source of the NMOS transistor 252 is connected to the ground 256, and the source of the NMOS transistor 253 is also connected to the ground 256.
The drain of the PMOS transistor 251 and the NMOS transistor 252 connected in common is connected to the gate of the PMOS transistor 254 and the gate of the NMOS transistor 253, the source of the PMOS transistor 254 is connected to the power supply VDD 254, and the drain is a virtual power supply (line). It is connected to VDD255.

When the “H” level voltage is supplied to the gate inputs of the PMOS transistor 251 and the NMOS transistor 252 constituting the inverter, the output becomes the “L” level, the PMOS transistor 254 is turned on, and the circuit starts operating. . At this time, the NMOS transistor 253 is OFF.
On the other hand, when the “L” level voltage is supplied to the input of the inverter, the output becomes the “H” level, and the PMOS transistor 254 of the power switch is turned off.
Further, the “H” level voltage of the inverter output is supplied to the gate of the NMOS transistor 253 to perform the ON operation, the “L” level voltage is fed back to the input, and this state is maintained.
Since the input of the PMOS transistor 251 and the NMOS transistor 252 constituting the inverter is “L” level and the output thereof is “H” level during the OFF period and the charge-up period of the keeper, the gate of the positive feedback NMOS transistor 253 is “ The H "level voltage is supplied and the ON operation is performed. As a result, the keeper input is held at the “L” level and the output is held at the “H” level.

As described above, the additional circuit (control signal generation circuit) itself when the Power Gate is applied can also be a target of the power gate, and a wasteful increase in leakage current generation sources can be suppressed.
In addition, the Power Gate application circuit and the signal transmission (control signal generation) circuit to the keeper share a virtual power supply line, so that the signal propagation speed during circuit activation is almost the same if both delay times are aligned. Thus, it is possible to dynamically know whether or not the circuit has been activated by monitoring the value of the keeper. By using the signal, it is possible to automatically generate a control signal for the indefinite value signal propagation blocking circuit and a control signal for the next Power Gate application block.

Next, a circuit in which the power gate block according to the embodiment shown in FIG. 1 is applied to the multiplier 300 will be described with reference to FIG.
6A shows a circuit when a power gate is applied to the multiplier 300 as in the past, and FIG. 6B shows a multiplier 350 using a minimum unit circuit block, and the circuit is divided into three domains ( The circuit is divided into a partial product (Partial Products), a Wallance tree (Wallance Tree, an adder; Adder). In FIGS. 6A and 6B, the solid line arrows indicate the propagation state of the input signal, and the dotted line arrows indicate the propagation state of the glitch naturally generated in the circuit.

In the multiplier 300 shown in FIG. 6A, three blocks indicated by broken lines of the partial product block 303, the Wallance tree block 304, and the adder block 305 are configured as one domain, and the output of the adder block 305 is an indefinite value. A signal propagation blocking circuit 306 is connected.
Further, a virtual ground (GND) is provided in the block of the partial product block 303, a virtual GND is provided in the wallance tree block 304, and a virtual GND is provided in the adder block 305.
However, as shown in the figure, the virtual GNDs provided in each of these blocks are connected to each other.

The virtual GND 310 of the partial product block 303 is connected to the drain of the power gate transistor (NMOS transistor) 307, the source of the NMOS transistor 307 is connected to the original ground, and the control signal 1 of the enable signal is supplied to the gate. The
The virtual GND 310 of the Wallance tree block 304 is connected to the drain of a power gate transistor (NMOS transistor) 308, the source of the NMOS transistor 308 is connected to the original ground, and the control signal 2 of the enable signal is supplied to the gate.
Similarly, the virtual GND 310 of the adder block 305 is connected to the drain of a power gate transistor (NMOS transistor) 309, the source of the NMOS transistor 309 is connected to the original ground, and the control signal 3 of the enable signal is supplied to the gate. The

The timing of the control signal supplied to the gates of the power gate transistors (NMOS transistors 307, 308, 309) is delayed from the time when the “H” level voltage of the control signal 1 is supplied to the gate of the NMOS transistor 307 at time t0. At time t 1, the control signals 2 and 3 having the “H” level voltage are simultaneously supplied to the gates of the NMOS transistors 308 and 309.
However, since the entire circuit is activated simultaneously, the propagation path length of the glitch becomes long.

A solid arrow shown in FIG. 6A indicates a state when the input signal propagates through each block. This input signal is the same as the signal propagation during normal operation, and each node switches several times according to the input signal (a, c, e).
On the other hand, the state of propagation of glitches (b, d, f, g, h, i) generated in each block is indicated by dotted arrows. For example, the glitch (b, d) generated in the partial product block 303 propagates through the Wallance tree block 304 and the adder block 305 and is output to the indeterminate value signal propagation cutoff circuit 306.
Further, the glitch (f, g) generated in the Wallance tree block 304 propagates through the adder block 305 and is output to the indeterminate value signal propagation cutoff circuit 306.
Similarly, the glitch (h, i) generated in the adder block 305 is output to the indeterminate value signal propagation cutoff circuit 306.
As described above, the naturally occurring glitch propagates in the circuit similarly to the propagation of the input signal, and propagates to the indefinite value signal propagation cutoff circuit 306 unless it is absorbed in the middle.
Further, in some cases, the switching is generated as much as the input is given several times to the circuit and propagates to the indefinite value signal propagation cutoff circuit 306.
Therefore, when a power gate circuit is applied to the multiplier 350 shown in FIG. 6A, useless power generated when the power gate application circuit is activated cannot be reduced.

Next, FIG. 6B shows a multiplier 350 to which a power gate according to an embodiment of the present invention is applied.
The circuit block of the multiplier 350 is the same as that shown in FIG. 6A, but each circuit block is configured as one domain and operates independently of each other.
The multiplier 350 will be specifically described below.
The multiplier (351) includes a partial product domain 353, a Wallance tree domain 354, an adder domain 355, an indeterminate value signal propagation cutoff circuit 356, a virtual GND (ground) 1 (360), a virtual GND2 (361), and a virtual It is composed of GND3 (362) and power gate transistors (NMOS transistors) 357, 358, and 359 for driving the GND3 (362).
An independent virtual GND 1 is provided in the partial product domain 353, and this virtual GND 1 is connected to the drain of a power gate transistor (NMOS transistor) 357, and a control signal 1 is supplied to the gate to turn ON (ON) and OFF (OFF). As a result, the virtual GND 1 and the original ground are connected or disconnected via the source.
An independent virtual GND 2 is provided in the Wallance tree domain 354, and this virtual GND 2 is connected to the drain of a power gate transistor (NMOS transistor) 358, supplied with a control signal 2 to the gate, and controlled ON and OFF, The GND 2 and the original ground are connected or disconnected via the source.
Similarly, an independent virtual GND 3 is also provided in the adder domain 355, and this virtual GND 3 is connected to the drain of a power gate transistor (NMOS transistor) 359, and a control signal 3 is supplied to the gate for ON / OFF control. Thus, the virtual GND 3 and the original ground are connected or disconnected via the source.

Next, the operation of the multiplier 350 to which the power gate circuit of FIG. 6B is applied will be described.
Prior to time t0, the control voltages 1, 2, and 3 supplied to the gates of the NMOS transistors 357, 358, and 359 are all at the “L” level, so that the operations of the NMOS transistors 357 to 359 are OFF and non- Conduction is established, and the virtual GND and the original ground are cut off.
As a result, all domains (partial product domain 353, Wallance tree domain 354, and adder domain 355) are in the off operation state.

At time t 0, the control signal 1 output from the control signal generation circuit (20, 100, 200) transitions from the “L” level to the “H” level, and the “H” level voltage is the gate of the NMOS transistor 357. To be supplied. Then, the NMOS transistor 357 is turned on, and the virtual GND 1 is connected to the original ground, and a normal voltage is supplied between the power supply of the partial product domain 353 and the ground to activate the NMOS transistor 357. Be started.
The input signal at this time is indicated by, for example, a1, c1, e1 and solid line arrows, and a glitch naturally generated in the partial product domain 353 is indicated by broken line arrows b1, d1.
The glitches b1 and d1 are supplied to the input of the next-stage Wallance Tree Domain 354, but since the Wallance Tree Domain 354 is not operating yet, this glitch is not input (FIG. 6B).

At time t1, since the control signal 2 output from the control signal generation circuit (20, 100, 200) is supplied to the gate of the NMOS transistor 358 and the control signal 2 is at “H” level, the ON operation is performed. Conduct. As a result, the virtual GND 2 is connected to the original ground.
Here, the time t1 is delayed by a predetermined time with respect to the time t0, but this delay time is the time from the time t0 until the power-on of the arithmetic processing is stabilized or the operation is completed for the partial product domain 353. is there.
The wallance tree domain 354 starts operation, and the result obtained by processing the signals a1, c1 and e1 in the partial product domain 353 is input, and the bit tree adder similar to the column adder performs the Wallance tree processing. Arithmetic processing for obtaining the sum of products is performed (solid arrow).
Similarly, in this Wallance tree domain 354, a glitch occurs spontaneously, and this state is represented by, for example, broken line arrows f1 and g1. The glitches f1 and g1 are output to the input of the adder domain 355 in the subsequent stage, but since the adder domain 355 is not yet operated, it is blocked by the input of the adder domain 355.

When the power-on operation of the arithmetic processing power supply stabilizes or completes in the Wallance tree domain 354 and the time t2 is reached, the “H” level voltage output from the control signal generation circuit (20, 100, 200) The control signal 3 is supplied to the gate of the NMOS transistor 359 and is turned on, and the virtual GND 3 is connected to the original ground. As a result, the adder domain 355 starts a predetermined operation.
The data (signals) a1 and e1 processed in the adder domain are output to the indeterminate value signal propagation cut-off circuit 356, and further the glitches h1 and i1 generated in this domain are sent to the indefinite value signal propagation cut-off circuit 356 in the subsequent stage. Is output.

As described above, in the multiplier 350 shown in FIG. 6B, the domain itself is not yet activated even if the input node (terminal) of the domain is switched by the input signal. Does not propagate to
Further, since the domain is activated after the input node is determined, the actual switching of the input node is not more than once from the viewpoint of the domain.
In this way, the number of switching operations can be greatly reduced at the entrance of each domain, so that the switching rate of the entire circuit can be reduced.Furthermore, glitches generated in each domain do not propagate in the subsequent domain, thus suppressing unnecessary switching. ing.
In this way, useless glitch propagation can be greatly reduced, and the switching rate of the entire circuit can be reduced.
As described above, by sequentially operating the domains in response to the control signal of the power gate, it is possible to reduce wasteful power generated when the Power Gate application circuit is activated.
Further, since the control signal generation circuit itself for controlling the power gate transistor of the multiplier 350 can also be power gate controlled, the power consumption can be further reduced.

FIG. 7 shows a signal processing circuit 400 having a power gate block according to another embodiment.
The domain of Power Gate Block in FIGS. 1 and 6-B shows an application example for an N-type (power gate using an N-channel MOS transistor) circuit using an NMOS transistor as a power switch. FIG. 7 shows a P-type circuit using a PMOS transistor.
The signal processing circuit 400 includes a domain 1 (401), a domain 2 (402),..., A domain N (403), an indeterminate value signal propagation blocking circuit 404, power gate transistors PMOS transistors 405, 407, and 409. It is configured.
Each of the domains 1 to N constituting the power gate block includes a virtual power supply line VDD (virtual VDD1 (406), virtual VDD2 (408),..., Virtual VDDN (410)).
These virtual power supply lines VDD are connected to the drains of the power gate transistors (PMOS transistors 405, 407, 409), the sources are connected to the original power supply VDD (power supply) lines, and the gates are the control signal 1 and control signal. 2, ..., the control signal N is supplied at a predetermined timing.

  In the N type, the virtual GND (line) is connected to the original ground by a power gate transistor (NMOS transistor). However, in the P type power gate block, the power gate transistor of the PMOS transistor is controlled by a control signal. The configuration is such that ON / OFF control is performed, and the virtual power supply (line) VDD provided in each domain is connected to or cut off from the original power supply (supply line).

The operation of the signal processing circuit 400 having the P-type power gate block shown in FIG. 7 will be described.
The control signal 1, the control signal 2,..., The control signal N output from the control signal generation circuit (20, 100, 200) are “H” level voltages, and the “H” level voltage is the power gate transistor. (PMOS transistors) 405, 407,..., 409 are supplied to the gates, and these PMOS transistors are all in the OFF operation state.
Therefore, the virtual power supplies VDD1, VDD2,..., VDDN of each domain 1, domain 2,..., Domain N are not connected to the original power supply VDD, and the operations of all domains are OFF.
Next, the control signal 1 output from the control signal generation circuit (20, 100, 200) transits from the “H” level to the “L” level, and the other control signals 2,. If the "H" level is maintained, only the PMOS transistor 405 of the power gate transistor is turned on, the virtual power supply VDD1 is connected to the original power supply VDD, and the other virtual power supplies VDD2, ..., VDDN and the original power supply The space remains blocked.
Then, the domain 1 starts operation, and signals (a2, b2, c2) are input from the input terminals, and signal processing is started. Further, during this signal processing, a glitch occurs spontaneously in the domain 1 and is output to the input terminal of the domain 2.
However, since the domain 2 is still in the OFF operation state at this time, even if a glitch is input, it is blocked on the input side and is not input to the domain 2. This operating state continues until domain 2 starts operating.

When the control signal 2 output from the control signal generation circuit (20, 100, 200) is delayed for a predetermined time from the control signal 1 and a voltage of “L” level is supplied to the PMOS transistor 407, the PMOS transistor 407 is turned on, and the virtual power supply VDD2 is connected to the original power supply VDD, and the domain 2 starts operation. At this time, the domain 1 is already activated, its operation state is stable, and the operation is started or completed.
The input signal (a2, b2, c2) starts signal processing in the domain 2, while a glitch occurs spontaneously in the domain 2. However, this glitch is blocked at the input end because the subsequent domain 3 is inactive.

Thereafter, the operation is repeated in the same manner.
When the control signal N output from the control signal generation circuit (20, 100, 200) changes from the “H” level to the “L” level, the PMOS transistor 409 is turned on, and the virtual power supply VDDN becomes the original power supply VDD. Once connected, domain N begins operation.
When the signal processing is completed in the domain N, the processed signal is output to the indeterminate value signal propagation blocking circuit 404 and output from the power gate block 400 at a predetermined timing.

As described above, in the signal processing circuit 400 having the P-type power gate block shown in FIG. 7, the domain itself is not activated even if the input node (terminal) of the domain is switched many times by the input signal. The resulting glitch does not propagate into the domain.
The switching frequency of the entire circuit can be reduced because the number of switching operations can be significantly reduced at the entrance of each domain. Further, since glitches generated in each domain do not propagate in the subsequent domain, unnecessary switching is suppressed.
In this way, useless glitch propagation can be greatly reduced, and the switching rate of the entire circuit can be reduced.
As described above, by sequentially operating the domains in response to the control signal of the power gate, it is possible to reduce wasteful power generated when the Power Gate application circuit is activated.
Further, since the control signal generation circuit itself for controlling the power gate transistor of the signal processing circuit 400 having this power gate block can also be power gate controlled, the power consumption can be further reduced.

FIG. 8 shows a signal processing circuit 450 having a PN type power gate block using both a PMOS transistor and an NMOS transistor as power gate transistors according to another embodiment.
A signal processing circuit 450 shown in FIG. 8 is provided with a virtual power supply VDD (line) and a virtual GND (line) in each domain, and the virtual power supply VDD and the virtual GND line are controlled by a control signal using a PMOS transistor and an NMOS transistor. The operation of each domain is controlled by operating ON and OFF and connecting or blocking both lines.

In the domain 1 (451), a virtual power supply VDD1 (457) and a virtual GND1 (458) are provided. The virtual power supply VDD1 is connected to the drain of the PMOS transistor 456, and the source of the PMOS transistor 456 is the original power supply. Connected to VDD, the control signal 1 is supplied to the gate.
The virtual GND 1 is connected to the drain of the NMOS transistor 458, the source of the NMOS transistor 458 is connected to the original GND, and a control signal obtained by inverting the control signal 1 by the inverter 455 is supplied to the gate.
Hereinafter, the virtual power supply VDD and virtual GND in each domain and the power gate transistor for driving the same are configured similarly.
From the control signal 1 to the control signal N, the “H” level is changed to the “L” level at a predetermined timing, and the operations of the respective domains 1 (451),..., Domain N (452) are sequentially performed correspondingly. Start.
When the domain up to the domain N-1 is stabilized or the operation is completed and the control signal N becomes the “L” level, the control signal 1,..., The control signal N are all at the “L” level at this time. , All domains are in operation.
Then, the signal processing is started in the domain N, and when the processing is completed, the signal processed in the domain N is output to the input of the indefinite value signal propagation cutoff circuit 453.
The signal processed by the power gate block 450 is output from the indeterminate value signal propagation cutoff circuit 453 at a predetermined timing.
Also in the signal processing circuit 450, each domain is a control signal 1 output from the control signal generating circuit (20, 100, 200),..., A control signal N corresponding to a domain 1 corresponding to the control signal 1 at a predetermined timing,. -Since it is supplied to the domain N, the glitch is not propagated downstream.

As described above, in the signal processing circuit 450 having the PN type power gate block shown in FIG. 8, the domain itself is not yet activated even if the input node (terminal) of the domain is switched by the input signal. The resulting glitch does not propagate into the domain.
The switching frequency of the entire circuit can be reduced because the number of switching operations can be significantly reduced at the entrance of each domain. Further, since glitches generated in each domain do not propagate in the subsequent domain, unnecessary switching is suppressed.
In this way, useless glitch propagation can be greatly reduced, and the switching rate of the entire circuit can be reduced.
As described above, by sequentially operating the domains in response to the control signal of the power gate, it is possible to reduce wasteful power generated when the Power Gate application circuit is activated.
Furthermore, since the control signal generation circuit itself for controlling the power gate transistor can also be power gate controlled, power consumption can be further reduced.

In addition, the domains shown in FIGS. 1, 6B, 7 and 8 are arranged in one column. However, if the domain has no feedback, the domain is not a topology arranged in one column. Also good.
FIG. 9 shows a signal processing circuit 500 having a power gate block according to another embodiment.
Here, in the signal processing circuit 500 of FIG. 9, the power gate transistor for controlling each domain and the control signal for controlling it are omitted.
In the signal processing circuit 500, domain 1 (501) and domain 2 (502) are arranged in parallel on the signal input side. Conventionally, it is arranged in the column direction, but in this example, it is arranged in the row direction.
Domain 3 (503) is arranged in the column direction with respect to domain 1, and a part thereof is adjacent to domain 2.
The domain 4 (504) is arranged in parallel and in the column direction with respect to the domain 3, and the domain 5 (505) and the domain 6 (506) are arranged in parallel.
In the following, domains are arbitrarily arranged, for example, along the signal flow, and finally an indefinite value signal propagation blocking circuit 507 is arranged at the output end of the signal processing circuit 500.

The operation of the domain shown in FIG. 9 and the accompanying signal flow will be described.
In accordance with the control signal output from the control signal generation circuit (20, 100, 200), the domain 1 operates first, and then the domain 2 operates. When domain 1 is operating, domain 2 is still inactive.
When the power-on operation of domain 1 is stabilized or the operation is completed, domain 2 is activated and starts operation. At this time, the domain 1 is also operating.
When the power supply rise of the domain 2 is stabilized or the operation is completed, the domain 3 is activated by the control signal to start the operation. At this time, the domain 3 is supplied with signals that have been subjected to signal processing from the outputs of both the domain 1 and the domain 2.
As another example, if the domain 1 and the domain 2 operate independently of each other and no signal is exchanged between them, the operation may be started simultaneously. In this case, when the power-up of the domains 1 and 2 is stabilized or the operation is completed, signals processed in these domains are output to the domain 3.
When the rise of the power supply is stabilized or the operation is completed in the domain 3, the domain 4 starts to operate according to the control signal. Then, for example, the signal processed in the domain 3 and the domain 2 is input to the domain 4 and signal processing is performed.
Thereafter, the same operation is repeated, and when the last domain is completed, the data obtained as a result is supplied to the indeterminate value signal propagation cutoff circuit 507 and output from the signal processing circuit 500 at a predetermined timing.

The domain regions and arrangements described above are only examples, and the arrangement can be arbitrarily changed.
Also in the signal processing circuit 500 shown in FIG. 9, the glitch generated in each domain does not propagate to the subsequent domain, and wasteful switching can be suppressed.
In addition, by sequentially operating the domains in response to the power gate control signal, it is possible to reduce wasteful power generated when the power gate block is activated.
Further, since the control signal generation circuit itself for controlling the domain of the power gate can also be power gate controlled, the power consumption can be further reduced.

As described above, since the glitch from the previous stage does not propagate to the domain that is not activated, the switching rate at the time of activation can be suppressed, and wasteful power consumption can be greatly reduced.
In addition, since the time for activating each domain is shorter than the time for activating the entire circuit block at the same time, the indefinite state of the internal node can be shortened, and the through current during activation can be reduced.
Furthermore, since the overhead that occurs in the ON operation from the OFF state of the power gate application circuit is suppressed, the minimum circuit OFF period for obtaining the leakage current reduction effect can be shortened.
Further, since the ON timing of the power gate transistor in the circuit block is shifted, a function of suppressing rush current can be included.
Further, the additional circuit itself at the time of applying the power gate can also be the target of the power gate, and a wasteful increase in the leakage current generation source can be suppressed.
Since the signal transmission circuit to the keeper of the Power Gate application circuit and the additional circuit shares a virtual power line, if the delay times of both are made uniform, the signal propagation speed during circuit activation is almost equal between the two. It is possible to dynamically know whether the circuit has been activated by monitoring the value of. By using the signal, it is possible to automatically generate a control signal for the indefinite value signal propagation blocking circuit and a control signal for the next Power Gate application block.

It is the circuit diagram which showed the circuit structure of the power gate block of this invention. FIG. 2 is a diagram showing a circuit configuration of a control signal generation circuit shown in FIG. 1. FIG. 3 is a diagram for explaining an operation of a control signal generation circuit shown in FIG. 2. It is a circuit diagram of the control signal generation circuit of the other embodiment of the present invention. FIG. 5 is a diagram showing a circuit configuration of a control signal generation circuit shown in FIG. 4. It is the circuit diagram which showed the circuit structure of the power gate block for comparing with the other power gate block of this invention. It is the circuit diagram which showed the structure of the signal processing circuit which has the other power gate block of this invention. It is the circuit diagram which showed the structure of the other signal processing circuit of this invention. It is the circuit diagram which showed the structure of the other signal processing circuit of this invention. It is the figure which showed arrangement | positioning of the other signal processing circuit of this invention.

Explanation of symbols

10, 300, 350, 400, 450, 500 ... signal processing circuit, 20, 100, 200 ... control signal generation (control) circuit, 21, 22, 23, 307, 308, 309, 357, 358, 359, 405 407, 409, 456, 459, 461, 464 ... power gate transistors, 41-43, 102, 220, 220A-220C, 310, 360-362, 458, 463 ... virtual power supply (GND; ground), 30, 301, 351, 430, 480, 530 ... power gate block, 31, 32, 33, 353, 354, 355, 401, 402, 403, 451, 452, 501-506 ... domain, 34, 306, 356, 404, 453 507... Undefined value signal propagation cutoff circuit, 106, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125, 127, 130, 131, 211, 212, 212A to 212C, 213, 213A to 213C, 252, 253 ... NMOS transistors, 105, 108, 110, 112, 114, 116 , 118, 120, 122, 124, 126, 128, 129, 251, 254 ... PMOS transistors, 201-205, 207, 204A-204C, 205A-205C, 207A-207C, 455,460 ... inverters, 255,406, 408, 410, 457, 462... Virtual VDD.

Claims (9)

A circuit block that processes signals while propagating;
A power supply line for supplying power for activating the circuit block;
A plurality of virtual power supply lines provided in each domain when the circuit block is divided into a plurality of domains in order of early signal propagation timing;
A plurality of switching means connected between each of the virtual power supply line and the power supply line, for connecting or blocking the virtual power supply line to the power supply line;
A control signal generating circuit for outputting a control signal to the plurality of switching means and activating a domain corresponding to the switching means supplied with the control signal;
The control signal generation circuit includes:
In order to sequentially activate the plurality of domains in the order of propagation timing of the signals, output control signals of individual timing to the plurality of switching means,
When outputting a control signal corresponding to a domain that is activated second or later in the order of propagation timing of the signal, the switching means of the domain that has already been activated according to the order of propagation timing of the signal Having a plurality of inverters to which an enable signal as a basis of the control signal for continuously outputting a control signal for maintaining each activated domain in an active state is input to the first stage;
The plurality of inverters are
Propagating while inverting the enable signal, and outputting the control signal for activating the next domain from the inverter corresponding to the operation completion time of each domain,
Of the plurality of inverters,
The inverter that outputs the control signal is connected to the power supply line,
The other inverters are connected to the virtual power line that is connected or disconnected by the switching means based on the control signal.
Signal processing circuit. The control signal generation circuit includes:
When the plurality of domains are sequentially activated by the plurality of control signals, from when a control signal for activating a certain domain is output until a control signal for activating the next domain is output The signal processing circuit according to claim 1, wherein a time until the operation is completed after the signal is propagated in the certain domain is secured as the time. A circuit block that processes signals while propagating;
A power supply line for supplying power for activating the circuit block;
A plurality of virtual power supply lines provided in each domain when the circuit block is divided into a plurality of domains in order of early signal propagation timing;
A plurality of switching means connected between each of the virtual power supply line and the power supply line, for connecting or blocking the virtual power supply line to the power supply line;
A control signal generating circuit for outputting a control signal to the plurality of switching means and activating a domain corresponding to the switching means supplied with the control signal;
Have
The control signal generation circuit includes:
In order to sequentially activate the plurality of domains in the order of propagation timing of the signals, output control signals of individual timing to the plurality of switching means,
When outputting a control signal corresponding to a domain that is activated second or later in the order of propagation timing of the signal, the switching means of the domain that has already been activated according to the order of propagation timing of the signal Having a plurality of inverters to which an enable signal as a basis of the control signal for continuously outputting a control signal for maintaining each activated domain in an active state is input to the first stage;
The plurality of inverters are
Propagating while inverting the enable signal, and outputting the control signal for activating the next domain from the inverter corresponding to the operation completion time of each domain,
A plurality of transistors provided in a one-to-one correspondence with each inverter that outputs the control signal;
Each transistor holds the value of each inverter
Signal processing circuit . The control signal generation circuit includes:
When the plurality of domains are sequentially activated by the plurality of control signals, from when a control signal for activating a certain domain is output until a control signal for activating the next domain is output 4. The signal processing circuit according to claim 3, wherein a time until the operation is completed after the signal is propagated in the certain domain is secured as the time . Of the plurality of inverters,
The inverter that outputs the control signal is connected to the power supply line,
5. The signal processing circuit according to claim 3 , wherein the other inverter is connected to the virtual power supply line that is connected or disconnected by the switching means based on the control signal . A circuit block that processes signals while propagating;
A power supply line for supplying power for activating the circuit block;
A plurality of virtual power supply lines provided in each domain when the circuit block is divided into a plurality of domains in order of early signal propagation timing;
A plurality of switching means connected between each of the virtual power supply line and the power supply line, for connecting or blocking the virtual power supply line to the power supply line;
A control signal generating circuit for outputting a control signal to the plurality of switching means and activating a domain corresponding to the switching means supplied with the control signal;
Have
The control signal generation circuit includes:
In order to sequentially activate the plurality of domains in the order of propagation timing of the signals, output control signals of individual timing to the plurality of switching means ,
When outputting a control signal corresponding to a domain that is activated second or later in the order of propagation timing of the signal, the switching means of the domain that has already been activated according to the order of propagation timing of the signal Continue to output a control signal that keeps each activated domain active,
An indefinite value propagation blocking circuit for forming a minimum unit circuit block to which a signal is input from a final domain of the circuit block;
The indefinite value propagation cutoff circuit is:
When a domain from the first stage to the last stage of the circuit block is in an inactive state where it is not activated, a constant value is output so as not to propagate an indefinite value signal of the circuit block.
Signal processing circuit. A circuit block that processes signals while propagating;
A power supply line for supplying power for activating the circuit block;
A plurality of virtual power supply lines provided in each domain when the circuit block is divided into a plurality of domains in order of early signal propagation timing;
A plurality of switching means connected between each of the virtual power supply line and the power supply line, for connecting or blocking the virtual power supply line to the power supply line;
A control signal generating circuit for outputting a control signal to the plurality of switching means and activating a domain corresponding to the switching means supplied with the control signal;
Have
The control signal generation circuit includes:
In order to sequentially activate the plurality of domains in the order of propagation timing of the signals, output control signals of individual timing to the plurality of switching means,
When outputting a control signal corresponding to a domain that is activated second or later in the order of propagation timing of the signal, the switching means of the domain that has already been activated according to the order of propagation timing of the signal Having a plurality of inverters to which an enable signal as a basis of the control signal for continuously outputting a control signal for maintaining each activated domain in an active state is input to the first stage;
The plurality of inverters are
Propagating while inverting the enable signal, and outputting the control signal for activating the next domain from the inverter corresponding to the operation completion time of each domain,
An indefinite value propagation blocking circuit for forming a minimum unit circuit block to which a signal is input from a final domain of the circuit block;
The indefinite value propagation cutoff circuit is:
Connected to the virtual power line to be connected or disconnected by the switching means with the power supply line,
Activation is controlled by the output signal of the inverter at the final stage of the control signal generation circuit.
Signal processing circuit . The control signal generation circuit includes:
An enable signal that is the basis of the control signal has a plurality of inverters that are input to the first stage,
The plurality of inverters are
The control signal for activating the next domain is output from the inverter corresponding to the operation completion time of each domain while delay-propagating while inverting the enable signal.
The signal processing circuit according to claim 6 . Of the plurality of inverters,
The inverter that outputs the control signal is connected to the power supply line,
The other inverters are connected to the virtual power line that is connected or disconnected by the switching means based on the control signal.
The signal processing circuit according to claim 7 or 8 .

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