KR101835615B1 - SYSTEM ON CHIP, DEVICES HAVING THE SAME, AND METHOD FOR POWER CONTROL OF THE SoC - Google Patents

Abstract

An integrated circuit device is disclosed. The integrated circuit device includes a plurality of power domain blocks, a core, and a power control circuit for independently controlling power supplied to the plurality of power domain blocks in response to the control of the core. The power control circuit includes a plurality of power clusters and a central cluster each corresponding to a plurality of power domain blocks. Each power cluster independently controls power supplied to a corresponding power area block among the plurality of power area blocks in response to control of the core. The central cluster controls the sequence of operations of the plurality of power clusters in response to control of the core.

Description

TECHNICAL FIELD [0001] The present invention relates to a system-on-a-chip (hereinafter referred to as " system ON chip "),

An embodiment according to the concept of the present invention relates to power management technology, and more particularly to a power management technology in which each power domain (< RTI ID = 0.0 > The present invention relates to a SoC capable of independently controlling a power state and an operation state of a power domain, devices including the same, and a power control method of the SoC.

With the development of semiconductor manufacturing technology, the number of devices that can be provided in an integrated circuit is increasing. As the number of devices that can be provided to an integrated circuit increases, components such as a memory, a processor, or a voltage control circuit are integrated into a single integrated circuit.

As described above, a system in which various components constituting one system such as the memory, the processor, or the power control circuit are integrated in one integrated circuit is called a system-on-chip (SoC) It is called. Since a system-on-chip (SoC) is composed of one chip, it occupies less area and consumes less power than conventional systems.

With the advancement of semiconductor manufacturing technology, the number of intellectual properties that can be integrated into a single integrated circuit, e.g., a system on chip (SoC), is increasing. Therefore, a method for controlling the power consumed by an electronic device including a SoC using a battery as a power source is being studied.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated circuit device with reduced area and reduced complexity.

According to another aspect of the present invention, there is provided a method for controlling a power state and an operation state of a plurality of power regions, the power state and the operation state of each of the plurality of power regions being independently controlled according to configuration register values set in each of a plurality of finite state machines And a power control method of the SoC.

An integrated circuit device according to an embodiment of the present invention includes a plurality of power domain blocks, a core, and a power control circuit configured to independently control power supplied to the plurality of power domain blocks in response to control of the core, . Wherein the power control circuit includes a plurality of power clusters and a central cluster each corresponding to the plurality of power domain blocks, wherein each power cluster is responsive to control of the core to provide power corresponding to one of the plurality of power domain blocks And the central cluster is configured to control an operation order of the plurality of power clusters in response to control of the core.

In an embodiment, a specific one of the plurality of power clusters is configured to block power supplied to a particular one of the plurality of power domain blocks corresponding to the particular power cluster in response to control of the core .

In an embodiment, the specific power cluster is configured to resume powering the particular power domain block under control of the core.

In an embodiment, the power control circuit further comprises a core power cluster configured to control power supplied to the core, wherein, in response to the control of the central cluster, the plurality of power clusters and the core power cluster And sequentially block the plurality of power area blocks and the power supplied to the core.

In an embodiment, the central cluster is configured to control a plurality of power area blocks and a power cluster corresponding to a power area block having a high access right among the cores, prior to the other power clusters.

In an embodiment, in response to the control of the central cluster, the plurality of power clusters and the core power cluster are configured to sequentially resume powering the plurality of power domain blocks and the core.

In an embodiment, the order in which the plurality of power area blocks and the power supply of the cores are resumed is a reverse order of the order in which the power supply blocks of the plurality of power area blocks and the cores are interrupted.

As an embodiment, when a first control signal is transferred from the core to a specific one of the plurality of power clusters, and a second control signal is transferred from the central cluster to the specific power cluster, And transmits a response signal for the second control signal to the central cluster, but ignores the second control signal.

In an embodiment, the power control circuit includes a plurality of clock clusters, each corresponding to the plurality of power domain blocks, configured to independently control a clock supplied to the plurality of power domain blocks in response to control of the core, Wherein the central cluster is configured to control an operation order of the plurality of clock clusters in response to control of the core.

As an embodiment, under the control of the power control circuit, the power supplied to the specific power area block is interrupted after the clock supplied to the specific power area block of the plurality of power area blocks is interrupted.

A system on chip (SoC) according to an embodiment of the present invention includes a plurality of power regions each including a plurality of IP properies, A power control unit including a plurality of finite state machines for independently controlling a power state and an operation state of each of the plurality of power regions, a power control unit including at least one And a central sequencer for determining the activation sequence or activation of each of the plurality of finite state machines according to a central configuration register value.

Each of the plurality of finite state machines includes a plurality of states, and the activation order or activation state of each of the plurality of states is determined according to the register values.

Wherein each of the plurality of finite state machines includes a plurality of sub-finite state machines each of which independently controls the power state and the operating state, and a plurality of sub-finite state machines And a main state machine for determining whether each activation sequence is activated or not.

The SoC further includes a CPU for monitoring the operation of each of the IPs included in each of the plurality of power regions and generating the register values for the power region to be controlled among the plurality of power regions according to the monitoring result do.

The final states of each of the plurality of power regions independently controlled by the central sequencer are equal to each other.

Wherein each of the plurality of finite state machines controls the power state defined by a power-up state, a power-down state, a power-up sequence, or a power-down sequence on a power domain basis, .

The SoC further includes a plurality of isolation circuits, each of the isolation circuits being connected between the plurality of power domains, each of the plurality of isolation circuits being operable to receive the register values stored in each of the plurality of finite state machines As shown in FIG.

Wherein each of the plurality of finite state machines includes a first sub-finite state machine for determining the power state and a second sub-finite state machine for determining the operating state, A power supply line for supplying corresponding power from among a plurality of powers output from the power supply circuit, a common power line to which a plurality of IPs contained therein are connected, A plurality of first switches which are switched according to the control of the first sub-finite state machine and a plurality of second switches which are provided for supplying each of the plurality of clock signals output from the clock control unit to each of the plurality of IPs contained therein Wherein the first sub-finite state machine includes a plurality of second switches, and the switching of each of the plurality of first switches is controlled by a first switch register It is determined by the values, whether the plurality of second switches each of the switching is the second sub-switch is determined in accordance with the second register values stored in the finite state machine.

Each of the plurality of finite state machines further comprising a third sub-finite state machine for determining the operating state, wherein each of the plurality of power regions comprises a first sub- 1 data storage device and a second data storage device, wherein the data stored in the first data storage device is stored in the first sub-finite state machine according to a retention control signal generated by a holding register value included in the third sub- And held in a second data storage device.

Each of the plurality of finite state machines further comprising a fourth sub-finite state machine for determining the operating state, wherein each of the plurality of power regions comprises a plurality Wherein the activation of each of the plurality of interfaces is determined according to control register values stored in the fourth sub-finite state machine.

One of the plurality of power regions includes a CPU including a first core and a second core, and a finite state machine capable of controlling any one of the plurality of finite state machines A first sub-finite state machine capable of controlling the power state and reset of the first core; and a second sub-finite state machine capable of controlling whether the power state of the second core is reset or not .

The SoC according to another embodiment of the present invention includes a plurality of power regions each including a plurality of intellectual properties, and a plurality of power regions, each of the plurality of power regions < RTI ID = 0.0 > A power control unit comprising a plurality of finite state machines for independently controlling the power state and the operating state of each of the regions, and at least one central configuration register A plurality of finite state machines capable of performing a reset operation among the plurality of finite state machines, and a controller for performing a reset operation of each of the plurality of finite state machines capable of performing a reset function among the plurality of finite state machines, And a reset sequencer for controlling the reset sequence.

A SoC according to another embodiment of the present invention includes a power control unit including a plurality of power regions each including a plurality of IPs and a plurality of hierarchically implemented finite state machines (FSMs) Wherein activation order or activation of each of the child FSMs among the plurality of FSMs is determined according to first register values set in a parent FSM to which each of the child FSMs belongs and activation of each of the child FSMs belonging to each of the child FSMs Order or activation is determined according to second register values set for each of the child FSMs, and each of the grandchild FSMs is configured to determine a power state and an operation state of each of the plurality of IPs included in each of the plurality of power regions Independently controlled.

The first FSM controls the power state defined by a power-up state, a power-down state, a power-up sequence, or a power-down sequence on a power-domain-by-power-unit basis. And a second FSM for controlling the operation state.

The SoC includes a CPU that monitors the operation of each of the IPs included in each of the plurality of power regions and generates the second register values for the power region to be controlled among the plurality of power regions according to the monitoring result .

An electronic device according to an embodiment of the present invention includes a System On Chip (SoC) including a plurality of power regions each including a plurality of IPs, and a plurality of peripheral devices operating in accordance with the control of each of the plurality of IPs Devices.

The SoC comprising: a power control unit including a plurality of finite state machines that independently control the power state and the operating state of each of the plurality of power regions according to register values set in registers implemented therein; And a central sequencer for determining the activation order or activation state of each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register included therein.

A portable communication apparatus according to an exemplary embodiment of the present invention includes: a SoC including a plurality of power regions each including a plurality of IPs; a SoC that includes any one of a plurality of IPs included in any one of the plurality of power regions And a memory device operative under the control of any one of a plurality of IPs included in the other one of the plurality of power domains,

The SoC comprising: a power control unit including a plurality of finite state machines that independently control the power state and the operating state of each of the plurality of power regions according to register values set in registers implemented therein; And a central sequencer for determining the activation order or activation state of each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register included therein.

A power control method of an SoC according to an embodiment of the present invention is a method for controlling a power of a SoC by generating a finite state machine of a plurality of finite state machines, each of which independently controls each of a plurality of power regions including a plurality of IPs, Wherein the one or more finite state machines control the power state of one of the plurality of power domains according to the configuration register values, And independently controlling the operation state of each of the at least two IPs included in the area.

The power control method of the SoC further includes determining an activation sequence or activation of each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register of the central sequencer.

The power control circuit of an integrated circuit device according to an embodiment of the present invention comprises power clusters and a central cluster. Thus, the area and complexity of the power control circuit of the integrated circuit device is reduced, and the adaptability is improved.

The SoC including a plurality of power regions according to the embodiment of the present invention can independently control the power state and the operation state of each of the plurality of power regions according to the configuration register values set in each of the plurality of finite state machines There is an effect. Therefore, the SoC can be implemented with a low design complexity.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more fully understand the drawings recited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a block diagram showing an integrated circuit device according to an embodiment of the present invention.
2 is a flowchart showing an operation method of the integrated circuit device of FIG.
FIG. 3 is a flowchart illustrating a step of entering a power saving mode or a normal mode in units of a power supply region block in FIG.
FIG. 4 is a block diagram illustrating a power region block of one of the first to n.sup.th power region blocks of FIG. 1. FIG.
5 is a state diagram illustrating a method of operating a power cluster for controlling the power domain block of FIG.
FIG. 6 is a flowchart showing another embodiment of the step of entering the power saving mode or the normal mode in units of the power supply region block in FIG.
FIG. 7 is a flowchart showing a step of controlling the power supply of the power area blocks by controlling the central cluster in FIG.
8 is a state diagram showing an operation method of the central cluster of FIG.
FIG. 9 is a flowchart showing another embodiment of controlling the power supply of the power area blocks by controlling the center cluster in FIG.
10 is a block diagram illustrating an integrated circuit device according to another embodiment of the present invention.
11 is a state diagram showing an operation method of the power control circuit of FIG.
12 shows a block diagram of an SoC according to an embodiment of the present invention.
13 shows a block diagram of the first power domain and the first finite state machine shown in FIG.
Fig. 14 shows a block diagram of the second power region shown in Fig. 12. Fig.
15 shows a block diagram of the data storage device shown in Fig.
Fig. 16 shows a block diagram of the separation circuit shown in Fig. 12. Fig.
17 shows a block diagram of the second finite state machine shown in Fig.
18 shows a generic state diagram of a finite state machine according to an embodiment of the present invention.
FIG. 19 shows a sub-set according to one embodiment of the state diagram shown in FIG.
20 shows a sub-set according to another embodiment of the state diagram shown in Fig.
FIG. 21 shows a sub-set according to another embodiment of the state diagram shown in FIG.
22 shows a sub-set according to another embodiment of the state diagram shown in Fig.
23 shows a sub-set according to another embodiment of the state diagram shown in Fig.
24 shows a state diagram of a finite state machine capable of performing a reset operation.
FIG. 25 is a flowchart for explaining the operation of the SoC shown in FIG. 12; FIG.
FIG. 26 conceptually illustrates one embodiment of a plurality of hierarchically implemented finite state machines.
FIG. 27 conceptually illustrates another embodiment of a plurality of hierarchically implemented finite state machines.
28 shows a block diagram of an electronic device including the SoC shown in Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. . The same elements will be referred to using the same reference numerals. Similar components will be referred to using similar reference numerals.

1 is a block diagram illustrating an integrated circuit device 100 in accordance with an embodiment of the present invention. 1, an integrated circuit device 100, such as an SoC, includes a system bus 110, a power supply circuit 120, first to nth power domain blocks 131 to 13n, and a power control circuit 140 ).

The system bus 110 provides a channel between the components of the integrated circuit device 100. The power supply circuit 120 receives power from the outside. The power supply circuit 120 is configured to convert the received external power into internal power and provide it to the components of the integrated circuit device 100.

The first to nth power region blocks 131 to 13n are connected to the system bus 110, respectively. The first to n < th > power region blocks 131 to 13n are each configured to perform predetermined operations. For example, each of the first to nth power region blocks 131 to 13n may include at least one of various components such as a core, an input / output interface, a memory, a clock generator, an internal interface, a timer, a power- .

Each power domain block is powered independently. For example, the k th power domain block 13k (k is a positive integer less than or equal to n) is powered through a power line different from the other power domain blocks. Thus, the power supplied to the k < th > power range block 13k can be controlled independently of the power supplied to the other power range blocks. That is, each of the first to nth power region blocks 131 to 13n may be independently controlled in one of a sleep mode and a normal mode.

(I is a positive integer less than n) of the first to the n-th power region blocks is a sub power region block of a j-th power region block (j is a positive integer smaller than n) Lt; / RTI > For example, the i < th > power area block may be a slave power area block of the j < th > power area block. When power is applied to the j th power region block, the power supplied to the ith power region block will be controlled independently of the other power region blocks. When the power supply of the j th power region block is interrupted, the power supply of the i th power region block will be shut off together.

Illustratively, at least one of the first to n < th > power region blocks 131 to 13n may be a power region block in which power supply interruption is prohibited. That is, at least one of the first to n-th power range blocks 131 to 13n may be a power range block that does not have a sleep mode.

Illustratively, it is assumed that the first power domain block 131 is a core. The core 131 is configured to control all operations of the integrated circuit device 100. For example, the core 131 may be an ARM processor. For example, at least two power region blocks among the first to nth power region blocks 131 to 13n may be cores, respectively. In the following, reference numeral 131 will be used to refer to the first power domain block or core.

By way of example, it is assumed that the second power range block 132 is an input / output interface. The input / output interface 132 is connected to the system bus 110. The input / output interface 132 may include at least one protocol for communicating with the outside. For example, the input / output interface 132 may be a USB (Universal Serial Bus) protocol, an MMC (multimedia card) protocol, a PCI (Peripheral Component Interconnection) protocol, a PCI- Of the various interface protocols, such as Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, IDE (Integrated Drive Electronics) protocol, Firewire protocol, And is configured to communicate with the outside based on at least one. Hereinafter, reference numeral 132 will be used to reference a second power domain block or an input / output interface.

The power control circuit 140 is configured to control the power supplied to the integrated circuit device 100. For example, the power control circuit 140 is configured to independently control the power supplied to the first to n < th > power region blocks 131 to 13n in response to the control of the core 131. [ For example, the power control circuit 140 is configured to independently control power supplied to the first to nth power region blocks 131 to 13n by adjusting the control signal CS.

The power control circuit 140 includes first to n-th power clusters 141 to 14n and a central cluster 150. [ The first to nth power clusters 141 to 14n correspond to the first to nth power domain blocks 131 to 13n, respectively. The first to nth power clusters 141 to 14n are connected to the first to nth power domain blocks 131 to 13n in response to the control of the core 131 or the central cluster 150, . For example, the first to nth power clusters 141 to 14n control the power supplied to the first to nth power region blocks 131 to 13n independently by controlling the control signal CS .

Illustratively, when the system bus 110 is comprised of one power domain block, at least one of the first through the n-th power clusters 141 through 14n will correspond to the system bus 110. Similarly, a power cluster corresponding to the power supply circuit 120 or the clock generation circuit (not shown) may also be provided.

For example, the kth power cluster (14k, k is a positive integer equal to or less than n) independently controls the power supplied to the kth power region block 13k. The kth power cluster 14k will block and resume the power supplied to the kth power domain block 13k in response to the control of the core 131. [

The central cluster 150 is configured to control the operation order of the first to n-th power clusters 141 to 14n in response to the control of the core 131. [ For example, the central cluster 150 is configured to sequentially activate or deactivate the first to n-th power clusters 141 to 14n in a specific order in response to the control of the core 131. [ For example, the central cluster 150 will simultaneously control at least two power clusters in response to control of the core 131. [

In Figure 1, the number of power domain blocks and the number of power clusters are shown as n each. However, the number of power domain blocks and the number of power clusters may be different.

FIG. 2 is a flowchart showing an operation method of the integrated circuit device 100 of FIG. Referring to Figures 1 and 2, in step S110, the power supply of at least one power domain block is controlled by controlling at least one power clusters. For example, under control of core 131, at least one power cluster will control the power supplied to the corresponding at least one power domain block. For example, under the control of at least one power cluster, the power supplied to at least one power domain block will be blocked or resumed.

In step S120, by controlling the central cluster 150, power supply of the power area blocks is controlled. For example, the central cluster 150 will sequentially control the first through the n-th power clusters 141 through 14n in response to the control of the core 131. [ The power supplied to the first to n < th > power region blocks 131 to 13n will be sequentially controlled by sequentially controlled first to n < th > power clusters 141 to 14n. For example, power supplied to the first to n < th > power region blocks 131 to 13n will be cut off or resumed.

Step S110 may be performed when the integrated circuit device 100 enters a sleep mode or a normal mode on a power supply domain block basis. Step S120 may be performed when the integrated circuit device 100 enters the sleep mode or the normal mode at the system level (for example, the entire integrated circuit device 100).

FIG. 3 is a flowchart illustrating a step S110 of entering a power saving mode or a normal mode in units of a power supply region block in FIG. Referring to FIGS. 1 and 3, in step S210, the core 131 transmits a power saving request to the second power cluster 142. In response to the received power saving request, the second power cluster 142 controls the second power region block 132 to power save mode (S215). For example, the second power cluster 142 blocks power supplied to the second power range block 132. [ Thereafter, the second power cluster 142 transmits a power save response to the core 131 (step S220).

Steps S210 to S220 will constitute an operation for controlling a specific power region block (for example, the second power region block 132) among the first to n < th > power region blocks 131 to 13n to the power save mode .

In step S225, the core 131 transmits a power save request to the third power cluster 143. [ In response to the received power saving request, the third power cluster 143 controls the third power region block 133 to power save mode (step S230). Thereafter, the third power cluster 143 transmits a power saving response to the core 131 (step S235). Steps S225 to S235 constitute an operation of controlling the power area block (for example, the third power area block 133) of the other one of the first to nth power area blocks 131 to 13n to the power saving mode something to do.

Steps S210 to S220 and steps S225 to S235 will be independently performed under the control of the core 131. [ For example, whether steps S210 through S220 have been performed, whether they are performed, and whether they will be performed will not affect the execution of steps S225 through S235. Likewise, whether steps S225 through S235 have been performed, whether they are performed, and whether they will be performed will not affect the execution of steps S210 through S220.

In step S240, the core 131 transmits a normal request to the second power cluster 142. [ In response to the received normal request, the second power cluster 142 controls the second power region block 132 to be in the normal mode (step S245). For example, under the control of the second power cluster 142, the power supply of the second power domain block 132 will be resumed. Thereafter, the second power cluster 142 transmits a normal response to the core 131 (step S250).

In step S255, the core 131 delivers a normal request to the third power cluster 143. [ In response to the received normal request, the third power cluster 143 controls the third power region block 133 in the normal mode (step S260). Thereafter, the third power cluster 143 transmits a normal response to the core 131 (step S265).

Steps S240 through S250 constitute an operation of controlling a specific power region block (for example, the second power region block 132) among the first through nth power region blocks 131 through 13n in the normal mode. In operation S255, the operation for controlling the power region block (for example, the third power region block 133) of the first to nth power region blocks 131 to 13n in the normal mode .

Steps S240 through S250 and steps S255 through S265 are performed independently. For example, whether steps S240 through S250 have been performed, performed, and performed will not affect whether steps S255 through S265 are performed. Likewise, whether steps S255 through S265 have been performed, performed, and performed will not affect whether steps S240 through S250 are performed.

In Fig. 3, an operation method in which the second and third power region blocks 132 and 133 are controlled to the power saving mode and the normal mode has been described. The remaining power region blocks other than the second and third power region blocks 132 and 133 are also controlled by the control of the core 131 and corresponding power clusters as well as the second and third power region blocks 132 and 133. [ The power saving mode and the normal mode can be controlled.

FIG. 4 is a block diagram illustrating a power region block 13k of one of the first through n.sup.th power region blocks 131 through 13n of FIG. 1. Referring to FIG. 4, the power region block 13k includes first to m-th switches SW1 to SWm, an inner block IB, a first isolation circuit IC1, and a second isolation circuit IC2 do.

The inner block IB is connected to the first to m-th power lines PL1 to PLm. The first to m-th power lines PL1 to PLm are connected to the system bus 110 through the first to m-th switches SW1 to SWm, respectively. The first to m-th switches SW1 to SWm are controlled in response to a control signal received via the system bus 110. [ Illustratively, the first to m-th switches SW1 to SWm will be controlled in response to a control signal received from the kth power cluster 14k corresponding to the kth power domain block 13k.

The inner block IB is supplied with power through the first to m-th power lines PL1 to PLm. That is, when the first to m-th switches SW1 to SWm are controlled under the control of the k-th power cluster 14k, the power supplied to the k-th power region block 13k can be controlled.

The internal block IB is connected to the system bus 110 via the signal line SL. The internal block IB communicates with the system bus 110 via the signal line SL. Illustratively, the signal line SL may be replaced by a plurality of signal lines.

The inner block IB communicates with the other power domain block via the first isolation circuit IC1. Illustratively, the inner block IB is shown as communicating with the k-1 power domain block 13 (k-1) via a first isolation circuit IC1.

The first isolation circuit IC1 is connected to the system bus 110 via the first control line CL1. The first isolation circuit IC1 is activated and deactivated in response to a control signal received via the first control line CL1. Illustratively, the first isolation circuit IC1 will operate in response to a control signal received via the first control line CL1 from the kth power cluster 14k.

The activated first isolation circuit IC1 isolates the internal block IB from the k-1 power block 13 (k-1) when the power of the k-th power block 13k is interrupted.

Illustratively, when the power supplied to the k < th > power domain block 13k is interrupted, the voltage level of the internal nodes of the k < th > power domain block 13k will be adjusted to the ground level. (K-1) from the k-th power region block 13 (k-1), when the node controlled by the ground level is a node connected to the external k-1 power region block 13 A current will flow to the block 13k. That is, a leakage current will be generated from the k-1 power region block 13 (k-1) to the k power region block 13k. The first isolation circuit IC1 is configured to isolate the kth power region block 13k from the k-1 power region block 13 (k-1), thereby preventing leakage current.

The inner block IB communicates with an outer power domain block via a second isolation circuit IC2. Illustratively, the inner block IB is shown communicating with the (k + 1) th power block 13 (k + 1) via the second isolation circuit IC2. The second isolation circuit IC2 is activated and deactivated in response to a control signal received via the second control line CL2 from the kth power cluster 14k.

Similarly to the activated first isolation circuit IC1, when the power of the kth power region block 13k is cut off, the second isolation circuit IC2 outputs the kth power region block 13k to the (k + 1) (13 (k + 1)).

In Fig. 4, the k-th power region block 13k is shown to include the first to m-th switches SW1 to SWm. However, the k < th > power region block 13k may be configured to be powered via one power line and one switch.

In Fig. 4, the k < th > power region block 13k is shown as communicating with two power region blocks. However, the k < th > power area block 13k may communicate with at least one power area block and may be configured not to communicate with other power area blocks. Illustratively, the k < th > power domain block 13k may comprise isolated circuits corresponding to the power domain blocks that communicate, respectively.

Illustratively, the k th power domain block 13k may comprise one isolated circuit, and an isolated circuit may be disposed between the inner block IB and the signal lines connected to the outside. That is, the signal lines in which the internal block IB communicates with the outside can be commonly connected to one isolation circuit.

5 is a state diagram illustrating a method of operating a power cluster 14k that controls the power domain block 13k of FIG. Referring to Figs. 4 and 5, under the control of the power cluster 14k, the power area block 13k operates in a power saving mode S11 and a normal mode S12.

When the power area block 13k is controlled from the power saving mode S11 to the normal mode S12, the power cluster 14k sequentially outputs the first to m-th switches SW1 to SWm of the power area block 13k As shown in FIG. That is, power is supplied to the k < th > power region block 13k. Thereafter, the force cluster 14k deactivates the first and second isolation circuits IC1 and IC2. That is, the k th power region block 13 k is controlled to be communicable with the outside. At this time, the kth power region block 13k enters the normal mode S12.

When the power area block 13k is controlled from the normal mode S12 to the power saving mode S11, the power cluster 14k activates the first and second isolation circuits IC1 and IC2. That is, the k th power region block 13 k is isolated from the outside. Thereafter, the power cluster 14k sequentially turns off the first to m-th switches of the power domain block 13k. That is, the power supplied to the power area block 13k is cut off. At this time, the power area block 13k enters the power saving mode S11.

Depending on the number of switches SW1 to SWm and the number of isolated circuits IC1 and IC2, the operation of the power cluster 14k can be changed. For example, when the number of switches SW1 to SWm is increased or decreased, the number of operations in which the power cluster 14k controls the switches SW1 to SWm will be increased or decreased. If the number of isolated circuits IC1 and IC2 is increased or decreased, the number of operations in which the power clusters 14k control the isolated circuits IC1 and IC2 will be increased or decreased.

Illustratively, the power cluster 14k may be a state machine that performs state control operations as shown in FIG. Illustratively, the power cluster 14k may be a processor that performs operations as shown in FIG.

In Figs. 4 and 5, the k < th > power region block 13k and the k < th > power cluster 14k have been described. The remaining power area blocks and the remaining power clusters will also be configured as described with reference to Figs.

FIG. 6 is a flowchart showing another embodiment of the step S110 for entering the power saving mode or the normal mode on a power block area basis in FIG. In Fig. 6, a detailed description of operation steps similar to the operation steps described with reference to Fig. 3 is omitted. Referring to FIGS. 1 and 6, in step S310, the core 131 transmits a power save request to the second power cluster 142. FIG. In step S315, the core 131 transmits a power saving request to the third power cluster 143. [

In step S320, the second power cluster 142 controls the second power region block 132 to the power saving mode. In step S325, the third power cluster 143 controls the third power region block 133 to the power saving mode.

In step S330, the second power cluster 142 sends a power save response to the core 131. [ In step S335, the third power cluster 143 transmits a power saving response to the core 131. [

That is, core 131 may send a power save request to a particular power cluster (e. G., Second power cluster 142) (E.g., the third power cluster 143).

In step S340, the core 131 sends a normal request to the second power cluster 142. In step S345, the core 131 sends a normal request to the third power cluster 143.

In step S350, the second power cluster 142 controls the second power region block 132 in the normal mode. In step S355, the third power cluster 143 controls the third power region block 133 in the normal mode.

In step S360, the second power cluster 142 transmits a normal response to the core 131. [ In step S365, the third power cluster 143 transmits a normal response to the core 131. [

That is, core 131 may send a normal request to a particular power cluster (e.g., second power cluster 142) (E.g., the third power cluster 143).

As described above, the core 131 is capable of controlling the first to n-th power clusters 141 to 14n in parallel.

FIG. 7 is a flowchart showing a step S120 of controlling the power supply of the power area blocks 141 to 14n by controlling the center cluster 150 in FIG. Referring to FIGS. 1 and 7, in step S410, the core 131 transmits a power saving request to the central cluster 150. FIG.

In step S415, the central cluster 150 sends a power save request to the first power cluster 141. [ In step S420, the first power cluster 141 controls the first power range block 131 to the power saving mode. Thereafter, in step S425, the first power cluster 141 sends a power save response to the central cluster 150. [ Steps S415 through S425 constitute an operation for the central cluster 150 to control the first power region block 131 in the power saving mode through the first power cluster 141. [

In step S430, the central cluster 150 sends a power save request to the second power cluster 142. [ In step S435, the second power cluster 142 controls the second power region block 132 to the power saving mode. Thereafter, in step S440, the second power cluster transmits a power save response to the central cluster 150. [

For the sake of brevity, the central cluster 150 has been described as transmitting power save requests to the first and second power clusters 141, 142. However, in response to the power saving request from the core 131, the central cluster 150 will sequentially transmit the power saving request to the first to nth power clusters 141 to 14n.

As illustrated with reference to FIG. 6, the central cluster 150 may send a power save request to a different power cluster before sending a power save request to a particular power cluster and then receiving a power save response from the particular power cluster. have.

Illustratively, after receiving a power save request from core 131, central cluster 150 will operate independently of core 131. The central cluster 150 and the power clusters 141 to 14n will control the power domain blocks 131 to 13n including the core 131 in the power saving mode. At this time, the central cluster 150 and the power clusters 141 to 14n will maintain the normal mode. The central cluster 150 will determine if a normal event is detected.

In step S445, a normal event is detected. For example, the central cluster 150 will detect a normal event. For example, a normal event may include access to pins corresponding to the normal mode of the input / output pins (not shown) of the integrated circuit device 100. That is, when access to the pin corresponding to the normal mode occurs, the central cluster 150 will determine that a normal event has been detected. For example, when a control signal is received from the outside, the central cluster 150 will determine that a normal event has been detected.

For example, the normal event will be detected according to the elapsed time after the first to nth power region blocks 131 to 13n enter the power saving mode. For example, when a specific time elapses after the first to nth power region blocks 131 to 13n enter the power save mode, the central cluster 150 will determine that a normal event has been detected. For example, the central cluster 150 may have a counter (not shown) for measuring time.

In step S450, the central cluster 150 sends a normal request to the first power cluster 141. In step S455, the first power cluster 141 controls the first power region block 131 to be in the normal mode. Thereafter, in step S460, the first power cluster 141 transmits a normal response to the central cluster 150. [

In step S465, the central cluster 150 sends a normal request to the second power cluster 142. In step S470, the second power cluster 142 controls the second power region block 132 in the normal mode. Thereafter, in step S475, the second power cluster 142 transmits a normal response to the central cluster 150. [

For the sake of brevity, the central cluster 150 has been described as sending a normal request to the first and second power clusters 141, 142 in response to detection of a normal event. However, the central cluster 150 will send a normal request to the first through n < th > power clusters 141 through 14n in response to detection of a normal event.

In step S480, the central cluster 150 transmits a normal response to the core 131. [

As described above, when the core 131 transmits a power save request to the central cluster 150, the first to nth power region blocks 131 to 13n including the core 131 are divided by the central cluster 150, This is controlled by the power saving mode. That is, the central cluster 150 allows the integrated circuit device 100 to be controlled in the power saving mode.

Also, when a normal event is detected by the central cluster 150, the first to n-th power region blocks 131 to 13n including the core 131 are controlled in the normal mode by the central cluster 150 . That is, the central cluster 150 can control the integrated circuit device 100 in the normal mode.

8 is a state diagram illustrating a method of operating the central cluster 150 of FIG. Referring to FIGS. 1, 7, and 8, the central cluster 150 controls the integrated circuit device 100 to the power saving mode S21 and the normal mode S22. Illustratively, the central cluster 150 controls the integrated circuit device 100 to power save mode S21 in response to a power save request received from the core 131. [ When a normal event is detected, the central cluster 150 controls the integrated circuit device 100 to the normal mode S22.

When the integrated circuit device 100 is controlled to the power save mode S21, the central cluster 150 sequentially selects the first to n-th power region blocks 131 to 13n, And sequentially controls the power clusters 141 to 14n.

Illustratively, the central cluster 150 will sequentially control the first through the n-th power clusters 141 through 14n in a specific order. For example, the core 131 is a component that generates an access request to the system bus 110 and other power domain blocks 132 through 13n. When an access request is generated from the core 131, the corresponding component is controlled to the normal mode even in the power saving mode. Accordingly, when the integrated circuit device 100 is controlled in the power saving mode, the central cluster 150 controls the first power cluster 141 corresponding to the core 131 before the other power clusters 142 to 14n will be.

For example, a bus master, such as input / output interface 132 or memory controller (not shown), is a component that generates an access request to system bus 110. When an access request is issued from the bus master, the system bus 110 is controlled to the normal mode even in the power saving mode. When the integrated circuit device 100 is controlled in the power saving mode, the central cluster 150 connects the second power cluster 142 corresponding to the bus master (for example, the input / output interface 132) Lt; RTI ID = 0.0 > 141 < / RTI >

For example, the central cluster 150 may control a power cluster corresponding to a power region block having a high access right among the first to nth power region blocks before another power cluster.

When the integrated circuit device 100 is controlled from the power saving mode S21 to the normal mode S22, the central cluster 150 sequentially controls the first to nth power clusters 141 to 14n in a specific order something to do. Illustratively, the operation order of the first to n-th power clusters 141 to 14n when the integrated circuit device 100 is controlled in the normal mode S22 is that the integrated circuit device 100 is in the power saving mode S21, Lt; th > power clusters 141 to 14n when the first to n < th >

As described with reference to Fig. 8, the central cluster 150 and the first to nth power clusters 141 to 14n are configured to operate even when the core 131 is in an inactive state. Accordingly, the central cluster 150 and the first to n-th power clusters 141 to 14n will be composed of hardware independent of the core 131. [ For example, the central cluster 150 and the first to nth power clusters 141 to 14n may be implemented as a state machine or a processor.

FIG. 9 is a flowchart showing another embodiment of step S120 of controlling the power supply of power area blocks by controlling the center cluster in FIG. Referring to FIGS. 1 and 9, in step S510, the core 131 transmits a maintenance request to the second power cluster 142. FIG.

In step S515, the core 131 transmits a power saving request to the central cluster 150. [ In step S520, the central cluster 150 transmits a power save request to the first power cluster 141. [ In step S525, the first power cluster 141 controls the first power domain block 131 in the power saving mode in response to the power saving request received from the central cluster 150. [ In step S530, the first power cluster 141 sends a power save response to the central cluster 150. [ In steps S520 to S530, the first power area block 131 is controlled by the central cluster 150 and the first power cluster 141 to the power saving mode.

In step S535, the central cluster 150 sends a power save request to the second power cluster 142. [ The second power cluster 142 operates in response to a maintenance request received from the core 131 in step S510 and a power save request received from the central cluster 150 in step S535. More specifically, the second power cluster 142, in response to a maintenance request received from the core 131, ignores the power save request received from the central cluster 150. For example, the second power cluster 150 does not control the second power domain block 132 in the power saving mode, and transmits a power save response to the central cluster 150 (step S540).

That is, when the integrated circuit device 100 is controlled in the power saving mode, at least one of the first to n < th > power region blocks 131 to 13n may maintain the normal mode in response to the control of the core 131. [

In step S545, the central cluster 150 detects a normal event. In step S550, the central cluster 150 sends a normal request to the first power cluster 141. In step S555, the first power cluster 141 controls the first power domain block 141 in the normal mode in response to the normal request received from the central cluster 150. [ In step S560, the first power cluster 141 transmits a normal response to the central cluster 150. [ In steps S550 to S560, the first power area block 131 is controlled in the normal mode by the center cluster 150 and the first power cluster 141. [

In step S565, the central cluster 150 sends a normal request to the second power cluster 142. However, the second power range block 132 maintains the normal mode according to the maintenance request in step S510. Thus, the second power cluster 142 ignores the normal request received from the central cluster 150. For example, the second power cluster 142 does not perform an operation according to the normal request received from the central cluster 150, and transmits a normal response to the central cluster 150.

As described above, according to the present invention, the power region blocks 131 to 13n can be independently controlled by the power clusters 141 to 14n. Since each power cluster has only the control function of the corresponding power domain block, the complexity of the power control circuit 140 can be reduced and the area can be reduced.

When the integrated circuit device 100 is controlled to the power saving mode or the normal mode, the operation order of the first to n-th power clusters 141 to 14n is controlled by the central cluster 150. [ Therefore, when the power region block is added to the integrated circuit device 100, the entire configuration of the power control circuit 140 need not be updated. When a power region block is added to the integrated circuit device 100, when a power cluster corresponding to the added power region block is added to the power control circuit 140, the added power region block is controlled to the power saving mode and the normal mode .

In addition, when the central cluster 150 is updated to include the operating sequence of the added power clusters, the integrated circuit device 100 including the added power domain block can be controlled to the power saving mode and the normal mode. That is, the adaptability of the power control circuit 140 of the integrated circuit device 100 is improved, and the time and cost associated with redesigning the power control circuit 140 can be reduced.

10 is a block diagram illustrating an integrated circuit device 200 according to another embodiment of the present invention. 10, the integrated circuit device 200 includes a system bus 210, a power supply circuit 220, first to nth power region blocks 231 to 23n, a power control circuit 240, Generating circuit 270 as shown in FIG.

The system bus 210, the power supply circuit 220 and the first to nth power region blocks 231 to 23n are connected to the system bus 110, the power supply circuit 120, n power area blocks 131 to 13n. Therefore, detailed description is omitted.

The clock generating circuit 270 is configured to generate a clock. The clock generated by the clock generating circuit 270 is transmitted to the respective components of the integrated circuit device 200 via the system bus 210. Illustratively, when the clock generating circuit 270 is composed of one power domain block, at least one of the first through the n-th power clusters 241 through 24n will correspond to the clock generating circuit 270.

The power control circuit 240 includes first through n-th power clusters 241 through 24n, first through pth clock clusters, and a center cluster 250.

The first to nth power clusters 241 to 24n correspond to the first to nth power region blocks 231 to 23n, respectively. As described with reference to Figs. 1 to 9, the first to the n-th power clusters 241 to 24n are configured to control power supplied to the first to nth power region blocks 231 to 23n .

The first through pth clock clusters 261 through 26p may correspond to the first through pth clock domain blocks. Illustratively, when the power area blocks and the clock area blocks in the integrated circuit device 200 match, the first to the n-th power region blocks 231 to 23n will be the first to the n-th clock region blocks. At this time, the first through pth clock clusters 261 through 26p correspond to the first through nth clock domain blocks 231 through 23n, respectively. Illustratively, in integrated circuit device 200, it is assumed that power domain blocks and clock domain blocks are matched. It is also assumed that the value of the variable p coincides with the value of the variable n.

Each clock cluster is configured to independently control the clock supplied to the corresponding clock domain block. For example, each clock cluster may be configured to control clock supply in response to control of the central cluster 250 or core 231.

The central cluster 250 is configured to control the operation order of the first to the n-th power clusters 241 to 24n and the first to p-th clock clusters 261 to 26p. Illustratively, as described with reference to Figs. 1-9, the central cluster 250 controls the order of operation of the first through pth clock clusters 261 through 26p in a particular order, N power clusters 241 to 24n in accordance with the operation of the first to n-th power clusters 241 to 24n.

11 is a state diagram showing an operation method of the power control circuit 240 of FIG. 10 and 11, the power control circuit 240 is configured to control the integrated circuit device 200 in a normal mode S31, a first power saving mode S32, and a second power saving mode S33 .

Illustratively, the power supply of the k < th > power region block 23k is controlled by the k < th > power cluster 24k and the clock supply of the k & . The kth power cluster 24k and the kth clock cluster 26k control the k th power region block 23k in one of the normal mode S31, the first power save mode S32, and the second power save mode S33 something to do.

When the kth power region block 23k is in the normal mode S31, the kth clock cluster 26k controls the k power region block 23k in the first power saving mode in response to the control of the core 231 . For example, in response to the control of the core 231, the kth clock cluster 26k will block the clock supplied to the kth power region block 23k. When the clock supply is interrupted, the kth power region block 23k enters the first power saving mode S32. For example, the first power saving mode S32 may be an operation stop mode for stopping the operation in accordance with the clock. That is, in the first power saving mode S32, static power consumption occurs in the kth power region block 23k, but dynamic power consumption is prevented.

The kth clock cluster 24k or the kth power cluster 26k responds to the control of the core 231 by the kth power region block 23k in response to the control of the core 231, 23k to the normal mode S31 or the second power saving mode S33.

Illustratively, under the control of the kth clock cluster 26k, the clock supply of the kth power region block 23k will be resumed. When the clock supply is resumed, the k th power region block 23k will enter normal mode S31. Illustratively, the operation of supplying and blocking the clock to the k power region block 23k, except that the power supply and power cutoff are replaced by clock supply and clock cutoff, is the same as that described with reference to Figures 3-6 Will be performed similarly.

Illustratively, under the control of the k-th power cluster 24k, the power supply of the k-th power region block 23k will be cut off. When the power supply is interrupted, the kth power region block 23k will enter the second power saving mode S33. In the second power save mode S33, the dynamic power consumption and the static power consumption of the kth power region block 23k will be prevented.

When the kth power area block 23k is in the second power saving mode S33, the kth power cluster 24k switches the kth power region block 23k under the control of the core 231 to the first power saving mode S32, . For example, under the control of the kth power cluster 24k, the power supply of the kth power region block 23k will be resumed. When the power supply is resumed, the kth power region block 23k will enter the first power saving mode S32.

Illustratively, the operation of supplying and blocking power to the kth power region block 23k will be performed as described with reference to Figures 3-6.

Illustratively, it is assumed that the integrated circuit device 200 is controlled by the central cluster 250. The central cluster 250 will control the integrated circuit device 200 to one of the normal mode S31, the first power save mode S32 and the second power save mode S33.

When the integrated circuit device 200 is in the normal mode S31, the central cluster 250 controls the integrated circuit device 200 to the first power saving mode S32 in response to the control of the core 231. [ For example, the central cluster 250 may control the first through pth clock clusters 261 through 26p in a specific order. In response to the control of the central cluster 250, the first to pth clock clusters 261 to 26p will block the clocks supplied to the first to the nth power region blocks 231 to 23n in a specific order .

When the integrated circuit device 200 is in the first power saving mode, the central cluster 250 controls the integrated circuit device 200 to the normal mode S31 or the second power saving mode S33.

For example, when a normal event is detected, the central cluster 250 will control the integrated circuit device 200 to the normal mode S31. For example, the central cluster 250 may control the first through pth clock clusters 261 through 26p in a specific order. In response to the control of the central cluster 250, the first to pth clock clusters 261 to 26p will resume the clock supply of the first to nth power region blocks 231 to 23n in a specific order . Illustratively, the operation of supplying and blocking the clocks to the first to n < th > power region blocks 231 to 23n, except that the power supply and power cutoff are replaced by clock supply and clock cutoff, Will be performed as described with reference to FIG.

Illustratively, when a power save event is detected, the central cluster 250 will control the integrated circuit device 200 to the second power save mode S33. For example, when a specific time elapses after the integrated circuit device 200 enters the first power saving mode S32, the central cluster 250 switches the integrated circuit device 200 to the second power saving mode S33 Control. For example, in response to an external control signal, the central cluster 250 may control the integrated circuit device 200 to the second power save mode S33.

The central cluster 250 will control the first through n-th power clusters 241 through 24n in a specific order. The first to nth power clusters 241 to 24n will block the power supplied to the first to nth power region blocks 231 to 23n according to a specific order.

When the integrated circuit device 200 is in the second power saving mode S33, the center cluster 250 will control the integrated circuit device 200 to the first power saving mode S32. For example, when a control signal is received from the outside, or when a certain time has elapsed after the integrated circuit device 200 enters the second power saving mode (S33), the central cluster 250 is connected to the integrated circuit device 200 ) To the first power saving mode (S32).

For example, the central cluster 250 may control the first through the n-th power clusters 241 through 24n in a specific order. The first to nth power clusters 241 to 24n will resume powering the first to nth power domain blocks 231 to 23n in a specific order.

The operation of interrupting and resuming the power supply to the first to nth power region blocks 231 to 23n will be performed as described with reference to Figs.

Illustratively, when the integrated circuit device 200 is in the normal mode S31, the central cluster 250 controls the integrated circuit device 200 to the second power saving mode S33 in response to the control of the core 231 . For example, when a power saving request is received from the core 231, the central cluster 250 controls the first to pth clock clusters 261 to 26p in a specific order, And control the power clusters 241 to 24n in a specific order.

Illustratively, when a normal event is detected, the central cluster 250 may control the integrated circuit device 200 from the second power save mode S33 to the normal mode S31. For example, the central cluster 250 may control the first through the n-th power clusters 241 through 24n in a specific order. Thereafter, the central cluster 250 will control the first through pth clock clusters 261 through 26p in a specific order.

That is, when the integrated circuit device 200 is controlled to the power saving mode, the first power saving mode S32 may be omitted. When the integrated circuit device 200 is controlled in the normal mode, the first power saving mode S32 may be omitted. Further, when the integrated circuit device 200 is controlled to the power saving mode and the normal mode, the first power saving mode S32 may be omitted.

In the above-described embodiment, it has been assumed that the power area blocks and the clock area blocks of the integrated circuit device 200 are matched. However, the power domain blocks and clock domain blocks of the integrated circuit device 200 may be different.

12 shows a block diagram of an SoC according to an embodiment of the present invention.

Referring to FIG. 12, a system on chip (SoC) 1010 may be included in an electronic device, a portable communication device, or an information technology device. The SoC 1010 includes a plurality of power domains 1011-1 to 1011-n (where n is a natural number), a power supply circuit 1013, and a power management unit (PMU) 1017).

Each of the power regions 1011-1 to 1011-n, the power supply circuit 1013, and the PMU 1017 can communicate with each other via a bus 1015. [

The SoC 1010 further includes a plurality of isolation circuits 1012-1, 1012-2, ..., each connected between a plurality of power domains 1011-1 through 1011-n .

According to the embodiment, each of the plurality of separation circuits 1012-1, 1012-2, ... may be connected or disconnected according to the register values stored in each of the plurality of finite state machines 1019-1 to 1019-n . According to another embodiment, each of the plurality of separation circuits 1012-1, 1012-2, ... includes a plurality of finite state machines 1019-1 to 1019-n, May be connected or separated according to the values (see FIG. 17).

Each of the plurality of separation circuits 1012-1, 1012-2, ... may be implemented inside or outside each of the plurality of power regions 1011-1 to 1011-n. For example, each of the plurality of isolation circuits 1012-1, 1012-2, ... may have a leakage current path that may occur between a plurality of power regions 1011-1 to 1011-n Can be blocked.

Each of the plurality of power domains 1011-1 through 1011-n includes a plurality of IPs (intellectual properties (IP)). Here, IP refers to an integrated circuit 1010, e.g., a circuit, logic, or a combination thereof that may be integrated into an SoC. Also, a code may be stored in the circuit or the logic.

For example, the IP may include a central processing unit (CPU), a plurality of cores included in the CPU, a multi-format codec (MFC), a video module (e.g., a camera interface, A video processor, a mixer, etc.), a 3D graphics core, an audio system, a driver, a display driver, a volatile memory a volatile memory device, a non-volatile memory, a memory controller, or a cache memory.

For example, each of the plurality of power domains 1011-1 through 1011-n may be a set of a plurality of applications or a set of a plurality of modules capable of performing a similar function . The application or module may be implemented in hardware or hardware in which the software is embedded.

The power supply circuit 1013 receives external power (EXPWR) supplied from external, for example, a battery, and generates a plurality of powers PWR1 to PWRn.

According to the embodiment, each of the plurality of powers PWR1 to PWRn may be supplied to each of the plurality of power regions 1011-1 to 1011-n. According to another embodiment, each of the plurality of powers PWR1 to PWRn may be supplied to each of the plurality of IPs included in each of the plurality of power regions 1011-1 to 1011-n. Thus, at least one power can be supplied to one power region.

PMU 1017 includes a number of finite state machines (FSM) 1019-1 through 1019-n. Each of the plurality of finite state machines 1019-1 to 1019-n is controlled according to the control of the CPU implemented in the CPU, for example, the first power range 1011-1, and in particular according to the configuration register values output from the CPU It is possible to independently control each of the plurality of power regions 1011-1 to 1011-n.

Each of the plurality of finite state machines 1019-1 to 1019-n includes a plurality of power regions 1011-1 to 1011-n in accordance with the configuration register values set in a configuration register included therein, the power state and / or the operation state of each of the first and second power sources may be independently controlled. The configuration register is an example of a storage capable of storing configuration register values containing one or more bits.

For example, the configuration register values may include a plurality of bits, and some bits of the plurality of bits may be used to identify each of a plurality of finite state machines 1019-1 to 1019-n May be used as identification bits.

Here, the power state includes a power-up state (or a power-on state), a power-down state (or a power-off state) , A power-up sequence (or a power-on sequence), or a power-down sequence (or a power-off sequence).

The power-up state means that the power (or voltage) of the power region to be controlled (e.g., the target power region) is fully powered up. The power-down state means a state in which the power of the target power region is turned off.

The power-up sequence means that the target power region transitions directly from the power-down state or through at least one state to the power-up state. The power-down sequence means that the target power region transits directly or through at least one state from the power-up state to the power-down state.

For example, when the first power region 1011-1 is in the power-up state under the control of the first finite state machine 1019-1, the second power region 1011-2 is connected to the second finite state machine 1019 -2), and the third power region 1011-3 can perform the power-up sequence under the control of the third finite state machine 1019-3.

The operation state includes whether or not a clock signal is supplied to each IP, whether data retention is stored in a data storage device implemented in each IP, Whether or not to use a pad implemented in each IP, whether or not an interface implemented in each IP is activated, and the like.

According to an embodiment, the power state and the operation state can be controlled by a power region unit or an IP unit. However, in the present specification, the power state is controlled for each power region for convenience of description, Is controlled.

However, when a CPU included in one power region includes a plurality of cores, the power state (e.g., power supply state) and operation state (e.g., reset state) of each of the plurality of cores ) May be independently controlled on a per-core basis.

For example, the CPU may determine the operation of each of a plurality of IPs included in each of the plurality of power domains 1011-1 to 1011-n (e.g., how much each IP is consuming power, And whether or not each IP is in an idle state) and monitors the power area to be controlled among the plurality of power areas 1011-1 to 1011-n according to the monitoring result, that is, Generate the configuration register values indicating the target power region, and output the generated configuration register values to the PMU 1017 via the bus 1015. [

The finite state machine capable of controlling the power state of the target power region can analyze the environment setting register values output from the CPU and control the power state of the target power region on a power domain basis according to the analysis result .

Also, the finite state machine may independently control the operation state of each of the plurality of IPs included in the target power region according to the configuration register values.

According to an embodiment, the PMU 1017 may be coupled to a plurality of finite state machines 1019-1 through 1019-n according to at least one central configuration register value set in the central configuration register 1021-1 included therein. And may further include a central sequencer 1021 that determines an activation sequence or activation.

For example, in accordance with at least one central configuration register value, the PMU 1017 controls the SoC-level (SoC-level) to control the power state of each power area 1011-1 to 1011- ) Power control operations or domain-level power control operations that independently control the power states of the respective power domains 1011-1 to 1011-n.

When referred to herein as an activation without a specific embodiment, the activation may be a specific operation (e.g., powering, clocking, data retention, isolation, or reset ) Means that a particular object, such as a state or finite state machine, performs a particular action or work.

The central sequencer 1021 may be implemented as a finite state machine that includes a number of states. For example, the state may be implemented as a circuit, logic, code, or a combination thereof.

Wherein the activation order or activation state of each of the plurality of states is determined according to the value of the at least one central configuration register, and the plurality of finite state machines (e.g., 1019-1 to 1019-n) can be determined.

The central sequencer 1021 determines only the activation order or activation state of each of the plurality of finite state machines 1019-1 to 1019-n and determines whether or not each of the finite state machines 1019-1 to 1019- Whether or not the operation is performed or the operation result is not determined. Therefore, even an activated finite state machine may not perform any action or work.

The central sequencer 1021 may communicate with each of the plurality of finite state machines 1019-1 through 1019-n via handshaking. The central sequencer 1021 is responsible for SoC-level power control, so that a number of finite state machines 1019-1 through 1019-n (e. ≪ RTI ID = 0.0 > The final states of the plurality of power areas 1011-1 to 1011-n independently controlled by each of the plurality of power areas 1011-1 to 1011-n are equal to each other.

If the final state means the final state of the finite state machine, the sub finite state machine corresponding to the final state may or may not perform a particular action or a particular task.

Illustratively, the final state may be a normal operation state, a sleep state, or a deep-stop state. In the normal operation state, all of the plurality of power regions 1011-1 to 1011-n are brought into a power-up state. In the sleep state, all of the power regions 1011-1 to 1011-n except for the PMU 1017 are in a power-down state. In the deep-stop state, the supply of the clock signal to each of the plurality of IPs implemented in each of the plurality of power areas 1011-1 to 1011-n is interrupted, and the power supplied to the CPU is also put into a power-down state .

In accordance with another embodiment, the PMU 1017 may include a number of finite state machines (e. G., Microprocessors) in accordance with a reset event (e.g., a hardware reset, a software reset, a warm reset, or a wakeup reset) And a reset sequencer 1023 capable of controlling the reset operation of each of a plurality of finite state machines capable of performing a reset function among the plurality of finite state machines 1019-1 to 1019-n and 21, have.

The reset sequencer 1023 may be implemented as a finite state machine including a plurality of states. As shown in Fig. 1, the reset sequencer 1023 can control the reset operation of each of the finite state machines 1019-1, 1019-2, and 1021. Fig.

As shown in FIG. 13, the first finite state machine 1019-1 includes a plurality of sub-finite state machines 1119-1 and 1119-2, The machine 1019-2 determines whether or not to activate the plurality of sub-finite state machines 1210-1 to 1210-s and the plurality of sub-finite state machines 1210-1 to 1210- And a main finite state machine 1200 that can determine the current state of the machine.

Each finite state machine described herein includes a configuration register for storing configuration register values output from the CPU 1111 despite its name.

13 shows a block diagram of the first power domain and the first finite state machine shown in FIG. 12 and 13, the exemplary first power region 1011-1 includes a CPU 1111, a power line 1101, and a plurality of switches 1110-1 and 1110-2. .

The CPU 1111 includes a plurality of cores 1111-1 and 1111-2 and the power PWR1 supplied to each of the cores 1111-1 and 1111-2 is supplied to each sub- 1 and 1119-2, respectively. Whether or not each of the cores 1111-1 and 1111-2 is reset can be independently controlled according to the control of each sub-finite state machine 1119-1 and 1119-2.

For example, the first sub-finite state machine 1119-1 outputs the first switching signal SW11 or the first reset signal RST1 according to the configuration register value set in the configuration register 1120-1 included therein, Lt; / RTI > The first switch 1110-1 supplies the power PWR1 to the first core 1111-1 or the power PWR1 supplied to the first core 1111-1 in accordance with the first switching signal SW11 ).

The second sub-finite state machine 1119-2 generates the second switching signal SW12 or the second reset signal RST2 according to the configuration register value set in the configuration register 1120-2 included therein . The second switch 1110-2 supplies the power PWR1 to the second core 1111-2 or the power PWR1 supplied to the second core 1111-2 in accordance with the second switching signal SW12 ).

For example, when the power states of the IPs 1111-1 and 1111-2 are supplied to the respective IPs 1111-1 and 1111-2 in the power-up state, that is, when the power PWR1 is supplied to the environment setting register 1120 -1 is set to 0x0 by the CPU 1111, the first sub-finite state machine 1119-1 outputs the switch signal SW11 having the high level. Therefore, since the switch 1110-1 implemented by the PMOS transistor is turned off, the power PWR1 supplied to the first core 1111-1 is cut off.

Conversely, when the power states of the respective IPs 1111-1 and 1111-2 are not supplied to the respective IPs 1111-1 and 1111-2 in the power-down state, that is, when the power PWR1 is supplied to the configuration registers 1120 -1 is set to Ox3 by the CPU 1111, the first sub-finite state machine 1119-1 outputs the switch signal SW11 having the low level. Therefore, the switch 1110-1 implemented by the PMOS transistor is turned on, so that the power PWR1 is supplied to the first core 1111-1.

The second sub-finite state machine 1119-2 supplies the power PWR1 to the second core 1111-2 or the second core 1111-2 in accordance with the configuration register value set in the configuration register 1120-2, The power PWR1 supplied to the power source 1111-2 can be cut off.

FIG. 14 shows a block diagram of the second power region shown in FIG. 12, FIG. 15 shows a block diagram of the data storage device shown in FIG. 13, FIG. 16 shows a block diagram of the separation circuit shown in FIG. And Fig. 17 shows a block diagram of the second finite state machine shown in Fig.

14 through 17, a second power region 1011-2 illustrated as an example includes a plurality of first switches 1130-1 through 1130-k (k is a natural number), a plurality of IPs 1140 A plurality of second switches 1149-1 to 1149-m, a clock management unit (CMU) 1150, and a phase locked loop (PLL) < / RTI >

Each of the plurality of first switches 1130-1 to 1130-k is connected between the power line 1131-1 and the common power line 1131-2.

For example, when each of the plurality of first switches 1130-1 to 1130-k is implemented as a PMOS transistor, in the power-down sequence, each of the plurality of first switches 1130-1 to 1130- May be turned off according to each of a plurality of switching signals SW31 to SW3k output from one sub-finite state machine 1210-1.

That is, the level of each of the plurality of switching signals SW31 to SW3k may be determined according to the configuration register values set in the configuration register 1211-1 implemented in the first sub-finite state machine 1210-1 .

In the power-up sequence, each of the plurality of first switches 1130-1 to 1130-k is connected to each of the plurality of switching signals SW31 to SW3k output from the first sub-finite state machine 1210-1 Can be turned on.

That is, the level of each of the plurality of switching signals SW31 to SW3k may be determined according to the configuration register values set in the configuration register 1211-1 implemented in the first sub-finite state machine 1210-1 . The CPU 1111 can set the environment setting register values to be stored in the environment setting register 1211-1.

Each of the IPs 1140-1 to 140-m includes respective internal logic circuits 1141-1 to 1141-m and respective interfaces 1145-1 to 1145-m. Each of the internal logic circuits 1141-1 to 1141-m is a core of each of the IPs 1140-1 to 1140-m and may include respective data storage devices 1143-1 to 1143-m .

The structure of each of the data storage devices 1143-1 to 1143-m is as shown in FIG. Since the structures of the respective data storage devices 1143-1 to 1143-m are substantially the same, one data storage device 1143-1 is shown for convenience of explanation.

Each data storage device 1143-1 to 1143-m is an example of a data storage device that performs a function of retention of data (DATA) to be stored in a power-down sequence or a power-down state.

The data storage device 1143-1 includes a first data storage device 1144-1 and a second data storage device 1144-2. The first data storage 1144-1 transfers the data stored therein to the second data storage 1144-2 in accordance with the maintenance control signal RC1 output from the third sub-finite state machine 1210-3 send. Thus, the second data storage device 1144-2 can maintain data even in the power-down sequence or power-down state. For example, each data storage device 1144-1 and 1144-2 may be implemented as a latch.

Whether or not data is retained in the respective data storage devices 1143-1 to 1143-m is determined based on the activation sequence of each of the plurality of control signals RC1 to RCm output from the third sub-finite state machine 1210-3, . The activation sequence or activation of each of the plurality of control signals RC1 to RCm is determined according to each of the configuration register values stored in the configuration register 1211-3 of the third sub-finite state machine 1210-3 . The CPU 1111 can set environment setting register values to be stored in the environment setting register 1211-3.

The activation order or activation state of each of the second switches 1149-1 to 1149-m is determined according to the activation order or activation of each of the plurality of control signals CT1 to CTm output from the CMU 1150 do. The CMU 1150 determines the activation order or activation state of each of the plurality of control signals CT1 to CTm according to the control signal CMUC output from the second sub-finite state machine 1210-2.

Depending on the embodiment, the activation sequence or activation of each of the second switches 1149-1 through 1149-m may be directly determined according to the control of the second sub-finite state machine 1210-2.

Each of the plurality of second switches 1149-1 through 1149-m may be implemented as an AND gate. Therefore, each of the AND gates 1149-1 to 1149-m supplies the respective clock signals CLK1 to CLKm to the respective IPs 1140-1 to 1140-m according to the level of each of the control signals CT1 to CTm Can be blocked.

The CMU 1150 can generate a plurality of clock signals CLK1 to CLKm in accordance with the clock signal CLK output from the PLL 1151. [ Each of the plurality of clock signals CLK1 to CLKm may be used as an operation clock signal of each of the plurality of IPs 1140-1 to 1140-m.

Each of the interfaces 1145-1 through 1145-m that may be implemented with circuitry or logic is a sub-finite state machine implemented in the PMU 1017 and capable of controlling the operation of each of the interfaces 1145-1 through 1145- And can be enabled or disabled according to the respective control signals PC1 to PCm output from the control circuit (not shown). The activation order or activation state of each control signal PC1 to PCm is determined according to each environment setting register value set in the environment setting register implemented in the sub-finite state machine.

Each of the interfaces 1145-1 through 1145-m may be a pad. Each pad can isolate, connect, or retention according to the respective control signals PC1 through PCm. In addition, each of the interfaces 1145-1 through 1145-m may be an oscillator pad. Each oscillator pad may be turned on or off according to the respective control signals PC1 through PCm.

As shown in FIG. 17, the second finite state machine 1019-2 includes a main finite state for determining the activation order or activation state of each of the plurality of sub-finite state machines 1210-1 to 1210-s, Machine 1200. The activation sequence or activation of each of the plurality of sub-finite state machines 1210-1 to 1210-s is determined according to the configuration register values set in the configuration register 1201 of the main finite state machine 1200. [ The CPU 1111 can set environment setting register values to be stored in the environment setting register 1201. [

As described above, the main finite state machine 1200 and the plurality of sub-finite state machines 1210-1 to 1210-s each communicate with each other through handshaking.

The CPU 1111 monitors the states of the respective IPs included in the power areas 1011-1 to 1011-n and sets them in the respective environment setting registers 1201 and 1211-1 to 1211-s according to the monitoring result You can create the configuration register values to be updated.

18 shows a comprehensive state diagram of a finite state machine according to an embodiment of the present invention. Referring to Fig. 7, the comprehensive state diagram includes a plurality of states (S1001 to S1023).

Each finite state machine described herein includes at least two states among a plurality of states (S1001 through S1023).

Each state S1001 to S1023 that can be implemented by a circuit, logic, code, or a combination thereof can control the operation of the lower finite state machine corresponding to each state S1001 to S1023. Each of the states S1001 to S1023 is a state in which a request signal and an acknowledge signal are exchanged through a handshaking with a lower finite state machine corresponding to each state S1001 to S1023 have.

Each condition, such as request signals C1 to C9, is a signal output from the upper finite state machine, and each condition, such as request signals C11 to C13, are signals generated within the finite state machine.

Referring to FIG. 18, each state (S1005, S1008, S1011, S1013, S1023, S1020, S1017, and S1015) is performed according to each request signal C1 to C9 output from the corresponding upper finite state machine.

The reset sequence includes a state S1001 to a state S1003. For example, when the reset event C9 is input in the state S1001, the reset sequencer 1023 sequentially performs the state S1002 and the state S1003. Each state (S1002 and S1003) communicates with each lower finite state machine via handshaking. Therefore, the target power region transits to the power-up state S1004 through the state S1002 and the state S1003.

The power-down sequence includes a state (S1005) to a state (S1013). The activation order or activation state of each of the plurality of states (S1005 to S1013) is determined according to the environment setting register values output from the CPU.

State S1004 transitions to state S1005 when a condition C1, for example, a power-down request signal, is input to the finite state machine having the power-up state S1004 from the upper finite state machine. The state (S1005) communicates with the lower finite state machine through its own hand-shaking, and the state (S1005) transits to the state (S1006) according to the response signal output from the lower state machine. The state S1006 communicates with the lower finite state machine through its own hand-shaking, and state S1006 transitions to state S1007 according to the response signal output from the lower state machine.

When the condition C11 occurs before the condition C2 is input from the upper finite state machine, the state S1007 transitions to the state S1021 without transition to the state S1008. However, when the condition C2 is input from the upper finite state machine before the condition C11 occurs, the state S1007 transitions to the state S1008. The power-up state (S1004) transits to the power-down state (S1014) through a plurality of states (S1005 to S1013).

The power-up sequence includes the state (S1015) to the state (S1023). The activation order or activation state of each of the plurality of states (S1015 to S1023) is determined according to the environment setting register values output from the CPU.

When the condition C8 is inputted from the upper finite state machine, the power-down state S1014 transitions to the state S1015, and the state S1015 communicates with the lower finite state machine through its own hand- When a response signal is inputted from the lower finite state machine, the state (S1015) transits to the state (S1016). State (S1016) communicates with its lower finite state machine through hand-shaking. When the condition C7 is input from the upper finite state machine, state S1016 transitions to state S1017 and state 1017 communicates with its lower finite state machine via hand-shaking. The state (S1014) transits to the power-up state (S104) through a plurality of states (S1015 to S1023).

For example, the lower finite state machine corresponding to the activated state may or may not perform an action or a task according to the request signal output from the state. For example, even if all of the states (S1005 to S1013) are activated in accordance with the configuration register values in the power-down sequence, the lower finite state machine corresponding to state (S1007) may not perform any action or anything. In this case, the state S1007 transits directly to the state S1008 according to the response signal output from the lower finite state machine. That is, the state S1007 can be bypassed. It can be defined that the finite state machine corresponding to the bypassed state or the bypassed state is deactivated.

For example, if the lower finite state machine in the state corresponding to the environment setting register value '1' performs the predetermined action or task and the lower finite state machine in the state corresponding to the environment setting register value '0' If not defined, the activation order or activation state of each of a plurality of states corresponding to each of the configuration register values can be determined.

For example, when the configuration register values are set to '111111111' in the power-down sequence, the plurality of states (S1005 to S1013) are sequentially activated and accordingly the lower finite state corresponding to each of the plurality of states (S1005 to S1013) The machine can perform a defined action or a set job. However, when the configuration register values are set to '101010101', each state (S1006, S1008, S1010, and S1012) is bypassed. That is, it can be defined that each state (S1006, S1008, S1010, and S1012) is deactivated.

(Or jump) to the state S1007 when the action or the work corresponding to the state S1005 is completed, and the state S1007 is changed to the state S1007 if the environment setting register values are set to '101010101' , The state S1007 transits to the state S1009. Similarly, the state S1009 transitions to the state S1011 and the state S1011 transitions to the state S1013. Thus, the configuration register values may determine the activation order or activation state of each of a plurality of states. The activation order or activation state of each of the plurality of finite state machines is determined according to the activation order or activation state of each of the plurality of states.

As described above, the state corresponding to the configuration register value 1 or the finite state machine corresponding to the state can be expressed as activated and the state corresponding to the configuration register value 0 or the finite state machine corresponding to the state is expressed as inactive .

19 shows a sub-set according to one embodiment of the state diagram shown in Fig. The sub-set shown in FIG. 19 is a state diagram of a finite state machine including only two states (S1004 and S1014) among a plurality of states (S1001 to S1023) included in the state diagram of FIG.

12, 13, 17, 18, and 19, each sub-finite state machine 1119-1 and 1210-1 includes two states (S1004 and S1014). In the power-up state (S1004), the target power region operates normally, and in the power-down state (S1014), the target power region is in the power-down state. The respective states (S1004 and S1014) transition according to the respective request signals (down_req and up_req). The sources of the respective request signals down_req and up_req are connected to the configuration registers 1120-1 and 1211-1 of the central sequencer 1021 or each of the sub-finite state machines 1119-1 and 1210-1, to be.

The central sequencer 1021 is responsible for SoC-level power control, and each configuration register 1120-1 and 1211-1 is responsible for domain-level power control.

20 shows a sub-set according to another embodiment of the state diagram shown in Fig. 20 includes a plurality of states (S1004 to S1007, S1009, S1014, S1019, and S1021 to S1023) among a plurality of states (S1001 to S1023) included in the state diagram of Fig. State machine.

20, there are a plurality of states (S1005, S1006, S1007, and S1009) between the power-up state (S1004) and the power-down state (S1014). The power-up state S1004 can transition to the power-down state S1014 through the plurality of states S1005 to S1009, according to one request signal (down_req) output from the upper finite state machine. That is, the power domain or IP with the power-up state S1004 can transition to the power-down state (S1014) via the power-down sequence including multiple states S1005, S1006, S1007, and S1009 have.

According to one request signal up_req output from the upper finite state machine, the power-down state S1014 transitions to the power-up state S1004 through the plurality of states S1019, S1021, S1022, and S1023. can do. That is, the power domain or IP with the power-down state S1014 can transition to the power-up state S1004 through the power-up sequence including the plurality of states S1019, S1021, S1022, and S1023 have.

FIG. 21 shows a sub-set according to another embodiment of the state diagram shown in FIG. 21, there are a plurality of states (S1005, S1006, S1007, and S1009) between the power-up state (S1004) and the power-down state (S1014). The power-up state S1004 is controlled by the power-down state S1014 via the plurality of states S1005, S1006, S1007, and S1009, depending on the plurality of request signals (down_req [0] and down_req [ . ≪ / RTI > That is, the power domain or IP with the power-up state S1004 can transition to the power-down state (S1014) via the power-down sequence including multiple states S1005, S1006, S1007, and S1009 have. Each of the plurality of request signals (down_req [0] and down_req [1]) may be output from the same upper finite state machine or from different upper finite state machines.

For example, all the bus masters corresponding to the target power region are disabled according to the first request signal (down_req [0]), and the power supplied to the target power region according to the second request signal (down_req [ .

The power-off state S1014 is switched to the power-up state S1004 through the plurality of states S1019, S1021, S1022, and S1023 according to the plurality of request signals up_req [0] and up_req [ . ≪ / RTI > That is, the power domain or IP with the power-up state S1004 can transition to the power-down state (S1014) via the power-down sequence including multiple states S1005, S1006, S1007, and S1009 have. Each of the plurality of request signals (up_req [0] and up_req [1]) may be output from the same upper finite state machine or from different upper finite state machines.

22 shows a sub-set according to another embodiment of the state diagram shown in Fig. Referring to FIGS. 21 and 22, the state S1007 included in the power-down sequence is included in the power-up sequence according to the condition C11 before reaching the power-down state S1014 through the state S1009 (S1021). ≪ / RTI > In this case, the power region or IP having the power-up state S1004 returns to the power-up state S1004 again via the respective states S1021, S1022, and S1023 before reaching the power-down state S1014 .

Data retention is performed on the L2 cache memory of the CPU in accordance with the first down request signal (down_req [0]), and the second down request signal down_req [0] 1]), the power supplied to the target power region, for example, the L2 cache memory, may be interrupted.

23 shows a sub-set according to another embodiment of the state diagram shown in Fig.

Referring to FIGS. 22 and 23, a finite state machine capable of performing a reset function includes a reset sequence including a plurality of states (S1002 and S1003) according to a reset request signal (reset_req) output from an upper finite state machine . Therefore, according to the control of the finite state machine, the corresponding power region transits from the state S1001 to the power-up state S1004.

24 shows a state diagram of a finite state machine capable of performing a reset operation.

Referring to FIGS. 12 and 24, when a reset event occurs (S1100), the reset sequencer 1023 performs a reset function among a plurality of finite state machines 1011-1 to 1011-n according to the reset event Lt; RTI ID = 0.0 > finite < / RTI >

For example, the reset sequencer 1023 may be implemented as a finite state machine without branches. 24, according to the control of the reset sequencer 1023, a finite state machine capable of performing a reset operation on a target power region or a target IP includes a plurality of states S1110 to S1150 .

In the reset operation, the reset sequencer 1023 or the reset sub finite state machine of the finite state machine waits for power supplied to the oscillator (S1110), the CMU is reset (S1120), the internal logic circuit is reset (S1130) Each sub-block included in the memory is reset (S1141, S1143, and S1145) and the CPU is reset (S1150). Accordingly, the corresponding power region or IP is brought into the power-up state (S1160).

FIG. 25 is a flowchart for explaining the operation of the SoC shown in FIG. 12; FIG.

12 and 25, the CPU monitors the operation of each of the IPs included in each of the plurality of power areas 1011-1 to 1011-n and generates configuration register values according to the monitoring result (S1200 ).

One of a plurality of finite state machines 1019-1 to 1019-n, each of which independently controls each of a plurality of power regions 1011-1 to 1011-n including a plurality of IPs, And receives the configuration register values output from the CPU (S1210).

In any one of the plurality of power domains 1011-1 to 1011-n, the finite state machine independently controls the power state and the operation state of the power domain according to the environment setting register values in operation S1220.

FIG. 26 conceptually illustrates one embodiment of a plurality of hierarchically implemented finite state machines. 12 and 26, the SoC 1010 includes a plurality of power areas 1011-1 to 1011-n, each of which includes a plurality of IPs, and a PMU 1017. [

The PMU 1017 includes a plurality of hierarchically implemented finite state machines (FSMs) 1021 and 1019-1 to 1019-n (GC1 to GCp). Although FIG. 26 shows a plurality of FSMs 1021, 1019-1 to 1019-n (GC1 to GCn) implemented in three layers for convenience of explanation, the present invention is not limited thereto.

The activation sequence or activation of each of the child FSMs 1019-1 to 1019-n among the plurality of FSMs 1021, 1019-1 to 1019-n (GC1 to GCn) is controlled by the child FSMs 1019-1 to 1019- n are determined according to the first register values set in the parent FSM 1021, e.g., the central sequencer, to which they belong.

The activation order or activation state of each of the FSM groups GC1 to GCp belonging to the child FSMs 1019-1 to 1019-n is determined by the second register set in each of the child FSMs 1019-1 to 1019- Is determined according to the values. Each of the grandchild FSM groups (GC1 through GCp) includes a plurality of grandchild FSMs.

Each of the child FSMs 1019-1 to 1019-n independently controls each of a plurality of power domains 1011-1 to 1011-n and a grandchild FSM Each independently control the power state and operation state of each of the plurality of IPs included in each of the plurality of power domains 1011-1 through 1011-n.

FIG. 27 conceptually illustrates another embodiment of a plurality of hierarchically implemented finite state machines. 12, 26, and 27, the PMU 1017 includes a plurality of finite state machines 1019-1 to 1019-n capable of performing a reset function among a plurality of finite state machines 1019-1 to 1019- 1 and 1019-2) for controlling the respective reset operations. The reset sequencer 1023 may control the reset operation of the central sequencer 1021 according to an embodiment.

28 shows a block diagram of an electronic device including the SoC shown in Fig.

12 and 28, the electronic device 1300 may be a personal computer (PC), a laptop computer, a mobile phone, a smart phone, a tablet PC, a PDA (personal digital assistant), or a portable multimedia player (PMP).

The electronic device 1300 includes a SoC 1010 and a plurality of interfaces 1311-1323. The CPU of the SoC 1010 controls the overall operation of the SoC 1010.

The SoC 1010 can communicate with each of a plurality of peripheral devices through each of a plurality of interfaces 1311 to 1323. For example, each of the plurality of interfaces 1311 to 1323 may transmit at least one control signal output from the corresponding IP among the plurality of IPs implemented in each of the power domains 1011-1 to 1011-n to the plurality of peripheral devices Respectively.

For example, the SoC 1010 can control the power state and operation state of each flat panel display through the respective display interfaces 1311 and 1312. [ The flat panel display device includes a liquid crystal device (LCD) display, a light emitting diode (LED) display, an organic light emitting diode (OLED) display, or an active matrix organic light emitting diode (AMOLED) display.

The SoC 1010 can control the power state and operation state of the camcorder via the camcorder interface 1313 and can control the power state and the operation state of the TV module through the TV interface 1314, 1315 to control the power state and the operation state of the camera module or the image sensor module.

The SoC 1010 can control the power state and the operation state of the GPS module through the GPS interface 1316 and the power state and the operation state of the UWB module via the UWB interface 1317 , And the USB drive interface 1318 to control the power state and operation state of the USB drive.

The SoC 1010 may control the power state and operating state of the DRAM via a dynamic random access memory interface (DRAM) interface 1320 and may be coupled to the non-volatile memory 1320, It is possible to control the power state and operation state of the flash memory and to control the power state and operation state of the audio module through the audio interface 1321 and to control the power state of the MFC through the MFC interface 1322 And can control the power state of the MP3 player through the MP3 player interface 1323. [ Wherein the module or interface may be implemented in hardware or software.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

100,200; integrated circuit device
Power supply circuit
131 to 13n, 231 to 23n, power area blocks
140,240; power control circuit
141 to 14n, 241 to 24n, power clusters
150,250; Central cluster
260, a clock generating circuit

Claims (36)

A plurality of power domain blocks;
core; And
And power control circuitry for independently controlling the power state of each of the plurality of power area blocks in response to control of the core,
Wherein the power control circuit includes a plurality of power clusters and a central cluster corresponding to each of the plurality of power domain blocks,
Each power cluster independently controlling a power state of a corresponding one of the plurality of power domain blocks in response to control of the core,
Wherein the central cluster controls an operation order of the plurality of power clusters in response to control of the core. The method according to claim 1,
Wherein a specific one of the plurality of power clusters blocks power supplied to a specific one of the plurality of power domain blocks corresponding to the particular power cluster in response to control of the core. The method according to claim 1,
Wherein the power control circuit further comprises a core power cluster for controlling a power state of the core,
And in response to the control of the central cluster, the plurality of power clusters and the core power cluster sequentially block power to the plurality of power domain blocks and power supplied to the core. The method according to claim 1,
When a first control signal is transmitted from the core to a specific one of the plurality of power clusters and a second control signal is transmitted from the central cluster to the specific power cluster, And transmits a response signal to the central cluster to the central cluster, ignoring the second control signal. The method according to claim 1,
The power control circuit
Further comprising a plurality of clock clusters each corresponding to the plurality of power domain blocks and independently controlling an operating state of the plurality of power domain blocks in response to control of the core,
Wherein the central cluster controls an operation order of the plurality of clock clusters in response to control of the core. A plurality of power domains, each power domain comprising a plurality of IPtellectual properties;
A plurality of finite state machines each independently controlling a power state and an operating state of each of the plurality of power regions according to register values set in a register implemented therein, unit; And
And a central sequencer for determining the activation order or activation state of each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register included therein, on Chip) 7. The apparatus of claim 6, wherein each of the plurality of finite state machines comprises:
Comprising a plurality of states,
Wherein the activation order or activation state of each of the plurality of states is determined according to the register values. 7. The apparatus of claim 6, wherein each of the plurality of finite state machines comprises:
A plurality of sub-finite state machines each independently controlling the power state and the operating state; And
And a main state machine for determining an activation order or activation state of each of the plurality of sub-finite state machines according to the register values set therein. 7. The system of claim 6,
A central processing unit (CPU) that monitors the operation of each of the IPs included in each of the plurality of power areas, and generates the register values for the power area to be controlled among the plurality of power areas according to the monitoring result More SoCs. The method according to claim 6,
The final state of each of the plurality of power regions independently controlled by the central sequencer is the same as the SoC. 7. The apparatus of claim 6, wherein each of the plurality of finite state machines comprises:
Controlling the power state defined by a power-up state, a power-down state, a power-up sequence, or a power-down sequence in units of a power region,
A SoC for controlling the operating state in IP units. 7. The system of claim 6,
Further comprising a plurality of isolation circuits each of which is connected between the plurality of power regions,
Wherein each of the plurality of separation circuits comprises:
The SoC being connected or disconnected according to the register values stored in each of the plurality of finite state machines. 7. The apparatus of claim 6, wherein each of the plurality of finite state machines comprises:
A first sub-finite state machine for determining the power state; And
And a second sub-finite state machine for determining the operating state,
Wherein each of the plurality of power regions comprises:
A power line for supplying a corresponding power from a plurality of powers output from the power supply circuit;
A common power line to which a plurality of IPs contained therein are connected;
A plurality of first switches each connected between the power line and the common power line and switched according to control of the first sub-finite state machine; And
And a plurality of second switches for supplying each of the plurality of clock signals output from the clock control unit to each of the plurality of IPs contained therein,
The switching of each of the plurality of first switches is determined according to the first switch register values stored in the first sub-finite state machine,
Wherein the switching of each of the plurality of second switches is determined according to second switch register values stored in the second sub-finite state machine. 7. The method of claim 6, wherein one of the plurality of power regions is a power region,
And a CPU including a first core and a second core,
A finite state machine capable of controlling any one of the plurality of finite state machines,
A first sub-finite state machine capable of controlling the power state and reset of the first core; And
A second sub-finite state machine capable of controlling the power state and reset of the second core. A plurality of power domains, each power domain comprising a plurality of IPtellectual properties;
A plurality of finite state machines each independently controlling a power state and an operating state of each of the plurality of power regions according to register values set in a register implemented therein, unit;
A central sequencer for determining an activation sequence or activation of each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register contained therein; And
And a reset sequencer for controlling a reset operation of each of a plurality of finite state machines capable of performing a reset function among the plurality of finite state machines. A plurality of power regions each comprising a plurality of intellectual properties (IPs); and
And a power control unit including a plurality of FSMs (finite state machines) hierarchically implemented,
Wherein activation order or activation of each of the child FSMs among the plurality of FSMs is determined according to first register values set in a parent FSM to which each of the child FSMs belongs,
The activation order or activation state of each of the grandchild FSMs belonging to the child FSMs is determined according to the second register values set for each of the child FSMs,
Each of the grandchild FSMs independently controlling a power state and an operation state of each of the plurality of IPs included in each of the plurality of power regions. A System on Chip (SoC) including a plurality of power regions, each of which includes a plurality of IPtellectual properties; And
Each of the plurality of peripheral devices operating under control of each of the plurality of IPs,
In the SoC,
A power control unit comprising a plurality of finite state machines that independently control the power state and the operating state of each of the plurality of power regions according to register values set in registers implemented therein; And
And a central sequencer for determining the activation order or activation of each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register contained therein. A System on Chip (SoC) including a plurality of power regions, each of which includes a plurality of IPtellectual properties;
A display device operating under control of any one of a plurality of IPs included in any one of the plurality of power domains;
And a memory device operable under the control of any one of a plurality of IPs included in another one of the plurality of power domains,
In the SoC,
A power control unit comprising a plurality of finite state machines that independently control the power state and the operating state of each of the plurality of power regions according to register values set in registers implemented therein; And
And a central sequencer for determining whether to activate or deactivate each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register contained therein, . A plurality of power regions each comprising a plurality of intellectual properties (IPs); and
A plurality of finite state machines each independently controlling a power state and an operating state of each of the plurality of power regions according to register values set in a register implemented therein, Unit,
Each of the plurality of finite state machines comprising:
A first sub-finite state machine for determining the power state; And
A second sub-finite state machine and a third sub-finite state machine for determining the operating state,
Wherein each of the plurality of power regions comprises:
A power line for supplying a corresponding power from a plurality of powers output from the power supply circuit;
A common power line to which a plurality of IPs contained therein are connected;
A plurality of first switches each connected between the power line and the common power line and switched according to control of the first sub-finite state machine;
A plurality of second switches for supplying each of the plurality of clock signals output from the clock control unit to each of the plurality of IPs contained therein; And
A first data storage device and a second data storage device implemented in each of the plurality of IPs included therein,
The switching of each of the plurality of first switches is determined according to the first switch register values stored in the first sub-finite state machine,
The switching of each of the plurality of second switches is determined according to the second switch register values stored in the second sub-finite state machine,
The data stored in the first data storage device is held in the second data storage device according to a retention control signal generated by a holding register value included in the third sub-finite state machine. One of a plurality of finite state machines, each of which independently controls each of a plurality of power regions including a plurality of IPs, receives the configuration register values generated by the CPU; And
Wherein the one finite state machine controls the power state of one of the plurality of power regions according to the environment setting register values and controls the power state of each of at least two IPs included in the one power region And independently controlling an operating state of the system-on-chip (SoC). delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

Images