JP4869859B2 - Pilot signal receiver - Google Patents

Description

  The present invention relates to a terrestrial digital television broadcast pilot signal receiver and a terrestrial digital television receiver using the receiver.

  Currently, an OFDM (Orthogonal Frequency Division Multiplexing) transmission system called ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) is in practical use as a transmission system for terrestrial digital broadcasting.

  According to the standard ARIB STD-B31 of the Radio Industry Association, the pilot signals of this ISDB-T include scattered pilot (SP), continuous pilot (CP), TMCC (Transmission Multiplexing Configuration Control), and AC (Auxiliity Channel). Are described. Hereinafter, the pilot signal handled by the pilot signal receiver will be described using TMCC as an example.

  FIG. 1 is a block diagram showing a configuration of a conventional pilot signal receiver that receives two TMCC carriers in combination. The pilot signal receiver includes a frequency conversion circuit 10, an A / D conversion circuit 11, an orthogonal demodulation circuit 12, a complex multiplication circuit 13, a TMCC carrier reception circuit 14, and an adder 31. The received ISDB-T signal is converted to an intermediate frequency by the frequency conversion circuit 10. Thereafter, the signal is converted into a digital signal by the A / D conversion circuit 11, and the I and Q signals are output by the orthogonal demodulation circuit 12. The I and Q signals are respectively input to the complex multiplication circuit 13 and input to the TMCC carrier reception circuit 14.

  The TMCC carrier reception circuit 14 includes multipliers 15 to 18, average addition circuits 19 to 22, coefficient sequence generation circuits 23 and 24, subtractors 25 and 28, adders 26 and 27, and delay detection circuits 29 and 30. Yes. In the TMCC carrier reception circuit 14, the multipliers 15 and 17 receive the I and Q signals and the coefficient sequence “1, 0, −1, 0,...” Supplied from the coefficient sequence generation circuit 23. The multipliers 16 and 18 multiply the I signal and the Q signal by the coefficient sequence “0, −1, 0, 1,...” Supplied from the coefficient sequence generation circuit 24. , And supplied to the average addition circuits 19-22. The average addition circuits 19 to 22 perform average addition. The signals after the average addition are subtracted by subtracters 25 and 28, added by adders 26 and 27, and supplied to delay detection circuits 29 and 30.

  Since the TMCC carrier is modulated by DBPSK (Differential Binary Phase Shift Keying) and is modulated only to the I signal which is the in-phase component of the output of the quadrature demodulation circuit 12, among the output signals of the delay detection circuits 29 and 30, By adding only the I signal by the adder 31, two-carrier combined reception becomes possible.

  FIG. 2 is a block diagram showing the configuration of the delay detection circuits 29 and 30 shown in FIG. The delay detection circuits 29 and 30 include 1-symbol delay units 32 and 33, multipliers 34 to 37, a subtracter 38, and an adder 39. The configurations of the delay detection circuit 29 and the delay detection circuit 30 are the same. The I signal is delayed by one symbol by the one symbol delay unit 32, and the previous symbol delayed by one symbol and the current symbol are multiplied by the multiplier 36. Further, the Q signal is delayed by one symbol by the one symbol delay unit 33, and the previous symbol delayed by one symbol and the current symbol are multiplied by the multiplier 37. Then, the output of the multiplier 36 and the output of the multiplier 37 are added by an adder 39, and a detection output I is obtained.

  On the other hand, the Q signal is delayed by one symbol by the one symbol delay unit 33, and the previous symbol delayed by one symbol and the current symbol of the I signal are multiplied by the multiplier 34. The I signal is delayed by one symbol by the one symbol delay unit 32, and the previous symbol delayed by one symbol and the current symbol of the Q signal are multiplied by the multiplier 35. The output of the multiplier 34 and the output of the multiplier 35 are subtracted by a subtracter 38 to obtain a detection output Q.

  FIG. 3 is a diagram showing a constellation of TMCC carrier detection output of DBPSK modulation by the delay detection circuits 29 and 30 shown in FIGS. The ISDB-T system is basically an OFDM signal, and the phase on the receiving side is shifted during the guard interval period due to the difference Δfc between the center frequency of the transmitted OFDM signal and the received OFDM carrier frequency. As it is, a phase shift on the receiving side occurs every symbol. Therefore, the pilot signal receiver shown in FIG. 1 and the delay detection circuits 29 and 30 shown in FIG. 2 have a π / 4 as shown in FIG. Phase rotation will occur. As a result, the amplitude in the I-axis direction is relatively 1 / √2, which hinders improvement in reception sensitivity by TMCC carrier synthesis. For details of the phase shift, refer to Japanese Patent No. 3046960.

  Further, in order to receive the ISDB-T pilot signal carrier in a state where the antenna of the portable terminal is housed such as in a bag or pocket, the gain obtained by the two-carrier combined reception is not sufficient.

  FIG. 4 is a block diagram showing a configuration of a conventional pilot signal receiver including a narrowband frequency correction circuit. The pilot signal receiver includes a frequency conversion circuit 40, an A / D conversion circuit 41, an orthogonal demodulation circuit 42, a complex multiplication circuit 43, a TMCC carrier reception circuit 50, and a narrowband frequency correction circuit 51. The received ISDB-T received signal is converted into an intermediate frequency by the frequency conversion circuit 40. Thereafter, the signal is converted into a digital signal by the A / D conversion circuit 41, and the I and Q signals are output by the orthogonal demodulation circuit. The complex multiplier circuit 43 multiplies the I and Q signals output from the quadrature demodulation circuit 42 by the coefficient supplied from the narrowband frequency correction circuit 51 to correct the frequency. Here, the complex multiplication circuit 43 includes multipliers 44 to 47, a subtracter 48, and an adder 49.

  The narrowband frequency correction circuit 51 includes effective symbol length delay units 52 and 53, multipliers 54 and 55, moving average calculation units 56 and 57, a frequency error detection unit 58, and an adaptive phase control circuit 59. In the narrowband frequency correction circuit 51, the effective symbol length delay units 52 and 53 delay the I and Q signals output from the complex multiplication circuit 43 by an effective symbol period, respectively. Multipliers 54 and 55 multiply the I and Q signals of the previous symbol delayed by the effective symbol period and the I signal of the current symbol, and moving average calculation units 56 and 57 determine the moving average. Thereby, the correlation output of the guard interval period is obtained. The frequency error is detected by obtaining the arctangent of the correlation output by the frequency error detector 58. The adaptive phase control circuit 59 multiplies the loop gain so as to cancel out the frequency error, and then converts it into sin and cos, and supplies the coefficient to the complex multiplier 43.

  In the complex multiplication circuit 43, the coefficients supplied from the narrowband frequency correction circuit 51 are multiplied by multipliers 44 to 47, subtracted by a subtractor 48, and added by an adder 49. Thereby, the frequency shift can be corrected. However, the narrowband frequency correction circuit 51 has a limitation that the frequency range in which frequency correction is possible is ± 1/2 of the carrier interval.

  The I and Q signals whose frequency shift is corrected by the complex multiplier circuit 43 are supplied to the TMCC carrier receiving circuit 50. Here, the TMCC carrier receiving circuit 50 has the same configuration as the TMCC carrier receiving circuit 14 shown in FIG. In FIG. 4, an adder provided at the subsequent stage of the TMCC carrier receiving circuit 50 is omitted.

  By the way, prior art documents related to the pilot signal receiver described above include those described in Patent Documents 1 and 2, for example.

JP 2005-295053 A JP 2005-333512 A

  In the conventional pilot signal receiver shown in FIG. 1, since a guard interval of 1/8 is added to the effective symbol length, a phase rotation of π / 4 occurs, and as a result, the amplitude of the detection output of the received signal is relative. Therefore, there is a problem that the performance improvement by the two-carrier synthesis is not sufficiently exhibited.

  Further, in the state where the antenna of a portable terminal or the like is housed, there is a problem that the reception sensitivity is not sufficiently improved by the two-carrier combined reception.

  Further, in the narrowband frequency correction circuit 51 provided in the conventional pilot signal receiver shown in FIG. 4, the frequency range in which frequency correction is possible is limited to ± 1/2 of the carrier interval, and the temperature change of the receiver tuner There was a problem that it was not possible to cope with frequency drift due to.

  Therefore, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a pilot signal receiver capable of improving the reception performance when combining and receiving pilot signal carriers. is there.

In order to solve the above-described problems, a pilot signal receiver according to the present invention receives a pilot signal carrier for terrestrial digital television broadcasting and demodulates a pilot signal from the pilot signal carrier. For the other pilot signal carrier and the other pilot signal carrier, the difference between the other pilot signal carrier frequency and one or two pilot signal carrier frequencies in the two-carrier receiving circuit is carrier-shifted in advance. One or two 1-carrier receiving circuits that respectively receive, and a carrier combining circuit that combines pilot signal carriers received by the two-carrier receiving circuit and the one-carrier receiving circuit, the one-carrier receiving circuit comprising: Receive A first detection circuit that performs correction by phase rotation for only one pilot signal carrier, and the two-carrier reception circuit performs a second detection circuit that performs correction by phase rotation for the two received pilot signal carriers. It is characterized by having .

As a result, since the phase rotation correction term is added to the pilot signal carrier at the time of detection, reception sensitivity is not impaired by carrier synthesis. In addition, since all TMCC carriers arranged in one segment are combined and received, it is possible to obtain a higher carrier combining gain than before, and the antenna is stored in a bag or pocket. However, the reception sensitivity can be further improved.

  The pilot signal receiver according to the present invention further includes a broadband frequency correction circuit that generates a coefficient for sequentially shifting the carrier with the carrier interval as a minimum unit. As a result, in a broadband frequency correction circuit that does not use a specific reference signal (pilot signal), carrier shift is performed with the carrier interval as the minimum unit after carrier synchronization. Frequency correction is possible.

  In this case, it is preferable that the broadband frequency correction circuit generates a coefficient for performing a carrier search alternately in the front-rear direction around a predetermined carrier frequency in the carrier shift direction on the frequency axis. Thereby, the time until TMCC carrier synchronization can be shortened.

  Further, it is preferable that the broadband frequency correction circuit generates a coefficient that limits a frequency range for carrier search after pilot signal synchronization is established. Thereby, when TMCC synchronization is established even for a moment, the time until TMCC carrier synchronization can be further shortened by narrowing the frequency range of carrier shift.

  As described above, according to the present invention, it is possible to improve the reception performance when combining and receiving a pilot signal carrier.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings.
[Π / 4 phase rotation correction]
FIG. 5 is a block diagram showing a configuration of a π / 4 shift delay detection circuit provided in the pilot signal receiver according to the embodiment of the present invention. This pilot signal receiver uses a TMCC carrier reception circuit in the conventional pilot signal receiver shown in FIG. 4 instead of the delay detection circuits 29 and 30 in the conventional pilot signal receiver shown in FIGS. Instead of the delay detection circuit (not shown) provided in 50, a π / 4 shift delay detection circuit 60 is provided. As shown in FIG. 5, the π / 4 shift delay detection circuit 60 includes 1-symbol delay units 61 and 62, adders 63 and 69, subtracters 64 and 70, and multipliers 65 to 68.

Here, the input signal of the in-phase component at a certain sample time n demodulated in quadrature is I _n , the signal delayed by one symbol period by the 1-symbol delay unit 61 is I _n−1 , and the input of the quadrature component at a certain sample time n _Let Q _n be the signal, and Q _n−1 be the signal delayed by one symbol period by the one symbol delay unit 62. If the input signal of the π / 4 shift delay detection circuit 60 is S _{in, n} and the output signal is S _{out, n} , the delay detection output is the complex conjugate of the current symbol S _{in, n} (I _n + jQ _n ) and the previous symbol. It can be expressed by multiplication with S _{in, n−1} ^* (I _n−1 −jQ _n−1 ).

（１）式をブロック図にしたものが図５である。 Further, since a phase rotation of −π / 4 is given to the output signal, it can be expressed by the following equation. However, S ^* represents the complex conjugate of S.

FIG. 5 is a block diagram of the equation (1).

  Since the TMCC signal is a DBPSK-modulated signal, and the modulated signal is included only in the in-phase component, the sign determination may be performed for the I signal. Therefore, this circuit can be simplified by omitting the Q signal output system circuit. FIG. 6 is a block diagram showing a circuit configuration in which the π / 4 shift delay detection circuit 60 shown in FIG. 5 is simplified. The simplified π / 4 shift delay detection circuit 60 includes 1-symbol delay units 61 and 62, adders 63 and 69, a subtracter 64, and multipliers 65 and 67. Compared to FIG. 5, it can be said that the π / 4 shift delay detection circuit 60 of FIG. 6 is simplified in that the subtracter 70 and the multipliers 66 and 68 are not provided.

  Note that the π / 4 shift delay detection circuit 60 simplified by omitting the Q signal output system circuit shown in FIG. 6 can be applied not only to the TMCC signal but also to the AC signal and the CP signal.

  FIG. 7 is a diagram showing a constellation of TMCC carrier detection output by the π / 4 shift delay detection circuit 60 shown in FIGS. 5 and 6. A constellation of DBPSK modulation as shown in FIG. 7 can be obtained by the π / 4 shift delay detection circuit 60.

  As described above, the π / 4 shift delay detection circuit 60 performs the phase rotation correction of −π / 4. As a result, it is possible to correct the π / 4 phase rotation accompanying the addition of a 1/8 guard interval to the effective symbol length. Therefore, reception sensitivity is not impaired by carrier synthesis.

[4-carrier composite reception]
FIG. 8 is a TMCC carrier arrangement diagram in mode 3 and segment number 0. From FIG. 8, it can be seen that the TMCC signal is assigned to carriers having carrier numbers 101, 131, 286, and 349. The carrier number 225 in the figure is the number of the carrier located at the center of 101 and 349 at both ends of the TMCC4 carrier.

  FIG. 9 is a block diagram showing a configuration of a pilot signal receiver according to the embodiment of the present invention for combining and receiving the TMCC4 carriers shown in FIG. This pilot signal receiver includes a frequency conversion circuit 101, an A / D conversion circuit 102, an orthogonal demodulation circuit 103, a complex multiplication circuit 104, a narrowband frequency correction circuit 105, a two-carrier reception circuit 110, a one-carrier reception circuit 120, 130, Adders 140 to 142 and a TMCC carrier determination circuit 143 are provided.

The frequency conversion circuit 101 receives an ISDB-T reception signal and converts the frequency to an intermediate frequency _fIF . The A / D conversion circuit 102 inputs the intermediate frequency f _IF signal subjected to frequency conversion, and performs A / D conversion. The quadrature demodulation circuit 103 receives the A / D converted digital signal and performs quadrature demodulation on the I and Q signals. The complex multiplication circuit 104 receives the I and Q signals, receives the sine coefficient and the cosine coefficient from the narrowband frequency correction circuit 105, and multiplies the I and Q signals by these coefficients to correct the frequency shift. Here, the complex multiplication circuit 104 and the narrowband frequency correction circuit 105 have the same functions as the complex multiplication circuit 43 and the narrowband frequency correction circuit 51 shown in FIG.

  The two-carrier receiving circuit 110 is a circuit that receives two carriers of the TMCC signal having the carrier number 101 (# 101) and the TMCC signal having the carrier number 349 (# 349). , Q signals are input, processing described later is performed, and two I signals of the TMCC carrier are output to the adder 140.

  The one-carrier receiving circuit 120 is a circuit that receives one carrier of the TMCC signal having the carrier number 131 (# 131). The I- and Q-signals whose frequency shift is corrected by the complex multiplication circuit 104 are input, and processing described later is performed. And outputs one I signal of the TMCC carrier to the adder 142.

  The one-carrier receiving circuit 130 is a circuit that receives one carrier of the TMCC signal having the carrier number 286 (# 286), inputs the I and Q signals whose frequency shift is corrected by the complex multiplier circuit 104, and performs processing described later. And outputs one I signal of the TMCC carrier to the adder 142.

  The adder 140 inputs I signals of two TMCC carriers from the 2-carrier receiving circuit 110 and adds them. The adder 142 inputs the I signal of one TMCC carrier from the 1-carrier receiving circuit 120 and the I signal of one TMCC carrier from the 1-carrier receiving circuit 130 and adds them. Then, the adder 141 adds the addition result of the adder 140 and the addition result of the adder 142, and obtains the I signal of the TMCC4 carrier combined output.

  The TMCC carrier determination circuit 143 inputs an I signal that is a composite output of the TMCC4 carrier, and performs bit comparison between the bit stream of this signal and a preset TMCC synchronization signal, and determines TMCC synchronization establishment. If the bits match, it is assumed that synchronization has been established, and a TMCC synchronization establishment signal (hereinafter referred to as synchronization establishment signal) is sent to the carrier shift amount instruction circuit 116 of the 2-carrier reception circuit 110 and the 1-carrier reception circuit 120 The data is output to the carrier shift amount instruction circuit 125 and the carrier shift amount instruction circuit 135 of the one carrier reception circuit 130. Details of the TMCC carrier determination circuit 143 will be described later.

  Here, the 2-carrier reception circuit 110 includes a complex multiplication circuit 111, a complex average addition circuit 112, π / 4 shift delay detection circuits 113 and 114, a coefficient generation circuit 115, and a carrier shift amount instruction circuit 116. The 1-carrier reception circuit 120 includes a complex multiplication circuit 121, a complex average addition circuit 122, a π / 4 shift delay detection circuit 123, a coefficient generation circuit 124, and a carrier shift amount instruction circuit 125. The 1-carrier reception circuit 130 includes a complex multiplication circuit 131, a complex average addition circuit 132, a π / 4 shift delay detection circuit 133, a coefficient generation circuit 134, and a carrier shift amount instruction circuit 135.

The initial value N _initial provided to the carrier shift amount instruction circuit 116 of the two carrier reception circuit 110, the carrier shift amount instruction circuit 125 of the one carrier reception circuit 120, and the carrier shift amount instruction circuit 135 of the one carrier reception circuit 130 is respectively 0, −30, +63. Carrier shift amount instruction circuits 116, 125, and 135 receive the synchronization establishment signal from TMCC carrier determination circuit 143, generate carrier shift amounts corresponding to _initial value N _initial , and output them to coefficient generation circuits 115, 124, and 134, respectively. To do. The details of the carrier shift amount instruction circuits 116, 125, and 135 will be described later.

  The coefficient generation circuits 115, 124, and 134 receive the carrier shift amount from the carrier shift amount instruction circuits 116, 125, and 135, and generate a sine coefficient and a cosine coefficient according to the carrier shift amount. Are output to the complex multiplication circuits 111, 121 and 131, respectively. Details of the coefficient generation circuits 115, 124, and 134 will be described later.

  The complex multiplication circuit 111 sets the shift amount 0 by the carrier shift amount instruction circuit 116 as an initial value, inputs a coefficient by the coefficient generation circuit 115, performs frequency shift, and inputs the frequency-shifted I and Q signals to the complex average addition circuit 112. Output. The complex multiplication circuit 121 receives the shift amount −30 from the carrier shift amount instruction circuit 125 as an initial value, inputs a coefficient from the coefficient generation circuit 124, performs frequency shift, and performs complex average addition of the frequency-shifted I and Q signals. Output to the circuit 122. The complex multiplication circuit 131 uses the shift amount +63 by the carrier shift amount instruction circuit 135 as an initial value, inputs a coefficient by the coefficient generation circuit 134, performs frequency shift, and a complex average addition circuit for the frequency-shifted I and Q signals. It outputs to 132. The complex multiplier circuits 111, 121, and 131 have the same configuration as the complex multiplier circuit 43 shown in FIG.

  FIG. 10 is a block diagram showing a configuration of a 2-carrier complex average addition circuit 112 included in the 2-carrier reception circuit 110 shown in FIG. The complex average addition circuit 112 includes multipliers 150 to 153, average addition circuits 154 to 157, coefficient sequence generation circuits 158 and 159, subtracters 160 and 163, and adders 161 and 162. Here, the complex average adder circuit 112 is configured by multipliers 15 to 18, average adder circuits 19 to 22, coefficient sequence generator circuits 23 and 24, subtractors 25 and 28 in the TMCC carrier receiver circuit 14 shown in FIG. Since the configuration is the same as that of the adders 26 and 27, the description thereof is omitted here.

  FIG. 11 is a block diagram showing a configuration of a 1-carrier complex average addition circuit 122 included in the 1-carrier reception circuit 120 shown in FIG. The complex average addition circuit 122 includes multipliers 170 to 173, average addition circuits 174 to 177, coefficient sequence generation circuits 178 and 179, a subtracter 180, and an adder 181. Here, the complex average addition circuit 122 is configured by multipliers 15 to 18, average addition circuits 19 to 22, coefficient sequence generation circuits 23 and 24, subtractor 25, and addition in the TMCC carrier reception circuit 14 shown in FIG. Since the configuration is the same as that of the device 27, the description is omitted here.

  12 is a block diagram showing a configuration of a complex average adding circuit 132 for one carrier included in the one carrier receiving circuit 130 shown in FIG. The complex average addition circuit 132 includes multipliers 190 to 193, average addition circuits 194 to 197, coefficient sequence generation circuits 198 and 199, a subtractor 201, and an adder 200. Here, the complex average adder circuit 132 includes multipliers 15 to 18, average adder circuits 19 to 22, coefficient sequence generator circuits 23 and 24, adder 26, and subtractor in the TMCC carrier receiver circuit 14 shown in FIG. Since the configuration is the same as that of the device 28, the description is omitted here.

The complex average addition circuit 122 shown in FIG. 11 and the complex average addition circuit 132 shown in FIG. 12 have the same configuration as part of the complex average addition circuit 112 shown in FIG. In other words, by adding an offset of −30 carriers to the frequency of the input signal, that is, by adding −30 of the initial value N _{initial in} the carrier shift amount instruction circuit 116, in the 2-carrier receiving circuit 110 of # 101 The # 131 TMCC carrier can be received. Similarly, by adding +63 of the initial value N _initial in the carrier shift amount instruction circuit 116, the # 286 TMCC carrier can be received in the # 349 two-carrier receiving circuit 110.

  The π / 4 shift delay detection circuits 113, 114, 123, and 133 perform −π / 4 phase rotation correction on the input I and Q signals, and output the corrected I signals to adders 140 and 142, respectively. Since the π / 4 shift delay detection circuits 113, 114, 123, 133 have the same configuration as the π / 4 shift delay detection circuit 60 shown in FIGS. 5 and 6, the description thereof is omitted here.

  As described above, according to the pilot signal receiver shown in FIG. 9, the 2-carrier receiving circuit 110 and the 1-carrier receiving circuits 120 and 130 detect the 4-carrier pilot signal, and the adders 140 to 142 detect the detected signals. Are added and synthesized. As a result, compared with the case where two carriers are detected and added and combined, a higher carrier combining gain can be obtained, and even with a mobile terminal in which an antenna is housed such as in a bag or pocket, the reception sensitivity can be improved. This can be further improved.

  Although the pilot signal receiver shown in FIG. 9 combines and receives TMCC4 carriers, the pilot signal receiver may be configured to combine and receive TMCC3 carriers. In this case, the two-carrier receiving circuit 110 and the one-carrier receiving circuit 120 may be provided, and the one-carrier receiving circuit 130 is not necessary.

[Frequency correction of 1/2 or more of the carrier interval]
FIG. 13 is a diagram for explaining the operation of the wideband frequency correction circuit that corrects the frequency of a frequency shift of ½ or more of the carrier interval. Here, the broadband frequency correction is an integer (n) times the carrier interval Δf away from the carrier frequency f _C synchronized by the conventional frequency correction circuit (the narrow band frequency correction circuit 51 shown in FIG. 4). In order to synchronize with the carrier, the frequency shift is performed in units of the carrier interval Δf. That is, the frequency is shifted from the synchronized carrier frequency f _C to f _C + nΔf.

  FIG. 14 is a block diagram showing a configuration of a pilot signal receiver according to an embodiment of the present invention including a wideband frequency correction circuit. The pilot signal receiver includes a frequency conversion circuit 70, an A / D conversion circuit 71, an orthogonal demodulation circuit 72, a complex multiplication circuit 73, a narrowband frequency correction circuit 74, a complex multiplication circuit 75, a wideband frequency correction circuit 76, and a TMCC carrier reception. A circuit 77 and an adder 84 are provided.

  The frequency conversion circuit 70, the A / D conversion circuit 71, the orthogonal demodulation circuit 72, the complex multiplication circuit 73, and the narrowband frequency correction circuit 74 are the frequency conversion circuit 101, A / D conversion circuit 102, and orthogonal demodulation circuit shown in FIG. 103, the complex multiplier circuit 104, and the narrowband frequency correction circuit 105 have the same configuration, and thus the description thereof is omitted here.

  The complex multiplication circuit 75 and the wideband frequency correction circuit 76 receive the I and Q signals whose frequency deviation is corrected within ± 1/2 of the carrier interval by the complex multiplication circuit 73 and the narrowband frequency correction circuit 74, and Correct frequency deviation of ± 1/2 or more. The complex multiplier circuit 75 has the same configuration as the complex multiplier circuit 73, and these circuits have the same configuration as the complex multiplier circuit 43 shown in FIG.

  The TMCC carrier receiving circuit 77 receives the I and Q signals corrected by a frequency shift of ± 1/2 or more of the carrier interval by the complex multiplication circuit 75 and the wideband frequency correction circuit 76, and outputs the I signal of the TMCC2 carrier. The adder 84 adds the I signal of the TMC2 carrier from the TMCC carrier reception circuit 77. Thereby, the composite reception of the TMCC2 carrier is performed. This pilot signal receiver can receive TMCC even if a frequency shift of ± 1/2 or more of the frequency interval occurs.

  FIG. 15 is a block diagram showing a configuration of wideband frequency correction circuit 76 shown in FIG. The broadband frequency correction circuit 76 includes a TMCC carrier determination circuit 85, a carrier shift amount instruction circuit 86, and a coefficient generation circuit 87. The wideband frequency correction circuit 76 receives two carrier combined output I signals from the adder 84 and generates a coefficient for multiplication in the complex multiplication circuit 75.

FIG. 16 is a block diagram showing a configuration of TMCC carrier determination circuit 85 shown in FIG. The TMCC carrier determination circuit 85 includes a bit comparator 88 and a TMCC synchronization signal generator (not shown). The bit comparator 88 alternately transmits the TMCC bit stream obtained by performing the code determination on the carrier synthesized output I signal from the adder 84 and the 16 bits transmitted every frame from the TMCC synchronization signal generator. TMCC synchronization signals w ₀ = 001101101101110 and w ₁ = 1100101000010001, which are fixed bit strings of If the compared bits all match the TMCC synchronization signal w ₀ or w ₁ , it is determined that the carrier that is frequency-synchronized is a TMCC carrier, and a synchronization establishment signal is output.

  FIG. 17 is a block diagram showing a configuration of carrier shift amount instruction circuit 86 shown in FIG. The carrier shift amount instruction circuit 86 includes a counter 89, a counter width control circuit 90, a carrier shift conversion circuit 91, and an adder 92. The counter 89 and the counter width control circuit 90 receive the synchronization establishment signal output from the TMCC carrier determination circuit 85. The counter 89 counts until a synchronization establishment signal is input, and outputs the count value to the carrier shift conversion circuit 91. When the synchronization establishment signal is input, the counter operation is stopped and the count value is held. When the synchronization establishment signal is input even once, the counter width control circuit 90 outputs a control signal for reducing the upper limit value of the counter number to the counter 89. If synchronization is established even for a moment, it is determined that the frequency is corrected to a relatively close frequency, the upper limit value of the counter number is lowered, and the frequency range of carrier shift is narrowed. Thereby, the time until TMCC carrier synchronization can be shortened.

  For example, the counter width control circuit 90 outputs a control signal whose upper limit of the count value is 100 to the counter 89 until the synchronization establishment signal is input, and the counter 89 uses 0 to 100 as the count value. Then, when the synchronization establishment signal is input, the counter width control circuit 90 outputs a control signal for setting the upper limit of the count value to 40 to the counter 89. The counter 89 receives a control signal from the counter width control circuit 90 and uses 0 to 40 as a count value until a synchronization establishment signal is further input after the synchronization is lost.

The carrier shift conversion circuit 91 receives the count value from the counter 89, and sets n _shift = “0, + 1, −1, + 2, −2, + 3, −3. Alternatively, conversion is performed so that positive and negative integers are alternately output (zigzag scan) as in “0, −1, +1, −2, +2, −3, +3,. By using such a carrier shift conversion circuit 91, around the carrier frequency f _C synchronized by narrowband frequency correction circuit 74, alternately in the positive and negative directions with respect to the upper frequency axis, the carrier frequency search is performed. As a result, when the adjacent carrier in the direction opposite to the search direction is a TMCC carrier, the time until the intended carrier synchronization can be significantly shortened.

The adder 92 adds the output n _shift of the carrier shift conversion circuit 91 and the initial value N _initial to output the carrier shift amount n. By adding this initial value N _initial , an offset can be added to the carrier shift. For example, it can be used like N _initial in the carrier shift amount instruction circuits 116, 125, and 135 shown in FIG.

  FIG. 18 is a block diagram showing a configuration of coefficient generation circuit 87 shown in FIG. Here, an example in which the number of samples of one effective symbol is 496 is shown. The coefficient generation circuit 87 includes an adder 93, a one sample delay unit 94, a remainder calculation circuit 95, a sin generator 96, and a cos generator 97. The adder 93 adds the carrier shift amount n from the carrier shift amount instruction circuit 86 and the signal one sample before delayed by one sample by the one sample delay unit 94. The remainder calculation circuit 95 receives the addition result from the adder 93 and outputs 496 remainders. A sin generator 96 and a cos generator 97 receive the remainder from the remainder calculation circuit 95 and output a sine coefficient and a cosine coefficient to the complex multiplication circuit 75, respectively.

  As described above, according to the pilot signal receiver shown in FIG. 14, the wideband frequency correction circuit 76 and the complex multiplication circuit 75 correct the frequency deviation having a carrier interval of ± 1/2 or more. As a result, even if a temperature drift occurs in the reception tuner, oscillator, etc., the frequency shift associated therewith can be corrected.

  Further, according to the pilot signal receiver shown in FIG. 14, until the carrier shift amount instruction circuit 86 of the wideband frequency correction circuit 76 is synchronized with TMCC, the complex multiplier circuit 75 makes positive and negative with the carrier frequency fc as the center. The carrier shift amount is output so that the frequency shifts alternately in the direction. As a result, the complex multiplier circuit 75 does not shift the frequency in one direction, but shifts alternately in the positive and negative directions, so that the time until carrier synchronization can be shortened.

It is a block diagram which shows the structure of the conventional pilot signal receiver which carries out two TMCC carrier synthetic | combination reception. FIG. 2 is a block diagram illustrating a configuration of a delay detection circuit in FIG. 1. FIG. 3 is a diagram illustrating a constellation of TMCC carrier detection output of DBPSK modulation by the delay detection circuit of FIGS. 1 and 2. It is a block diagram which shows the structure of the conventional pilot signal receiver containing a narrow-band frequency correction circuit. It is a block diagram which shows the structure of the (pi) / 4 shift delay detection circuit with which the pilot signal receiver by embodiment of this invention was equipped. It is a block diagram which shows the structure of the simplified (pi) / 4 shift delay detection circuit. It is a figure which shows the constellation of the TMCC carrier detection output by a pi / 4 shift delay detection circuit. It is a TMCC carrier arrangement diagram in mode 3 and segment number 0. It is a block diagram which shows the structure of the pilot signal receiver by embodiment of this invention which carries out synthetic reception of the TMCC4 carrier. FIG. 10 is a block diagram illustrating a configuration of a complex average addition circuit (for two carriers) in FIG. 9. FIG. 10 is a block diagram illustrating a configuration of a complex average adder circuit A (for one carrier) in FIG. 9. FIG. 10 is a block diagram illustrating a configuration of a complex average adder circuit B (for one carrier) in FIG. 9. It is a figure explaining operation | movement of a wideband frequency correction circuit. It is a block diagram which shows the structure of the pilot signal receiver by embodiment of this invention containing a wideband frequency correction circuit. It is a block diagram which shows the structure of the wideband frequency correction circuit of FIG. It is a block diagram which shows the structure of the TMCC carrier determination circuit of FIG. FIG. 16 is a block diagram showing a configuration of a carrier shift amount instruction circuit of FIG. 15. FIG. 16 is a block diagram illustrating a configuration of a coefficient generation circuit (in the case of 496 samples) in FIG. 15.

Explanation of symbols

10, 40, 70, 101 Frequency conversion circuit 11, 41, 71, 102 A / D conversion circuit 12, 42, 72, 103 Orthogonal demodulation circuit 13, 43, 73, 75, 104, 111, 121, 131 Complex multiplication circuit 14, 50, 77 TMCC carrier receiving circuit 15-18, 34-37, 44-47, 54, 55, 65-68, 150-153, 170-173, 190-193 Multipliers 19-22, 154-157, 174 to 177, 194 to 197 Average addition circuit 23, 24, 158, 159, 178, 179, 198, 199 Coefficient sequence generation circuit 25, 28, 38, 48, 64, 70, 78, 81, 160, 163, 180 , 201 Subtractor 26, 27, 31, 39, 49, 63, 69, 79, 80, 84, 92, 93, 140 to 142, 161, 1 2,181,200 Adder 29,30 Delay detection circuit 32,33,61,62 1 symbol delay unit 51,74,105 Narrow band frequency correction circuit 52,53 Effective symbol length delay unit 56,57 Moving average calculation unit 58 Frequency error detector 59 Adaptive phase control circuit 60, 82, 83, 113, 114, 123, 133 π / 4 shift delay detection circuit 76 Broadband frequency correction circuit 85, 143 TMCC carrier determination circuit 86, 116, 125, 135 Carrier shift Quantity indicating circuit 87, 115, 124, 134 Coefficient generation circuit 88 Bit comparator 89 Counter 90 Counter width control circuit 91 Carrier shift conversion circuit 94 1 sample delay circuit 95 Remainder operation circuit 96 sin generator 97 cos generator 110 2 carrier reception Circuit 112, 122, 132 Complex plane Average addition circuit 120, 130 1-carrier reception circuit

Claims (4)

In a pilot signal receiver that receives a pilot signal carrier of digital terrestrial television broadcasting and demodulates a pilot signal from the pilot signal carrier,
A two-carrier receiving circuit for simultaneously receiving two pilot signal carriers;
For other pilot signal carriers, one or two ones for receiving a carrier shift in advance for the difference between the other pilot signal carrier frequency and one or two pilot signal carrier frequencies in the two-carrier receiving circuit, respectively. A carrier receiving circuit;
A carrier synthesizing circuit that synthesizes a pilot signal carrier received by the two-carrier receiving circuit and the one-carrier receiving circuit;
The one-carrier receiving circuit has a first detection circuit that performs correction by phase rotation for one received pilot signal carrier,
The pilot signal receiver, wherein the two-carrier reception circuit includes a second detection circuit that performs correction by phase rotation on the two received pilot signal carriers . The pilot signal receiver according to claim 1 , wherein
Further, a pilot signal receiver comprising a wideband frequency correction circuit for generating a coefficient for sequentially shifting carriers with a carrier interval as a minimum unit. The pilot signal receiver according to claim 2 , wherein
The pilot signal receiver, wherein the broadband frequency correction circuit generates a coefficient for performing a carrier search alternately in the front-rear direction around a predetermined carrier frequency in a carrier shift direction on a frequency axis. The pilot signal receiver according to claim 3 , wherein
A pilot signal receiver, wherein the broadband frequency correction circuit generates a coefficient that limits a frequency range for carrier search after pilot signal synchronization is established.

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