JP2005331368A - Gps receiver and synchronization retaining method in gps receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain the pull-in state of a Costas loop as long as possible even when the radio waves from the caught satellite become weak after the pulling-in has finished as well as making pull-in easily from a wide frequency range. <P>SOLUTION: A GPS receiver controls such that at the time of acquiring synchronization, a loop gain is made high, and a oscillation frequency range of NCO of the Costas loop is widened, and in retaining the synchronization, when the loop gain is low, the frequency range of NCO of the Costas loop is narrowed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a GPS (Global Positioning System) receiver and a synchronization maintaining method in the GPS receiver.

  In a GPS system that measures the position of a moving object using an artificial satellite (hereinafter referred to as a GPS satellite), a GSP receiver receives signals from four or more GPS satellites and uses the received signals to determine the position of the receiver. The basic function is to calculate and inform the user.

  The GPS receiver demodulates a received signal from a GPS satellite (hereinafter, this signal is referred to as a GPS satellite signal) to acquire GPS satellite orbit data, and from the GPS satellite orbit and time information and the delay time of the GPS satellite signal. The three-dimensional position of the receiving device is derived by simultaneous equations. The reason why the signals from the four GPS satellites are required for the positioning calculation is that there is an error between the time in the GPS receiver and the time of the satellite, and the influence of the error is removed.

  In the case of a consumer GPS receiver, a signal radio wave spectrum-spread by a spread code called an L1 band, C / A (Clear and Acquisition) code from a GPS satellite (Navstar) is received, and a positioning calculation is performed.

  The C / A code is a spreading code composed of a code of a PN (pseudo random noise) sequence having a transmission signal speed (chip rate) of 1.023 MHz and a code length of 1023, for example, a Gold code. The signal from the GPS satellite is a signal obtained by BPSK (Binary Phase Shift Keying) modulation of a carrier having a frequency of 1575.42 MHz by a signal obtained by spectrum-spreading 50 bps data using a spreading code. In this case, since the code length is 1023, as shown in FIG. 11A, the C / A code has 1023 chips as one period (and therefore one period = 1 millisecond). It is to repeat.

  The PN sequence code of the C / A code is different for each GPS satellite, but which GPS satellite uses which PN sequence code can be detected in advance by the GPS receiver. In addition, the GPS receiver can determine from which GPS satellite a signal can be received at that point and at that point by a navigation message (orbit information) as will be described later. Therefore, in the GPS receiver, for example, in the case of three-dimensional positioning, radio waves from four or more GPS satellites that can be acquired at that point and at that point are received, the spectrum is despread, and the positioning calculation is performed. Try to find the position.

  As shown in FIG. 11B, one bit of the satellite signal data (navigation message data) is transmitted for 20 periods of the PN sequence code, that is, in units of 20 milliseconds. That is, the data transmission rate is 50 bps. The 1023 chips for one period of the PN sequence code are inverted when the bit is “1” and when it is “0”.

  As shown in FIG. 11C, in GPS, one word is formed with 30 bits (600 milliseconds). Then, as shown in FIG. 11D, one subframe (6 seconds) is formed with 10 words. As shown in FIG. 11E, a preamble that always has a prescribed bit pattern is inserted into the first word of one subframe, even when data is updated, and data is transmitted after this preamble. It will be.

  Furthermore, one main frame (30 seconds) is formed by 5 subframes. The navigation message is transmitted in data units of one main frame. The first three subframes of the data of one main frame are orbit information unique to each satellite called ephemeris information. The ephemeris information is repeatedly sent in units of one main frame (30 seconds), and includes parameters for obtaining the orbit of the satellite that transmits the information, and the transmission time of the signal from the satellite.

  That is, the second word of the three subframes of the ephemeris information includes TOW (Time Of Week), and the third word of the first subframe 1 of the main frame includes time data called “Week Number”. Is included. The Week Number is information that counts up every week, starting from January 6, 1980 (Sunday) as the 0th week. Further, TOW is information on the time to count up every 6 seconds (subframe period) with 0 am on Sunday as 0.

  All GPS satellites are equipped with atomic clocks and use common time data, and the transmission time of signals from each GPS satellite is synchronized with the atomic clock. The absolute time is obtained by receiving the above two time data. The value of 6 seconds or less is synchronized with the time of the satellite with the accuracy of the reference oscillator included in the GPS receiver in the process of synchronously locking to the radio wave of the satellite.

  Also, the PN sequence code of each GPS satellite is generated in synchronization with the atomic clock. Further, from this ephemeris information, the position of the satellite and the speed of the satellite used for the positioning calculation in the GPS receiver are obtained.

  The ephemeris information is a highly accurate calendar that is updated relatively frequently by control from the control station on the ground. In the GPS receiver, by holding this ephemeris information in a memory, the ephemeris information can be used for positioning calculation. However, due to its accuracy, the usable lifetime is normally about 2 hours, and the GPS receiver monitors the elapse of time since the ephemeris information was stored in the memory, and when the lifetime is exceeded. The ephemeris information in the memory is updated and rewritten.

  Note that it takes at least 18 seconds (3 subframes) to acquire new ephemeris information from a GPS satellite and update the memory contents to the acquired ephemeris information. 30 seconds are required.

  The orbit information of the remaining two subframes of the data of one main frame is information transmitted in common from all satellites called almanac information. This almanac information is required for 25 frames in order to acquire all information, and includes approximate position information of each GPS satellite, information indicating which GPS satellite can be used, and the like.

  This almanac information is also updated at least every several days under the control of the control station on the ground. This almanac information can also be stored and used in the memory of the GPS receiver, but its lifetime is supposed to be several months, and the positioning accuracy of the satellite deteriorates with time. It can be used enough to know the position. Usually, it is normally updated when using a GPS receiver for almanac information. If this almanac information is stored in the memory of the GPS receiver, it is possible to calculate which channel should be assigned to which channel after the power is turned on.

  In order to obtain the above-mentioned data by receiving the GPS satellite signal by the GPS receiver, the same PN series as the C / A code used in the GPS satellite to be received is prepared in the GPS receiver. Code (hereinafter, in this specification, a PN sequence spreading code is referred to as a PN code. A PN sequence spreading code of a GPS satellite is referred to as a satellite PN code, and a corresponding PN sequence spreading code of a GPS receiver is a replica. The GPS satellite signal is captured by phase-synchronizing the C / A code with respect to the GPS satellite signal, and the spectrum is despread. When phase synchronization with the C / A code is taken and despreading is performed, bits are detected, and a navigation message including time information and the like can be acquired from a GPS satellite signal.

  The acquisition of the GPS satellite signal is performed by the phase synchronization search of the C / A code. In this phase synchronization search, the correlation between the replica PN code of the GPS receiver and the satellite PN code of the GPS satellite is detected, for example, When the correlation value of the correlation detection result is larger than a predetermined value, it is determined that the two are synchronized. When it is determined that the synchronization is not achieved, the phase of the replica PN code of the GPS receiver is controlled using some synchronization technique so as to synchronize with the satellite PN code.

  By the way, as described above, a GPS satellite signal is a signal obtained by BPSK modulation of a carrier with a signal obtained by spreading data with a satellite PN code. Therefore, in order for the GPS receiver to receive the GPS satellite signal, only the PN code is used. However, it is necessary to synchronize the carrier and data, but the PN code and the carrier cannot be synchronized independently.

  In the GPS receiver, the received signal is usually converted to an intermediate frequency within several MHz of the carrier frequency, and the above-described synchronization detection processing is performed on the intermediate frequency signal. For the carrier frequency (intermediate frequency carrier frequency (hereinafter referred to as IF carrier frequency)), the frequency error due to the Doppler shift mainly according to the moving speed of the GPS satellite and the GPS reception when the received signal is converted into the intermediate frequency signal. The frequency error of the local oscillator generated inside the device is included. The frequency error of the local oscillator included in the intermediate frequency signal is hereinafter referred to as an intermediate frequency carrier error (hereinafter referred to as IF carrier error).

Here, if the IF carrier frequency of the received signal is f _IF , the defined IF carrier frequency is F _IF , the GPS satellite Doppler shift is fD, and the IF carrier error is Δf _IF , the IF carrier frequency f _IF is
f _IF = F _IF + fD + Δf _IF (formula a)
It is represented by

  Due to the above frequency error factors, the carrier frequency in the intermediate frequency signal is unknown, and it is necessary to perform a frequency search to synchronize the intermediate frequency carrier (hereinafter referred to as IF carrier). In addition, since the synchronization point (synchronization phase) within one period of the PN code depends on the positional relationship between the GPS receiver and the GPS satellite, it is also unknown. Therefore, as described above, some synchronization method is required. Become.

  If it takes time to synchronize the spread code and the IF carrier, the response of the GPS receiver becomes slow, resulting in inconvenience in use.

  In a conventional GPS receiver, synchronization detection for carriers and spreading codes is performed by sliding correlation with frequency search, and at the same time, synchronization acquisition and synchronization holding operations are performed by DLL (Delay Locked Loop) and Costas loop. Yes. However, synchronization acquisition by sliding correlation and synchronization maintenance by DLL and Costas loop are not suitable for high-speed synchronization acquisition in principle, and the actual GPS receiver shortens the processing until synchronization acquisition by using multiple channels and parallel processing. doing.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2003-258769), a synchronization acquisition unit and a synchronization holding unit are divided, the synchronization acquisition unit is configured using a matched filter, and the synchronization holding unit uses a DLL and a Costas loop. It has also been proposed that the synchronization acquisition and synchronization maintenance can be performed at high speed by configuring the above.

The above-mentioned patent documents are as follows.
JP 2003-258769 A

  When the GPS signal captured by the GPS receiver is strong, the carrier frequency of the GPS signal is successfully pulled and followed by the Costas loop. However, in situations such as when moving between buildings by a car, where the radio wave from the satellite randomly becomes stronger or weaker, the carrier frequency can be pulled in and followed up. It becomes difficult, and the oscillation frequency of the variable frequency oscillator of the Costas loop may shift to a frequency that cannot be redrawn.

  Thus, in order to prevent the oscillation frequency from shifting to a frequency that cannot be redrawn, a limiter is provided in the variable range of the oscillation frequency of the variable frequency oscillator of the Costas loop, and the oscillation frequency of the variable frequency oscillator is not redrawn. It is effective to prevent the frequency from becoming impossible.

  That is, with respect to the output oscillation frequency of the variable frequency oscillator, an upper limit frequency and a lower limit frequency are provided around the center frequency of the variable frequency oscillator, and the output oscillation frequency has an upper limit frequency or a lower limit frequency. It is controlled not to exceed. If the frequency control signal for the variable frequency oscillator indicates a frequency in the range exceeding the upper limit frequency or the lower limit frequency, the variable frequency oscillator is fixed at the upper limit frequency or the lower limit frequency, respectively. It is.

  In this way, even if the radio wave from the GPS satellite temporarily weakens and the oscillation frequency of the variable frequency oscillator of the Costas loop greatly deviates, the radio wave from the GPS satellite becomes strong. Sometimes the oscillation frequency of the variable frequency oscillator is easily re-incorporated into the GPS signal.

  However, in this case, when the variable frequency range of the Costas loop variable frequency oscillator set by the limiter, that is, the limiter range is constant, the following problem occurs.

  In other words, if the limiter range of the set variable frequency is too narrow, if the carrier frequency of the satellite that is trying to acquire synchronization is out of the limiter range when the GPS signal is acquired from the satellite, it will no longer be However, there is a problem that the GPS signal cannot be synchronously captured even if the signal strength is strong.

  In addition, if the limiter range of the set variable frequency is too wide, after the oscillation frequency of the Costas loop variable frequency oscillator has shifted to the full limiter range, the GPS signal strength is weak, so that redrawing cannot occur. However, there is a problem that the DLL cannot be kept synchronized.

  In view of the above points, the present invention facilitates the pull-in from a wide frequency range, and once the pull-in is completed, even if the radio wave from the captured satellite becomes weak, the Costas loop It is an object of the present invention to provide a GPS receiving apparatus and method capable of maintaining the pull-in state.

In order to solve the above problem, the GPS receiver of the invention of claim 1
A frequency conversion means for converting a carrier frequency of a received signal from an artificial satellite that is spread spectrum modulated by a PN code into an intermediate frequency and outputting an intermediate frequency signal;
PN code generating means for generating a receiving device side PN code corresponding to the PN code of the received signal from the artificial satellite;
A first variable frequency oscillator is provided, and the intermediate frequency signal is subjected to inverse spread spectrum using the PN code on the receiving device side, and an output signal of the first variable frequency oscillator and the inverse spread spectrum intermediate frequency signal are obtained. The first control signal based on the comparison result is supplied to the first variable frequency oscillator, and a signal synchronized with the intermediate frequency signal is obtained as an output signal of the first variable frequency oscillator. A first loop circuit;
A second variable frequency oscillator for generating a clock signal for controlling the generation frequency and generation phase of the PN code from the PN code generation means, and the intermediate frequency signal is despread by the PN code on the receiver side Performing a comparison between the output signal of the first variable frequency oscillator and the inverse spectrum spread intermediate frequency signal, and supplying a second control signal based on the comparison result to the second variable frequency oscillator; A second loop circuit for causing the receiver side PN code to synchronize with the PN code of the received signal from the artificial satellite;
In the first loop circuit, when the signal from the artificial satellite is captured with the loop gain increased, the oscillation frequency range of the first variable frequency oscillator is widened and the loop gain is decreased. Control means for controlling to narrow the oscillation frequency range of the first variable frequency oscillator at the time of holding synchronization;
It is characterized by providing.

  In the invention of claim 1 having the above-described configuration, the oscillation frequency range of the first variable frequency oscillator is set at the time of synchronization acquisition when the loop gain of the first loop circuit (for example, Costas loop) is increased by the control means. Since it is widened, the GPS signal can be drawn from the wide frequency range at the time of synchronization acquisition where the exact frequency is unknown.

  Further, at the time of synchronization holding in which the loop gain of the first loop circuit (for example, Costas loop) is lowered, the control means narrows the oscillation frequency range of the first variable frequency oscillator. The frequency of the first variable frequency oscillator is controlled in a narrow frequency range around the correct frequency, and stable synchronization can be maintained.

The invention of claim 2 is the GPS receiver of claim 1,
Correlation detecting means for calculating a correlation value indicating a degree of correlation between the output signal of the first variable frequency oscillator and the intermediate frequency signal based on the comparison result of the first loop circuit;
The control means variably controls the oscillation frequency range of the first variable frequency oscillator according to the correlation value from the correlation detection means during the synchronization holding.

  According to the second aspect of the present invention, the limiter is applied so that the variable range of the oscillation frequency of the first variable frequency oscillator falls within a narrow frequency range at the time of maintaining the synchronization. However, the limiter range is not fixed and is correlated. Variable control is performed according to the correlation value from the detection means. Accordingly, when the correlation is strong, the limiter range can be controlled to be wider, and when the correlation is weak, the limiter range can be controlled to be narrower.

The invention of claim 3 is the GPS receiver according to claim 1,
Correlation detecting means for calculating a correlation value indicating a degree of correlation between the output signal of the first variable frequency oscillator and the intermediate frequency signal based on the comparison result of the first loop circuit;
The control means compares the correlation value from the correlation detection means with a predetermined value at the time of holding the synchronization, and based on the comparison result, the received signal from the artificial satellite is a weak signal. If it is discriminated, the oscillation frequency range of the first variable frequency oscillator is controlled to be further narrowed.

  According to the third aspect of the present invention, even when the synchronization is maintained, when the signal is weak, the limiter range is further narrowed. Even if the GPS signal becomes weak, the first loop circuit can keep the GPS signal in a redrawable state.

  In the GPS receiver, there are situations where the radio waves of the captured satellites are weakened, the radio waves are momentarily interrupted, or affected by noise. According to the present invention, such situations occur. However, since it is possible to immediately return to a good synchronization holding state when a normal radio wave is received, there is a high possibility that the GPS receiver can execute the positioning calculation.

  Also, even if the GPS signal from the satellite becomes weak and the satellite signal cannot be used for positioning calculation temporarily, the frequency pull-in when the GPS signal returns to the normal state from the weak state is completed immediately. Therefore, positioning accuracy does not decrease. Therefore, it is effective in improving the positioning rate and positioning accuracy of the GPS receiver.

  Embodiments of a GPS receiver and a synchronization maintaining method according to the present invention will be described below with reference to the drawings. First, the GPS receiver used in the embodiment of the present invention will be described.

[Configuration of GPS receiver]
The GPS receiver according to the embodiment described below performs synchronization acquisition operation on the carrier and the PN code at the same time by performing the sliding correlation with the conventional frequency search, the DLL (Delay Locked Loop), and the Costas loop. The structure which improved the fault of the method to do is provided.

  That is, in the conventional method of performing synchronization acquisition for the IF carrier and the satellite PN code simultaneously with the sliding correlation accompanied by the frequency search, the DLL and the Costas loop, the sliding correlation associated with the frequency search is performed. As described above, the method is not suitable for high-speed synchronization in principle, and has a drawback that it takes time to synchronize the spreading code (PN code) and the carrier. If it takes time to synchronize the PN code and the carrier in this way, the response of the GPS receiver becomes slow, resulting in inconvenience in use.

  Conventionally, in an actual GPS receiver, in order to improve the above-described drawbacks, it is necessary to search for synchronization points in parallel by increasing the number of channels. Is complicated, and the cost is high, and since the synchronization point is searched in parallel with multiple channels, the power consumption is large. The problem of power consumption is a big problem in the case of a portable GPS receiver.

  Further, in the above-described conventional case, the synchronization acquisition and synchronization maintenance of the PN code and the carrier are integrally performed by the sliding correlation accompanied by the frequency search, the DLL, and the Costas loop. When the above signal is interrupted, it is necessary to perform synchronization acquisition and synchronization holding together again, and there is a problem that time until resynchronization acquisition and synchronization holding becomes long.

  Further, in the above-described conventional case, the synchronization acquisition and the synchronization maintenance of the PN code and the carrier are integrally performed by the sliding correlation accompanied by the frequency search, the DLL, and the Costas loop. When trying to increase the sensitivity, the processing time for capturing and maintaining synchronization becomes longer in principle, and there is a problem that it is not easy to increase the sensitivity of the GPS receiver.

  The GPS receiver used in this embodiment is configured to solve the above problems, and the basic configuration is the same as that described in Patent Document 1.

[Overall Configuration of GPS Receiver of Embodiment]
FIG. 1 is a block diagram showing a configuration example of the GPS receiver of this embodiment. The frequency converter 10, the synchronization acquisition unit 20, the synchronization holding unit 30, the control unit 40, the GPS antenna 1, and the temperature A reference oscillation circuit 2 composed of a crystal oscillation circuit with compensation, a timing signal generation circuit 3, and a crystal oscillation circuit 4 are provided.

  The control unit 40 has a program ROM (Read Only Memory) 42, a work area RAM (Random Access Memory) 43, and a real time (RTC (Real Time Clock)) for a CPU (Central Processing Unit) 41. A clock circuit 44 for measuring, a timer 45, and a nonvolatile memory 46 are connected to each other.

The timer 45 is used for generating various timing signals necessary for the operation of each unit and for referring to the time. The non-volatile memory 46 stores orbit information composed of almanac information and ephemeris information extracted from GPS satellite signals, as well as GPS receiver position information and IF carrier error obtained when the power is turned on before the power is turned off. Δf _IF is stored. The ephemeris information is updated with respect to the nonvolatile memory 46, for example, every two hours, as will be described later, and the almanac information is updated, for example, every few days when the GPS receiver is updated. The nonvolatile memory 46 may be a battery-backed RAM.

  The reference clock signal from the reference oscillation circuit 2 is supplied to the multiplication / frequency division circuit 3 and also to a frequency conversion local oscillation circuit 15 of the frequency conversion unit 10 as described later. The multiplier / divider circuit 3 multiplies and divides the reference clock signal to generate a clock signal to be supplied to the synchronization acquisition unit 20, the synchronization holding unit 30, the control unit 40, and the like. The multiplication / division circuit 3 is controlled by the CPU 41 of the control unit 40 for the multiplication ratio and the division ratio.

  The clock signal from the crystal oscillation circuit 4 is for the clock circuit 44 of the control unit 40. A clock signal of a part other than the clock circuit 44 of the control unit 40 is a clock signal from the multiplication / frequency division circuit 3.

[Configuration of Frequency Conversion Unit 10]
As described above, the GPS satellite signal is a signal transmitted from each GPS satellite, and transmission data of 50 bps is determined for each GPS satellite with a transmission signal speed of 1.023 MHz and a code length of 1023. A carrier (carrier wave) having a frequency of 1575.42 MHz is BPSK-modulated with a signal spread by a satellite PN code (C / A code) having a predetermined pattern.

  A GPS satellite signal of 1575.42 MHz received by the antenna 1 is supplied to the frequency converter 10. In the frequency converter 10, the GPS satellite signal received by the antenna 1 is amplified by the low noise amplifier circuit 11, and then supplied to the bandpass filter 12 to remove unnecessary band components. The signal from the band pass filter 12 is supplied to the intermediate frequency conversion circuit 14 through the high frequency amplifier circuit 13.

  The output of the reference oscillation circuit 2 is supplied to a local oscillation circuit 15 of a PLL (Phase Locked Loop) synthesizer system, and the local oscillation whose frequency ratio is fixed to the output frequency of the reference oscillator 2 from the local oscillation circuit 15 Output is obtained. Then, the local oscillation output is supplied to the intermediate frequency conversion circuit 14, and the carrier frequency of the GPS satellite signal is low-frequency converted to an intermediate frequency that is easy to process, for example, 1.023 MHz. An intermediate frequency signal is obtained. Hereinafter, the carrier of the intermediate frequency signal, that is, the intermediate frequency carrier is referred to as an IF carrier.

  The intermediate frequency signal from the intermediate frequency conversion circuit 14 is amplified by the amplification circuit 16, band-limited by the low-pass filter 17, and then a 1-bit digital signal (hereinafter referred to as IF data) by the A / D converter 18. ). This IF data is supplied to the synchronization capturing unit 20 and the synchronization holding unit 30.

  That is, in this embodiment, the IF data is not supplied to a conventional synchronization acquisition / synchronization holding integrated circuit such as a sliding correlation and Costas loop + DLL, but a functionally separated synchronization acquisition unit 20; It is supplied to the synchronization holding unit 30.

  In this embodiment, the synchronization acquisition unit 20 performs synchronization acquisition on a GPS satellite signal, that is, detects the phase of the satellite PN code of the GPS satellite signal and the frequency of the IF carrier. This IF carrier frequency is hereinafter referred to as IF carrier frequency. The synchronization holding unit 30 performs synchronization holding of the satellite PN code of the GPS satellite signal captured by the synchronization capturing unit 20 and the IF carrier.

[Configuration of Synchronization Capturing Unit 20 and Synchronization Holding Unit 30]
In this embodiment, as will be described later, the synchronization acquisition unit 20 captures a predetermined amount of IF data from the frequency conversion unit 10 in a memory, and the IF data captured in the memory is combined with the satellite PN code of the GPS satellite signal. Then, the correlation calculation with the replica PN code of the GPS receiver corresponding to the satellite PN code of each GPS satellite is performed, and the phase synchronization acquisition of the spread code is performed.

  With respect to the phase synchronization acquisition of the spread code, there is a method using a matched filter as a method of performing high-speed acquisition of the spread spectrum signal without using the above-described sliding correlation technique.

  The matched filter can be digitally realized by a transversal filter. In recent years, spreading code synchronization has been achieved by a digital matched filter using fast Fourier transform (hereinafter referred to as FFT (Fast Fourier Transform)) processing due to improvements in hardware capabilities typified by DSP (Digital Signal Processor). Has been realized at high speed. However, the digital matched filter itself does not have a function of maintaining the synchronization of the spread code.

  The latter method using FFT processing is based on a correlation calculation speed-up method that has been known for a long time. When there is a correlation between the replica PN code on the receiver side and the satellite PN code, the correlation peak is obtained. Is detected, and the peak position is the leading phase of the satellite PN code. Therefore, by detecting this correlation peak, the synchronization of the satellite PN code can be captured, that is, the phase of the satellite PN code in the received signal of the GPS satellite can be detected.

  The carrier (intermediate frequency) of the received signal from the GPS satellite can be detected together with the phase of the satellite PN code by an operation in the FFT frequency domain by a method using FFT. The phase of the satellite PN code is converted into a pseudorange, and if it is detected for four or more satellites, the position of the GPS receiver can be calculated. Further, when the carrier frequency is detected, the Doppler shift amount is known, and thereby the speed of the GPS receiver can be calculated.

  From the above, in this embodiment, the correlation calculation is performed on the PN code by the digital matched filter using the fast Fourier transform (hereinafter referred to as FFT (Fast Fourier Transform)) process, and the synchronization acquisition process is performed based on the correlation calculation. Is performed at high speed.

  The GPS satellite signal received by the antenna 1 includes signals from a plurality of GPS satellites, but the synchronization acquisition unit 20 prepares information on replica PN codes for all GPS satellites. By using the information of the prepared replica PN code and calculating the correlation with the satellite PN code of the plurality of GPS satellite signals that can be used by the GPS receiver at that time, the plurality of GPS satellite signals It is possible to acquire synchronization.

  The synchronization acquisition unit 20 detects which of the GPS satellites has acquired the synchronization, depending on which GPS satellite replica PN code information is used for the synchronization acquisition. For example, a GPS satellite number is used as the identifier of the GPS satellite that has been acquired by synchronization.

  Then, the synchronization acquisition unit 20 includes information on the satellite number of the GPS satellite acquired by synchronization acquisition, information on the phase of the satellite PN code detected by synchronization acquisition, information on the IF carrier frequency, and, if necessary, correlation. The signal strength information including the correlation detection signal indicating the degree is passed to the synchronization holding unit 30.

  As a method of passing the satellite number, the phase of the satellite PN code, the IF carrier frequency, and the signal strength information detected by the synchronization acquisition unit 20 to the synchronization holding unit 30, after determining the data format, the interrupt method, etc. There are a method of passing directly from the synchronization capturing unit 20 to the synchronization holding unit 30 and a method of passing through the control unit 40.

  In the former case, the synchronization acquisition unit 20 generates information to be passed to the synchronization holding unit 30. Or the control part comprised by DSP is provided in the synchronous holding | maintenance part 30, for example, It is set as the structure which produces | generates required information in the synchronous holding | maintenance part 30 based on the information from the synchronous acquisition part 20 with the control part.

  In the latter case, the CPU 41 of the control unit 40 can control and exchange information via the CPU 41, and the CPU 41 can control the synchronization acquisition unit 20 and the synchronization holding unit 30. It becomes easy to set various phase synchronization procedures according to the phase correction of the code and the situation of the synchronization acquisition unit 20 and the synchronization holding unit 30.

  Therefore, in the embodiment described below, as a method of passing the information of the satellite number, the phase of the satellite PN code, the IF carrier frequency, and the signal strength from the synchronization acquisition unit 20 to the synchronization holding unit 30, the control unit 40 is used. Is adopted.

  Since the configuration of the synchronization capturing unit 20 is described in detail in Patent Document 1, the description thereof is omitted in this specification.

  If the synchronization acquisition unit 20 can acquire signals from four or more GPS satellites, the GPS receiver can calculate the position and velocity of the GPS receiver from the phase of the PN code and the IF carrier frequency. Is possible. That is, positioning calculation can be performed without providing the synchronization holding unit 30.

  However, in order to perform sufficiently accurate positioning and velocity calculation as a GPS receiver, it is necessary to detect the phase of the PN code and the IF carrier frequency with high accuracy. For this purpose, sampling is performed when performing FFT calculation. It is necessary to increase the sampling frequency in the circuit and to increase the time length of IF data taken into the buffer memory as a unit of FFT processing.

  Furthermore, when the digital acquisition filter 20 is configured to use a digital matched filter, it must be considered that the digital matched filter itself does not have a synchronization holding function.

  As described above, if the GPS receiver position calculation and speed calculation are performed with sufficient accuracy using only the synchronization acquisition unit 20, the cost increases due to the increase in hardware size and the power consumption increases. It becomes a big problem at the time of manufacturing.

  Therefore, in this embodiment, the synchronization acquisition with coarse accuracy is performed by the dedicated synchronization acquisition unit 20, and synchronization synchronization of a plurality of GPS satellite signals and navigation message demodulation are performed by the synchronization retention unit 30. Then, the synchronization acquisition unit 20 transmits the detected GPS satellite number, the phase of the satellite PN code, the IF carrier frequency, and the signal strength information including the correlation detection signal to the synchronization holding unit 30 through the control unit 40 as data. As will be described later, the synchronization holding unit 30 starts the operation using the data as an initial value.

[Configuration of Synchronization Holding Unit 30]
In order to perform synchronization holding of a plurality of GPS satellite signals in parallel, the synchronization holding unit 30 includes a plurality of channels with each GPS satellite signal as one channel.

  FIG. 2 shows a configuration example of the synchronization holding unit 30 in this embodiment. The synchronization holding unit 30 includes channel synchronization holding units 30CH1, 30CH2,..., 30CHn for n channels and a control register 33. Each of the channel synchronization holding units 30CH1, 30CH2,..., 30CHn includes a Costas loop 31 and a DLL (Delay Locked Loop) 32.

  The control register 33 is connected to the CPU 41 of the control unit 40. As will be described later, the control register 33 receives loop filter parameters of the Costas loop 31 and DLL 32 and data for determining the filter characteristics. The data is set in the part indicated by. The control register 33 receives correlation value information and frequency information from the Costas loop 31 and the loop filter of the DLL 32, and passes the information to the CPU 41 in response to access from the CPU 41.

[Configuration of Costas Loop 31 and DLL 32]
FIG. 3 is a block diagram illustrating a configuration example of the Costas loop 31, and FIG. 4 is a block diagram illustrating a configuration example of the DLL 32.

  The Costas loop 31 is a part that maintains IF carrier frequency synchronization and extracts a navigation message that is transmission data, and the DLL 32 is a part that maintains phase synchronization of the satellite PN code of the GPS satellite signal. Then, the Costas loop 31 and the DLL 32 cooperate to perform spectrum despreading on the GPS satellite signal to obtain a signal before spread spectrum, and to demodulate the signal before spread spectrum to obtain a navigation message for control. To the CPU 41 of the unit 40. Hereinafter, the configuration and operation of the Costas loop 31 and the DLL 32 will be specifically described.

[About Costas Loop 31]
The IF data from the frequency conversion unit 10 is supplied to the multiplier 201. The multiplier 201 is supplied with the replica PN code from the DLL 32 PN code generator 220 shown in FIG.

  From the PN code generation unit 220 of the DLL 32, three-phase replica PN codes, a coincidence (prompt) PN code P, an advance (Early) PN code E, and a delay (rate) PN code L, are generated. As will be described later, the DLL 32 calculates the correlation between the advanced PN code E and the delayed PN code L and IF data, and generates a replica PN code from the PN code generator 220 so that the respective correlation values are equal. The phase is controlled so that the phase of the coincident PN code P coincides with the phase of the satellite PN code of the GPS satellite signal.

  The coincidence PN code P from the PN code generator 220 is supplied to the despreading multiplier 101 of the Costas loop 31 and despread. The despread IF data from the multiplier 101 is supplied to the multipliers 102 and 103.

  As shown in FIG. 3, the Costas loop 31 includes multipliers 102 and 103, low-pass filters 104 and 105, a phase detector 106, a loop filter 107, and an NCO (Numerally Controlled Oscillator) as an example of a variable frequency oscillator; (Numerically controlled oscillator) 108, correlation detector 109, binarization circuit 110, PN code lock determination unit 111, switch circuit 112, and IF carrier lock determination unit 113.

  The variable range of the oscillation frequency of the NCO 108 is controlled by the CPU 41 of the control unit 40. In other words, the CPU 41 applies a limiter to the variable range of the oscillation frequency of the NCO 108. In this embodiment, the limiter range is applied to the loop gain of the Costas loop 31 and the signal strength of the GPS signal, as will be described later. Accordingly, it is variably controlled.

  The switch circuit 112 is for opening and closing the loop of the Costas loop 31 and is turned on / off by a switching control signal from the CPU 41. In an initial state before the start of the synchronization holding operation, the switch circuit 112 is turned off and the loop is opened. As described later, the synchronization holding operation starts and the Costas loop correlation detector 109 is started. The switch circuit 112 is turned on to close the loop when the correlation output of is higher than a significant correlation level.

  Further, even during the synchronization holding operation, when the radio wave from the satellite that has acquired and held synchronization becomes weak and it becomes difficult to follow the carrier frequency in the Costas loop 31, the correlation of the correlation detector 109 is detected. Since the output is smaller than the significant correlation level, the switch circuit 112 is turned off and the loop is opened.

  The cutoff frequency information of the low-pass filters 104 and 105, the parameters that determine the filter characteristics of the loop filter 107, and the frequency information that determines the oscillation center frequency of the NCO 108 are synchronized with the synchronization capturing unit 20 as described later. Based on the result, it is set from the CPU 41 through the control register 33.

  Further, the CPU 41 controls the cut-off frequency information of the low-pass filters 104 and 105 and the parameters that determine the filter characteristics of the loop filter 107 in accordance with the limiter control for the oscillation frequency range of the NC 0108, and the oscillation frequency band of the NCO 108. Controlled to fit the width.

  The signal despread in the multiplier 101 is supplied to the multipliers 102 and 103. These multipliers 102 and 103 are supplied with the quadrature phase I (Cosine) signal and Q (Sine) signal from the NCO 108 which are substantially set to the IF carrier frequency based on the frequency information from the CPU 41 of the control unit 40. The Here, the system of the multiplier 102 to which the I signal is supplied is referred to as an I arm, and the system of the multiplier 103 to which the Q signal is supplied is referred to as a Q arm. The same applies to the DLL 32 described later.

  The multiplication results of the multipliers 102 and 103 are supplied to the phase detector 106 through the low-pass filters 104 and 105. The low-pass filters 104 and 105 receive cut-off frequency information from the CPU 41 of the control unit 40, and remove out-of-band noise from signals supplied thereto.

  The phase detector 106 detects a phase error between the IF carrier and the frequency signal from the NCO 108 based on the signals from the low-pass filters 104 and 105, and supplies this phase error to the NCO 108 via the loop filter 107. As a result, the NCO 108 is controlled so that the phase of the output frequency signal from the NCO 108 is synchronized with the IF carrier component.

  The loop filter 107 integrates the phase error information from the phase detector 106 according to the parameter supplied from the CPU 41 of the control unit 40 to form an NCO control signal for controlling the NCO 108. As described above, the NCO 108 synchronizes the phase of the output frequency signal from the NCO 108 with the IF carrier component by the NCO control signal from the loop filter 107.

  The outputs of the low pass filters 104 and 105 of the Costas loop 31 are supplied to the correlation detector 109. Correlation detector 109 squares the output signals of low-pass filters 104 and 105 supplied thereto, adds them, and outputs the result. The output of the correlation detector 109 indicates the correlation value CV (P) between the IF data and the matched PN code P from the PN code generator 220. This correlation value CV (P) is passed to the CPU 41 of the control unit 40 through the control register 33.

  The output signal of the low-pass filter 104 is supplied to the binarization circuit 110, and navigation message data is output from the binarization circuit 110.

  Further, the correlation value CV (P) output from the correlation detector 109 is supplied to the PN code lock determination unit 111. The PN code lock determination unit 111 compares the correlation value CV (P) output with a predetermined threshold value. When the correlation value CV (P) output is greater than the threshold value, the PN code lock determination unit 111 maintains synchronization. Is in the locked state, and when the correlation value CV (P) output is smaller than the threshold value, a PN code lock determination output indicating that the synchronization hold is in the unlocked state is output.

  In this embodiment, the PN code lock determination output is sent to the CPU 41 of the control unit 40, and the CPU 41 recognizes the lock state and unlock state of the PN code in the synchronization holding unit 30 from the PN code lock determination output. To. From this PN code lock determination output, the CPU 41 determines only that PN code synchronization is maintained. Therefore, the CPU 41 does not detect the state in which the IF carrier is unlocked from the PN code lock determination output, although the PN code is synchronized. The CPU 41 determines from the output of the IF carrier lock determination unit 113 whether or not the IF carrier frequency lock is released.

  The outputs of the low pass filters 104 and 105 are supplied to the IF carrier lock determination unit 113. This IF carrier lock determination unit 113 obtains the ratio of the absolute values of the outputs of the low-pass filters 104 and 105, and when the value of the ratio is equal to or greater than a predetermined threshold value, the synchronization of the IF carrier is locked. If not, an IF carrier lock determination output indicating that the IF carrier is out of synchronization (unlocked state) is output.

That is, the IF carrier lock determination output is obtained when the output of the low-pass filter 104 is Io, the output of the low-pass filter 105 is Qo, and the threshold value is th.
| Io | / | Qo |> th
If it is, it indicates a locked state, otherwise it indicates an unlocked state.

  In this embodiment, this IF carrier lock determination output is sent to the CPU 41 of the control unit 40. The CPU 41 recognizes the locked state and unlocked state of the IF carrier from the IF carrier lock determination output.

[About DLL32]
As shown in FIG. 4, in the DLL 32, the IF data from the frequency conversion unit 10 is supplied to multipliers 201 and 211. The multiplier 201 is supplied with the advance PN code E from the PN code generator 220, and the multiplier 211 is supplied with the delayed PN code L from the PN code generator 220.

  The multiplier 201 performs spectrum despreading by multiplying the IF data and the advance PN code E, and supplies the signals subjected to the despreading to the multipliers 202 and 203. The multiplier 202 is supplied with the I signal from the NCO 108 of the aforementioned Costas loop 31, and the multiplier 203 is supplied with the Q signal from the NCO 108.

  The multiplier 202 multiplies the despread IF data and the I signal from the NCO 108, and supplies the result to the correlation detector 206 through the low-pass filter 204. Similarly, the multiplier 203 multiplies the despread IF data and the Q signal from the NCO 108 and supplies the result to the correlation detector 206 through the low-pass filter 205.

  The low-pass filters 204 and 205 receive the cut-off frequency information from the CPU 41 of the control unit 40 and remove out-of-band noise from the signal supplied thereto, as with the low-pass filters 104 and 105 of the Costas loop 31. To do.

  The correlation detector 206 squares and adds the output signals from the low-pass filters 204 and 205 supplied thereto, and outputs the result. The output from the correlation detector 206 indicates the correlation value CV (E) between the IF data and the advanced PN code E from the PN code generator 220. The correlation value CV (E) is supplied to the phase detector 221 and stored in the control register 33 so that the CPU 41 of the control unit 40 can use it.

  Similarly, the multiplier 211 performs spectrum despreading by multiplying the IF data and the delayed PN code L, and supplies the despread signals to the multipliers 212 and 213. As described above, the multiplier 212 is supplied with the I signal from the NCO 108, and the multiplier 213 is supplied with the Q signal from the NCO 108.

  The multiplier 212 multiplies the despread IF data and the I signal from the NCO 108, and supplies the result to the correlation detector 216 through the low-pass filter 214. Similarly, the multiplier 213 multiplies the despread IF data by the Q signal from the NCO 108 and supplies the result to the correlation detector 216 through the low-pass filter 215. Similarly to the low-pass filters 204 and 205 described above, the low-pass filters 214 and 215 receive cutoff frequency information from the CPU 41 of the control unit 40 and remove out-of-band noise from signals supplied thereto. .

  The correlation detector 216 squares and adds the output signals from the low-pass filters 214 and 215 supplied thereto, and outputs the calculation result. The output from the correlation detector 216 indicates the correlation value CV (L) between the IF data and the delayed PN code L from the PN code generator 220. The correlation value CV (L) is supplied to the phase detector 221 and stored in the control register 33 so that the CPU 41 of the control unit 40 can use it.

  The phase detector 221 calculates the difference between the correlation value CV (E) from the correlation detector 206 and the correlation value CV (L) from the correlation detector 216, and the coincidence PN code P and the satellite PN code of the GPS satellite signal. And a signal corresponding to the phase difference is supplied as a numerical control signal of the NCO 223 via the loop filter 222.

  An output signal of the NCO (Numerally Controlled Oscillator) 223 is supplied to the PN code generator 220, and the output frequency of the NCO 223 is controlled, so that the PN code generator 220 receives the PN code from the PN code generator 220. The code generation frequency and phase are controlled.

  As will be described later, the NCO 223 receives supply of frequency information for controlling the initial oscillation frequency from the CPU 41 of the control unit 40 according to the synchronization acquisition result of the synchronization acquisition unit 20.

  The NCO 223 is controlled by the loop control in the DLL 32 described above, and the PN code generator 220 causes the PN code P, E, L so that the correlation value CV (E) and the correlation value CV (L) are at the same level. Controls the generation phase. As a result, the coincidence PN code P generated from the PN code generator 220 is phase-synchronized with the PN code in which the IF data is spread spectrum. As a result, the IF data is accurately inverted by the coincidence PN code P. The navigation message data is demodulated and output from the binarization circuit 110 in the Costas loop 31.

  The demodulated output of the navigation message data is supplied to a data demodulation circuit (not shown), demodulated into data usable by the control unit 40, and then supplied to the control unit 40. In the control unit 40, the navigation message data is used for positioning calculation, and orbit information (almanac information and ephemeris information) is appropriately extracted and stored in the nonvolatile memory 46.

  Similar to the loop filter 107 of the Costas loop 31 described above, the loop filter 222 of the DLL 32 integrates the phase error information from the phase detector 221 based on the parameters supplied from the CPU 41 of the control unit 40, and An NCO control signal for controlling the NCO 223 is formed.

  Also in the DLL 32, a switch circuit 224 for loop opening / closing control is provided between the loop filter 222 and the NCO 223, and is turned on / off by a switching control signal from the CPU 41.

  In the initial state before the synchronization holding operation is started, the switch circuit 224 is turned off and the loop is opened. As described later, the synchronization holding operation starts and the correlation detector of the Costas loop is started. When the correlation output 109 becomes a significant level, the switch circuit 224 is turned on to close the loop.

[Transition from synchronization acquisition to synchronization maintenance]
In this embodiment, as described above, the synchronization acquisition unit 20 uses the detected GPS satellite number, the phase of the satellite PN code, the IF carrier frequency, and the signal strength information as data as the CPU 41 of the control unit 40. To pass. The signal strength information is not essential as information for shifting to the synchronization holding process.

  Based on the acquired data, the CPU 41 of the control unit 40 generates data to be supplied to the synchronization holding unit 30 and passes it to the synchronization holding unit 30. The synchronization holding unit 30 starts the synchronization holding operation using the data as an initial value.

  Data passed from the CPU 41 of the control unit 40 to the synchronization holding unit 30 is a numerical value for determining the initial oscillation frequency (oscillation center frequency) of the NCO 223 that controls the generation phase of the replica PN code from the PN code generator 220 of the DLL 32. Information, numerical information for determining the initial oscillation frequency (oscillation center frequency) of the NCO 108 of the Costas loop 31, parameters for determining the filter characteristics of the loop filters 107 and 222, low-pass filters 104, 105, 204, This is coefficient information for determining the cut-off frequencies 205, 214, and 215 and determining the width of the frequency band.

  At this time, the information supplied from the CPU 41 to the synchronization holding unit 30 is the initial value for determining the phase and frequency at which the synchronization holding unit 30 starts the synchronization holding of the PN code and the synchronization holding of the IF carrier, and the filter characteristics. Although it is data, the CPU 41 generates the initial value data so as to start the synchronization holding from the vicinity of the phase of the PN code and the IF carrier frequency detected as a result of the synchronization acquisition by the synchronization acquisition unit 20.

  Therefore, the synchronization holding unit 30 can start the synchronization holding operation from the vicinity of the phase of the PN code detected by the synchronization acquisition unit 20 and the vicinity of the detected IF carrier frequency to quickly set the synchronization holding locked state. become able to.

  By the way, in order for the GPS receiver to calculate the position and velocity, it is necessary to establish and hold synchronization for four or more GPS satellites from the start of synchronization acquisition. Example of a process of holding synchronization of signals from four or more GPS satellites by the synchronization acquisition unit 20, the synchronization holding unit 30, and the CPU 41 that controls both (hereinafter, this process is called a synchronization acquisition / synchronization holding process) Will be described next.

[Example of acquisition and synchronization process]
In the example described below, when the synchronization acquisition unit 20 acquires one of the GPS satellite signals in synchronization, the CPU 41 immediately sends an interrupt instruction for starting the synchronization holding operation, the GPS satellite number as the synchronization acquisition result, The signal strength indicating the phase of the satellite PN code, the IF carrier frequency, and the correlation detection level is transferred, and when the transfer is completed, the synchronization acquisition for another GPS satellite is started.

  Each time the CPU 41 receives an interrupt instruction from the synchronization acquisition unit 20, it assigns an independent channel to the synchronization holding unit 30 and sets an initial value so as to start the synchronization holding operation.

  FIG. 5 is a flowchart for explaining the flow of the synchronization acquisition process in the synchronization acquisition unit 20 in the example of the synchronization acquisition / synchronization holding process.

  First, initial setting for acquisition of synchronization is performed (step S11). In this initial setting, the GPS satellites to be searched for synchronization acquisition and the search order are set based on valid orbit information stored in the nonvolatile memory 46 by the GPS receiver. Also, the carrier frequency considering the Doppler shift is calculated from the trajectory information, and the center and range of the IF carrier frequency to be searched are set.

  Also, if the GPS receiver has found out about the oscillator error obtained in the past operation before power-on, the GPS receiver position is stored at the time of power-on, that is, the previous power-off. If the center and range of the IF carrier frequency to be searched are determined in accordance with the Doppler shift calculated from the trajectory information on the assumption that the position is the immediately preceding position, the time required until synchronization can be further reduced.

  When the initial setting is completed, one GPS satellite to be synchronously acquired is set according to the search order (step S12). As a result, the satellite number for synchronization acquisition is determined, and the PN code for which correlation is to be detected is determined.

  Next, the synchronization capturing unit 20 starts capturing sampled IF data, and starts a timer at this start timing (step S13). Here, the timer 45 of the control unit 40 is used as this timer. The timer 45 is also used when setting the synchronization holding process start timing, as will be described later.

  Next, correlation detection processing is performed on the satellite PN code of the GPS satellite signal set in step S12 by the above-described synchronization acquisition processing using the digital matched filter (step S14).

  Then, it is determined whether or not a correlation has been detected for the satellite PN code of the GPS satellite signal, that is, whether or not the GPS satellite signal has been synchronized (step S15). An instruction is generated, and the GPS satellite number, the phase of the satellite PN code, the IF carrier frequency, and the signal strength information are passed to the CPU 41 as a detection result of synchronization acquisition (step S16).

  Then, it is determined whether or not the synchronization acquisition search for all of the GPS satellites to be searched has been completed (step S17). If there are still GPS satellites to be searched, the process returns to step S82 and the next GPS to be acquired synchronously. Set the satellite and repeat the above acquisition process. If it is determined in step S17 that the synchronization acquisition has been completed for all GPS satellites to be searched, the synchronization acquisition operation is ended and the synchronization acquisition unit 20 is set in a standby state (standby state).

  If it is determined in step S15 that the correlation cannot be detected, it is determined whether or not the state has exceeded a predetermined time (step S18). If the predetermined time has not elapsed, the process returns to step S15 to return to the correlation. Continue detection.

  When it is determined in step S18 that the predetermined time has elapsed, the process proceeds to step S17, where it is determined whether or not the synchronization acquisition search for all of the GPS satellites to be searched is completed, and when there are still GPS satellites to be searched. Returning to step S12, the next GPS satellite to be synchronized is set, and the above-described synchronization capturing process is repeated.

  If it is determined in step S17 that the synchronization acquisition has been completed for all GPS satellites to be searched, the synchronization acquisition operation is ended and the synchronization acquisition unit 20 is set in a standby state (standby state).

  In this embodiment, the CPU 41 can perform on / off control of power supply to the synchronization acquisition unit 20 or on / off control of operation clock supply from the multiplication / frequency division circuit 3 to the synchronization acquisition unit 20. In the standby state of the synchronization acquisition unit 20 described above, the CPU 41 turns off the power supply to the synchronization acquisition unit 20 or stops the operation clock supply, thereby suppressing unnecessary power consumption. Yes.

  When the synchronization acquisition unit 20 is configured with a digital matched filter as described above, it is desirable to operate with a high clock in order to speed up the FFT calculation. Therefore, power consumption during operation increases, but the synchronization acquisition unit If the synchronization acquisition detection of the signals from all the GPS satellites that have been initially set is completed and the synchronization holding unit 30 holds four or more synchronizations at 20, the role of the synchronization acquisition unit 20 ends.

  In this embodiment, as described above, the CPU 41 is in a standby state after the end of the role of the synchronization capturing unit 20, so that unnecessary power consumption in the synchronization capturing unit 20 is suppressed.

  In the above example, the CPU 41 shifts the synchronization acquisition unit 20 to the standby state after completing the synchronization acquisition for all the initially set GPS satellites. However, the synchronization holding unit 30 can hold the synchronization. After confirming that the number of GPS satellites is four or more, the CPU 41 may cause the synchronization acquisition unit 20 to shift to a standby state.

  Of course, the CPU 41 can return the synchronization acquisition unit 20 once in the standby state to the operation state when the synchronization acquisition unit 20 needs to be re-synchronized.

  Next, the control processing of the synchronization holding unit 30 by the CPU 41 that has received an interrupt instruction from the synchronization capturing unit 20 will be described with reference to the flowcharts of FIGS. 6, 7, 8, and 9.

  FIG. 6 shows the synchronization holding unit 30 when the CPU 41 receives from the synchronization acquisition unit 20 information on the phase of the satellite PN code, IF carrier frequency, GPS satellite number, and signal strength as an interrupt instruction and synchronization acquisition result. This is a process for assigning channels and starting synchronization holding. FIG. 7 is a flowchart for controlling synchronization holding processing in each channel of the synchronization holding unit 30 that has been started to hold synchronization by the CPU 41. First, the synchronization holding start process of FIG. 6 will be described.

  When the power to the GPS receiver is turned on, the CPU 41 initializes constants to the NCO, low-pass filter, loop filter, etc. of the synchronization holding unit 30 (step S21). At this time, in the Costas loop 31 and the DLL 32, the switch circuits 112 and 224 are turned off, and the initial state of each is the loop open.

  Next, the CPU 41 monitors the interrupt instruction from the synchronization acquisition unit 20 (step S22). When detecting the interrupt instruction, the CPU 41 receives the GPS satellite number, the phase of the satellite PN code, the IF carrier frequency, the signal from the synchronization acquisition unit 20. In addition to receiving the strength information, the synchronization holding unit 30 is set to assign an independent channel to the received GPS satellite number (step S23).

  Then, the CPU 41 calculates the synchronization holding start timing from the phase of the satellite PN code received from the synchronization acquisition unit 20, and supplies the initial value supplied to each part in the allocated channel of the synchronization holding unit 30 to the synchronization acquisition unit. It is generated based on the IF carrier frequency received from 20 (step S24).

  Then, the CPU 41 sends the generated initial value to each part in the channel assigned in step S23 of the synchronization holding unit 30 through the control register 33, and also in the channel assigned in step S23 of the synchronization holding unit 30. The generation phase of the coincidence PN code P from the PN code generator 220 is controlled to be the synchronization holding start timing, and the synchronization holding operation is started (step S25). At this time, the Costas loop 31 and DLL 32 remain open.

  As described above, a channel for holding synchronization is assigned to the GPS satellite signal acquired in synchronization, and when synchronization holding is started, the process returns to step S22 to wait for the next interrupt.

  Next, the synchronization holding process for each channel started as described above will be described with reference to the flowchart of FIG.

  First, the CPU 41 determines whether or not the correlation value CV (P) from the synchronization holding unit 30 has become a significant level (step S31), and when the correlation value CV (P) has become a significant level, the Costas loop 31. Then, the loop of DLL 32 is closed and the synchronization holding operation is performed (step S32).

  Then, the loop gain of the loop filter 107 of the Costas loop 31 is set to the high gain G1. Then, as will be described later, as the loop gain of the loop filter 107 is set to the high gain G1, the CPU 41 controls the variable oscillation frequency limiter range of the NCO 108 of the Costas loop 31 to be a wide range W1. To do. Further, the cut-off frequency of the low-pass filters 104 and 105 and the used frequency band of the loop filter 107 are also controlled by the CPU 41 according to the limiter range of the variable oscillation frequency of the NCO 108 (step S33).

  Next, the CPU 41 monitors the lock determination output from the lock determination unit 111 of the Costas loop 31 of the synchronization holding unit 30 (step S34). Is incremented by 1 (step S35), and the synchronization holding state is continued (step S36). In this synchronized holding continuation state, the CPU 41 changes the setting of the loop gain of the loop filter 107 of the Costas loop 31 to the low gain G2 (G2 <G1) or G3 (G3 <G2 <G1), and the Costas loop The limiter range of the oscillation frequency of 31 NCOs 108 is narrower than the limiter range until the synchronous holding is locked in accordance with the loop gain setting change, as will be described later, W2 (G2 <G1) or W3 (G3 <G2 <G1).

  Then, the CPU 41 monitors the lock determination output from the lock determination unit 111 of the Costas loop 31 (step S37), and when the lock for synchronization holding is confirmed, the CPU 41 returns to step S36 and continues the synchronization holding state. When it is determined in step S37 that the synchronization holding lock has been released, the number of GPS satellites that are held in synchronization is decremented by 1 (step S38), and the processing when the synchronization holding is released is performed (step S38). S39). The description of the processing when the synchronization is lost is omitted.

  When the CPU 41 determines that the synchronization holding unit 30 has held the synchronization of four or more GPS satellite signals, the CPU 41 calculates the position of the GPS receiver and the velocity.

  If it is determined in step S31 that the correlation value CV (P) does not become a significant level, it is determined whether or not the state has exceeded a predetermined time (step S41), and it is determined that the predetermined time has passed. In some cases, the channel of the synchronization holding unit 30 assigned in step S23 of FIG. 6 is returned to an empty channel, and the synchronization holding of the channel is stopped (step S42).

  In step S34, when the lock state cannot be detected by the lock determination output, it is determined whether or not the state has exceeded a predetermined time (step S43). If it is determined that the predetermined time has passed, step S23 is determined. The channel of the synchronization holding unit 30 assigned in step 1 is returned to the empty channel, and the synchronization holding of the channel is stopped (step S42).

  Steps S41, S42 and S43 are provided for the following reason. In other words, even if the correlation detected by the synchronization capturing unit 20 is at a significant level, there may be a false synchronization that occurs accidentally due to noise. The synchronization holding unit 30 does not establish synchronization for a false synchronization that does not persist, such as occurs unexpectedly. Therefore, if synchronization cannot be established within a certain search time by the synchronization holding unit 30, the synchronization holding operation is stopped, the assigned channel is returned to the free channel state, and the next interrupt is waited for. Is.

[Details of processing in step S36]
As described above, in step S36, since the synchronization holding lock has been made, the loop gain of the Costas loop 31 is changed to values G2 and G3 that are lower than the initial value G1. In accordance with the setting change of the loop gain, the limiter range of the oscillation frequency of the NCO 108 of the Costas loop 31 is also controlled to a range W2 (W2 <W1) or W3 (W3 <W2 <W1) narrower than the initial setting value W1. To do.

  FIG. 8 is a process for setting and changing the loop gain of the Costas loop 31 in the synchronization holding lock state. In this example, this process is a process for determining the bit edge of the trajectory data obtained from the binarization circuit 110. Has been.

  The CPU 41 first determines whether or not a bit edge has been determined for the output data of the binarization circuit 110 (step S51). If it is confirmed, this routine is directly exited. When it is determined in step S51 that the edge of the bit is not fixed, the CPU 41 determines the edge of the bit from the switching of the correlation value in units of 1 millisecond, which is the chip period of the PN code (step S52). ).

  Next, the CPU 41 determines whether or not the bit edge has been confirmed for the output data of the binarization circuit 110 by the process of step S52 (step S53). The gain is set to a gain G2 lower than the initial value G1 (step S54).

  When it is determined in step S53 that the bit edge cannot be determined for the output data of the binarization circuit 110, the CPU 41 determines whether or not the bit edge cannot be determined because the GPS signal is weak. A determination is made (step S55). This determination is performed based on the correlation value CV (P) from the correlation detector 109.

  If it is determined in step S55 that the GPS signal is weak and the bit edge cannot be determined, the CPU 41 exits this processing routine as it is. If it is determined in step S55 that the GPS signal is weak and the bit edge cannot be determined, the CPU 41 determines whether a predetermined time, for example, 500 milliseconds has elapsed since the activation of the synchronization holding circuit 30. It is determined whether or not (step S56).

  When it is determined in step S56 that 500 milliseconds have not elapsed, the CPU 41 causes the process routine to be left as it is. When it is determined in step S56 that 500 milliseconds have elapsed, the CPU 41 controls the gain of the loop filter 107 of the Costas loop 31 to be set to a gain G3 that is lower than the gain G2 (step S57). ). Then, the process routine is exited.

  Next, control of the limiter range of the NCO 108 of the Costas loop 31 performed in parallel with the processing of FIG. 8 will be described with reference to FIG.

  That is, the CPU 41 determines whether or not the gain of the loop filter 107 is a high gain G1 within a predetermined time from the activation of the synchronization holding circuit 30 (step S61).

  When it is determined in this step S61 that the gain of the loop filter 107 is the high gain G1, the CPU 41 compares the limiter range of the oscillation frequency of the NCO 108 of the Costas loop 31 as shown in FIG. A wide W1 is set (step S62). That is, the limiter range of the oscillation frequency of the NCO 107 of the Costas loop 31 is set to a range of ± a (a is a fixed value) with respect to the average value (corresponding to the center frequency) of the oscillation frequency. Thereafter, the process routine is exited.

  If it is determined in step S61 that the gain of the loop filter 107 is not G1, the correlation value CV (P) from the correlation detector 109 is equal to or greater than a predetermined value, and the GPS signal carrier and the GPS receiver It is determined whether or not there is a correlation with the oscillation frequency of the NCO 108 of the Costas loop (step S63).

  If it is determined in step S63 that there is a correlation, the CPU 41 sets the limiter range of the oscillation frequency of the NCO 108 of the Costas loop 31 to W2 narrower than W1 as shown in FIG. 10 (step S64). This limiter range is a range of ± b × correlation value CV (P) with respect to the average value of the oscillation frequency of the NCO 108. That is, the limiter range of the oscillation frequency of the NCO 108 of the Costas loop 31 is variably controlled according to the correlation value CV (P). Thereafter, the process routine is exited.

  If it is determined in step S63 that there is no correlation, the CPU 41 sets the limiter range of the oscillation frequency of the NCO 108 of the Costas loop 31 to W3 narrower than W2 as shown in FIG. 10 (step S65). That is, the limiter range of the oscillation frequency of the NCO 107 of the Costas loop 31 is set to a range of ± c (c is a fixed value) with respect to the average value (corresponding to the center frequency) of the oscillation frequency. Thereafter, the process routine is exited.

  As described above, by setting the limiter range of the oscillation frequency of the NCO 108, immediately after the synchronization holding start instruction from the synchronization acquisition circuit 20, the limiter range is wide and the loop gain for the NCO 108 is high. You can expect to lock into the state easily.

  In addition, when the GPS signal strength is weakened, the limiter range is narrowed and the loop gain is low, so that redrawing is easy.

[Modification]
Note that the present invention is not limited to the GPS receiver configured to be divided into the synchronization acquisition unit and the synchronization holding unit as in the above-described example, and the carrier and spreading are performed by the sliding correlation with the frequency search described as the conventional example. The present invention can also be applied to a GPS receiver that performs synchronization acquisition and synchronization holding operation by means of DLL and Costas loop at the same time as detecting synchronization for codes.

  In that case, at the time of synchronization acquisition, the loop gain of the Costas loop is increased to, for example, G1, and the limiter range of the oscillation frequency of the NCO 108 is increased to, for example, W1. For example, the limit range of the oscillation frequency of the NCO 108 may be narrowed as in W2 and W3, for example, as G2 and G3.

It is a block diagram which shows the structural example of embodiment of the GPS receiver by this invention. It is a block diagram which shows the structural example of the synchronous holding | maintenance part which is a part of FIG. It is a block diagram which shows the structural example of the Costas loop which comprises a part of synchronization holding | maintenance part of FIG. It is a block diagram which shows the structural example of DLL which comprises a part of synchronization holding | maintenance part of FIG. It is a flowchart for demonstrating the flow of an example of a synchronous acquisition process. It is a flowchart for demonstrating the flow of a synchronous holding | maintenance start process. It is a flowchart for demonstrating the flow of a synchronization holding process for every channel. It is a flowchart for demonstrating the detailed process example of the process performed in the one part step of FIG. It is a flowchart for demonstrating the detailed process example of the process performed in the one part step of FIG. It is a figure used for description of the process performed in the one part step of FIG. It is a figure which shows the structure of the signal from a GPS satellite.

Explanation of symbols

31 ... Costas loop, 32 ... DLL, 40 ... control unit, 41 ... CPU of control unit 40, 107 ... loop filter, 108 and 223 ... NCO, 109 ... correlation detector,

Claims (4)

A frequency conversion means for converting a carrier frequency of a received signal from an artificial satellite that is spread spectrum modulated by a PN code into an intermediate frequency and outputting an intermediate frequency signal;
PN code generating means for generating a receiving device side PN code corresponding to the PN code of the received signal from the artificial satellite;
A first variable frequency oscillator is provided, and the intermediate frequency signal is subjected to inverse spread spectrum using the PN code on the receiving device side, and an output signal of the first variable frequency oscillator and the inverse spread spectrum intermediate frequency signal are obtained. The first control signal based on the comparison result is supplied to the first variable frequency oscillator, and a signal synchronized with the intermediate frequency signal is obtained as an output signal of the first variable frequency oscillator. A first loop circuit;
A second variable frequency oscillator for generating a clock signal for controlling the generation frequency and generation phase of the PN code from the PN code generation means, and the intermediate frequency signal is despread by the PN code on the receiver side Performing a comparison between the output signal of the first variable frequency oscillator and the inverse spectrum spread intermediate frequency signal, and supplying a second control signal based on the comparison result to the second variable frequency oscillator; A second loop circuit for causing the receiver side PN code to synchronize with the PN code of the received signal from the artificial satellite;
In the first loop circuit, when the loop gain is increased and the signal from the artificial satellite is captured synchronously, the oscillation frequency range of the first variable frequency oscillator is widened and the loop gain is decreased. Control means for controlling the oscillation frequency range of the first variable frequency oscillator to be narrowed when the synchronization is maintained;
A GPS receiving device comprising: The GPS receiver according to claim 1,
Correlation detecting means for calculating a correlation value indicating a degree of correlation between the output signal of the first variable frequency oscillator and the intermediate frequency signal based on the comparison result of the first loop circuit;
The GPS receiver according to claim 1, wherein the control means variably controls the oscillation frequency range of the first variable frequency oscillator in accordance with a correlation value from the correlation detection means when the synchronization is maintained. The GPS receiver according to claim 1,
Correlation detecting means for calculating a correlation value indicating a degree of correlation between the output signal of the first variable frequency oscillator and the intermediate frequency signal based on the comparison result of the first loop circuit;
The control means compares the correlation value from the correlation detection means with a predetermined value at the time of holding the synchronization, and based on the comparison result, the received signal from the artificial satellite is a weak signal. When it is determined, the GPS receiver is controlled to further narrow the oscillation frequency range of the first variable frequency oscillator. A frequency conversion means for converting a carrier frequency of a received signal from an artificial satellite that is spread spectrum modulated by a PN code into an intermediate frequency and outputting an intermediate frequency signal;
PN code generating means for generating a receiving device side PN code corresponding to the PN code of the received signal from the artificial satellite;
A first variable frequency oscillator is provided, and the intermediate frequency signal is subjected to inverse spread spectrum using the PN code on the receiving device side, and an output signal of the first variable frequency oscillator and the inverse spread spectrum intermediate frequency signal are obtained. The first control signal based on the comparison result is supplied to the first variable frequency oscillator, and a signal synchronized with the intermediate frequency signal is obtained as an output signal of the first variable frequency oscillator. A first loop circuit;
A second variable frequency oscillator for generating a clock signal for controlling the generation frequency and generation phase of the PN code from the PN code generation means, and the intermediate frequency signal is despread by the PN code on the receiver side Performing a comparison between the output signal of the first variable frequency oscillator and the inverse spectrum spread intermediate frequency signal, and supplying a second control signal based on the comparison result to the second variable frequency oscillator; A second loop circuit for causing the receiver side PN code to synchronize with the PN code of the received signal from the artificial satellite;
A synchronization holding method in a GPS receiver comprising:
In the first loop circuit, when the loop gain is increased and the signal from the artificial satellite is captured synchronously, the oscillation frequency range of the first variable frequency oscillator is widened and the loop gain is decreased. A synchronization holding method in a GPS receiver, comprising: a step of controlling the first variable frequency oscillator to narrow an oscillation frequency range when holding the synchronization.

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