JP4108939B2 - Orthogonal frequency division multiplexed signal receiver - Google Patents

Description

【００５４】
クロック信号の位相誤差を検出することは，式（１）において係数ｓを求めることによって実現できる。
【００５５】
まずデータ送信用副搬送波成分抽出部５００において、フーリエ変換部４の出力信号から、データを送信している副搬送波成分を抽出して出力する。例えばＡ／Ｄ変換部１に入力される第ｉ番目のシンボルｒ_iについて、フーリエ変換部４から副搬送波成分ｘ_i,0，ｘ_i,1，…，ｘ_i,N-1が得られる。但し、副搬送波成分ｘ_i,k+1の周波数は、副搬送波成分ｘ_i,kの周波数よりも周波数間隔ｆ₀だけ高い。
【００５６】
例えば副搬送波成分ｘ_i,0，ｘ_i,1，…，ｘ_i,N-1は、この順にフーリエ変換部４から出力される。これらの中からデータ送信用副搬送波の成分のみが抽出されて、隣接データ送信用副搬送波成分分離部５０１に与えられる。隣接データ送信用副搬送波成分分離部５０１は、データ送信用副搬送波成分抽出部５００の出力を入力し、周波数が異なって対をなす副搬送波成分として、データ送信用第１副搬送波成分ｃ_i,k及びデータ送信用第２副搬送波成分ｐ_i,kの対を少なくとも一つ出力する。ここで、データ第１送信用副搬送波成分ｃ_i,kの周波数は、データ送信用第２副搬送波成分ｐ_i,kの周波数よりも高い。
【００５７】
データ第１送信用副搬送波成分ｃ_i,kの周波数ｆ_cik及びデータ送信用第２副搬送波成分ｐ_i,kの周波数ｆ_pikとの差をｍｆ₀とすると（ｍ≧１）、データ送信用副搬送波成分に関しては、式（２）が成立する。
【００５８】
【数２】

【００５９】
クロック位相誤差検出部５は、共役複素数変換部５０２と複素乗算部５０３とを更に備えている。共役複素数変換部５０２はデータ送信用第２副搬送波成分ｐ_i,kの共役複素数ｐ_i,k ^*を求め、複素乗算部５０３はデータ送信用第１副搬送波成分ｃ_i,kとデータ送信用第２副搬送波成分ｐ_i,kの共役複素数ｐ_i,k ^*との複素乗算を行う。但し、記号の右上に付記されたアスタリスク（＊）は、これが付記された複素数の共役複素数を表す。
【００６０】
複素乗算部５０３のから出力される複素信号Ｒ_i,kは式（１），（２）に基づき、式（３）で表される。
【００６１】
【数３】

【００６２】
データ送信用副搬送波の変調方式がＤＱＰＳＫ（Differentially Encoded Quadrature Phase Shift Keying）、π／４シフトＤＱＰＳＫ、ＱＰＳＫ（Quadrature Phase Shift Keying）である（本明細書ではこれらを総称して「ＱＰＳＫ系変調」と称す）とすると、ａ_i,k-m ^*・ａ_i,k＝Ａ²（Ａ：信号振幅）と表される。また、ｍの値を小さくすることにより、データ第１送信用副搬送波成分ｃ_i,kに対応する伝送路の伝達関数Ｈ_i,k-mをデータ送信用第２副搬送波成分ｐ_i,kに対応する伝送路の伝達関数Ｈ_i,kと等しいと近似することができる。この場合、式（３）は式（４）で近似できる。
【００６３】
【数４】

【００６４】
式（４）において、ｌ_i,kは周波数ｆ_pikの副搬送波で変調されたデータと、周波数ｆ_cikの副搬送波で変調されたデータとの位相差を表しており、０，１，２，３のいずれかの値をとり得る。
【００６５】
データ間位相差li,kの値に依存しないように係数ｓを検出するために、クロック位相誤差検出部５は座標変換部５０４を更に備えている。座標変換部５０４では、入力される複素信号Ｒ_i,kの位相成分の絶対値が複素座標平面上で０〜π／４ラジアンに収まるように座標軸を変換する。
【００６６】
図６（ａ）は複素信号Ｒ_i,kの、図６（ｂ）は複素信号Ｒ^’ _i,kの、複素座標平面でのそれぞれの位置を示すグラフである。複素信号Ｒ_i,kはデータ間位相差li,kの値に依存して４象限のいずれかの位置を占めるが、複素信号Ｒ^’ _i,kはデータ間位相差li,kの値に依存せずに、その実部及び虚部を共に正に設定することができる。
【００６７】
座標変換部５０４は具体的には、入力される複素信号Ｒ_i,kの実部と虚部の符号と絶対値に応じて、出力する複素信号Ｒ^’ _i,kを生成する。座標変換部５０４の処理の具体例を下表に示す。但し、記号Reはその右隣の［］に納められた複素数の実部を、記号Imはその右隣の［］に納められた複素数の虚部を、それぞれ表す。
【００６８】
【表１】

【００６９】
そして複素信号Ｒ^’ _i,kは式（５）で表される。
【００７０】
【数５】

【００７１】
複素信号Ｒ^’ _i,kからクロック位相誤差についての検出出力を求めるために、クロック位相誤差検出部５は正接計算部５０５及び位相計算部５０６を更に備えている。正接計算部５０５は、複素信号Ｒ^’ _i,kの位相に対する正接を計算して出力する。具体的には例えば、Im［Ｒ^’ _i,k］／Re［Ｒ^’ _i,k］で求められる。そして位相計算部５０６は正接計算部５０５の出力を入力し、これに対応する位相θ_i,kを出力する。位相計算部５０６は、例えばルック・アップ・テーブルなどに正接に対応する位相を格納しておき、入力に応じた値を出力するようにすればよい。位相θ_i,kは式（６）で表される。
【００７２】
【数６】

【００７３】
データ送信用第１副搬送波成分ｃ_i,k及びデータ送信用第２副搬送波成分ｐ_i,kの対は、ある一つのシンボルｒ_iに対して副搬送波番号ｋを更新して複数を採用することができる。そして１シンボル期間内でｋを更新して計算された位相θ_i,kの平均値を計算するため、クロック位相誤差検出部５は位相平均化部５０７を更に備えている。位相平均化部５０７は、位相計算部５０６の出力たる位相θ_i,kを入力し、１シンボル期間内で更新された副搬送波番号ｋについて平均値を計算して第ｉ番目のシンボルにおけるクロック信号の位相誤差を反映する検出出力ｙ_iを出力する。つまり第ｉ番目のシンボルにおけるクロック信号の位相誤差を反映する検出出力ｙ_iは、データ送信用副搬送波同士の位相差を１シンボル内で平均したものであり、明らかにその値はクロック信号の位相誤差に比例するスカラー量となる。
【００７４】
しかも式（２）を満足していれば、いずれの対においてもデータ送信用副搬送波同士は同じ間隔ｍｆ₀だけ離れているので、周波数間隔に応じた補正を必要としたり、同じクロック位相誤差に対してその検出値にばらつきが生じることも回避できる。
【００７５】
また直交周波数分割多重変調としてＱＰＳＫ系変調を採用することにより、データ送信用副搬送波成分の絶対値の大きさはいずれも等しい（式（４）、（５）ではＡとして表記）ので、複素乗算結果を得る際に、データ送信用副搬送波成分の大きさで正規化する必要も無い。
【００７６】
以上のように、実施の形態３によれば、１シンボル内で一対または複数対をなす副搬送波における位相差に基づき、クロック信号の位相誤差を検出する。従ってクロック再生を行うフェーズ・ロックド・ループにおいて、高精度かつ安定なクロック信号を再生することができる。
【００７７】
なお、副搬送波にはデータ以外にも、復調器において信号を再生する場合に使用するパイロットや、同期用のパイロット、伝送パラメータを表すデータなど、様々な情報を送信している場合が多い。しかしパイロット用副搬送波はデータ送信用副搬送波よりもその数が少なく、また不規則な周波数位置に配置される。よってパイロット用副搬送波を用いて位相誤差を求める場合に比べ、実施の形態３ではデータ送信用副搬送波を用いて位相誤差を求めるので、高精度にクロック位相の誤差が求められる。
【００７８】
データ送信用第１副搬送波成分ｃ_i,k及びデータ送信用第２副搬送波成分ｐ_i,kの対は、ある一つのシンボルｒ_iに対して一対のみ求めてもよく、その場合には位相平均化部５０７は不要となる。しかし、位相誤差を求める精度を高めるためには複数の上記対を求めることが望ましい。
【００７９】
実施の形態４．
実施の形態４でも、クロック位相誤差検出部５１として採用できるクロック位相誤差検出部５１ｂの構成を呈示する。クロック位相誤差検出部５１ｂではデータ送信用副搬送波ではなく、パイロット用の副搬送波（パイロット用副搬送波）、特にシンボルによって周波数位置が変化するパイロット用副搬送波を用いてクロックの位相誤差を検出する。
【００８０】
図７は、クロック位相誤差検出部５１ｂの構成を例示するブロック図である。クロック位相誤差検出部５１ｂはパイロット用副搬送波成分抽出部５１１を備えており、これがフーリエ変換部４から副搬送波成分ｘ_i,kを入力し、ある種のパイロット用副搬送波成分を抽出する。
【００８１】
一般に、パイロット用副搬送波はデータ送信用副搬送波に比べ、その絶対数が少ない場合が多い。従って、一般のパイロット用副搬送波を実施の形態３で示されたクロック位相誤差検出部５１ａに用いると、雑音の影響を受けやすい。また、一般のパイロット用副搬送波はその周波数配置が不規則な場合がある。この場合には、抽出される副搬送波の周波数間隔が一定ではないため、周波数間隔に応じた補正を必要としたり、同じクロック位相誤差に対しても検出値にばらつきが生じるという問題が生じる。更に、一定の間隔で配置されたパイロット用副搬送波を用いた場合は、検出値のばらつきは発生しないが、その間隔が大きいほど検出範囲が小さくなってしまう。
【００８２】
ところが、パイロット用副搬送波のうち、同期変調された副搬送波を復調するために使用される副搬送波は、同一シンボル内の周波数間隔が一定値Ｍｆ₀（ｆ₀は副搬送波番号が隣接する副搬送波同士の周波数間隔）であって、かつその周波数配置がシンボル毎に一定のオフセットｎｆ₀を持つ場合がある（以下「特定パイロット用副搬送波」と称す）。図８はそのようなパイロットを含むシンボルを示す模式図であり、行毎に異なるシンボル（例えばｒ_i）が例示されている。白丸及び黒丸は副搬送波の位置を示し、右に行くほど副搬送波番号ｋが大きく、その対応する周波数が高い。同一シンボル内で隣接するパイロット用副搬送波の周波数間隔が１２ｆ₀（即ちＭ＝１２）であり、隣接するシンボル同士ではパイロット用副搬送波のオフセットが３ｆ₀（即ちｎ＝３）である場合が図示されている。このようなパイロットの例として、日本における地上波デジタルＴＶ方式でのScattered Pilotを挙げることができる。
【００８３】
特定パイロット用副搬送波を用いることにより、後述するようにクロック信号の位相誤差の検出範囲を広げると共に、位相誤差の検出に供される副搬送波数を増加させることができる。よってクロック信号の位相誤差の検出精度を向上することができる。
【００８４】
更にＱＰＳＫ系以外の多値同期変調、例えば多値ＱＡＭ（Quadrature Amplitude Modulation）等が用いられた場合には、抽出されるデータ送信用副搬送波の位相誤差の検出は複雑になる。一方、パイロット用副搬送波の変調方式としては通常ＢＰＳＫ（Binary Phase Shift Keying）やＤＢＰＳＫ（Differentially Encoded Binary Phase Shift Keying）が用いられ、しかもそのデータの値は既知である。このような場合にはパイロット用副搬送波を用いてクロック信号の位相誤差を検出する方が、回路規模を削減できる。
【００８５】
クロック位相誤差検出部５１ｂは除算部５１２を更に備え、パイロット用副搬送波成分抽出部５１１で抽出されたパイロット用副搬送波成分ｘ_i,k ^(p)を、既知パイロットデータａ_i,k ^(p)で除算する。既知パイロットデータは、抽出されたパイロット用副搬送波に対応するパイロットのデータを表す既知信号である。これによりパイロット用副搬送波成分が正規化され、パイロットのデータの値によらずにクロック信号の位相誤差を求めることができる。
【００８６】
副搬送波成分ｘ_i,kがパイロット用副搬送波成分ｘ_i,k ^(p)であった場合、これが式（１）で表されるとすれば、除算部５１２の出力、即ち正規化されたパイロット用副搬送波成分ｘ^’ _i,k ^(p)は式（７）で表され、本明細書では「伝送路特性成分」とも称する。
【００８７】
【数７】

【００８８】
伝送路特性成分ｘ^’ _i,k ^(p)は、該当する副搬送波に対する伝送路特性Ｈ_i,kとクロック信号の位相誤差を反映する位相回転項exp［ｊ２π（ｋ／Ｎ）ｓ］との積で表されている。
【００８９】
クロック位相誤差検出部５１ｂは伝送路特性成分メモリ部５１３を更に備え、伝送路特性成分ｘ^’ _i,k ^(p)を少なくとも１シンボル分以上メモリに格納する。望ましくは（Ｍ／ｎ−１）個の異なるシンボルについての伝送路特性成分を格納する。
【００９０】
クロック位相誤差検出部５１ｂは隣接伝送路特性成分分離部５１４を更に備え、伝送路特性成分メモリ部５１３の出力と、除算部５１２の出力とを入力し、パイロット用第１伝送路特性成分ｃ_i,k ^(p)及びパイロット用第２伝送路特性成分ｐ_i,k ^(p)の対を出力する。
【００９１】
図９は、パイロット用第１伝送路特性成分ｃ_i,k ^(p)及びパイロット用第２伝送路特性成分ｐ_i,k ^(p)を得る様子を示す概念図である。黒丸はパイロットの副搬送波の位置を、白丸はそれ以外の信号の副搬送波の位置を、それぞれ示しており、除算部５１２、伝送路特性成分メモリ部５１３から得られる副搬送波は黒丸で示された位置に対応するものである。ここでは特定パイロット用副搬送波が副搬送波番号ｋ＝０，３，６，９，１２，１５の副搬送波の中から選択され、かつ同一パイロットにおいては特定パイロット用副搬送波同士が副搬送波番号が１２個分離れている場合が図示されている。つまり図８で説明された場合と同様に同一シンボル内で隣接する特定パイロット用副搬送波の周波数間隔が１２ｆ₀（即ちＭ＝１２）であり、隣接するシンボル同士では特定パイロット用副搬送波のオフセットが３ｆ₀（即ちｎ＝３）である場合が図示されている。
【００９２】
第ｉ番目のシンボルにおいて、特定パイロット用副搬送波は副搬送波番号ｋ＝６であり、伝送路特性成分ｘ^’ _i,6 ^(p)が除算部５１２から得られている場合を想定する。これに先立って既に除算部５１２からは、第（ｉ−１）番目のシンボルについて伝送路特性成分ｘ^’ _i-1,3 ^(p)，ｘ^’ _i-1,15 ^(p)が、第（ｉ−２）番目のシンボルについて伝送路特性成分ｘ^’ _i-2,0 ^(p)，ｘ^’ _i-2,12 ^(p)が、第（ｉ−３）番目のシンボルについて伝送路特性成分ｘ^’ _i-3,9 ^(p)が、それぞれ得られ、かつ伝送路特性成分メモリ部５１３から出力される。
【００９３】
従って隣接伝送路特性成分分離部５１４には、ｘ^’ _i-2,0 ^(p)，ｘ^’ _i-1,3 ^(p)，ｘ^’ _i,6 ^(p)，ｘ^’ _i-3,9 ^(p)，ｘ^’ _i-2,12 ^(p)，ｘ^’ _i-1,15 ^(p)が入力されることになり、異なるシンボルに亘ってはいるものの、特定パイロット用副搬送波のオフセットｎｆ₀ずつ異なる複数の伝送路特性成分が得られることになる。従って除算部５１２から第ｉ番目のシンボルについての伝送路特性成分が得られた際に、パイロット用第１伝送路特性成分ｃ_i,k ^(p)及びパイロット用第２伝送路特性成分ｐ_i,k ^(p)の複数対を出力することができる。例えばｃ_i,15 ^(p)＝ｘ^’ _i-1,15 ^(p)，ｐ_i,15 ^(p)＝ｘ^’ _i-2,12 ^(p)の対、ｃ_i,12 ^(p)＝ｘ^’ _i-2,12 ^(p)，ｐ_i,12 ^(p)＝ｘ^’ _i-3,9 ^(p)の対、ｃ_i,9 ^(p)＝ｘ^’ _i-3,9 ^(p)，ｐ_i,9 ^(p)＝ｘ^’ _i,6 ^(p)の対、ｃ_i,6 ^(p)＝ｘ^’ _i,6 ^(p)，ｐ_i,6 ^(p)＝ｘ^’ _i-1,3 ^(p)の対、ｃ_i,3 ^(p)＝ｘ^’ _i-1,3 ^(p)，ｃ_i,3 ^(p)＝ｘ^’ _i-1,3 ^(p)，ｐ_i,3 ^(p)＝ｘ^’ _i-2,0 ^(p)の対である。
【００９４】
換言すれば、除算部５１２から出力される現在のシンボルに対する伝送路特性成分と、伝送路特性成分メモリ部５１３から出力される、それ以前のシンボルの伝送路特性成分とを採用し、これらの中から選択して、周波数が互いに隣接する伝送路特性成分が対となって出力される。
【００９５】
クロック位相誤差検出部５１ｂは共役複素数変換部５１５を更に備え、これはパイロット用第２パイロット用伝送路特性成分ｐ_i,k ^(p)の共役複素数ｐ_i,k ^(p)*を出力する。そして第２の複素乗算部５１６は、共役複素数変換部５１５からの出力ｐ_i,k ^(p)*と、隣接伝送路特性成分分離部５１４からのパイロット用第１伝送路特性成分ｃ_i,k ^(p)との複素乗算を行う。複素乗算部５１６の出力Ｒ_i,k ^(p)は式（７）に基づき、式（８）で表される。
【００９６】
【数８】

【００９７】
クロック位相誤差検出部５１ｂは実施の形態３で採用されたものと同じ機能を果たす正接計算部５０５、位相計算部５０６、位相平均化部５０７を更に備えている。正接計算部５０５は、複素乗算部５１６の出力Ｒ_i,k ^(p)の正接（その虚部をその実部で除した値）を計算して出力する。以降の処理は実施の形態３と同様にして、第ｉ番目のシンボルにおける検出出力ｙ_iを得ることができる。
【００９８】
以上のように、本実施の形態によれば、１シンボル内に等周波数間隔で配置されかつシンボル毎にその配置がオフセットを持つ特定パイロット用副搬送波に着目し、これから得られる伝送路特性成分を複数のシンボルに亘って採用し、その中から選択される少なくとも一つの対の伝送路特性成分同士の位相差を検出する。従って同一のシンボルからのみ特定パイロット用副搬送波成分を得る場合よりも周波数間隔が小さく、従って対となる伝送路特性成分の間で伝達関数はほぼ等しいとする近似の精度も高められる。また参照する副搬送波の数を多く得ることができ、クロック再生を行うフェーズ・ロックド・ループにおいて、高精度かつ安定なクロック信号を再生することができる。
【００９９】
また、同様の理由から、周波数・時間配置が不規則なパイロット用副搬送波を用いる場合に必要となる検出値のばらつきをなくし、またクロック信号の位相誤差の検出範囲を増大することができる。
【０１００】
なお、図９に示されたように、隣接するシンボル間において、必ずオフセットｎｆ₀分離れた一対の伝送路特性成分が得られる場合には、伝送路特性成分メモリ部５１３はシンボル一つ分を格納してもよい。その場合には１シンボル当たりに一対のパイロット用第１伝送路特性成分ｃ_i,k ^(p)及びパイロット用第２伝送路特性成分ｐ_i,k ^(p)が得られることになり、出力位相平均化部５０７は不要となる。しかし、位相誤差を求める精度を高めるためには複数の上記対を求めることが望ましい。
【０１０１】
実施の形態５．
実施の形態５では、同期変調された副搬送波を復調する場合に用いられる伝送路推定結果の出力をもとにクロックの位相誤差を検出する。図１０は、この発明の実施の形態５による直交周波数分割多重信号受信装置１０３の構成を示すブロック図である。その概略として、図１で示されたクロック位相誤差検出部５１をクロック位相誤差検出部５２に、直交周波数分割多重信号受信装置１０１のデータ再生部７を副搬送波復調部１３に、それぞれ置換し、伝送路推定部１２を追加した構成を有している。
【０１０２】
より詳細には直交周波数分割多重信号受信装置１０３は、いずれも実施の形態１に採用されたものと同じ機能を果たすＡ／Ｄ変換部１、副搬送波周波数補正部２、ガード期間除去部３、フーリエ変換部４、ループフィルタ部６、発振器制御部８、クロック発振器９を備えている。
【０１０３】
伝送路推定部１２はフーリエ変換部４から副搬送波成分ｘ_i,kを入力し、同期変調された副搬送波を復調するために挿入されているパイロットの副搬送波成分をもとに、伝送路の特性を推定する。図１１は伝送路推定部１２の構成を例示するブロック図である。実施の形態４と同様にして伝送路特性成分ｘ^’ _i,k ^(p)を得るための、パイロット用副搬送波成分抽出部５１１、除算部５１２が伝送路推定部１２に備えられている。
【０１０４】
除算部５１２から伝送路特性成分ｘ^’ _i,k ^(p)が得られる際には、既に第（ｉ−１）番目以前の複数のシンボルについての伝送路特性成分が得られている。これらを格納するために伝送路特性成分メモリ部５１３も設けられている。そして第ｉ番目以前の複数のシンボルについての伝送路特性成分が内挿部５１９に与えられる。
【０１０５】
内挿部５１９では、特定パイロット用副搬送波について得られた伝送路特性成分を時間方向及び周波数方向について内挿を用いた近似によって、特定パイロット用副搬送波以外の副搬送波についての伝送路特性成分を推定する。これにより全ての副搬送波についての伝送路特性成分ｈ_i,kが出力される。上記内挿のため、伝送路特性成分メモリ部５１３は（Ｍ／ｎ）個の異なるシンボルについての伝送路特性成分を格納することが望ましい。
【０１０６】
副搬送波復調部１３は、フーリエ変換部４から出力される副搬送波成分ｘ_i,kを、伝送路特性ｈ_i,kに基づいて復調し、再生データｓ_i,kを出力する。具体的にはｓ_i,k＝ｘ_i,k／ｈ_i,kで求めることができる。
【０１０７】
上記のようにして得られた伝送路特性ｈ_i,0〜ｈ_i,K（０≦ｋ≦Ｋ）は、クロック位相誤差検出部５２に与えられ、クロック信号の位相誤差を反映する検出出力ｙ_iが出力される。図１２はクロック位相誤差検出部５２に採用できるクロック位相誤差検出部５２ａの構成を示すブロック図である。クロック位相誤差検出部５２ａはクロック位相誤差検出部５１ｂからパイロット用副搬送波成分抽出部５１１、除算部５１２、伝送路特性成分メモリ部５１３を除いた構成を有している。
【０１０８】
具体的にはクロック位相誤差検出部５２ａは隣接伝送路特性成分分離部５１４を有しており、伝送路特性ｈ_i,0〜ｈ_i,Kから第１副搬送波伝送路特性成分ｃ_i,k ^(h)及び第２副搬送波伝送路特性成分ｐ_i,k ^(h)の対を少なくとも一つ出力する。ここで、第１副搬送波伝送路特性成分ｃ_i,k ^(h)の周波数は、第２副搬送波伝送路特性成分ｐ_i,k ^(h)の周波数よりも高い。例えばｃ_i,k1 ^(h)＝ｈ_i,k1，ｐ_i,k1 ^(h)＝ｈ_i,k1-t（１≦ｔ≦ｋ１）に選択することができる。但し実施の形態１においてｍを小さくするほど位相誤差を精度良く求めやすいのと同様に、ｔは小さい方が望ましい。
【０１０９】
クロック位相誤差検出部５２ａは更に共役複素数変換部５１５、複素乗算部５１６、正接計算部５０５、位相計算部５０６、位相平均化部５０７を備え、これらはそれぞれ実施の形態３に示された機能を果たす。即ち、共役複素数変換部５１５は第２副搬送波伝送路特性成分ｐ_i,k ^(h)の共役複素数ｐ_i,k ^(h)*を出力する。そして複素乗算部５１６において第１副搬送波伝送路特性成分ｃ_i,k ^(h)と共役複素数ｐ_i,k ^(h)*との複素乗算が行われ、複素信号Ｒ_i,k ^(h)が出力される。これから正接計算部５０５、位相計算部５０６によって位相θ_i,kが求められ、更にその副搬送波番号ｋについての平均が位相平均化部５０７によって計算されて第ｉ番目のシンボルについての検出出力ｙ_iが求められる。
【０１１０】
以上のように、本実施の形態によれば、同期変調された副搬送波の復調時に必要となる伝送路推定部の出力として得られる伝送路特性をもとに、クロック信号の位相誤差を検出する。従って、参照する副搬送波の数を任意に増加することができる。そしてクロック信号の位相誤差を、パイロット用副搬送波成分の値によらずに求めることができる。これによりクロック再生を行うフェーズ・ロックド・ループにおいて、高精度かつ安定なクロック信号を再生することができる。またクロック信号の位相誤差の検出範囲を増大することができる。
【０１１１】
なお、本実施の形態で採用されるべきパイロット用副搬送波は、実施の形態５で採用される特定パイロット用副搬送波のような「１シンボル内に等周波数間隔で配置されかつシンボル毎にその配置がオフセットを持つ」という特性を備えることは、必ずしも要求されない。同期変調された副搬送波の復調時に通常用いられる、伝送路推定部の出力を採用してクロック信号の位相誤差を求めるからである。
【０１１２】
また、本実施の形態ではクロック位相誤差検出部５２ａが出力する検出出力ｙ_iに基づいてクロック発振部９のクロック信号を制御する直交周波数分割多重信号受信装置１０３を例示したが、実施の形態２に示される直交周波数分割多重信号受信装置１０２のように、フィルタ係数出力部１０及びリサンプリング部１１を用いてもよい。
【０１１３】
実施の形態６．
実施の形態６では、副搬送波の変調方式として同期変調と差動変調が混在する場合のクロック信号の位相誤差を検出する技術を呈示する。但し、ここでいう差動変調とは、ＤＱＰＳＫやπ／４シフトＤＱＰＳＫを、また同期変調はＱＰＳＫや多値ＱＡＭを意味する。
【０１１４】
図１３は、この発明の実施の形態６による直交周波数分割多重信号受信装置１０４の構成を示すブロック図である。直交周波数分割多重信号受信装置１０４は直交周波数分割多重信号受信装置１０１においてクロック位相誤差検出部５１をクロック位相誤差検出部５３に置換し、また変調方式識別情報デコード部１４を追加した構成を有している。
【０１１５】
変調方式識別情報デコード部１４は、フーリエ変換部４から副搬送波成分ｘ_i,kを入力し、副搬送波の中に挿入されている各副搬送波の変調方式を識別するための情報を再生する。これにより、各々の副搬送波についての変調方式が差動変調であるか同期変調であるかを表す変調方式識別信号Ｄを出力する。クロック位相誤差検出部５３では、変調方式識別信号Ｄに応じてクロック信号の位相誤差検出を行う。
【０１１６】
図１４はクロック位相誤差検出部５３に採用できるクロック位相誤差検出部５３ａの構成を示すブロック図である。クロック位相誤差検出部５３ａは複素信号Ｒ^’ _i,kを得るために実施の形態３で示されたクロック位相誤差検出部５１ａが備えていた、データ送信用副搬送波成分抽出部５００、隣接データ送信用副搬送波成分分離部５０１、共役複素数変換部５０２、複素乗算部５０３、座標変換部５０４を備えている。そして複素信号Ｒ^’ _i,kは信号選択部５２２の一方の入力となっている。
【０１１７】
またクロック位相誤差検出部５３ａは複素信号Ｒ_i,k ^(p)を得るために実施の形態４で示されたクロック位相誤差検出部５１ｂが備えていた、パイロット用副搬送波成分抽出部５１１、除算部５１２、伝送路特性成分メモリ部５１３、隣接伝送路特性成分分離部５１４、共役複素数変換部５１５、複素乗算部５１６を備えている。そして出力Ｒ_i,k ^(p)は信号選択部５２２の他方の入力となっている。
【０１１８】
更に、クロック位相誤差検出部５３ａは信号選択部５２２の出力が与えられる正接計算部５０５、正接計算部５０５の出力が与えられる位相計算部５０６、位相計算部５０６から位相θ_i,kを得て検出出力ｙ_iを出力する位相平均化部５０７を備えている。
【０１１９】
そしてクロック位相誤差検出部５３ａは変調方式識別信号Ｄによって２入力から一つを選択して出力する信号選択部５２２を備えている。従ってクロック位相誤差検出部５３ａは、信号選択部５２２からの出力に応じて、実施の形態３で示されたクロック位相誤差検出部５１ａ（図４）、実施の形態４で示されたクロック位相誤差検出部５１ｂ（図７）のいずれかの機能を果たす。
【０１２０】
信号選択部５２２は、変調方式識別信号Ｄが、副搬送波成分ｘ_i,kが差動変調されていると判断した場合には座標変換部５０４の出力Ｒ^’ _i,kを、副搬送波成分ｘ_i,kが同期変調されていると判断した場合には複素乗算部５１６の出力Ｒ_i,k ^(p)を、それぞれ選択して出力する。
【０１２１】
以上のように、本実施の形態では副搬送波の変調方式に応じてクロック信号の位相誤差を検出する。従って本実施の形態によれば、差動変調と同期変調が混在するような直交周波数分割多重信号を受信する際に高精度なクロック再生を実現することができる。
【０１２２】
なお、本実施の形態ではクロック位相誤差検出部５３ａが出力する検出出力ｙ_iに基づいてクロック発振部９のクロック信号を制御する直交周波数分割多重信号受信装置１０４を例示したが、実施の形態２に示される直交周波数分割多重信号受信装置１０２のように、フィルタ係数出力部１０及びリサンプリング部１１を用いてもよい。
【０１２３】
実施の形態７．
実施の形態７は実施の形態３乃至実施の形態６の変形である。
【０１２４】
図１５は実施の形態７のうち、実施の形態３の変形を示すブロック図であり、クロック位相誤差検出部５１ｃの構成を示す。クロック位相誤差検出部５１ｃは、図４に示されたクロック位相誤差検出部５１ａの位相計算部５０６、位相平均化部５０７を正接平均化部５０８に置換した構成を有している。クロック位相誤差検出部５１ｃも、直交周波数分割多重信号受信装置１０１，１０２が備えるクロック位相誤差検出部５１として採用することができる。
【０１２５】
図１６は実施の形態７のうち、実施の形態４の変形を示すブロック図であり、クロック位相誤差検出部５１ｄの構成を示す。クロック位相誤差検出部５１ｄは、図７に示されたクロック位相誤差検出部５１ｂの位相計算部５０６、位相平均化部５０７を正接平均化部５０８に置換した構成を有している。クロック位相誤差検出部５１ｄも、直交周波数分割多重信号受信装置１０１，１０２が備えるクロック位相誤差検出部５１として採用することができる。
【０１２６】
図１７は実施の形態７のうち、実施の形態５の変形を示すブロック図であり、クロック位相誤差検出部５２ｂの構成を示す。クロック位相誤差検出部５２ｂは、図１２に示されたクロック位相誤差検出部５２ａの位相計算部５０６、位相平均化部５０７を正接平均化部５０８に置換した構成を有している。クロック位相誤差検出部５２ｂも、直交周波数分割多重信号受信装置１０３が備えるクロック位相誤差検出部５２として採用することができる。
【０１２７】
図１８は実施の形態７のうち、実施の形態６の変形を示すブロック図であり、クロック位相誤差検出部５３ｂの構成を示す。クロック位相誤差検出部５３’は、図１４に示されたクロック位相誤差検出部５３ａの位相計算部５０６、位相平均化部５０７を正接平均化部５０８に置換した構成を有している。クロック位相誤差検出部５３ｂも、直交周波数分割多重信号受信装置１０４が備えるクロック位相誤差検出部５３として採用することができる。
【０１２８】
正接平均化部５０８は、正接計算部５０５の出力を入力とし、１シンボル期間内に計算された位相情報の正接の平均値を計算する。その結果はクロック信号の位相誤差を反映するスカラー量となるので、これを第ｉ番目のシンボルについての検出出力ｙ_iとして扱うことができる。
【０１２９】
以上のように、本実施の形態では正接計算部５０５の出力を１シンボル期間平均化したものをクロック位相誤差検出部５１，５２，５３の出力ｙ_iとする。従って、正接から位相を求める必要が無く、回路規模を削減することができる。
【０１３０】
実施の形態８．
実施の形態８は、実施の形態３の変形としての実施の形態７の、更に変形である。図１９はクロック位相誤差検出部５１ｅの構成を示すブロック図であり、クロック位相誤差検出部５１ｅは直交周波数分割多重信号受信装置１０１，１０２が備えるクロック位相誤差検出部５１として採用することができる。
【０１３１】
クロック位相誤差検出部５１ｅは図１５に示されたクロック位相誤差検出部５１ｃの正接計算部５０５、正接平均化部５０８を、それぞれ虚部情報抽出部５０９、虚部平均化部５１０に置換した構成を有している。
【０１３２】
クロック位相誤差検出部５１ｅはクロック位相誤差検出部５１ａ，５１ｃと同様にして、座標変換部から複素信号Ｒ^’ _i,kを得る。そして虚部情報抽出部５０９は複素信号Ｒ^’ _i,kの虚部Im［Ｒ^’ _i,k］を出力する。これはクロック位相誤差検出部５１ａ，５１ｃの正接計算部５０５の出力に複素信号Ｒ^’ _i,kの実部Re［Ｒ^’ _i,k］を乗じたものに相当する。虚部平均化部５１０は虚部Im［Ｒ^’ _i,k］を、副搬送波番号ｋについての平均をとって出力する。その結果はクロック信号の位相誤差を反映するスカラー量となるので、これを第ｉ番目のシンボルについての検出出力ｙ_iとして扱うことができる。
【０１３３】
以上のように、本実施の形態では、虚部情報の１シンボルの平均値をクロック位相誤差検出部５１の出力とする。従って、正接や位相を求める必要が無く、回路規模を削減することができる。
【０１３４】
実施の形態９．
実施の形態９は、実施の形態４の変形としての実施の形態７の、更に変形である。図２０はクロック位相誤差検出部５１ｆの構成を示すブロック図であり、クロック位相誤差検出部５１ｆは直交周波数分割多重信号受信装置１０１，１０２が備えるクロック位相誤差検出部５１として採用することができる。
【０１３５】
クロック位相誤差検出部５１ｆは図１６に示されたクロック位相誤差検出部５１ｄの共役複素数変換部５１５、複素乗算部５１６、正接計算部５０５、正接平均化部５０８を虚部情報生成用乗算部５１７、虚部平均化部５１０に置換した構成を有している。
【０１３６】
クロック位相誤差検出部５１ｆはクロック位相誤差検出部５１ｂ，５１ｄと同様にして、隣接伝送路特性成分分離部５１４からパイロット用第１伝送路特性成分ｃ_i,k ^(p)及びパイロット用第２伝送路特性成分ｐ_i,k ^(p)を得る。虚部情報生成用乗算部５１７は、これらを入力し、式（９）に基づいて虚部情報ｑ_i,k ^(p)を計算して出力する。
【０１３７】
【数９】

【０１３８】
つまり虚部情報ｑ_i,k ^(p)は、クロック位相誤差検出部５１ｂ，５１ｄにおいて正接計算部５０５から得られる正接の値に（Re［ｃ_i,k ^(p)］・Re［ｐ_i,k ^(p)］＋Im［ｃ_i,k ^(p)］・Im［ｐ_i,k ^(p)］）を乗じた値である。虚部平均化部５１０は虚部情報ｑ_i,k ^(p)を、副搬送波番号ｋについての平均をとって出力する。その結果はクロック信号の位相誤差を反映するスカラー量となるので、これを第ｉ番目のシンボルについての検出出力ｙ_iとして扱うことができる。
【０１３９】
以上のように、本実施の形態では、虚部情報の１シンボルの平均値をクロック位相誤差検出部５１の出力とする。従って、複素乗算のように（Re［ｃ_i,k ^(p)］・Re［ｐ_i,k ^(p)］＋Im［ｃ_i,k ^(p)］・Im［ｐ_i,k ^(p)］）を求める必要は無く、正接や位相を求める必要も無く、回路規模を削減することができる。
【０１４０】
実施の形態１０．
実施の形態１０は実施の形態５の変形としての実施の形態７の、更に変形である。図２１はクロック位相誤差検出部５２ｃの構成を示すブロック図であり、クロック位相誤差検出部５２ｃは直交周波数分割多重信号受信装置１０３が備えるクロック位相誤差検出部５２として採用することができる。
【０１４１】
クロック位相誤差検出部５２ｃは図１７に示されたクロック位相誤差検出部５２ｂの共役複素数変換部５１５、複素乗算部５１６、正接計算部５０５、正接平均化部５０８を虚部情報生成用乗算部５１７、虚部平均化部５１０に置換した構成を有している。
【０１４２】
クロック位相誤差検出部５２ｃはクロック位相誤差検出部５２ａ，５２ｂと同様にして、隣接伝送路特性成分分離部５１４から第１伝送路特性成分ｃ_i,k ^(h)及び第２伝送路特性成分ｐ_i,k ^(h)を得る。虚部情報生成用乗算部５１７は、これらを入力し、式（１０）に基づいて虚部情報ｑ_i,k ^(h)を計算して出力する。
【０１４３】
【数１０】

【０１４４】
つまり虚部情報ｑ_i,k ^(h)は、クロック位相誤差検出部５２ａ，５２ｂにおいて正接計算部５０５から得られる正接の値に（Re［ｃ_i,k ^(h)］・Re［ｐ_i,k ^(h)］＋Im［ｃ_i,k ^(h)］・Im［ｐ_i,k ^(h)］）を乗じた値である。虚部平均化部５１０は虚部情報ｑ_i,k ^(h)を、副搬送波番号ｋについての平均をとって出力する。その結果はクロック信号の位相誤差を反映するスカラー量となるので、これを第ｉ番目のシンボルについての検出出力ｙ_iとして扱うことができる。
【０１４５】
以上のように、本実施の形態では、虚部情報の１シンボルの平均値をクロック位相誤差検出部５１の出力とする。従って、複素乗算のように（Re［ｃ_i,k ^(h)］・Re［ｐ_i,k ^(h)］＋Im［ｃ_i,k ^(h)］・Im［ｐ_i,k ^(h)］）を求める必要は無く、正接や位相を求める必要も無く、回路規模を削減することができる。
【０１４６】
実施の形態１１．
実施の形態１１は実施の形態６の変形としての実施の形態７の、更に変形である。図２２はクロック位相誤差検出部５３ｃの構成を示すブロック図であり、クロック位相誤差検出部５３ｃは直交周波数分割多重信号受信装置１０４が備えるクロック位相誤差検出部５３として採用することができる。
【０１４７】
クロック位相誤差検出部５３ｃは図１８に示されたクロック位相誤差検出部５３ｂの正接計算部５０５、正接平均化部５０８を虚部情報抽出部５０９、虚部平均化部５１０に置換した構成を有している。
【０１４８】
従って、変調方式識別信号Ｄによって信号選択部５２２が座標変換部５０４の出力Ｒ^’ _i,kを出力した場合には、実施の形態８と同様にしてIm［Ｒ^’ _i,k］が虚部平均化部５１０に与えられる。また変調方式識別信号Ｄによって信号選択部５２２が複素乗算部５１６の出力Ｒ_i,k ^(p)を出力した場合には、実施の形態９と同様にして虚部情報ｑ_i,k ^(p)が虚部平均化部５１０に与えられる。
【０１４９】
以上のように、本実施の形態では、虚部情報の１シンボル平均値をクロック位相誤差検出部５の出力とする。従って正接または位相を求める回路が不要となり、回路規模を削減することができる。
【０１５０】
【発明の効果】
この発明のうち請求項１乃至請求項４にかかる直交周波数分割多重信号の受信装置によれば、クロック信号の位相誤差についてのフェーズ・ロックド・ループを有しているので、高精度で安定なクロック再生を行うことができる。またクロック信号の周波数誤差も局所的には位相誤差としてみなすことができる。従って、直交周波数分割多重信号のデータ再生後の誤り率が低減される。
【０１５１】
しかも、クロック信号の位相誤差を求めるための副搬送波の数を多く採用することができ、クロック信号の位相誤差を反映する検出出力が高精度に求められる。
【０１５２】
この発明のうち請求項５にかかる直交周波数分割多重信号の受信装置によれば、データ送信用副搬送波成分の絶対値の大きさはいずれも等しいので、クロック信号の位相誤差を反映する検出出力を求める際に、データ送信用副搬送波成分の大きさで正規化する必要が無い。
【０１５３】
この発明のうち請求項６にかかる直交周波数分割多重信号の受信装置によれば、周波数間隔に応じた補正を必要としたり、同じクロック信号の位相誤差に対してその検出値にばらつきが生じることを回避できる。
【０１５４】
この発明のうち請求項７にかかる直交周波数分割多重信号の受信装置によれば、クロック信号の位相誤差を反映する検出出力を、データ送信用副搬送波成分のデータ同士の位相差によらずに求めることができる。
【０１５５】
この発明のうち請求項８にかかる直交周波数分割多重信号の受信装置によれば、座標変換された複素乗算結果に基づいて、クロック信号の位相誤差を求めることができる。
【０１５６】
この発明のうち請求項９にかかる直交周波数分割多重信号の受信装置によれば、データ送信用副搬送波成分に基づく位相を求める必要がない。
【０１５７】
この発明のうち請求項１０にかかる直交周波数分割多重信号の受信装置によれば、データ送信用副搬送波成分に基づく正接や位相を求める必要がない。
【０１５８】
この発明のうち請求項１１にかかる直交周波数分割多重信号の受信装置によれば、クロック信号の位相誤差は、１シンボル毎に、周波数・時間配置が規則的なパイロット用副搬送波を用いて求められるので、周波数・時間配置が不規則なパイロット用副搬送波を用いて位相差を検出する場合に比べ、高精度にクロック信号の位相誤差が求められる。
【０１５９】
この発明のうち請求項１２にかかる直交周波数分割多重信号の受信装置によれば、クロック信号の位相誤差を反映する検出出力を、１シンボル毎に、パイロット用副搬送波を用いて求めることができ、位相誤差を求めるための副搬送波の数を多く採用することができる。
【０１６０】
この発明のうち請求項１３、請求項１４にかかる直交周波数分割多重信号の受信装置によれば、クロック信号の位相誤差を、パイロット用副搬送波成分の値によらずに求めることができる。
【０１６１】
この発明のうち請求項１５にかかる直交周波数分割多重信号の受信装置によれば、複素乗算結果に基づく位相を求める必要がない。
【０１６２】
この発明のうち請求項１６、請求項１７にかかる直交周波数分割多重信号の受信装置によれば、同期変調された副搬送波の復調の為に通常用いられる伝送路推定部の出力を採用して、クロック信号の位相誤差を反映する検出出力が求められる。またクロック信号の位相誤差を求めるための副搬送波の数を多く採用することができ、クロック信号の位相誤差を反映する検出出力が高精度に求められる。
【０１６３】
この発明のうち請求項１８にかかる直交周波数分割多重信号の受信装置によれば、複素乗算結果に基づく位相を求める必要がない。
【０１６４】
この発明のうち請求項１９にかかる直交周波数分割多重信号の受信装置によれば、複素乗算や正接、位相を求める必要がない。
【０１６５】
この発明のうち請求項２０、請求項２１にかかる直交周波数分割多重信号の受信装置によれば、差動変調と同期変調が混在するような直交周波数分割多重信号を受信する際に高精度なクロック再生を実現することができる。
【図面の簡単な説明】
【図１】 この発明の実施の形態１の構成を示すブロック図である。
【図２】 この発明の実施の形態１の動作を示すグラフである。
【図３】 この発明の実施の形態２の構成を示すブロック図である。
【図４】 この発明の実施の形態３の構成を示すブロック図である。
【図５】 この発明の実施の形態３の動作を示すグラフである。
【図６】 この発明の実施の形態３の動作を示すグラフである。
【図７】 この発明の実施の形態４の構成を示すブロック図である。
【図８】 この発明の実施の形態４の動作を示す模式図である。
【図９】 この発明の実施の形態４の動作を示す概念図である。
【図１０】 この発明の実施の形態５の構成を示すブロック図である。
【図１１】 この発明の実施の形態５の構成を示すブロック図である。
【図１２】 この発明の実施の形態５の構成を示すブロック図である。
【図１３】 この発明の実施の形態６の構成を示すブロック図である。
【図１４】 この発明の実施の形態６の構成を示すブロック図である。
【図１５】 この発明の実施の形態７の構成を示すブロック図である。
【図１６】 この発明の実施の形態７の構成を示すブロック図である。
【図１７】 この発明の実施の形態７の構成を示すブロック図である。
【図１８】 この発明の実施の形態７の構成を示すブロック図である。
【図１９】 この発明の実施の形態８の構成を示すブロック図である。
【図２０】 この発明の実施の形態９の構成を示すブロック図である。
【図２１】 この発明の実施の形態１０の構成を示すブロック図である。
【図２２】 この発明の実施の形態１１の構成を示すブロック図である。
【図２３】 従来の技術の構成を示すブロック図である。
【符号の説明】
ａ_i,k ^(p) 既知パイロットデータ、ｃ_i,k データ送信用第１副搬送波成分、ｐ_i,k データ送信用第２副搬送波成分、ｃ_i,k ^(p) パイロット用第１伝送路特性成分、ｐ_i,k ^(p) パイロット用第２伝送路特性成分、ｃ_i,k ^(h) 第１副搬送波伝送路特性成分、ｐ_i,k ^(h) 第２副搬送波伝送路特性成分、Ｒ_i,k，Ｒ^’ _i,k 複素信号、ｘ_i,k 副搬送波成分、ｙ_i 検出出力、θ_i,k 位相。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an orthogonal frequency division multiplex signal receiving apparatus and a clock recovery method in a receiving system.
[0002]
[Prior art]
FIG. 23 is a block diagram showing a configuration of a conventional orthogonal frequency division multiplex signal receiving apparatus 100. This technique is introduced in, for example, Kimura et al., “Examination of frequency synchronization in OFDM demodulation”, Television Society Technical Report, vol. 20, no. 53, pp. 61-66, Oct. 1996.
[0003]
The A / D conversion unit 1 inputs a clock signal having a predetermined frequency from the clock oscillation unit 9. Based on this clock signal, the received signal is analog / digital converted and output. The received signal is demodulated to a predetermined frequency band by quasi-synchronous detection, and is output from a tuner (not shown), for example. As an example, the i-th symbol r input to the A / D converter 1_iIs shown.
[0004]
The subcarrier frequency correction unit 2 inputs the output of the Fourier transform unit 4. Based on this, the subcarrier frequency error between the transmitted and received signals remaining in the output signal of the A / D converter 1 is corrected and output as a complex signal. The guard period removal unit 3 receives the output of the subcarrier frequency correction unit 2 and removes a signal corresponding to the guard period. Generally, in the transmission symbol of the orthogonal frequency division multiplexing signal, a part of the last part of the effective symbol is added to the head of the symbol as a guard period. Therefore, the effective symbol in each symbol is output by the above processing.
[0005]
The Fourier transform unit 4 performs a discrete Fourier transform on the effective symbol output from the guard period removal unit 3 with a predetermined number of points. The output of the Fourier transform unit 4 represents a component (subcarrier component) for each subcarrier in the orthogonal frequency division multiplexed signal. The data reproducing unit 7 demodulates the output of the Fourier transform unit 4 according to the modulation scheme of each subcarrier. As a result, the transmission data is reproduced. As an example, the output s from the data recovery unit 7 for the data transmitted by the k-th subcarrier in the i-th symbol_{i, k}Is shown.
[0006]
The delay unit 15 receives the output of the subcarrier frequency correction unit 2, delays the signal by one effective symbol, and outputs the delayed signal. The signal in the guard period is a part located at the end of the signal in the effective symbol period. Therefore, if the frequency error of the subcarrier, the frequency error of the sampling clock, and the phase error are all negligible, and the transmission path can be regarded as an ideal transmission path and noise can be ignored, the output of the delay unit 15 and the subcarrier The output of the frequency correction unit 2 can be regarded as the same.
[0007]
The positive frequency pass filter unit 16 outputs a positive frequency domain signal in the complex signal output from the delay unit 15. The negative frequency pass filter unit 17 outputs a negative frequency domain signal in the complex signal output from the delay unit 15. The complex multiplication unit 18 calculates a correlation vector between the output of the subcarrier frequency correction unit 2 and the output of the positive frequency pass filter unit 16. The complex multiplication unit 19 calculates a correlation vector between the output of the subcarrier frequency correction unit 2 and the output of the negative frequency pass filter unit 17.
[0008]
When there is a frequency error in the clock signal, the delay time delayed in the delay unit 15 causes an error with respect to the original delay time. Correspondingly, phase rotation occurs in the correlation vector obtained as the output of the complex multiplication unit 18 and the correlation vector obtained as the output of the complex multiplication unit 19, respectively. Both phase rotations have the same absolute value but different polarities. Since this phase rotation reflects the clock frequency error, the clock frequency error can be corrected by detecting this and adopting a phase-locked loop.
[0009]
Therefore, first, the outputs of the complex multipliers 18 and 19 are integrated by the integrators 20 and 21 during the period corresponding to the guard period in one symbol. Then, the output of the integration unit 20 is subtracted from the output of the integration unit 21 in the subtraction unit 22, and a detection output signal that is a scalar quantity proportional to the frequency error of the clock is output. The loop filter unit 6 limits the frequency band of the detection output signal and outputs it. Based on the output of the loop filter unit 6, the oscillator control unit 8 converts the clock signal into a control signal format necessary for the clock oscillation unit 9 to control the frequency of the clock signal and outputs the control signal format. The clock oscillating unit 9 oscillates based on the output of the oscillator control unit 8 and gives a clock signal to the A / D converter 1.
[0010]
[Problems to be solved by the invention]
The conventional orthogonal frequency division multiplex signal receiving apparatus 100 detects the frequency error of the clock signal and regenerates the clock, and there is a problem that the error cannot be detected for the phase error of the clock.
[0011]
The present invention has been made to solve the above-described problems, and by detecting a clock phase error, highly accurate and stable clock recovery is performed, and errors after data recovery of an orthogonal frequency division multiplexed signal are performed. The purpose is to reduce the rate.
[0012]
[Means for Solving the Problems]
  According to a first aspect of the present invention, there is provided a receiving apparatus for orthogonal frequency division multiplexing signals, wherein a reception signal demodulated from a signal subjected to orthogonal frequency division multiplexing into a predetermined frequency band is sampled at a timing based on a clock signal. An analog / digital conversion unit, a Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the analog / digital conversion unit,A clock phase error detector for obtaining a detection output reflecting the phase error of the clock signal based on the phase between the plurality of subcarrier components in the same symbol;in frontInspectionA clock oscillation unit that outputs a clock signal based on the output.
[0013]
  According to a second aspect of the present invention, there is provided an orthogonal frequency division multiplex signal receiving apparatus for sampling a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal. An analog / digital conversion unit that performs a resampling unit that resamples the output of the analog / digital conversion unit, a Fourier transform unit that obtains a plurality of subcarrier components based on the output of the resampling unit,A clock phase error detector for obtaining a detection output reflecting the phase error of the clock signal based on the phase between the plurality of subcarrier components in the same symbol;Is provided. And beforeInspectionBased on the output, the output of the analog / digital converter is resampled.
[0014]
  The invention according to claim 3 is the invention.,straightAn apparatus for receiving an alternating frequency division multiplexed signal,An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal, and a plurality of subcarriers based on the output of the analog / digital converter A Fourier transform unit for obtaining a component; and a clock oscillation unit for outputting a clock signal based on a detection output reflecting a phase error of the clock signal obtained from the plurality of subcarrier components. Then, a plurality of transmission path characteristics are obtained based on the plurality of subcarrier components having different symbols and different frequencies, and the detection output is obtained based on the phase between the plurality of transmission path characteristics.
[0015]
  The invention according to claim 4 is the invention,straightAn apparatus for receiving an alternating frequency division multiplexed signal,An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal, and a resampling unit that resamples the output of the analog / digital converter And a Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the resampling unit. Then, the output of the analog / digital conversion unit is resampled based on the detection output reflecting the phase error of the clock signal obtained from the plurality of subcarrier components. AlsoA plurality of transmission path characteristics are obtained based on the plurality of subcarrier components having different symbols and different frequencies, and the detection output is obtained based on a phase between the plurality of transmission path characteristics.
[0016]
  The invention according to claim 5 is claimed in claim1 or claim 2The orthogonal frequency division multiplexing signal receiving apparatus according to claim 1, wherein the plurality of subcarrier components in the same symbol used for obtaining the detection output are data in which QPSK modulation is adopted as orthogonal frequency division multiplexing modulation. This is a subcarrier for transmission.
[0017]
According to a sixth aspect of the present invention, there is provided the orthogonal frequency division multiplexing signal receiving apparatus according to the fifth aspect, wherein at least one pair of the subcarrier components for data transmission is used to obtain the detection output. The interval between the at least one pair of the subcarrier components for data transmission is constant.
[0018]
According to a seventh aspect of the present invention, there is provided the orthogonal frequency division multiplex signal receiving apparatus according to the sixth aspect, wherein the clock phase error detector extracts a plurality of subcarrier components for data transmission for each symbol. A data transmission subcarrier component extraction unit, an adjacent data transmission subcarrier component separation means for outputting the at least one pair of data transmission subcarrier components from the plurality of data transmission subcarrier components; A conjugate complex number conversion unit that outputs one conjugate complex signal of one pair of data transmission subcarrier components, the other of the at least one pair of data transmission subcarrier components, and the at least one pair of data transmission subcarrier components A complex multiplier that outputs a complex multiplication result of the subcarrier component with the one conjugate complex signal; and an absolute value of a phase component of the complex multiplication result And a coordinate conversion unit to output the coordinate transformation is performed to fit the 0~π / 4 radians in a plane.
[0019]
According to an eighth aspect of the present invention, there is provided the orthogonal frequency division multiplex signal receiving apparatus according to the seventh aspect, wherein the tangent calculation unit outputs the tangent of the output of the coordinate transformation unit and outputs the tangent. A phase calculation unit that obtains a phase between the at least one pair of subcarrier components for data transmission in the symbol from the output of the unit, and a phase average for obtaining the detection output by obtaining an average value of the phase for each symbol And a control unit.
[0020]
According to a ninth aspect of the present invention, there is provided an orthogonal frequency division multiplex signal receiving apparatus according to the seventh aspect, wherein a tangent calculation unit for obtaining and outputting a tangent of the output of the coordinate conversion unit, and each symbol And a tangent averaging unit that obtains an average value of the outputs of the tangent calculation unit to obtain the detection output.
[0021]
A tenth aspect of the present invention is the orthogonal frequency division multiplex signal receiving apparatus according to the seventh aspect, wherein the imaginary part information extracting unit obtains and outputs the imaginary part of the output of the coordinate transformation unit; An imaginary part averaging unit that obtains an average value of outputs of the imaginary part information extraction unit for each symbol and obtains the detection output is further included.
[0022]
  The invention according to claim 11 is the claim.3 or claim4. The reception apparatus for orthogonal frequency division multiplexing signals according to 4, wherein the detection output is obtained for each symbol using a pilot subcarrier, and the pilot subcarrier has a constant frequency interval within the same symbol. Moreover, the frequency arrangement has a certain offset for each symbol.
[0023]
According to a twelfth aspect of the present invention, there is provided the orthogonal frequency division multiplex signal receiving apparatus according to the eleventh aspect, wherein at least one pair of the pilot subcarriers differing by the offset over a plurality of symbols. A clock phase error detector for obtaining the detection output based on the phase between the components is provided.
[0024]
According to a thirteenth aspect of the present invention, there is provided the orthogonal frequency division multiplex signal receiving apparatus according to the twelfth aspect, wherein the clock phase error detector extracts the pilot subcarrier component for each symbol. A sub-carrier component extraction unit, a division unit that divides the pilot sub-carrier component by known pilot data and outputs a channel characteristic component, and at least one pair that differs by the offset over the plurality of symbols. And an adjacent transmission line characteristic component separation unit that outputs the transmission line characteristic component.
[0025]
According to a fourteenth aspect of the present invention, there is provided the orthogonal frequency division multiplexing signal receiving apparatus according to the thirteenth aspect, wherein the conjugate complex number outputs one conjugate complex signal of the at least one pair of transmission path characteristic components. A conversion unit; a complex multiplication unit that outputs a complex multiplication result of the other of the at least one pair of transmission path characteristic components and the one conjugate complex signal of the at least one pair of transmission path characteristic components; A tangent calculation unit that obtains and outputs a tangent of a complex multiplication result; a phase calculation unit that obtains a phase between the at least one pair of transmission path characteristic components in the symbol from the output of the tangent calculation unit; And a phase averaging unit for obtaining an average value of the phases and obtaining the detection output.
[0026]
A fifteenth aspect of the present invention is the orthogonal frequency division multiplexing signal receiving apparatus according to the thirteenth aspect, wherein the conjugate complex number outputs one conjugate complex signal of the at least one pair of transmission path characteristic components. A conversion unit; a complex multiplication unit that outputs a complex multiplication result of the other of the at least one pair of transmission path characteristic components and the one conjugate complex signal of the at least one pair of transmission path characteristic components; A tangent calculating unit that obtains and outputs the tangent of the complex multiplication result, and a tangent averaging unit that obtains an average value of the outputs of the tangent calculating unit for each symbol and obtains the detection output.
[0027]
  The invention according to claim 16 is the claim.3 or claim5. The orthogonal frequency division multiplex signal receiving apparatus according to claim 4, wherein the plurality of subcarrier components include a plurality of pilot subcarrier components inserted into the received signal for demodulation of the synchronously modulated subcarrier. A transmission path estimation unit that estimates the plurality of transmission path characteristics based on the plurality of pilot subcarrier components; and a clock phase error detection section that calculates the detection output based on the plurality of transmission path characteristics. Prepare.
[0028]
According to a seventeenth aspect of the present invention, there is provided an orthogonal frequency division multiplex signal receiving apparatus according to the sixteenth aspect, wherein an adjacent transmission line characteristic component separation unit that outputs at least one pair of the transmission line characteristic components; A conjugate complex number conversion unit that outputs one conjugate complex signal of the at least one pair of transmission line characteristic components; the other of the at least one pair of transmission line characteristic components; and the at least one pair of transmission line characteristic components. From the output of the complex multiplication unit that outputs a complex multiplication result with the one conjugate complex signal of the one, a tangent calculation unit that obtains and outputs a tangent of the complex multiplication result, and the output of the tangent calculation unit, in the symbol, A phase calculation unit that obtains a phase between at least one pair of transmission path characteristic components, and a phase averaging unit that obtains the average value of the phase for each symbol and obtains the detection output To.
[0029]
According to an eighteenth aspect of the present invention, there is provided an orthogonal frequency division multiplex signal receiving apparatus according to the sixteenth aspect, wherein an adjacent transmission path characteristic component separation unit that outputs at least one pair of the transmission path characteristic components; A conjugate complex number conversion unit that outputs one conjugate complex signal of the at least one pair of transmission line characteristic components; the other of the at least one pair of transmission line characteristic components; and the at least one pair of transmission line characteristic components. A complex multiplication unit that outputs a complex multiplication result with one of the conjugate complex signals, a tangent calculation unit that calculates and outputs a tangent of the complex multiplication result, and an average value of the output of the tangent calculation unit for each symbol. And a tangent averaging unit for obtaining the detection output.
[0030]
According to a nineteenth aspect of the present invention, there is provided the orthogonal frequency division multiplex signal receiving apparatus according to the thirteenth or sixteenth aspect, wherein one real part of the at least one pair of transmission line characteristic components and the From the product of the at least one pair of transmission line characteristic components with the other imaginary part, the one imaginary part of the at least one pair of transmission line characteristic components and the other of the at least one pair of transmission line characteristic components It further includes an imaginary part information generating unit that generates imaginary part information by subtracting a product from the real part, and an imaginary part averaging unit that obtains an average value of the imaginary part information for each symbol and obtains the detection output.
[0031]
  Of the present invention, the one according to claim 20,straightAn apparatus for receiving an alternating frequency division multiplexed signal,An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal, and a plurality of subcarriers based on the output of the analog / digital converter A Fourier transform unit for obtaining a component; and a clock oscillation unit for outputting a clock signal based on a detection output reflecting a phase error of the clock signal obtained from the plurality of subcarrier components. AndWhen the plurality of subcarrier components are differentially modulated, the detection output is obtained based on the phase between the plurality of subcarrier components in the same symbol, and the plurality of subcarrier components are tuned. If it is modulated, the detection output is obtained based on the phase between at least one pair of specific pilot subcarrier components that differ by a predetermined offset over a plurality of symbols, and the specific pilot subcarrier is obtained. The frequency interval in the same symbol is constant, and the frequency arrangement has the predetermined offset for each symbol.
According to a twenty-first aspect of the present invention, there is provided an orthogonal frequency division multiplexing signal receiving apparatus, wherein a reception signal demodulated from a signal subjected to orthogonal frequency division multiplexing into a predetermined frequency band is received at a timing based on a clock signal. An analog / digital conversion unit for sampling, a resampling unit for resampling the output of the analog / digital conversion unit, and a Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the resampling unit. Then, the output of the analog / digital conversion unit is resampled based on the detection output reflecting the phase error of the clock signal obtained from the plurality of subcarrier components. When the plurality of subcarrier components are differentially modulated, the detection output is obtained based on the phase between the plurality of subcarrier components in the same symbol, and the plurality of subcarrier components are In the case of being tuned and modulated, the detection output is obtained based on the phase between at least one pair of specific pilot subcarrier components that differ by a predetermined offset over a plurality of symbols, and the specific pilot subcarrier is obtained. The carrier wave has a constant frequency interval within the same symbol, and the frequency arrangement has the predetermined offset for each symbol.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of an orthogonal frequency division multiplexing signal receiving apparatus 101 according to Embodiment 1 of the present invention. The orthogonal frequency division multiplex signal receiving apparatus 101 is schematically shown as a delay unit 15, a positive frequency pass filter unit 16, and a negative frequency pass filter unit 17 of the conventional orthogonal frequency division multiplex signal receiving apparatus 100 shown in FIG. The complex multipliers 18 and 19, the integrators 20 and 21, and the subtractor 22 are replaced with a clock phase error detector 51.
[0033]
Specifically, the orthogonal frequency division multiplex signal receiving apparatus 101 includes an A / D conversion unit 1, a subcarrier frequency correction unit 2, a guard period removal unit 3, a Fourier transform unit 4, and a data reproduction unit 7.
[0034]
The A / D conversion unit 1 inputs a clock signal having a predetermined frequency from the clock oscillation unit 9. Then, sampling is performed at timing based on the clock signal, and the received signal is converted from analog to digital and output. The received signal is demodulated to a predetermined frequency band by quasi-synchronous detection from the orthogonal frequency division multiplexed signal, and is output from a tuner (not shown), for example. As an example, the i-th symbol r input to the A / D converter 1_iIs shown.
[0035]
FIG. 2 is a graph illustrating a signal waveform input to the A / D converter 1 when the subcarrier frequency is completely synchronized. In the transmission symbol of the orthogonal frequency division multiplexing signal, a part of the last part of the effective symbol is added to the head of the symbol as a guard period.
[0036]
The subcarrier frequency correction unit 2 inputs the output of the Fourier transform unit 4. Based on this, the subcarrier frequency error between the transmitted and received signals remaining in the output signal of the A / D converter 1 is corrected and output as a complex signal. The guard period removal unit 3 receives the output of the subcarrier frequency correction unit 2, removes a signal corresponding to the guard period, and outputs an effective symbol in each symbol.
[0037]
The Fourier transform unit 4 performs a discrete Fourier transform on the effective symbol output from the guard period removal unit 3 with a predetermined number of points. The output of the Fourier transform unit 4 represents a component (subcarrier component) for each subcarrier in the orthogonal frequency division multiplexed signal. As an example, the k-th subcarrier component x in the i-th symbol_{i, k}Is shown.
[0038]
The data reproducing unit 7 demodulates the output of the Fourier transform unit 4 according to the modulation scheme of each subcarrier. As a result, the transmission data is reproduced. As an example, for the data transmitted by the k-th subcarrier in the i-th symbol, the output s from the data reproducing unit 7_{i, k}Is shown.
[0039]
The orthogonal frequency division multiplexing signal receiving apparatus 101 further includes a clock phase error detection unit 51, a loop filter unit 6, an oscillator control unit 8, and a clock oscillation unit 9. The clock phase error detection unit 51 receives the output of the Fourier transform unit 4 and receives the clock signal supplied to the A / D conversion unit 1 based on the phase error between the transmission line characteristic components in the subcarrier component in one symbol. The detection output reflecting the phase error is detected for each symbol, and a detection output signal is output. For example, the detection output y reflecting the phase error of the clock signal in the i-th symbol_iIs shown. Specific configuration examples and operations of the clock phase error detection unit 51 will be described in detail in other embodiments.
[0040]
The loop filter unit 6 limits the frequency band of the detection output signal obtained from the clock phase error detection unit 51 and outputs it. Based on the output of the loop filter unit 6, the oscillator control unit 8 converts the clock signal into a control signal format necessary for the clock oscillation unit 9 to control the frequency of the clock signal. The clock oscillating unit 9 oscillates based on the output of the oscillator control unit 8 and gives a clock signal to the A / D converter 1. Therefore, it can be said that the orthogonal frequency division multiplexing signal receiving apparatus 101 has a phase locked loop with respect to the phase error of the clock signal.
[0041]
When there is a phase error in the clock signal, the signal input to the Fourier transform unit 4 is a signal that is shifted in time with respect to the signal that should be input. Due to the nature of the Fourier transform, the time shift in the time domain appears as a phase rotation term in the frequency domain. In the orthogonal frequency division multiplexing signal receiving apparatus 101, the clock phase error detection unit 51 detects this phase rotation component, thereby detecting the phase error of the clock signal. In addition, since the frequency error of the clock signal can be locally recognized as a phase error, both the phase and the frequency of the clock signal can be obtained by configuring a phase locked loop for the phase error of the clock signal. Can be corrected.
[0042]
As described above, the orthogonal frequency division multiplex signal receiving apparatus 101 has the phase locked loop for the phase error of the clock signal. The error rate after data reproduction is reduced.
[0043]
Embodiment 2. FIG.
FIG. 3 is a block diagram showing a configuration of orthogonal frequency division multiplexing signal receiving apparatus 102 according to Embodiment 2 of the present invention. As an outline, the orthogonal frequency division multiplexing signal receiving apparatus 102 has a resampling section 11 between the A / D conversion section 1 and the subcarrier frequency correction section 2 of the orthogonal frequency division multiplexing signal receiving apparatus 101 shown in FIG. And the oscillator control unit 8 and the clock control unit 9 are replaced with a filter coefficient output unit 10. In the second embodiment, data resampling is performed on the output of the A / D converter 1 while the clock signal used in the A / D converter 1 is kept constant.
[0044]
More specifically, the A / D conversion unit 1, the subcarrier frequency correction unit 2, the guard period removal unit 3, the Fourier transform unit 4, the clock phase error detection unit 51, the loop filter unit 6, and the data reproduction unit 7 are described in the embodiment. It performs the same function as that adopted in 1. The output of the A / D conversion unit 1 is given to the resampling unit 11, and the output of the resampling unit 11 is given to the subcarrier frequency correction unit 2 together with the output of the Fourier transform unit 4. The filter coefficient output unit 10 inputs the output of the loop filter unit 6 and supplies the output to the resampling unit 11.
[0045]
The filter coefficient output unit 10 outputs the coefficient value of the resampling filter for the phase error of the clock signal whose frequency band has been limited, obtained from the loop filter unit 6. For example, the filter coefficient output unit 10 may be configured so that coefficient values for correcting the phase error of the clock are stored in advance in a look-up table and a coefficient corresponding to the input signal is output.
[0046]
The resampling unit 11 includes a resampling filter, and based on the coefficient value of the resampling filter obtained from the filter coefficient output unit 10, the phase error of the clock signal remaining at the output of the A / D conversion unit 1 The component of is corrected. As a result, the output value of the original sampling point with the phase error suppressed is output.
[0047]
As described above, also in the orthogonal frequency division multiplex signal receiving apparatus 102 according to the second embodiment, the phase locked loop is configured for the phase error of the clock signal, so that highly accurate and stable clock recovery is performed. The error rate after data reproduction of the orthogonal frequency division multiplexed signal is reduced.
[0048]
Embodiment 3 FIG.
The third embodiment exemplifies the configuration of the clock phase error detection unit 51 used in the orthogonal frequency division multiplexing signal receiving apparatuses 101 and 102 shown in the first and second embodiments, respectively.
[0049]
FIG. 4 is a block diagram illustrating a configuration of a clock phase error detection unit 51 a that can be employed as the clock phase error detection unit 51. The clock phase error detection unit 51a has a subcarrier component x_{i, k}The data transmission subcarrier component extraction unit 500 and the data transmission subcarrier component extraction unit 500 are input, and one or more pairs of data transmission subcarrier components are output. And a component separation unit 501. Here, the subcarrier for data transmission is a subcarrier used for data transmission. The data here means data intended to be transmitted by the system, such as video information and audio information. In the third embodiment, the phase error of the clock signal is detected using a data transmission subcarrier for each symbol.
[0050]
FIG. 5 is a graph showing the concept of sampling in the A / D converter 1, the broken line indicates the waveform of the received signal input to the A / D converter 1, and the white circle is the phase of the original sampling point, that is, the clock signal. Sampling points when there is no error are shown. When there is no phase error in the clock signal supplied to the A / D converter 1, sampling is performed at the boundary between the guard period and the effective symbol period. In this case, sampling points indicated by double circles, that is, original sampling points within the effective symbol period are output from the Fourier transform unit 4.
[0051]
However, the phase error sT (where T is an effective symbol period and the frequency interval f between adjacent subcarriers is included in the clock signal.₀In the case where there is a different coefficient depending on the phase error of the clock signal: the leading phase is positive), sampling is performed at sampling points indicated by black circles. Therefore, the sampling point output from the Fourier transform unit 4 is a sampling point indicated by a black circle and further surrounded by a white circle, and an undesirable operation of giving the waveform of the guard period to the data reproducing unit 7 also occurs.
[0052]
If the boundary between the guard period and the effective symbol period is a phase reference point, the phase error of the clock signal with respect to the reference point can be defined in the range of −2zπ to 2zπ (z: integer). At this time, the value of the transmission data is set to a_{i, k}, The transfer function of the transmission path for the corresponding subcarrier is H_{i, k}, Where N is the number of points of the discrete Fourier transform executed by the Fourier transform unit 4, the output x of the Fourier transform unit 4_{i, k}Can be approximated by equation (1).
[0053]
[Expression 1]

[0054]
Detection of the phase error of the clock signal can be realized by obtaining the coefficient s in equation (1).
[0055]
First, the data transmission subcarrier component extraction unit 500 extracts and outputs the subcarrier component transmitting data from the output signal of the Fourier transform unit 4. For example, the i-th symbol r input to the A / D converter 1_iFor the subcarrier component x from the Fourier transform unit 4_{i, 0}, X_{i, 1}, ..., x_{i, N-1}Is obtained. However, subcarrier component x_{i, k + 1}Of the subcarrier component x_{i, k}Frequency interval f than the frequency of₀Only expensive.
[0056]
For example, subcarrier component x_{i, 0}, X_{i, 1}, ..., x_{i, N-1}Are output from the Fourier transform unit 4 in this order. Only the data transmission sub-carrier component is extracted from these, and provided to the adjacent data transmission sub-carrier component separation unit 501. The adjacent data transmission subcarrier component separation unit 501 receives the output of the data transmission subcarrier component extraction unit 500, and uses the data transmission first subcarrier component c as a subcarrier component paired at different frequencies._{i, k}And the second subcarrier component p for data transmission_{i, k}Output at least one pair. Here, the data first transmission subcarrier component c_{i, k}Of the second subcarrier component for data transmission p_{i, k}Higher than the frequency of.
[0057]
Data first transmission subcarrier component c_{i, k}Frequency f_cikAnd the second subcarrier component p for data transmission_{i, k}Frequency f_pikAnd the difference from mf₀Then (m ≧ 1), Equation (2) is established for the subcarrier component for data transmission.
[0058]
[Expression 2]

[0059]
The clock phase error detection unit 5 further includes a conjugate complex number conversion unit 502 and a complex multiplication unit 503. The conjugate complex number conversion unit 502 includes a second subcarrier component p for data transmission._{i, k}The conjugate complex number p of_{i, k} ^*The complex multiplier 503 obtains the first subcarrier component c for data transmission._{i, k}And second subcarrier component p for data transmission_{i, k}The conjugate complex number p of_{i, k} ^*Performs complex multiplication with. However, an asterisk (*) appended to the upper right of the symbol represents a conjugate complex number of the complex number to which this is appended.
[0060]
Complex signal R output from complex multiplier 503_{i, k}Is represented by equation (3) based on equations (1) and (2).
[0061]
[Equation 3]

[0062]
The sub-carrier modulation scheme for data transmission is DQPSK (Differentially Encoded Quadrature Phase Shift Keying), π / 4 shift DQPSK, and QPSK (Quadrature Phase Shift Keying). A)_{i, km} ^*・ A_{i, k}= A²(A: signal amplitude). Further, by reducing the value of m, the data first transmission subcarrier component c_{i, k}The transfer function H of the transmission line corresponding to_{i, km}The second subcarrier component p for data transmission_{i, k}The transfer function H of the transmission line corresponding to_{i, k}Can be approximated as In this case, equation (3) can be approximated by equation (4).
[0063]
[Expression 4]

[0064]
In equation (4), l_{i, k}Is the frequency f_pikData modulated with subcarriers of frequency f and frequency f_cikRepresents a phase difference from the data modulated by the sub-carrier, and can take any of 0, 1, 2, and 3.
[0065]
In order to detect the coefficient s so as not to depend on the value of the inter-data phase difference li, k, the clock phase error detection unit 5 further includes a coordinate conversion unit 504. In the coordinate transformation unit 504, the input complex signal R_{i, k}The coordinate axes are converted so that the absolute value of the phase component of falls within 0 to π / 4 radians on the complex coordinate plane.
[0066]
FIG. 6A shows the complex signal R._{i, k}FIG. 6B shows the complex signal R.^' _{i, k}It is a graph which shows each position in a complex coordinate plane. Complex signal R_{i, k}Occupies one of the four quadrants depending on the value of the interphase phase difference li, k, but the complex signal R^' _{i, k}Can set both the real part and the imaginary part positive without depending on the value of the phase difference li, k between the data.
[0067]
Specifically, the coordinate conversion unit 504 receives the input complex signal R._{i, k}Output complex signal R according to the sign and absolute value of the real and imaginary parts of^' _{i, k}Is generated. Specific examples of processing of the coordinate conversion unit 504 are shown in the table below. However, the symbol Re represents the real part of the complex number stored in [] on the right side, and the symbol Im represents the imaginary part of the complex number stored in [] on the right side.
[0068]
[Table 1]

[0069]
And complex signal R^' _{i, k}Is represented by equation (5).
[0070]
[Equation 5]

[0071]
Complex signal R^' _{i, k}The clock phase error detection unit 5 further includes a tangent calculation unit 505 and a phase calculation unit 506 in order to obtain a detection output regarding the clock phase error. Tangent calculation unit 505 generates complex signal R^' _{i, k}Calculate and output the tangent to the phase of. Specifically, for example, Im [R^' _{i, k}] / Re [R^' _{i, k}]. The phase calculation unit 506 inputs the output of the tangent calculation unit 505, and the corresponding phase θ_{i, k}Is output. The phase calculation unit 506 may store the phase corresponding to the tangent in, for example, a look-up table and output a value corresponding to the input. Phase θ_{i, k}Is represented by Equation (6).
[0072]
[Formula 6]

[0073]
Data transmission first subcarrier component c_{i, k}And the second subcarrier component p for data transmission_{i, k}Is a symbol r_iCan be used by updating the subcarrier number k. And the phase θ calculated by updating k within one symbol period_{i, k}The clock phase error detection unit 5 further includes a phase averaging unit 507. The phase averaging unit 507 outputs the phase θ output from the phase calculation unit 506._{i, k}The detection output y reflecting the phase error of the clock signal in the i-th symbol by calculating an average value for the subcarrier number k updated within one symbol period_iIs output. That is, the detection output y reflecting the phase error of the clock signal in the i-th symbol_iIs an average of the phase differences between the subcarriers for data transmission within one symbol, and obviously the value is a scalar quantity proportional to the phase error of the clock signal.
[0074]
In addition, if the expression (2) is satisfied, the data transmission subcarriers are the same distance mf in any pair.₀Therefore, it is possible to avoid the need for correction according to the frequency interval and the occurrence of variations in the detected value for the same clock phase error.
[0075]
Further, by adopting QPSK modulation as orthogonal frequency division multiplexing modulation, the magnitudes of the absolute values of the subcarrier components for data transmission are all equal (denoted as A in equations (4) and (5)). In obtaining the result, there is no need to normalize the size of the subcarrier component for data transmission.
[0076]
As described above, according to the third embodiment, the phase error of the clock signal is detected based on the phase difference between one or more subcarriers in one symbol. Therefore, a highly accurate and stable clock signal can be reproduced in a phase-locked loop that performs clock reproduction.
[0077]
In addition to the data, in many cases, various information such as a pilot used when a signal is reproduced by a demodulator, a pilot for synchronization, and data representing a transmission parameter are transmitted to the subcarrier. However, the number of pilot subcarriers is smaller than that of data transmission subcarriers, and they are arranged at irregular frequency positions. Therefore, compared with the case where the phase error is obtained using the pilot subcarrier, the phase error is obtained using the data transmission subcarrier in the third embodiment, so that the clock phase error can be obtained with high accuracy.
[0078]
Data transmission first subcarrier component c_{i, k}And the second subcarrier component p for data transmission_{i, k}Is a symbol r_iIn this case, the phase averaging unit 507 is not necessary. However, it is desirable to obtain a plurality of the above pairs in order to improve the accuracy of obtaining the phase error.
[0079]
Embodiment 4 FIG.
Also in the fourth embodiment, a configuration of a clock phase error detection unit 51b that can be adopted as the clock phase error detection unit 51 is presented. The clock phase error detection unit 51b detects a clock phase error using not a data transmission subcarrier but a pilot subcarrier (pilot subcarrier), in particular, a pilot subcarrier whose frequency position changes according to a symbol.
[0080]
FIG. 7 is a block diagram illustrating the configuration of the clock phase error detection unit 51b. The clock phase error detection unit 51 b includes a pilot subcarrier component extraction unit 511, which converts the subcarrier component x from the Fourier transform unit 4._{i, k}To extract a certain kind of pilot subcarrier component.
[0081]
In general, pilot subcarriers are often smaller in absolute number than data transmission subcarriers. Therefore, when a general pilot subcarrier is used in the clock phase error detector 51a shown in the third embodiment, it is easily affected by noise. In addition, the frequency distribution of a general pilot subcarrier may be irregular. In this case, since the frequency interval of the subcarriers to be extracted is not constant, there arises a problem that correction according to the frequency interval is necessary and that the detected value varies even for the same clock phase error. Further, when pilot subcarriers arranged at a constant interval are used, the detection value does not vary, but the detection range becomes smaller as the interval increases.
[0082]
However, among the pilot subcarriers, the subcarrier used for demodulating the synchronously modulated subcarrier has a constant frequency interval Mf within the same symbol.₀(F₀Is a frequency interval between adjacent subcarriers), and the frequency arrangement is a constant offset nf for each symbol.₀(Hereinafter referred to as “subcarrier for specific pilot”). FIG. 8 is a schematic diagram showing a symbol including such a pilot, and a different symbol for each row (for example, r_i) Is illustrated. White circles and black circles indicate the positions of the subcarriers, and the subcarrier number k increases toward the right, and the corresponding frequency increases. The frequency interval between adjacent pilot subcarriers in the same symbol is 12f.₀(Ie, M = 12), and the offset of the pilot subcarrier is 3f between adjacent symbols.₀The case where (ie n = 3) is shown. An example of such a pilot is Scattered Pilot in the terrestrial digital TV system in Japan.
[0083]
By using the specific pilot subcarrier, the detection range of the phase error of the clock signal can be expanded as will be described later, and the number of subcarriers used for detecting the phase error can be increased. Therefore, the detection accuracy of the phase error of the clock signal can be improved.
[0084]
Furthermore, when multi-level synchronous modulation other than QPSK, for example, multi-level QAM (Quadrature Amplitude Modulation) is used, detection of the phase error of the extracted data transmission subcarrier becomes complicated. On the other hand, BPSK (Binary Phase Shift Keying) and DBPSK (Differentially Encoded Binary Phase Shift Keying) are usually used as modulation schemes for pilot subcarriers, and the data values are known. In such a case, the circuit scale can be reduced by detecting the phase error of the clock signal using the pilot subcarrier.
[0085]
The clock phase error detector 51b further includes a divider 512, and the pilot subcarrier component x extracted by the pilot subcarrier component extractor 511._{i, k} ^(p)For the known pilot data a_{i, k} ^(p)Divide by. The known pilot data is a known signal representing pilot data corresponding to the extracted pilot subcarrier. Thus, the pilot subcarrier component is normalized, and the phase error of the clock signal can be obtained regardless of the pilot data value.
[0086]
Subcarrier component x_{i, k}Is the pilot subcarrier component x_{i, k} ^(p)If this is expressed by Expression (1), the output of the division unit 512, that is, the normalized pilot subcarrier component x^' _{i, k} ^(p)Is represented by Equation (7), and is also referred to as “transmission path characteristic component” in this specification.
[0087]
[Expression 7]

[0088]
Transmission line characteristic component x^' _{i, k} ^(p)Is the transmission path characteristic H for the corresponding subcarrier._{i, k}And the phase rotation term exp [j2π (k / N) s] reflecting the phase error of the clock signal.
[0089]
The clock phase error detection unit 51b further includes a transmission path characteristic component memory unit 513, and a transmission path characteristic component x^' _{i, k} ^(p)Are stored in the memory for at least one symbol. Desirably, transmission path characteristic components for (M / n-1) different symbols are stored.
[0090]
The clock phase error detection unit 51b further includes an adjacent transmission line characteristic component separation part 514, which receives the output of the transmission line characteristic component memory part 513 and the output of the division part 512, and receives the first transmission line characteristic component c for pilot._{i, k} ^(p)And pilot second transmission line characteristic component p_{i, k} ^(p)Output a pair of
[0091]
FIG. 9 shows the first transmission line characteristic component for pilot c_{i, k} ^(p)And pilot second transmission line characteristic component p_{i, k} ^(p)It is a conceptual diagram which shows a mode that it obtains. The black circles indicate the positions of the pilot subcarriers, the white circles indicate the positions of the subcarriers of the other signals, and the subcarriers obtained from the division unit 512 and the transmission path characteristic component memory unit 513 are indicated by black circles. It corresponds to the position. Here, the specific pilot subcarriers are selected from the subcarriers of subcarrier numbers k = 0, 3, 6, 9, 12, and 15, and in the same pilot, the specific pilot subcarriers have a subcarrier number of 12. The case where it is separated is shown. That is, as in the case described with reference to FIG. 8, the frequency interval between adjacent subcarriers for specific pilots within the same symbol is 12f.₀(That is, M = 12), and the offset of the subcarrier for specific pilot is 3f between adjacent symbols.₀The case where (ie n = 3) is shown.
[0092]
In the i-th symbol, the subcarrier for specific pilot is subcarrier number k = 6, and the transmission path characteristic component x^' _{i, 6} ^(p)Is obtained from the division unit 512. Prior to this, the division unit 512 has already transmitted the channel characteristic component x for the (i−1) -th symbol.^' _i-1,3 ^(p), X^' _i-1,15 ^(p)Is the transmission line characteristic component x for the (i-2) th symbol.^' _i-2,0 ^(p), X^' _i-2,12 ^(p)Is the transmission line characteristic component x for the (i-3) th symbol.^' _i-3,9 ^(p)Are obtained and output from the transmission path characteristic component memory unit 513.
[0093]
Therefore, the adjacent transmission line characteristic component separation unit 514 has x^' _i-2,0 ^(p), X^' _i-1,3 ^(p), X^' _{i, 6} ^(p), X^' _i-3,9 ^(p), X^' _i-2,12 ^(p), X^' _i-1,15 ^(p), And the offset nf of the subcarrier for the specific pilot, although it is spread over different symbols₀A plurality of transmission path characteristic components that are different from each other are obtained. Therefore, when the channel characteristic component for the i-th symbol is obtained from the division unit 512, the first channel characteristic component for pilot c_{i, k} ^(p)And pilot second transmission line characteristic component p_{i, k} ^(p)Can output multiple pairs. For example c_{i, 15} ^(p)= X^' _i-1,15 ^(p), P_{i, 15} ^(p)= X^' _i-2,12 ^(p)The pair, c_{i, 12} ^(p)= X^' _i-2,12 ^(p), P_{i, 12} ^(p)= X^' _i-3,9 ^(p)The pair, c_{i, 9} ^(p)= X^' _i-3,9 ^(p), P_{i, 9} ^(p)= X^' _{i, 6} ^(p)The pair, c_{i, 6} ^(p)= X^' _{i, 6} ^(p), P_{i, 6} ^(p)= X^' _i-1,3 ^(p)The pair, c_{i, 3} ^(p)= X^' _i-1,3 ^(p), C_{i, 3} ^(p)= X^' _i-1,3 ^(p), P_{i, 3} ^(p)= X^' _i-2,0 ^(p)It is a pair.
[0094]
In other words, the transmission path characteristic component for the current symbol output from the division unit 512 and the transmission path characteristic component of the previous symbol output from the transmission path characteristic component memory unit 513 are employed. And transmission path characteristic components whose frequencies are adjacent to each other are output as a pair.
[0095]
The clock phase error detection unit 51b further includes a conjugate complex number conversion unit 515, which is a pilot second pilot channel characteristic component p._{i, k} ^(p)The conjugate complex number p of_{i, k} ^{(p) *}Is output. Then, the second complex multiplier 516 outputs the output p from the conjugate complex number converter 515._{i, k} ^{(p) *}And the first transmission line characteristic component c for pilot from the adjacent transmission line characteristic component separation unit 514_{i, k} ^(p)Performs complex multiplication with. Output R of complex multiplier 516_{i, k} ^(p)Is represented by equation (8) based on equation (7).
[0096]
[Equation 8]

[0097]
The clock phase error detection unit 51b further includes a tangent calculation unit 505, a phase calculation unit 506, and a phase averaging unit 507 that perform the same functions as those employed in the third embodiment. Tangent calculation unit 505 outputs R of complex multiplication unit 516._{i, k} ^(p)Is calculated and output (the value obtained by dividing the imaginary part by the real part). Subsequent processing is the same as in the third embodiment, and the detection output y at the i-th symbol._iCan be obtained.
[0098]
As described above, according to the present embodiment, focusing on the specific pilot subcarriers arranged at equal frequency intervals in one symbol and having an offset for each symbol, the transmission path characteristic component obtained therefrom is Employed over a plurality of symbols, the phase difference between at least one pair of transmission path characteristic components selected from them is detected. Therefore, the frequency interval is smaller than in the case where the specific pilot subcarrier component is obtained only from the same symbol, and therefore, the accuracy of approximation that the transfer functions are approximately equal between the paired transmission line characteristic components is also improved. In addition, it is possible to obtain a large number of subcarriers to be referenced, and it is possible to reproduce a highly accurate and stable clock signal in a phase-locked loop that performs clock reproduction.
[0099]
For the same reason, it is possible to eliminate variations in detection values required when using pilot subcarriers with irregular frequency / time arrangements, and to increase the detection range of the phase error of the clock signal.
[0100]
As shown in FIG. 9, the offset nf is always between adjacent symbols.₀When a pair of separated transmission path characteristic components is obtained, the transmission path characteristic component memory unit 513 may store one symbol. In that case, a pair of pilot first transmission line characteristic components c per symbol_{i, k} ^(p)And pilot second transmission line characteristic component p_{i, k} ^(p)Therefore, the output phase averaging unit 507 is not necessary. However, it is desirable to obtain a plurality of the above pairs in order to improve the accuracy of obtaining the phase error.
[0101]
Embodiment 5 FIG.
In the fifth embodiment, the phase error of the clock is detected based on the output of the transmission path estimation result used when demodulating the synchronously modulated subcarrier. FIG. 10 is a block diagram showing a configuration of orthogonal frequency division multiplexing signal receiving apparatus 103 according to Embodiment 5 of the present invention. As an outline, the clock phase error detection unit 51 shown in FIG. 1 is replaced with the clock phase error detection unit 52, and the data recovery unit 7 of the orthogonal frequency division multiplexing signal receiving apparatus 101 is replaced with the subcarrier demodulation unit 13, respectively. The transmission path estimation unit 12 is added.
[0102]
More specifically, the orthogonal frequency division multiplexing signal receiving apparatus 103 includes an A / D conversion unit 1, a subcarrier frequency correction unit 2, a guard period removal unit 3 that perform the same functions as those employed in Embodiment 1. A Fourier transform unit 4, a loop filter unit 6, an oscillator control unit 8, and a clock oscillator 9 are provided.
[0103]
The transmission path estimation unit 12 receives the subcarrier component x from the Fourier transform unit 4._{i, k}, And the characteristics of the transmission path are estimated based on the pilot subcarrier component inserted to demodulate the synchronously modulated subcarrier. FIG. 11 is a block diagram illustrating the configuration of the transmission path estimation unit 12. Transmission path characteristic component x as in the fourth embodiment^' _{i, k} ^(p)The transmission channel estimation unit 12 is provided with a pilot subcarrier component extraction unit 511 and a division unit 512 for obtaining the above.
[0104]
Transmission path characteristic component x from division unit 512^' _{i, k} ^(p)Is already obtained, the transmission path characteristic components for the (i-1) th and earlier symbols. In order to store these, a transmission path characteristic component memory unit 513 is also provided. Then, the transmission line characteristic components for the plurality of symbols before the i-th symbol are given to the interpolation unit 519.
[0105]
Interpolation section 519 approximates the channel characteristic component obtained for the specific pilot subcarrier to the channel characteristic component for subcarriers other than the specific pilot subcarrier by approximation using interpolation in the time direction and frequency direction. presume. As a result, the transmission path characteristic component h for all subcarriers_{i, k}Is output. For the above interpolation, it is desirable that the transmission path characteristic component memory unit 513 stores transmission path characteristic components for (M / n) different symbols.
[0106]
The subcarrier demodulator 13 generates a subcarrier component x output from the Fourier transform unit 4._{i, k}, Transmission line characteristics h_{i, k}Demodulated based on the reproduced data s_{i, k}Is output. Specifically, s_{i, k}= X_{i, k}/ H_{i, k}Can be obtained.
[0107]
Transmission path characteristics h obtained as described above_{i, 0}~ H_{i, K}(0 ≦ k ≦ K) is given to the clock phase error detector 52, and the detection output y reflecting the phase error of the clock signal_iIs output. FIG. 12 is a block diagram showing a configuration of a clock phase error detection unit 52 a that can be employed in the clock phase error detection unit 52. The clock phase error detection unit 52a has a configuration in which the pilot subcarrier component extraction unit 511, the division unit 512, and the transmission path characteristic component memory unit 513 are excluded from the clock phase error detection unit 51b.
[0108]
Specifically, the clock phase error detection unit 52a has an adjacent transmission line characteristic component separation part 514, and the transmission line characteristic h._{i, 0}~ H_{i, K}To the first subcarrier transmission line characteristic component c_{i, k} ^(h)And the second subcarrier transmission line characteristic component p_{i, k} ^(h)Output at least one pair. Here, the first subcarrier transmission line characteristic component c_{i, k} ^(h)Of the second subcarrier transmission line characteristic component p_{i, k} ^(h)Higher than the frequency of. For example c_{i, k1} ^(h)= H_{i, k1}, P_{i, k1} ^(h)= H_{i, k1-t}(1 ≦ t ≦ k1) can be selected. However, it is desirable that t is small as in the first embodiment, as m is made smaller, the phase error can be obtained more accurately.
[0109]
The clock phase error detection unit 52a further includes a conjugate complex number conversion unit 515, a complex multiplication unit 516, a tangent calculation unit 505, a phase calculation unit 506, and a phase averaging unit 507, each of which has the function described in the third embodiment. Fulfill. That is, the conjugate complex number conversion unit 515 receives the second subcarrier transmission line characteristic component p._{i, k} ^(h)The conjugate complex number p of_{i, k} ^{(h) *}Is output. In the complex multiplier 516, the first subcarrier transmission line characteristic component c_{i, k} ^(h)And conjugate complex number p_{i, k} ^{(h) *}And the complex signal R_{i, k} ^(h)Is output. From this, the tangent calculation unit 505 and the phase calculation unit 506 perform the phase θ_{i, k}Further, the average for the subcarrier number k is calculated by the phase averaging unit 507, and the detection output y for the i-th symbol is calculated._iIs required.
[0110]
As described above, according to the present embodiment, the phase error of the clock signal is detected based on the transmission path characteristic obtained as the output of the transmission path estimation unit required when demodulating the synchronously modulated subcarrier. . Therefore, the number of subcarriers to be referenced can be arbitrarily increased. The phase error of the clock signal can be obtained regardless of the value of the pilot subcarrier component. As a result, a highly accurate and stable clock signal can be reproduced in a phase-locked loop that performs clock reproduction. In addition, the detection range of the phase error of the clock signal can be increased.
[0111]
The pilot subcarriers to be employed in the present embodiment are “arranged at equal frequency intervals within one symbol and arranged for each symbol, like the specific pilot subcarriers employed in the fifth embodiment. It is not always required to have the property that “has an offset”. This is because the phase error of the clock signal is obtained by employing the output of the transmission path estimation unit, which is normally used when demodulating the synchronously modulated subcarrier.
[0112]
In the present embodiment, the detection output y output from the clock phase error detection unit 52a._iThe orthogonal frequency division multiplex signal receiving apparatus 103 that controls the clock signal of the clock oscillating unit 9 based on the above is illustrated. However, like the orthogonal frequency division multiplex signal receiving apparatus 102 shown in the second embodiment, the filter coefficient output unit 10 The resampling unit 11 may be used.
[0113]
Embodiment 6 FIG.
In the sixth embodiment, a technique for detecting a phase error of a clock signal when synchronous modulation and differential modulation are mixed as a subcarrier modulation scheme is presented. However, differential modulation here means DQPSK or π / 4 shift DQPSK, and synchronous modulation means QPSK or multilevel QAM.
[0114]
FIG. 13 is a block diagram showing a configuration of orthogonal frequency division multiplex signal receiving apparatus 104 according to Embodiment 6 of the present invention. The orthogonal frequency division multiplex signal receiver 104 has a configuration in which the clock phase error detector 51 is replaced with the clock phase error detector 53 in the orthogonal frequency division multiplex signal receiver 101 and a modulation scheme identification information decoder 14 is added. ing.
[0115]
The modulation scheme identification information decoding unit 14 receives the subcarrier component x from the Fourier transform unit 4._{i, k}To reproduce the information for identifying the modulation scheme of each subcarrier inserted in the subcarrier. As a result, a modulation system identification signal D indicating whether the modulation system for each subcarrier is differential modulation or synchronous modulation is output. The clock phase error detection unit 53 detects the phase error of the clock signal in accordance with the modulation scheme identification signal D.
[0116]
FIG. 14 is a block diagram showing a configuration of a clock phase error detector 53a that can be employed in the clock phase error detector 53. As shown in FIG. The clock phase error detection unit 53a has a complex signal R.^' _{i, k}The data transmission subcarrier component extraction unit 500, the adjacent data transmission subcarrier component separation unit 501, the conjugate complex number conversion unit 502, which the clock phase error detection unit 51a shown in the third embodiment includes, A complex multiplier 503 and a coordinate converter 504 are provided. And complex signal R^' _{i, k}Is one input of the signal selector 522.
[0117]
The clock phase error detection unit 53a also has a complex signal R._{i, k} ^(p)In order to obtain the above, the clock phase error detection unit 51b shown in the fourth embodiment includes the pilot subcarrier component extraction unit 511, the division unit 512, the transmission path characteristic component memory section 513, and the adjacent transmission path characteristic component separation. Unit 514, conjugate complex number conversion unit 515, and complex multiplication unit 516. And output R_{i, k} ^(p)Is the other input of the signal selector 522.
[0118]
Furthermore, the clock phase error detection unit 53a receives a tangent calculation unit 505 to which the output of the signal selection unit 522 is given, a phase calculation unit 506 to which an output of the tangent calculation unit 505 is given, and a phase θ from the phase calculation unit 506._{i, k}Detection output y_iIs provided. A phase averaging unit 507 is provided.
[0119]
The clock phase error detector 53a includes a signal selector 522 that selects and outputs one of the two inputs according to the modulation scheme identification signal D. Therefore, the clock phase error detection unit 53a, in response to the output from the signal selection unit 522, the clock phase error detection unit 51a (FIG. 4) shown in the third embodiment and the clock phase error shown in the fourth embodiment. It fulfills one of the functions of the detector 51b (FIG. 7).
[0120]
The signal selection unit 522 receives the modulation scheme identification signal D from the subcarrier component x_{i, k}Is determined to be differentially modulated, the output R of the coordinate converter 504^' _{i, k}Subcarrier component x_{i, k}Is determined to be synchronously modulated, the output R of the complex multiplier 516_{i, k} ^(p)Are selected and output.
[0121]
As described above, in this embodiment, the phase error of the clock signal is detected according to the modulation method of the subcarrier. Therefore, according to the present embodiment, it is possible to realize highly accurate clock recovery when receiving an orthogonal frequency division multiplexed signal in which differential modulation and synchronous modulation are mixed.
[0122]
In the present embodiment, the detection output y output from the clock phase error detection unit 53a._iThe orthogonal frequency division multiplex signal receiving device 104 that controls the clock signal of the clock oscillating unit 9 based on the above is illustrated. However, like the orthogonal frequency division multiplex signal receiving device 102 shown in the second embodiment, the filter coefficient output unit 10 The resampling unit 11 may be used.
[0123]
Embodiment 7 FIG.
The seventh embodiment is a modification of the third to sixth embodiments.
[0124]
FIG. 15 is a block diagram showing a modification of the third embodiment of the seventh embodiment, and shows the configuration of the clock phase error detection unit 51c. The clock phase error detection unit 51c has a configuration in which the phase calculation unit 506 and the phase averaging unit 507 of the clock phase error detection unit 51a shown in FIG. The clock phase error detection unit 51c can also be employed as the clock phase error detection unit 51 included in the orthogonal frequency division multiplexing signal receiving apparatuses 101 and 102.
[0125]
FIG. 16 is a block diagram showing a modification of the fourth embodiment of the seventh embodiment, and shows the configuration of the clock phase error detector 51d. The clock phase error detection unit 51d has a configuration in which the phase calculation unit 506 and the phase averaging unit 507 of the clock phase error detection unit 51b shown in FIG. The clock phase error detection unit 51d can also be employed as the clock phase error detection unit 51 provided in the orthogonal frequency division multiplexing signal receiving apparatuses 101 and 102.
[0126]
FIG. 17 is a block diagram showing a modification of the fifth embodiment of the seventh embodiment, and shows the configuration of the clock phase error detection unit 52b. The clock phase error detection unit 52b has a configuration in which the phase calculation unit 506 and the phase averaging unit 507 of the clock phase error detection unit 52a shown in FIG. The clock phase error detector 52b can also be employed as the clock phase error detector 52 provided in the orthogonal frequency division multiplex signal receiving apparatus 103.
[0127]
FIG. 18 is a block diagram showing a modification of the sixth embodiment of the seventh embodiment, and shows the configuration of the clock phase error detection unit 53b. The clock phase error detection unit 53 ′ has a configuration in which the phase calculation unit 506 and the phase averaging unit 507 of the clock phase error detection unit 53 a shown in FIG. 14 are replaced with a tangent averaging unit 508. The clock phase error detection unit 53b can also be employed as the clock phase error detection unit 53 provided in the orthogonal frequency division multiplex signal receiving apparatus 104.
[0128]
Tangent averaging unit 508 receives the output of tangent calculation unit 505 as input, and calculates the average value of the tangents of the phase information calculated within one symbol period. Since the result is a scalar quantity that reflects the phase error of the clock signal, this is the detection output y for the i-th symbol._iCan be treated as
[0129]
As described above, in this embodiment, the output y of the clock phase error detectors 51, 52, and 53 is obtained by averaging the output of the tangent calculator 505 for one symbol period._iAnd Therefore, there is no need to obtain the phase from the tangent, and the circuit scale can be reduced.
[0130]
Embodiment 8 FIG.
The eighth embodiment is a further modification of the seventh embodiment as a modification of the third embodiment. FIG. 19 is a block diagram showing the configuration of the clock phase error detection unit 51e. The clock phase error detection unit 51e can be employed as the clock phase error detection unit 51 provided in the orthogonal frequency division multiplexing signal receiving apparatuses 101 and 102.
[0131]
The clock phase error detection unit 51e is configured by replacing the tangent calculation unit 505 and the tangent averaging unit 508 of the clock phase error detection unit 51c shown in FIG. 15 with an imaginary part information extraction unit 509 and an imaginary part averaging unit 510, respectively. have.
[0132]
The clock phase error detector 51e receives a complex signal R from the coordinate converter in the same manner as the clock phase error detectors 51a and 51c.^' _{i, k}Get. Then, the imaginary part information extracting unit 509 outputs a complex signal R^' _{i, k}Imaginary part Im [R^' _{i, k}] Is output. This is because the complex signal R is output from the tangent calculation unit 505 of the clock phase error detection units 51a and 51c.^' _{i, k}Real part of Re [R^' _{i, k}] Is multiplied. The imaginary part averaging unit 510 has an imaginary part Im [R^' _{i, k}] For the subcarrier number k is output. Since the result is a scalar quantity that reflects the phase error of the clock signal, this is the detection output y for the i-th symbol._iCan be treated as
[0133]
As described above, in this embodiment, the average value of one symbol of the imaginary part information is used as the output of the clock phase error detection unit 51. Accordingly, there is no need to obtain the tangent or phase, and the circuit scale can be reduced.
[0134]
Embodiment 9 FIG.
The ninth embodiment is a further modification of the seventh embodiment as a modification of the fourth embodiment. FIG. 20 is a block diagram showing a configuration of the clock phase error detection unit 51f. The clock phase error detection unit 51f can be employed as the clock phase error detection unit 51 included in the orthogonal frequency division multiplexing signal receiving apparatuses 101 and 102.
[0135]
The clock phase error detector 51f includes a conjugate complex number converter 515, a complex multiplier 516, a tangent calculator 505, and a tangent averager 508 of the clock phase error detector 51d shown in FIG. The imaginary part averaging unit 510 is replaced.
[0136]
Similarly to the clock phase error detectors 51b and 51d, the clock phase error detector 51f receives the pilot first transmission line characteristic component c from the adjacent transmission line characteristic component separator 514._{i, k} ^(p)And pilot second transmission line characteristic component p_{i, k} ^(p)Get. The imaginary part information generating multiplication unit 517 inputs these, and the imaginary part information q based on the equation (9)._{i, k} ^(p)Is calculated and output.
[0137]
[Equation 9]

[0138]
In other words, the imaginary part information q_{i, k} ^(p)Is the value of the tangent obtained from the tangent calculation unit 505 in the clock phase error detection units 51b and 51d (Re [c_{i, k} ^(p)] ・ Re [p_{i, k} ^(p)] + Im [c_{i, k} ^(p)] ・ Im [p_{i, k} ^(p)]). The imaginary part averaging unit 510 has imaginary part information q._{i, k} ^(p)Are averaged for the subcarrier number k and output. Since the result is a scalar quantity that reflects the phase error of the clock signal, this is the detection output y for the i-th symbol._iCan be treated as
[0139]
As described above, in this embodiment, the average value of one symbol of the imaginary part information is used as the output of the clock phase error detection unit 51. Therefore, as in complex multiplication (Re [c_{i, k} ^(p)] ・ Re [p_{i, k} ^(p)] + Im [c_{i, k} ^(p)] ・ Im [p_{i, k} ^(p)]), And there is no need to obtain the tangent or phase, and the circuit scale can be reduced.
[0140]
Embodiment 10 FIG.
The tenth embodiment is a further modification of the seventh embodiment as a modification of the fifth embodiment. FIG. 21 is a block diagram showing the configuration of the clock phase error detection unit 52c. The clock phase error detection unit 52c can be employed as the clock phase error detection unit 52 provided in the orthogonal frequency division multiplexing signal receiving apparatus 103.
[0141]
The clock phase error detector 52c includes a conjugate complex number converter 515, a complex multiplier 516, a tangent calculator 505, and a tangent averaging unit 508 of the clock phase error detector 52b shown in FIG. The imaginary part averaging unit 510 is replaced.
[0142]
Similarly to the clock phase error detectors 52a and 52b, the clock phase error detector 52c is connected to the first transmission line characteristic component c from the adjacent transmission line characteristic component separator 514._{i, k} ^(h)And the second transmission line characteristic component p_{i, k} ^(h)Get. The imaginary part information generating multiplication unit 517 inputs these, and based on the equation (10), the imaginary part information q_{i, k} ^(h)Is calculated and output.
[0143]
[Expression 10]

[0144]
In other words, the imaginary part information q_{i, k} ^(h)Is the value of the tangent obtained from the tangent calculation unit 505 in the clock phase error detection units 52a and 52b (Re [c_{i, k} ^(h)] ・ Re [p_{i, k} ^(h)] + Im [c_{i, k} ^(h)] ・ Im [p_{i, k} ^(h)]). The imaginary part averaging unit 510 has imaginary part information q._{i, k} ^(h)Are averaged for the subcarrier number k and output. Since the result is a scalar quantity that reflects the phase error of the clock signal, this is the detection output y for the i-th symbol._iCan be treated as
[0145]
As described above, in this embodiment, the average value of one symbol of the imaginary part information is used as the output of the clock phase error detection unit 51. Therefore, as in complex multiplication (Re [c_{i, k} ^(h)] ・ Re [p_{i, k} ^(h)] + Im [c_{i, k} ^(h)] ・ Im [p_{i, k} ^(h)]), And there is no need to obtain the tangent or phase, and the circuit scale can be reduced.
[0146]
Embodiment 11 FIG.
The eleventh embodiment is a further modification of the seventh embodiment as a modification of the sixth embodiment. FIG. 22 is a block diagram showing a configuration of the clock phase error detection unit 53c. The clock phase error detection unit 53c can be employed as the clock phase error detection unit 53 provided in the orthogonal frequency division multiplex signal receiving apparatus 104.
[0147]
The clock phase error detection unit 53c has a configuration in which the tangent calculation unit 505 and the tangent averaging unit 508 of the clock phase error detection unit 53b shown in FIG. 18 are replaced with an imaginary part information extraction unit 509 and an imaginary part averaging unit 510. is doing.
[0148]
Accordingly, the signal selection unit 522 outputs the output R of the coordinate conversion unit 504 according to the modulation system identification signal D.^' _{i, k}Is output in the same manner as in the eighth embodiment.^' _{i, k}] Is provided to the imaginary part averaging unit 510. Further, the signal selection unit 522 outputs the output R of the complex multiplication unit 516 according to the modulation scheme identification signal D._{i, k} ^(p)Is output in the same manner as in the ninth embodiment._{i, k} ^(p)Is provided to the imaginary part averaging unit 510.
[0149]
As described above, in this embodiment, the 1-symbol average value of the imaginary part information is used as the output of the clock phase error detection unit 5. Accordingly, a circuit for obtaining the tangent or phase is not necessary, and the circuit scale can be reduced.
[0150]
【The invention's effect】
    Claim 1 of the present inventionTo claim 4The orthogonal frequency division multiplex signal receiving apparatus according to (1) has a phase-locked loop for the phase error of the clock signal, so that highly accurate and stable clock recovery can be performed. The frequency error of the clock signal can also be regarded locally as a phase error. Therefore, the error rate after data reproduction of the orthogonal frequency division multiplexed signal is reduced.
[0151]
  MoreoverA large number of subcarriers for obtaining the phase error of the clock signal can be employed, and a detection output reflecting the phase error of the clock signal is obtained with high accuracy.
[0152]
According to the orthogonal frequency division multiplex signal receiving apparatus of the present invention, since the absolute values of the subcarrier components for data transmission are all equal, the detection output reflecting the phase error of the clock signal is provided. When obtaining, there is no need to normalize with the magnitude of the subcarrier component for data transmission.
[0153]
According to the orthogonal frequency division multiplexing signal receiving apparatus of the present invention, the correction according to the frequency interval is required, or the detection value varies with respect to the phase error of the same clock signal. Can be avoided.
[0154]
According to the orthogonal frequency division multiplexing signal receiving apparatus of the present invention, the detection output reflecting the phase error of the clock signal is obtained irrespective of the phase difference between the data of the subcarrier components for data transmission. be able to.
[0155]
According to the orthogonal frequency division multiplexing signal receiving apparatus of the present invention, the phase error of the clock signal can be obtained based on the complex-transformed complex multiplication result.
[0156]
According to the orthogonal frequency division multiplex signal receiving apparatus of the ninth aspect of the present invention, there is no need to obtain the phase based on the subcarrier component for data transmission.
[0157]
According to the orthogonal frequency division multiplex signal receiving apparatus of the tenth aspect of the present invention, it is not necessary to obtain the tangent or phase based on the subcarrier component for data transmission.
[0158]
According to the orthogonal frequency division multiplexing signal receiving apparatus of the present invention, the phase error of the clock signal is obtained for each symbol using a pilot subcarrier having a regular frequency / time arrangement. Therefore, the phase error of the clock signal can be obtained with higher accuracy than in the case where the phase difference is detected by using pilot subcarriers with irregular frequency / time arrangement.
[0159]
According to the orthogonal frequency division multiplex signal receiving apparatus of the twelfth aspect of the present invention, the detection output reflecting the phase error of the clock signal can be obtained for each symbol using the pilot subcarrier, A large number of subcarriers for obtaining the phase error can be employed.
[0160]
According to the orthogonal frequency division multiplexing signal receiving apparatus according to claims 13 and 14 of the present invention, the phase error of the clock signal can be obtained irrespective of the value of the pilot subcarrier component.
[0161]
According to the orthogonal frequency division multiplex signal receiving apparatus of the fifteenth aspect of the present invention, there is no need to obtain the phase based on the complex multiplication result.
[0162]
According to the orthogonal frequency division multiplexing signal receiving apparatus according to claims 16 and 17 of the present invention, the output of the transmission path estimation unit normally used for demodulating the synchronously modulated subcarrier is adopted. A detection output that reflects the phase error of the clock signal is required. Further, a large number of subcarriers for obtaining the phase error of the clock signal can be employed, and a detection output that reflects the phase error of the clock signal is obtained with high accuracy.
[0163]
According to the orthogonal frequency division multiplex signal receiving apparatus of the eighteenth aspect of the present invention, there is no need to obtain the phase based on the complex multiplication result.
[0164]
According to the orthogonal frequency division multiplex signal receiving apparatus of the nineteenth aspect of the present invention, there is no need to obtain complex multiplication, tangent, or phase.
[0165]
  Claim 20 of the present invention., Claim 21According to the receiving apparatus for orthogonal frequency division multiplexing signals according to the above, it is possible to realize highly accurate clock recovery when receiving an orthogonal frequency division multiplexing signal in which differential modulation and synchronous modulation are mixed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.
FIG. 2 is a graph showing the operation of the first embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a third embodiment of the present invention.
FIG. 5 is a graph showing the operation of the third embodiment of the present invention.
FIG. 6 is a graph showing the operation of the third embodiment of the present invention.
FIG. 7 is a block diagram showing a configuration of a fourth embodiment of the present invention.
FIG. 8 is a schematic diagram showing the operation of the fourth embodiment of the present invention.
FIG. 9 is a conceptual diagram showing the operation of the fourth embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of a fifth embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration of a fifth embodiment of the present invention.
FIG. 12 is a block diagram showing a configuration of a fifth embodiment of the present invention.
FIG. 13 is a block diagram showing a configuration of a sixth embodiment of the present invention.
FIG. 14 is a block diagram showing a configuration of a sixth embodiment of the present invention.
FIG. 15 is a block diagram showing a configuration of a seventh embodiment of the present invention.
FIG. 16 is a block diagram showing a configuration of a seventh embodiment of the present invention.
FIG. 17 is a block diagram showing a configuration of a seventh embodiment of the present invention.
FIG. 18 is a block diagram showing a configuration of a seventh embodiment of the present invention.
FIG. 19 is a block diagram showing a configuration of an eighth embodiment of the present invention.
FIG. 20 is a block diagram showing a configuration of a ninth embodiment of the present invention.
FIG. 21 is a block diagram showing the configuration of the tenth embodiment of the present invention.
FIG. 22 is a block diagram showing a configuration of an eleventh embodiment of the present invention.
FIG. 23 is a block diagram showing a configuration of a conventional technique.
[Explanation of symbols]
a_{i, k} ^(p)  Known pilot data, c_{i, k}  First subcarrier component for data transmission, p_{i, k}  Second subcarrier component for data transmission, c_{i, k} ^(p)  First transmission line characteristic component for pilot, p_{i, k} ^(p)  Second transmission line characteristic component for pilot, c_{i, k} ^(h)  First subcarrier transmission line characteristic component, p_{i, k} ^(h)  Second subcarrier transmission line characteristic component, R_{i, k}, R^' _{i, k}  Complex signal, x_{i, k}  Subcarrier component, y_i  Detection output, θ_{i, k}  phase.

Claims (21)

An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal;
A Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the analog / digital conversion unit;
A clock phase error detector for obtaining a detection output reflecting the phase error of the clock signal based on the phase between the plurality of subcarrier components in the same symbol;
Receiver of an orthogonal frequency division multiplexed signal and a clock oscillation unit that outputs a clock signal based on the previous dangerous out output. An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal;
A resampling unit for resampling the output of the analog / digital conversion unit;
A Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the resampling unit ;
A clock phase error detector for obtaining a detection output reflecting the phase error of the clock signal based on the phase between the plurality of subcarrier components in the same symbol ,
Resampling the output of the analog / digital conversion unit based on previous dangerous out output, the receiving apparatus of orthogonal frequency division multiplexed signal. An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal;
A Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the analog / digital conversion unit;
A clock oscillation unit for outputting a clock signal based on a detection output reflecting a phase error of the clock signal obtained from the plurality of subcarrier components;
With
A plurality of transmission line characteristics are obtained based on the plurality of subcarrier components of different symbols and different frequencies,
An apparatus for receiving an orthogonal frequency division multiplex signal , wherein the detection output is obtained based on a phase between the plurality of transmission path characteristics . An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal;
A resampling unit for resampling the output of the analog / digital conversion unit;
A Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the resampling unit;
With
Re-sampling the output of the analog / digital converter based on the detection output reflecting the phase error of the clock signal determined from the plurality of sub-carrier components;
A plurality of transmission path characteristics are obtained based on the plurality of subcarrier components having different symbols and different frequencies,
The detection output is obtained based on the phase between the plurality of channel characteristics, the receiving apparatus of the Cartesian frequency division multiplexed signal. Wherein the plurality of sub-carrier components in the same symbols used for determining the detection output is data transmission subcarriers QPSK system modulation is employed as the orthogonal frequency division multiplexing modulation, claim 1 or claim 2 An orthogonal frequency division multiplex signal receiving apparatus as described. At least one pair of the subcarrier components for data transmission is used to determine the detection output;
6. The orthogonal frequency division multiplex signal receiver according to claim 5, wherein an interval between the at least one pair of subcarrier components for data transmission is constant. The clock phase error detector is
A subcarrier component extraction unit for data transmission that extracts a plurality of subcarrier components for data transmission for each symbol;
An adjacent data transmission subcarrier component separating means for outputting the at least one pair of data transmission subcarrier components from the plurality of data transmission subcarrier components;
A conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of data transmission subcarrier components;
A complex multiplier that outputs a complex multiplication result of the other of the at least one pair of data transmission subcarrier components and the one conjugate complex signal of the at least one pair of data transmission subcarrier components;
7. The reception of the orthogonal frequency division multiplex signal according to claim 6, further comprising: a coordinate conversion unit that performs coordinate conversion that outputs an absolute value of a phase component of the complex multiplication result within 0 to π / 4 radians on a complex coordinate plane. apparatus. A tangent calculation unit that calculates and outputs a tangent of the output of the coordinate conversion unit;
A phase calculation unit that obtains a phase between the at least one pair of data transmission subcarrier components in the symbol from the output of the tangent calculation unit;
The orthogonal frequency division multiplexing signal receiving apparatus according to claim 7, further comprising: a phase averaging unit that obtains the average value of the phase for each symbol and obtains the detection output. A tangent calculation unit that calculates and outputs a tangent of the output of the coordinate conversion unit;
The orthogonal frequency division multiplex signal receiver according to claim 7, further comprising: a tangent averaging unit that obtains an average value of outputs of the tangent calculation unit for each symbol to obtain the detection output. An imaginary part information extraction unit that obtains and outputs an imaginary part of the output of the coordinate conversion unit;
The orthogonal frequency division multiplex signal receiving apparatus according to claim 7, further comprising: an imaginary part averaging unit that obtains an average value of an output of the imaginary part information extraction unit for each symbol to obtain the detection output. The detection output is obtained for each symbol using a pilot subcarrier,
5. The orthogonal frequency division multiplexing signal receiving apparatus according to claim 3 , wherein the pilot subcarrier has a constant frequency interval in the same symbol and a frequency arrangement having a constant offset for each symbol. . The orthogonal frequency division according to claim 11, further comprising: a clock phase error detection unit that obtains the detection output based on a phase between at least one pair of pilot subcarrier components that differ by the offset over a plurality of symbols. Multiple signal receiver. The clock phase error detector is
A pilot subcarrier component extraction unit for extracting the pilot subcarrier component for each symbol;
A division unit that divides the pilot subcarrier component by known pilot data and outputs a transmission line characteristic component;
13. The orthogonal frequency division multiplex signal receiver according to claim 12, further comprising: an adjacent transmission path characteristic component separation unit that outputs at least one pair of the transmission path characteristic components that differ by the offset over the plurality of symbols. . A conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission path characteristic components;
A complex multiplier that outputs a complex multiplication result between the other of the at least one pair of transmission line characteristic components and the one conjugate complex signal of the at least one pair of transmission line characteristic components;
A tangent calculation unit for obtaining and outputting a tangent of the complex multiplication result;
A phase calculation unit that obtains a phase between the at least one pair of transmission line characteristic components in the symbol from the output of the tangent calculation unit;
The orthogonal frequency division multiplexing signal receiving apparatus according to claim 13, further comprising: a phase averaging unit that obtains the average value of the phase for each symbol and obtains the detection output. A conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission path characteristic components;
A complex multiplier that outputs a complex multiplication result between the other of the at least one pair of transmission line characteristic components and the one conjugate complex signal of the at least one pair of transmission line characteristic components;
A tangent calculation unit for obtaining and outputting a tangent of the complex multiplication result;
The orthogonal frequency division multiplex signal receiving apparatus according to claim 13, further comprising: a tangent averaging unit that obtains an average value of outputs of the tangent calculation unit for each symbol to obtain the detection output. The plurality of subcarrier components include a plurality of pilot subcarrier components inserted into the received signal for demodulation of a synchronously modulated subcarrier,
A transmission path estimator for estimating the plurality of transmission path characteristics based on the plurality of pilot subcarrier components;
5. The orthogonal frequency division multiplex signal receiving apparatus according to claim 3 , further comprising a clock phase error detection unit that obtains the detection output based on the plurality of transmission path characteristics. An adjacent transmission line characteristic component separation unit that outputs at least one pair of the transmission line characteristic components;
A conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission path characteristic components;
A complex multiplier that outputs a complex multiplication result between the other of the at least one pair of transmission line characteristic components and the one conjugate complex signal of the at least one pair of transmission line characteristic components;
A tangent calculation unit for obtaining and outputting a tangent of the complex multiplication result;
A phase calculation unit that obtains a phase between the at least one pair of transmission line characteristic components in the symbol from the output of the tangent calculation unit;
The orthogonal frequency division multiplexing signal receiving apparatus according to claim 16, further comprising: a phase averaging unit that obtains an average value of the phase for each symbol and obtains the detection output. An adjacent transmission line characteristic component separation unit that outputs at least one pair of the transmission line characteristic components;
A conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission path characteristic components;
A complex multiplier that outputs a complex multiplication result between the other of the at least one pair of channel characteristic components and one of the conjugate complex signals of the at least one pair of channel characteristic components;
A tangent calculation unit for obtaining and outputting a tangent of the complex multiplication result;
The orthogonal frequency division multiplex signal receiving apparatus according to claim 16, further comprising: a tangent averaging unit that obtains an average value of outputs of the tangent calculation unit for each symbol to obtain the detection output. From the product of one real part of the at least one pair of transmission line characteristic components and the other imaginary part of the at least one pair of transmission line characteristic components, the one of the at least one pair of transmission line characteristic components is An imaginary part information generating unit that generates an imaginary part information by subtracting a product of an imaginary part and the other real part of the at least one pair of transmission line characteristic components;
The orthogonal frequency division multiplex signal receiving apparatus according to claim 13 or 16, further comprising an imaginary part averaging unit that obtains an average value of the imaginary part information for each symbol and obtains the detection output. An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal;
A Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the analog / digital conversion unit;
A clock oscillation unit for outputting a clock signal based on a detection output reflecting a phase error of the clock signal obtained from the plurality of subcarrier components;
With
If the plurality of subcarrier components are differentially modulated, the detection output is obtained based on the phase between the plurality of subcarrier components in the same symbol,
When the plurality of subcarrier components are tuned and modulated, the detection output is calculated based on the phase between at least one pair of specific pilot subcarrier components that differ by a predetermined offset over a plurality of symbols. Seeking
The subcarriers for a particular pilot, a frequency interval within the same symbol is constant and whose frequency allocation has said predetermined offset for each symbol, the receiving apparatus of the Cartesian frequency division multiplexed signal.   An analog / digital converter that samples a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal;
  A Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the analog / digital conversion unit;
  A clock oscillation unit for outputting a clock signal based on a detection output reflecting a phase error of the clock signal obtained from the plurality of subcarrier components;
With
  If the plurality of subcarrier components are differentially modulated, the detection output is obtained based on the phase between the plurality of subcarrier components in the same symbol,
  When the plurality of subcarrier components are tuned and modulated, the detection output is calculated based on the phase between at least one pair of specific pilot subcarrier components that differ by a predetermined offset over a plurality of symbols. Seeking
  The specific pilot subcarrier is an orthogonal frequency division multiplexing signal receiving apparatus in which frequency intervals within the same symbol are constant and the frequency arrangement has the predetermined offset for each symbol.

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