JP2002280996A - Receiver for orthogonal frequency division multiplex signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver that regenerates transmission data from a signal, subjected to orthogonal frequency division multiplex processing, conducts stable recovery of the clocks with high accuracy and reduces the error rate after data regeneration. SOLUTION: A phase error of the clock is detected by detecting the phase rotation amount of each sub carrier in one symbol from the Fourier transform output of a received orthogonal frequency division multiplex signal, and phase- locked loop corrects the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal frequency division multiplexed signal receiving apparatus and a clock recovery method in a receiving method.

[0002]

2. Description of the Related Art FIG. 23 is a block diagram showing a configuration of a conventional orthogonal frequency division multiplex signal receiving apparatus 100. Such techniques are described in, for example, Kimura et al., "Study of Frequency Synchronization in OFDM Demodulation," Television Society Technical Report, vol. 20, n.
o.53, pp.61-66, Oct. 1996.

The A / D converter 1 inputs a clock signal having a predetermined frequency from a clock oscillator 9. Then, based on this clock signal, the received signal is converted from analog to digital and output. The received signal is demodulated to a predetermined frequency band by quasi-synchronous detection, and is output from, for example, a tuner (not shown). As an example, the i-th symbol r _i input to the A / D converter 1 is shown.

[0004] The sub-carrier frequency correction unit 2 receives the output of the Fourier transform unit 4. And based on this, A / D
The subcarrier frequency error between the transmission and reception signals remaining in the output signal of the conversion unit 1 is corrected and output as a complex signal. The guard period removing unit 3 receives the output of the subcarrier frequency correcting unit 2 and removes a signal corresponding to the guard period. Generally, a transmission symbol of an orthogonal frequency division multiplex signal has a part of the last part of an effective symbol added to the beginning of the symbol as a guard period. Therefore, by the above-described processing, an effective symbol in each symbol is output.

The Fourier transform unit 4 includes a guard period removing unit 3
Performs a discrete Fourier transform with a predetermined number of points on the effective symbols output from. The output of the Fourier transformer 4 represents a component (subcarrier component) for each subcarrier in the orthogonal frequency division multiplexed signal. Data playback unit 7
Performs demodulation on the output of the Fourier transform unit 4 according to the modulation method of each subcarrier. As a result, the transmission data is reproduced. As an example, in the i-th symbol, the k-th symbol
The output s _{i, k} from the data recovery unit 7 for the data transmitted by the subcarrier is shown.

The delay section 15 receives the output of the sub-carrier frequency correction section 2, delays the signal by one effective symbol, and outputs the delayed signal. The signal in the guard period is a part located at the end of the signal in the effective symbol period. Therefore, the frequency error of the sub-carrier, the frequency error of the sampling clock, and the phase error can all be ignored. If the transmission path can be regarded as an ideal transmission path and the noise can be ignored, the output of the delay unit 15 and the sub-carrier The output of the frequency correction unit 2 can be regarded as the same.

[0007] The positive frequency pass filter section 16 outputs a signal in the positive frequency domain of the complex signal output from the delay section 15. The negative frequency pass filter unit 17 outputs a signal in the negative frequency domain of the complex signal output from the delay unit 15. The complex multiplication unit 18 calculates a correlation vector between the output of the subcarrier frequency correction unit 2 and the output of the positive frequency pass filter unit 16. The complex multiplication unit 19 calculates a correlation vector between the output of the subcarrier frequency correction unit 2 and the output of the negative frequency pass filter unit 17.

When a frequency error exists in the clock signal, the delay time delayed in the delay unit 15 causes an error with respect to the original delay time. Correspondingly, a phase rotation occurs in the correlation vector obtained as the output of the complex multiplier 18 and the correlation vector obtained as the output of the complex multiplier 19, respectively. The two phase rotations have the same absolute value but different polarities. Since this phase rotation reflects the clock frequency error, the clock rotation error can be corrected by detecting this and employing a phase locked loop.

Therefore, first, the outputs of the complex multipliers 18 and 19 are integrated by the integrators 20 and 21 during a period corresponding to a guard period in one symbol. Then, the output of the integrator 20 is subtracted from the output of the integrator 21 in the subtractor 22, and a detection output signal that is a scalar amount proportional to the clock frequency error is output. Loop filter section 6
Outputs a signal with the frequency band of the detection output signal limited. The oscillator control unit 8 converts the output into a control signal format necessary for the clock oscillation unit 9 to control the frequency of the clock signal based on the output of the loop filter unit 6 and outputs the control signal. Then, the clock oscillating unit 9 performs an oscillating operation based on the output of the oscillator control unit 8, and supplies a clock signal to the A / D conversion unit 1.

[0010]

[SUMMARY OF THE INVENTION] In the receiving apparatus 100 of a conventional orthogonal frequency division multiplex signal, and a clock is reproduced by detecting a frequency error of the clock signal, the error can not be detected with respect to the clock of the phase error There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and detects a clock phase error to perform stable clock recovery with high accuracy and to reproduce data of an orthogonal frequency division multiplexed signal. The purpose is to reduce the error rate later.

[0012]

Means for Solving the Problems Claim 1 of the present invention
The present invention relates to an orthogonal frequency division multiplexed signal receiving apparatus, comprising: an analog / digital converter for sampling a received signal demodulated from an orthogonal frequency division multiplexed signal into a predetermined frequency band at a timing based on a clock signal; A Fourier transform unit for obtaining a plurality of subcarrier components based on the output of the analog / digital converter, and a clock signal based on a detection output reflecting a phase error of the clock signal obtained from the plurality of subcarrier components. And a clock oscillating unit for outputting.

According to a second aspect of the present invention, there is provided an apparatus for receiving an orthogonal frequency division multiplexed signal, wherein a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal is based on a clock signal. An analog / digital converter for sampling at a timing, a resampling unit for resampling the output of the analog / digital converter, and a Fourier transformer for obtaining a plurality of subcarrier components based on the output of the resampling unit are provided. . Then, the output of the analog / digital converter is resampled based on a detection output reflecting a phase error of the clock signal obtained from the plurality of subcarrier components.

According to a third aspect of the present invention,
The orthogonal frequency division multiplexed signal receiving apparatus according to claim 1 or 2, further comprising a clock phase error detection unit that obtains the detection output based on a phase between the plurality of subcarrier components in the same symbol. Prepare.

According to a fourth aspect of the present invention,
The orthogonal frequency division multiplexed signal receiving apparatus according to claim 1, wherein a plurality of transmission path characteristics are obtained based on the plurality of subcarrier components having different symbols and different frequencies, and The detection output is obtained based on the phase between the transmission path characteristics.

According to a fifth aspect of the present invention,
4. The receiving apparatus for an orthogonal frequency division multiplexed signal according to claim 3, wherein the plurality of subcarrier components in the same symbol used for obtaining the detection output employ QPSK modulation as orthogonal frequency division multiplexing modulation. Data transmission subcarrier to be transmitted.

According to a sixth aspect of the present invention, there is provided:
6. The apparatus for receiving an orthogonal frequency division multiplexed signal according to claim 5, wherein at least one pair of said data transmission subcarrier components is used for obtaining said detection output, and said at least one pair of said data transmission subcarrier components are used. The interval between the subcarrier components is constant.

According to a seventh aspect of the present invention,
7. The receiving apparatus for an orthogonal frequency division multiplexed signal according to claim 6, wherein the clock phase error detection unit extracts a plurality of subcarrier components for data transmission for each symbol, and extracts a subcarrier component for data transmission. A plurality of data transmission sub-carrier components, adjacent data transmission sub-carrier component separation means for outputting the at least one pair of data transmission sub-carrier components, and one of the at least one pair of data transmission sub-carrier components; A conjugate complex conversion unit that outputs a conjugate complex signal of the other, the other of the at least one pair of data transmission subcarrier components, and the one of the at least one pair of data transmission subcarrier components, the one of the conjugate complex signals. And a complex multiplier that outputs the complex multiplication result of the complex multiplication result, and stores the absolute value of the phase component of the complex multiplication result in 0 to π / 4 radians on a complex coordinate plane. And a coordinate conversion unit to output was converted.

According to the eighth aspect of the present invention,
The orthogonal frequency division multiplexed signal receiving apparatus according to claim 7, wherein a tangent calculation unit that obtains and outputs a tangent of an output of the coordinate transformation unit; A phase calculating unit that obtains a phase between the two pairs of subcarrier components for data transmission; and a phase averaging unit that obtains the detection output by obtaining an average value of the phase for each symbol.

According to a ninth aspect of the present invention, there is provided:
8. The receiving apparatus for an orthogonal frequency division multiplexed signal according to claim 7, wherein a tangent calculator for calculating and outputting a tangent of an output of the coordinate converter, and an average value of an output of the tangent calculator for each symbol. And a tangent averaging unit for obtaining the detection output.

According to a tenth aspect of the present invention, there is provided the orthogonal frequency division multiplexed signal receiving apparatus according to the seventh aspect, wherein an imaginary part of the output of the coordinate transformation unit is obtained and output. And an imaginary part averaging unit for obtaining an average value of the output of the imaginary part information extraction unit for each symbol to obtain the detection output.

An eleventh aspect of the present invention is the orthogonal frequency division multiplexed signal receiving apparatus according to the fourth aspect, wherein the detection output is obtained for each symbol using a pilot subcarrier. The pilot subcarriers have a constant frequency interval within the same symbol, and the frequency arrangement has a constant offset for each symbol.

According to a twelfth aspect of the present invention, there is provided the orthogonal frequency division multiplexed signal receiving apparatus according to the eleventh aspect, wherein at least one pair of the pilots differing by the offset over a plurality of symbols. A clock phase error detector for obtaining the detection output based on the phase between the subcarrier components for use.

According to a thirteenth aspect of the present invention, there is provided the orthogonal frequency division multiplexed signal receiving apparatus according to the twelfth aspect, wherein the clock phase error detecting unit detects the pilot subcarrier component for each symbol. A pilot subcarrier component extraction unit to be extracted, a division unit that outputs a transmission path characteristic component by dividing the pilot subcarrier component by known pilot data, and, over the plurality of symbols, different by the offset, at least An adjacent transmission path characteristic component separation unit that outputs one pair of the transmission path characteristic components.

According to a fourteenth aspect of the present invention, there is provided the orthogonal frequency division multiplexed signal receiving apparatus according to the thirteenth aspect, wherein one of the at least one pair of transmission path characteristic components is output as a conjugate complex number signal. A conjugate complex number conversion unit, and a complex multiplication unit that outputs a complex multiplication result of the other of the at least one pair of transmission path characteristic components and the one of the conjugate complex number signals of the at least one pair of transmission path characteristic components. A tangent calculation unit that calculates and outputs a tangent of the complex multiplication result, and a phase calculation unit that obtains a phase between the at least one pair of transmission path characteristic components in the symbol from an output of the tangent calculation unit; A phase averaging unit that obtains the detection output by obtaining an average value of the phase for each of the symbols.

According to a fifteenth aspect of the present invention, there is provided the orthogonal frequency division multiplexed signal receiving apparatus according to the thirteenth aspect, wherein one of the at least one pair of transmission path characteristic components is output as a conjugate complex number signal. A conjugate complex number conversion unit, and a complex multiplication unit that outputs a complex multiplication result of the other of the at least one pair of transmission path characteristic components and the one of the conjugate complex number signals of the at least one pair of transmission path characteristic components. A tangent calculation unit for obtaining and outputting a tangent of the complex multiplication result, and a tangent averaging unit for obtaining the detection output by obtaining an average value of the output of the tangent calculation unit for each symbol.

According to a sixteenth aspect of the present invention, there is provided the receiver for an orthogonal frequency division multiplexed signal according to the fourth aspect, wherein the plurality of subcarrier components are used for demodulating a synchronously modulated subcarrier. A transmission path estimating unit having a plurality of pilot subcarrier components inserted into the received signal, and estimating the plurality of transmission path characteristics based on the plurality of pilot subcarrier components; and A clock phase error detection unit for obtaining the detection output based on the characteristic.

According to a seventeenth aspect of the present invention, there is provided the orthogonal frequency division multiplexed signal receiving apparatus according to the sixteenth aspect, wherein at least one pair of the adjacent transmission line characteristic components is output. A separation unit, a conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission path characteristic components, the other of the at least one pair of transmission path characteristic components, and transmission of the at least one pair. A complex multiplication unit that outputs a complex multiplication result of the one of the conjugate complex number signals of a path characteristic component, a tangent calculation unit that calculates and outputs a tangent of the complex multiplication result, and outputs the symbol from the output of the tangent calculation unit. In, a phase calculator for obtaining a phase between the at least one pair of transmission path characteristic components,
A phase averaging unit that obtains the detection output by obtaining an average value of the phase for each of the symbols.

An eighteenth aspect of the present invention is the orthogonal frequency division multiplexed signal receiving apparatus according to the sixteenth aspect, wherein at least one pair of the adjacent transmission line characteristic components is output. A separation unit, a conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission path characteristic components, the other of the at least one pair of transmission path characteristic components, and transmission of the at least one pair. A complex multiplication unit that outputs a complex multiplication result of the one of the path characteristic components and the conjugate complex signal, a tangent calculation unit that obtains and outputs a tangent of the complex multiplication result, and an output of the tangent calculation unit for each symbol. A tangent averaging unit for obtaining the detection output by obtaining an average value.

According to a nineteenth aspect of the present invention, there is provided the orthogonal frequency division multiplexed signal receiving apparatus according to the thirteenth or sixteenth aspect, wherein one of the at least one pair of transmission path characteristic components is implemented. From the product of the part and the other imaginary part of the at least one pair of transmission line characteristic components, the one imaginary part of the at least one pair of transmission line characteristic components and the at least one pair of transmission line characteristic components An imaginary part information generating unit that generates imaginary part information by subtracting a product of the other real part, and an imaginary part averaging unit that obtains the detection output by obtaining an average value of the imaginary part information for each symbol. Have more.

According to a twentieth aspect of the present invention, there is provided the apparatus for receiving an orthogonal frequency division multiplexed signal according to any one of the first and second aspects, wherein the plurality of subcarrier components are different. If it is dynamically modulated, determine the detection output based on the phase between the plurality of sub-carrier components in the same symbol, when the plurality of sub-carrier components are those that have been tuned modulation Determines the detection output based on the phase between at least one pair of specific pilot subcarrier components that differ by a predetermined offset over a plurality of symbols, and the specific pilot subcarrier is a frequency interval within the same symbol. Is constant and the frequency arrangement has the predetermined offset for each symbol.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing a configuration of an orthogonal frequency division multiplexed signal receiving apparatus 101 according to Embodiment 1 of the present invention. Orthogonal frequency division multiplex signal receiving apparatus 101 includes, as its outline, a conventional orthogonal frequency division multiplex signal receiving apparatus shown in FIG. 23 100
In which the delay unit 15, the positive frequency pass filter unit 16, the negative frequency pass filter unit 17, the complex multiplication units 18, 19, the integration units 20, 21 and the subtraction unit 22 are replaced with a clock phase error detection unit 51. Have.

More specifically, the orthogonal frequency division multiplexed signal receiving apparatus 101 includes an A / D converter 1, a subcarrier frequency corrector 2, a guard period remover 3, a Fourier transformer 4, and a data reproducer 7. I have.

The A / D converter 1 inputs a clock signal having a predetermined frequency from the clock oscillator 9. Then, sampling is performed at a timing based on the clock signal, and the received signal is converted from analog to digital and output. The received signal is demodulated to a predetermined frequency band by quasi-synchronous detection from the orthogonal frequency division multiplexed signal, and is output from, for example, a tuner (not shown). As an example, the i-th symbol r _i input to the A / D converter 1 is shown.

FIG. 2 is a graph illustrating a signal waveform input to the A / D converter 1 when the frequencies of the subcarriers are completely synchronized. For the transmission symbol of the orthogonal frequency division multiplex signal, a part of the last part of the effective symbol is added to the head of the symbol as a guard period.

The subcarrier frequency correction unit 2 receives the output of the Fourier transform unit 4. And based on this, A / D
The subcarrier frequency error between the transmission and reception signals remaining in the output signal of the conversion unit 1 is corrected and output as a complex signal. The guard period removing unit 3 receives the output of the sub-carrier frequency correcting unit 2, removes a signal corresponding to the guard period, and outputs an effective symbol in each symbol.

The Fourier transform unit 4 includes a guard period removing unit 3
Performs a discrete Fourier transform with a predetermined number of points on the effective symbols output from. The output of the Fourier transformer 4 represents a component (subcarrier component) for each subcarrier in the orthogonal frequency division multiplexed signal. As an example, the k-th subcarrier component x _{i, k} in the i-th symbol is shown.

The data reproducing unit 7 demodulates the output of the Fourier transform unit 4 according to the modulation method of each subcarrier.
As a result, the transmission data is reproduced. As an example, i-th
For data transmitted by the k-th subcarrier in the k-th symbol, output s
_{i, k} are shown.

The orthogonal frequency division multiplexed signal receiving apparatus 101 further includes a clock phase error detecting section 51, a loop filter section 6, an oscillator control section 8, and a clock oscillating section 9. The clock phase error detecting section 51 receives the output of the Fourier transform section 4 and receives the output of the A / D converting section 1 based on the phase error between the transmission path characteristic components in the subcarrier component within one symbol.
, A detection output reflecting the phase error of the clock signal supplied to each symbol is detected for each symbol, and a detection output signal is output. As an example, a detection output y _i reflecting the phase error of the clock signal in the ith symbol is shown. A specific configuration example and operation of the clock phase error detection unit 51 will be described in detail in another embodiment.

The loop filter 6 limits the frequency band of the detection output signal obtained from the clock phase error detector 51 and outputs the signal. The oscillator control unit 8 includes a loop filter unit 6
Is converted into a control signal format necessary for the clock oscillating unit 9 to control the frequency of the clock signal.
Then, the clock oscillating unit 9 performs an oscillating operation based on the output of the oscillator control unit 8, and supplies a clock signal to the A / D conversion unit 1. Therefore, the orthogonal frequency division multiplex signal receiving apparatus 10
1 has a phase locked loop for the phase error of the clock signal.

If the clock signal has a phase error, the signal input to the Fourier transform unit 4 is a signal that is temporally shifted from the signal that should be input. Due to the nature of the Fourier transform, the time lag in the time domain appears as a phase rotation term in the frequency domain. In the orthogonal frequency division multiplexed signal receiving apparatus 101, the phase error of the clock signal can be detected by detecting the phase rotation component in the clock phase error detection unit 51.
Also, the frequency error of the clock signal can be locally regarded as a phase error. Therefore, by configuring a phase locked loop for the phase error of the clock signal, both the phase and the frequency of the clock signal can be obtained. Can be corrected.

As described above, since the orthogonal frequency division multiplex signal receiving apparatus 101 has the phase locked loop for the phase error of the clock signal, it performs highly accurate and stable clock recovery, and The error rate after data reproduction of the multiplex signal is reduced.

Embodiment 2 FIG. 3 is a block diagram showing a configuration of an orthogonal frequency division multiplexed signal receiving apparatus 102 according to Embodiment 2 of the present invention. The orthogonal frequency division multiplexed signal receiving apparatus 102 is, as an outline, an A / D converter 1 of the orthogonal frequency division multiplexed signal receiving apparatus 101 shown in FIG.
Resampling unit 1 between the subcarrier frequency correcting unit 2
1 and the oscillator control unit 8 and the clock control unit 9 are replaced by a filter coefficient output unit 10. In the second embodiment, the output of the A / D converter 1 is resampled while the clock signal used in the A / D converter 1 is kept constant.

More specifically, the A / D converter 1, sub-carrier frequency corrector 2, guard period remover 3, Fourier transformer 4, clock phase error detector 51, loop filter 6, and data reproducer 7 Performs the same function as that employed in the first embodiment. The output of the A / D converter 1 is provided to the resampling unit 11, and the output of the resampling unit 11 is provided to the subcarrier frequency correction unit 2 together with the output of the Fourier transform unit 4. The filter coefficient output unit 10
Inputs the output of the loop filter unit 6 and supplies the output to the resampling unit 11.

The filter coefficient output unit 10 outputs the coefficient value of the resampling filter for the phase error of the clock signal whose frequency band is limited, obtained from the loop filter unit 6. For example, a coefficient value for correcting a clock phase error may be stored in a look-up table in advance, and the filter coefficient output unit 10 may be configured to output a coefficient corresponding to an input signal.

The resampling section 11 is constituted by a resampling filter. Based on the coefficient value of the resampling filter obtained from the filter coefficient output section 10, A
The phase error component of the clock signal remaining in the output of the / D converter 1 is corrected. As a result, the output value of the original sampling point with the phase error suppressed is output.

As described above, also in the orthogonal frequency division multiplexed signal receiving apparatus 102 according to the second embodiment, since the phase locked loop is configured for the phase error of the clock signal, the clock can be reproduced with high accuracy and stability. Is performed, and the error rate after data reproduction of the orthogonal frequency division multiplexed signal is reduced.

Embodiment 3 In the third embodiment, the configuration of the clock phase error detection unit 51 used in the orthogonal frequency division multiplexed signal receiving apparatuses 101 and 102 shown in the first and second embodiments will be exemplified.

FIG. 4 is a block diagram illustrating the configuration of a clock phase error detection section 51a that can be employed as the clock phase error detection section 51. Clock phase error detector 51
a is a data transmission sub-carrier component extraction unit 500 for inputting sub-carrier components x _{i, k} and an output of the data transmission sub-carrier component extraction unit 500, and receives one or more pairs of data transmission sub-carrier components. And an adjacent data transmission sub-carrier component separating section 501 for outputting the same. Here, the subcarrier for data transmission is a subcarrier used for data transmission. The data here means data that the system originally intends to transmit, such as video information and audio information. In the third embodiment, the phase error of the clock signal is detected for each symbol using the subcarrier for data transmission.

FIG. 5 is a graph showing the concept of sampling in the A / D converter 1, in which a broken line indicates a waveform of a received signal input to the A / D converter 1, and a white circle indicates an original sampling point, that is, a clock. This shows a sampling point when the signal has no phase error. When there is no phase error in the clock signal supplied to the A / D converter 1, sampling is performed at the boundary between the guard period and the effective symbol period. In this case, the sampling points indicated by double circles, that is, the original sampling points within the effective symbol period are output from the Fourier transform unit 4.

However, the clock signal has a phase error sT (T is an effective symbol period, which is the reciprocal of the frequency interval f ₀ of the adjacent subcarriers, and s is a coefficient different according to the phase error of the clock signal: the leading phase is positive. ) Is present,
Sampling is performed at sampling points indicated by black circles. Therefore, the sampling points output from the Fourier transform unit 4 are indicated by black circles and further surrounded by white circles, and an undesired operation of giving the waveform of the guard period to the data reproducing unit 7 occurs.

Assuming that the boundary between the guard period and the effective symbol period is a reference point of the phase, the phase error of the clock signal with respect to the reference point can be defined in the range of -2zπ to 2zπ (z: integer). At this time, assuming that the value of the transmission data is a _{i, k} , the transfer function of the transmission path to the corresponding subcarrier is H _{i, k} , and the number of points of the discrete Fourier transform executed by the Fourier transform unit 4 is N, the Fourier transform The output x _{i, k} of the unit 4 can be approximated by equation (1).

[0053]

(Equation 1)

Detecting the phase error of the clock signal can be realized by obtaining the coefficient s in equation (1).

First, a sub-carrier component extracting unit 50 for data transmission.
At 0, a subcarrier component transmitting data is extracted from the output signal of the Fourier transform unit 4 and output. For example, the i-th symbol r _i input to the A / D converter 1
, From the Fourier transform unit 4, the subcarrier components x _{i, 0} ,
x _{i, 1} ,..., x _{i, N−1} are obtained. Where the subcarrier component x
The frequency of _{i, k + 1} is higher than the frequency of the subcarrier component x _{i, k by} a frequency interval f ₀ .

For example, sub-carrier components x _{i, 0} , x _{i, 1} ,.
_{i, N-1} are output from the Fourier transform unit 4 in this order.
Only the component of the subcarrier for data transmission is extracted from these, and is provided to the subcarrier component separation unit 501 for adjacent data transmission. Adjacent data transmission subcarrier component separation unit 50
Reference numeral 1 denotes an input of the output of the data transmission sub-carrier component extraction unit 500, and as a pair of sub-carrier components having different frequencies, the data transmission first sub-carrier component c _{i, k} and the data transmission second sub-carrier Output at least one pair of components p _{i, k} . Here, the frequency of the data first transmission sub-carrier component c _{i, k} is higher than the frequency of the data transmission second sub-carrier component p _{i, k} .

_Assuming that the difference between the frequency f _cik of the data first transmission sub-carrier component c _{i, k and} the frequency f _pik of the data transmission second sub-carrier component p _{i, k} is mf ₀ (m ≧ 1), Equation (2) holds for the subcarrier component for data transmission.

[0058]

(Equation 2)

The clock phase error detecting section 5 has a conjugate complex number
It further includes a conversion unit 502 and a complex multiplication unit 503.
The conjugate complex number converter 502 generates a second subcarrier for data transmission.
Minute p _{i, k}Complex conjugate p of_{i, k} ^*And a complex multiplication unit 503
Is the first subcarrier component c for data transmission_{i, k}And data transmission
Second subcarrier component p_{i, k}Complex conjugate p of_{i, k} ^*Complex power with
Perform the calculation. However, an asterisk added to the upper right of the symbol
(*) Indicates the complex conjugate of the complex number to which this is added.
You.

The complex signal R _{i, k} output from the complex multiplication unit 503 is expressed by equation (3) based on equations (1) and (2).

[0061]

(Equation 3)

The modulation method of the data transmission subcarrier is DQP
SK (Differentially Encoded Quadrature Phase Shif
t Keying), π / 4 shift DQPSK, QPSK (Quad
rature Phase Shift Keying) (in the present specification, these are collectively referred to as “QPSK modulation”).
a _{i, km} ^* · a _{i, k} = A ² (A: signal amplitude). Further, by reducing the value of m, the transfer function H _{i, km of} the transmission path corresponding to the data first transmission subcarrier component c _{i, k} is _obtained.
Can be approximated as being equal to the transfer function H _{i, k of} the transmission path corresponding to the second sub-carrier component p _{i, k} for data transmission.
In this case, equation (3) can be approximated by equation (4).

[0063]

(Equation 4)

[0064] formula _(4), l i, _k represents the data modulated on a subcarrier of a frequency f _pik, the phase difference between the modulated data on a subcarrier frequency f _cik, 0,
It can take any value of 1, 2, and 3.

In order to detect the coefficient s so as not to depend on the value of the data phase difference li, k, the clock phase error detector 5
Further includes a coordinate conversion unit 504. Coordinate converter 50
In step 4, the coordinate axes are converted so that the absolute value of the phase component of the input complex signal R _{i, k} falls within the range of 0 to π / 4 radian on the complex coordinate plane.

FIG. 6A shows the complex signal R _{i, k} of FIG.
(B) is a graph showing each position of the complex signal R ^′ _{i, k} on the complex coordinate plane. The complex signal R _{i, k} occupies one of the four quadrants depending on the value of the data phase difference li, k, while the complex signal R ^′ _{i, k} depends on the value of the data phase difference li, k. Instead, both the real and imaginary parts can be set to be positive.

[0067] The coordinate transformation unit 504 Specifically, the complex signal R _i to be _inputted, according to the sign and absolute value of the real part and the imaginary part of _k, the output to the complex signal R _^'i, and generates a _k. A specific example of the process of the coordinate conversion unit 504 is shown in the table below. Here, the symbol Re represents the real part of the complex number contained in [] on the right side thereof, and the symbol Im represents the imaginary part of the complex number contained in [] on the right side thereof.

[0068]

[Table 1]

Then, the complex signal R ^′ _{i, k} is represented by equation (5).

[0070]

(Equation 5)

The clock phase error detecting section 5 further includes a tangent calculating section 505 and a phase calculating section 506 in order to obtain a detection output regarding the clock phase error from the complex signal R ^′ _{i, k} . The tangent calculator 505 calculates and outputs a tangent to the phase of the complex signal R ^′ _{i, k} . Specifically, for _{^{example, Im [R 'i, k}} ] / Re [R' i, k] obtained by. Then, the phase calculator 506 receives the output of the tangent calculator 505 and outputs the corresponding phase θ _{i, k} . The phase calculator 506 may store the phase corresponding to the tangent in, for example, a look-up table, and output a value corresponding to the input. The phase θ _{i, k} is represented by Expression (6).

[0072]

(Equation 6)

The pair of the first sub-carrier component for data transmission c _{i, k} and the second sub-carrier component for data transmission p _{i, k} is obtained by updating the sub-carrier number k for a certain symbol r _i . Can be adopted. And k within one symbol period
The clock phase error detection unit 5 further includes a phase averaging unit 507 to calculate the average value of the phase θ _{i, k} calculated by updating The phase averaging unit 507 includes the phase calculation unit 5
06, the output θ _{i, k} is input, the average value is calculated for the subcarrier number k updated within one symbol period, and the detection output y _i reflecting the phase error of the clock signal in the ith symbol is calculated. Is output. That is, the detection output y _i that reflects the phase error of the clock signal in the _ith symbol is the average of the phase difference between the data transmission subcarriers within one symbol, and the value is clearly the phase of the clock signal. It is a scalar quantity proportional to the error.

Further, if the expression (2) is satisfied, the subcarriers for data transmission have the same interval m in any pair.
Since they are separated by f _0, it is possible to avoid the need for correction according to the frequency interval and the occurrence of variations in the detected values for the same clock phase error.

Further, QPS is used as orthogonal frequency division multiplex modulation.
By employing K-system modulation, the magnitudes of the absolute values of the subcarrier components for data transmission are all equal (Equation (4),
(Indicated as A in (5).) Therefore, when obtaining a complex multiplication result, there is no need to normalize by the size of the subcarrier component for data transmission.

As described above, according to the third embodiment, 1
A phase error of a clock signal is detected based on a phase difference between a pair or a plurality of pairs of subcarriers in a symbol.
Therefore, a high-precision and stable clock signal can be reproduced in a phase locked loop that performs clock reproduction.

It should be noted that, in addition to data, various information such as a pilot used for reproducing a signal in the demodulator, a pilot for synchronization, and data representing transmission parameters may be transmitted to the subcarrier. Many. However, the number of pilot subcarriers is smaller than the number of subcarriers for data transmission, and they are arranged at irregular frequency positions. Therefore, compared with the case where the phase error is obtained using the pilot subcarrier, the phase error is obtained using the data transmission subcarrier in the third embodiment, so that the clock phase error can be obtained with high accuracy.

A pair of the first sub-carrier component for data transmission c _{i, k} and the second sub-carrier component for data transmission p _{i, k} may be obtained for only one symbol r _i . Does not require the phase averaging unit 507. However, it is desirable to obtain a plurality of the pairs in order to increase the accuracy of obtaining the phase error.

Embodiment 4 Also in the fourth embodiment, a configuration of a clock phase error detection unit 51b that can be adopted as the clock phase error detection unit 51 is presented. Rather than the clock phase error detector 51b in the data transmission subcarriers, to detect a phase error of the clock by using a pilot for subcarrier subcarriers for pilot (Pilot subcarriers), which is particularly frequency positions by a symbol changes.

FIG. 7 is a block diagram illustrating the configuration of the clock phase error detector 51b. The clock phase error detecting section 51b includes a pilot sub-carrier component extracting section 511, which inputs the sub-carrier component x _{i, k} from the Fourier transform section 4 and extracts a certain kind of pilot sub-carrier component.

In general, pilot subcarriers are often smaller in absolute number than data transmission subcarriers.
Therefore, when a general pilot subcarrier is used for clock phase error detecting section 51a shown in the third embodiment, it is easily affected by noise. Further, the frequency allocation of general pilot subcarriers may be irregular. In this case, since the frequency intervals of the extracted subcarriers are not constant, there arises a problem that correction according to the frequency intervals is required, and a variation occurs in the detection value even for the same clock phase error. Furthermore, when pilot sub-carriers arranged at regular intervals are used, there is no variation in the detected values, but the larger the interval, the smaller the detection range.

[0082] However, one of the pilot for the sub-carrier,
The subcarrier used for demodulating the synchronously modulated subcarrier has a frequency interval within the same symbol of a fixed value Mf _0.
(F ₀ is the frequency interval between adjacent sub-carriers whose sub-carrier number is adjacent), and the frequency arrangement may have a fixed offset nf ₀ for each symbol (hereinafter referred to as “specific pilot sub-carrier”). ). FIG. 8 is a schematic diagram showing a symbol including such a pilot, and a different symbol (for example, r _i ) is illustrated for each row. The white circles and the black circles indicate the positions of the sub-carriers, and the sub-carrier number k increases toward the right, and the corresponding frequency increases. The frequency interval between adjacent pilot subcarriers in the same symbol is 1
2f ₀ (ie, M = 12), and the case where the offset of the pilot subcarrier is 3f ₀ (ie, n = 3) between adjacent symbols is shown. An example of such a pilot is a scattered pilot in the terrestrial digital TV system in Japan.

By using the specific pilot sub-carriers, the detection range of the phase error of the clock signal can be expanded as described later, and the number of sub-carriers used for detecting the phase error can be increased. Therefore, the detection accuracy of the phase error of the clock signal can be improved.

Further, when multi-level synchronous modulation other than the QPSK system, for example, multi-level QAM (Quadrature Amplitude Modulation) or the like is used, detection of the phase error of the extracted data transmission subcarrier becomes complicated. On the other hand, the modulation method of the pilot subcarrier is usually BPSK (Binary Pha
se Shift Keying) and DBPSK (Differentially Enco
ded Binary Phase Shift Keying) is used, and the value of the data is known. In such a case, detecting the phase error of the clock signal using the pilot subcarrier can reduce the circuit scale.

The clock phase error detecting section 51b includes a dividing section 5
12 and a pilot subcarrier component extraction unit 51
The pilot subcarrier component x _{i, k} ^(p) extracted in 1 is
Divide by the known pilot data a _{i, k} ^(p) . The known pilot data is a known signal representing pilot data corresponding to the extracted pilot subcarrier. As a result, the pilot subcarrier component is normalized, and the phase error of the clock signal can be obtained regardless of the value of the pilot data.

If the sub-carrier component x _{i, k} is the pilot sub-carrier component x _{i, k} ^(p) , assuming that this is expressed by equation (1), the output of the division unit 512, ie, the normalized The pilot subcarrier component x ^′ _{i, k} ^(p) thus obtained is represented by equation (7), and is also referred to as “transmission path characteristic component” in this specification.

[0087]

(Equation 7)

[0088] channel characteristic components x _{^'i, k} ^(p), the transmission path characteristics H _i for the corresponding _subcarrier, the phase rotation term exp reflecting the phase error of _k clock signal [j2π (k / N) s ]
And the product of

The clock phase error detecting section 51b further includes a transmission path characteristic component memory section 513, and the transmission path characteristic component x ^′.
_{i, k} ^(p) is stored in the memory for at least one symbol. Desirably, transmission path characteristic components for (M / n-1) different symbols are stored.

The clock phase error detection section 51b performs adjacent transmission
A channel characteristic component separation unit 514 is further provided to
Input of the output of the memory unit 513 and the output of the division unit 512
And the first transmission path characteristic component c for pilot_{i, k} ^(p)And pie
Second transmission path characteristic component p for lot _{i, k} ^(p)Is output.

FIG. 9 shows a pilot first transmission path characteristic component c _{i, k} ^(p) and a pilot second transmission path characteristic component p _{i, k} ^(p).
FIG. The black circles indicate the positions of the pilot subcarriers, and the white circles indicate the positions of the subcarriers of the other signals. The subcarriers obtained from the division unit 512 and the transmission path characteristic component memory unit 513 are indicated by black circles. It corresponds to the position. Here, the specific pilot subcarriers are subcarrier numbers k = 0, 3, 6, 9, 1
The figure shows a case where two subcarriers are selected from 2, 15 subcarriers, and 12 subcarrier numbers are separated from the specific pilot subcarriers in the same pilot. That is, as in the case described with reference to FIG. 8, the frequency spacing between adjacent specific pilot subcarriers within the same symbol is 12f.
₀ (that is, M = 12), and the offset of the specific pilot subcarrier between adjacent symbols is 3f ₀ (that is, n = 3).

In the ith symbol, it is assumed that the subcarrier for the specific pilot has the subcarrier number k = 6, and the transmission path characteristic component x ^′ _{i, 6} ^(p) is obtained from the divider 512. . Prior to this, the division unit 512 already has
For the (i-1) -th symbol, the channel characteristic component x
_{^{'I-1,3 (p),}} x' i-1,15 (p) is the (i-2) -th transmission path for the symbol characteristic components _{^{x 'i-2,0 (p)}} , x'
_i-2,12 ^(p) is the (i-3) th transmission path for the symbol characteristic components x ^{_'i-3,9 (p)} are obtained respectively, and the output from the transmission path characteristic component memory section 513 Is done.

Therefore, the adjacent transmission path characteristic component separation section 514 includes x ^′ _i−2,0 ^(p) , x ^′ _i−1,3 ^(p) , x ^′ _{i, 6} ^(p) , and x ^{′.
_{i-3,9 (p), x}} 'i-2,12 (p), x' will _{be i-1,15} ^(p) is input, although the over different symbol, for a particular pilot A plurality of transmission path characteristic components that differ by the subcarrier offset nf ₀ are obtained. Therefore, when the channel characteristic component for the i-th symbol is obtained from the division unit 512, the pilot first channel characteristic component c _{i, k} ^(p) and the pilot second channel characteristic component p _{i, k}
Multiple pairs of ^(p) can be output. For example, c _{i, 15} ^{(p)
_{= X 'i-1,15 (p}} ), p i, 15 (p) = x' i-2,12 pair ^(p), c
^{_{i, 12 (p) = x}} 'i-2,12 (p), p i, 12 (p) = x' i -3,9 pairs _{^{(p), c i, 9}} (p) = x 'i _-3,9 ^(p) , p _{i, 9} ^(p) = x ^′ _{i, 6} ^(p) pair, c _{i, 6} ^(p) = x ^′ _{i, 6} ^(p) , p _{i, 6} ^{(p )} = X ^′ _i−1,3 ^(p) pair, c _{i, 3} ^(p) = x ^′ _i−1,3 ^(p) , c _{i, 3} ^{( p)} =
It is a pair of x ^′ _i−1,3 ^(p) and p _{i, 3} ^(p) = x ^′ _i−2,0 ^(p) .

In other words, the channel characteristic component for the current symbol output from the division unit 512 and the channel characteristic component of the previous symbol output from the channel characteristic component memory unit 513 are adopted. By selecting from these, transmission path characteristic components whose frequencies are adjacent to each other are output as a pair.

The clock phase error detection section 51b further includes a conjugate complex number conversion section 515, which is a conjugate complex number p _{i, k of the} pilot second pilot transmission path characteristic component p _{i, k} ^{(p).
(p) *} is output. Then, the second complex multiplication unit 516 outputs the output p _{i, k} ^{(p) *} from the conjugate complex number conversion unit 515 and the pilot first transmission path characteristic component c _{i, k} from the adjacent transmission path characteristic component separation unit 514. Performs complex multiplication with ^(p) . Complex multiplier 5
The 16 outputs R _{i, k} ^(p) are expressed by equation (8) based on equation (7).

[0096]

(Equation 8)

The clock phase error detecting section 51b has the tangent calculating section 5 having the same function as that employed in the third embodiment.
05, a phase calculation unit 506, and a phase averaging unit 507. The tangent calculator 505 calculates and outputs the tangent of the output R _{i, k} ^(p) of the complex multiplier 516 ⁽ the value obtained by dividing the imaginary part by the real part). Subsequent processing can obtain the detection output y _i in the i-th symbol in the same manner as in the third embodiment.

As described above, according to the present embodiment, 1
Attention is paid to a specific pilot subcarrier that is arranged at equal frequency intervals within a symbol and the arrangement of each symbol has an offset, and a transmission path characteristic component obtained from this is adopted over a plurality of symbols, and selected from among them. A phase difference between at least one pair of transmission path characteristic components.
Therefore, the frequency interval is smaller than when the specific pilot subcarrier component is obtained only from the same symbol, and the accuracy of the approximation that the transfer function is substantially equal between the pair of transmission path characteristic components is also improved. In addition, a large number of subcarriers to be referenced can be obtained, and a phase
In a locked loop, a highly accurate and stable clock signal can be reproduced.

For the same reason, it is necessary to eliminate the dispersion of the detection values required when using a pilot subcarrier having an irregular frequency / time arrangement and to increase the detection range of the phase error of the clock signal. it can.

As shown in FIG. 9, when a pair of transmission path characteristic components separated by an offset nf _{0 is} always obtained between adjacent symbols, the transmission path characteristic component memory unit 513 stores the symbol one symbol. May be stored. In that case, a pair of pilot first
The transmission path characteristic component c _{i, k} ^(p) and the pilot second transmission path characteristic component p _{i, k} ^(p) are obtained, and the output phase averaging unit 507 becomes unnecessary. However, it is desirable to obtain a plurality of the pairs in order to increase the accuracy of obtaining the phase error.

Embodiment 5 FIG. In the fifth embodiment, a clock phase error is detected based on an output of a transmission path estimation result used when demodulating a synchronously modulated subcarrier.
FIG. 10 is a block diagram showing a configuration of an orthogonal frequency division multiplexed signal receiving apparatus 103 according to Embodiment 5 of the present invention. As an outline thereof, the clock phase error detection unit 51 shown in FIG. 1 is replaced with a clock phase error detection unit 52, and the data recovery unit 7 of the orthogonal frequency division multiplexed signal receiving apparatus 101 is replaced with a subcarrier demodulation unit 13, respectively. Transmission channel estimation unit 12
Is added.

More specifically, orthogonal frequency division multiplexed signal receiving apparatus 103 has A / D conversion section 1, subcarrier frequency correction section 2, guard period elimination, which perform the same functions as those employed in the first embodiment. A section 3, a Fourier transform section 4, a loop filter section 6, an oscillator control section 8, and a clock oscillator 9 are provided.

The transmission path estimating unit 12 receives the sub-carrier component x _{i, k} from the Fourier transform unit 4 and, based on the sub-carrier component of the pilot inserted for demodulating the synchronously modulated sub-carrier, Estimate the characteristics of the transmission path. FIG. 11 is a block diagram illustrating the configuration of the transmission path estimating unit 12. The transmission channel estimating unit 12 includes a pilot subcarrier component extracting unit 511 and a dividing unit 512 for obtaining the transmission channel characteristic component x ^′ _{i, k} ^(p) in the same manner as in the fourth embodiment.

From the division unit 512, the transmission path characteristic component x ^′ _{i, k}
^{When (p)} is obtained, transmission path characteristic components for a plurality of (i-1) -th and earlier symbols have already been obtained. To store these, the transmission path characteristic component memory unit 5
13 is also provided. Then, the transmission path characteristic components of the plurality of symbols before the i-th symbol are provided to the interpolation unit 519.

The interpolation section 519 approximates the transmission path characteristic component obtained for the specific pilot sub-carrier by using interpolation in the time direction and the frequency direction, for the transmission path for sub-carriers other than the specific pilot sub-carrier. Estimate characteristic components. As a result, the transmission path characteristic components hi _{, k} for all subcarriers are output. For the above interpolation,
It is preferable that the transmission path characteristic component memory unit 513 stores transmission path characteristic components for (M / n) different symbols.

The sub-carrier demodulation unit 13 includes a Fourier transform unit 4
Subcarrier components x _i, the _k output from the transmission path characteristic h _{i, k}
, And outputs reproduced data s _{i, k} . Specifically, it can be obtained by s _{i, k} = x _{i, k} / h _{i, k} .

The transmission path characteristic h obtained as described above
_{i, 0 ~h i, K (} 0 ≦ k ≦ K) is provided to the clock phase error detector 52, the detection output y _i reflecting the phase error of the clock signal is output. FIG. 12 is a block diagram showing a configuration of a clock phase error detection section 52a that can be employed in the clock phase error detection section 52. The clock phase error detection unit 52a has a configuration in which the pilot subcarrier component extraction unit 511, the division unit 512, and the transmission path characteristic component memory unit 513 are removed from the clock phase error detection unit 51b.

More specifically, clock phase error detecting section 52a
Has an adjacent transmission path characteristic component separation unit 514, and
Road characteristics h_{i, 0}~ H_{i, K}From the first subcarrier transmission path characteristic component c
_{i, k} ^{( h)}And the second subcarrier transmission path characteristic component p_{i, k} ^(h)A pair of
Output at least one. Here, the first subcarrier transmission path
Characteristic component c_{i, k} ^(h)Frequency is the second subcarrier transmission path characteristic
Component p_{i, k} ^(h)Higher than the frequency. For example, c_{i, k1} ^(h)=
h_{i, k1}, P_{i, k1} ^(h)= H _{i, k1-t}(1 ≦ t ≦ k1)
can do. However, in the first embodiment, m is small.
As it becomes easier to find the phase error with higher precision,
It is desirable that t is small.

The clock phase error detector 52a further comprises a conjugate complex number converter 515, a complex multiplier 516, and a tangent calculator 5
05, a phase calculation unit 506 and a phase averaging unit 507,
These perform the functions described in the third embodiment, respectively. That is, the conjugate complex number converter 515 outputs the conjugate complex number p _{i, k} ^{(h) *} of the second subcarrier transmission path characteristic component p _{i, k} ^(h) . Then, the complex multiplication unit 516 performs a complex multiplication of the first sub-carrier transmission path characteristic component c _{i, k} ^(h) and the conjugate complex number p _{i, k} ^{(h) *} to obtain a complex signal R _{i, k} ^(h). Is output. From this, the phase θ is calculated by the tangent calculation unit 505 and the phase calculation unit 506.
_{i, k} is obtained, and the average of the subcarrier number k is calculated by the phase averaging section 507 to obtain the detection output y _i for the i-th symbol.

As described above, according to the present embodiment, the phase error of the clock signal is determined based on the transmission path characteristics obtained as the output of the transmission path estimator required when demodulating the synchronously modulated subcarrier. Is detected. Therefore, the number of referenced subcarriers can be arbitrarily increased. Then, the phase error of the clock signal can be obtained without depending on the value of the pilot subcarrier component. As a result, a highly accurate and stable clock signal can be reproduced in a phase locked loop that performs clock recovery. Further, the detection range of the phase error of the clock signal can be increased.

The pilot sub-carriers to be adopted in the present embodiment are similar to the specific pilot sub-carriers employed in the fifth embodiment. Is not always required. This is because the phase error of the clock signal is obtained by using the output of the transmission path estimator, which is usually used when demodulating the synchronously modulated subcarrier.

In the present embodiment, the clock phase error
A detection output y output by the detection unit 52a _iBased on the clock
Frequency division multiplexer for controlling the clock signal of the clock oscillator 9
Although the heavy signal receiving apparatus 103 has been exemplified,
Like an orthogonal frequency division multiplexed signal receiving apparatus 102
, The filter coefficient output unit 10 and the resampler 11
May be used.

Embodiment 6 FIG. In the sixth embodiment, a technique for detecting a phase error of a clock signal in a case where synchronous modulation and differential modulation are mixed as a subcarrier modulation method will be presented.
However, the differential modulation here is DQPSK or π / 4 shift DQPSK, and the synchronous modulation is QPSK or multi-level QA
Means M.

FIG. 13 is a block diagram showing a configuration of an orthogonal frequency division multiplexed signal receiving apparatus 104 according to Embodiment 6 of the present invention. Orthogonal frequency division multiplex signal receiving apparatus 10
Reference numeral 4 denotes a clock phase error detector 5 in the orthogonal frequency division multiplexed signal receiver 101.
3 and a modulation system identification information decoding unit 14 is added.

The modulation scheme identification information decoding section 14 receives the subcarrier components x _{i, k} from the Fourier transform section 4 and outputs information for identifying the modulation scheme of each subcarrier inserted in the subcarrier. Reproduce. As a result, a modulation scheme identification signal D indicating whether the modulation scheme for each subcarrier is differential modulation or synchronous modulation is output. The clock phase error detector 53 detects a phase error of the clock signal according to the modulation scheme identification signal D.

FIG. 14 is a block diagram showing a configuration of a clock phase error detecting section 53a that can be employed in the clock phase error detecting section 53. The clock phase error detection unit 53a includes a data transmission sub-carrier component extraction unit 500, an adjacent data transmission unit, provided in the clock phase error detection unit 51a described in the third embodiment to obtain the complex signal R ^′ _{i, k.} A trust subcarrier component separation unit 501, a conjugate complex number conversion unit 502, a complex multiplication unit 503, and a coordinate conversion unit 504 are provided. The complex signal R ^′ _{i, k} is one input of the signal selection unit 522.

The clock phase error detecting section 53a is provided with a pilot subcarrier component extracting section provided in the clock phase error detecting section 51b shown in the fourth embodiment to obtain the complex signal R _{i, k} ^(p). 511, division unit 512, transmission line characteristic component memory unit 513, adjacent transmission line characteristic component separation unit 51
4, a conjugate complex number converter 515 and a complex multiplier 516 are provided. The output R _{i, k} ^(p) is the other input of the signal selection unit 522.

Further, the clock phase error detecting section 53a includes a tangent calculating section 505 to which the output of the signal selecting section 522 is given,
Phase calculator 50 to which the output of tangent calculator 505 is given
6. The phase θ _{i, k} is obtained from the phase calculator 506 _, and the detection output y _i is obtained.
Is provided.

The clock phase error detecting section 53a includes a signal selecting section 522 for selecting and outputting one of two inputs according to the modulation scheme identification signal D. Therefore, the clock phase error detecting section 53a outputs the clock phase error detecting section 51a (FIG. 4) described in the third embodiment and the clock phase error detecting section 51a described in the fourth embodiment in accordance with the output from the signal selecting section 522. It performs any of the functions of the detection unit 51b (FIG. 7).

The signal selection section 522 outputs the modulation scheme identification signal D
Is the subcarrier component x_{i, k}Is determined to be differentially modulated.
Output, the output R of the coordinate conversion unit 504^' _{i, k}, Sub-transport
Wave component x_{i, k}Is determined to be synchronously modulated
Output R of complex multiplier 516_{i, k} ^(p)And select each
Output.

As described above, in this embodiment, the phase error of the clock signal is detected according to the modulation method of the subcarrier. Therefore, according to the present embodiment, it is possible to realize high-precision clock reproduction when receiving an orthogonal frequency division multiplexed signal in which differential modulation and synchronous modulation are mixed.

In the present embodiment, the clock phase error
A detection output y output by the detection unit 53a _iBased on the clock
Frequency division multiplexer for controlling the clock signal of the clock oscillator 9
Although the heavy signal receiving apparatus 104 has been exemplified,
Like an orthogonal frequency division multiplexed signal receiving apparatus 102
, The filter coefficient output unit 10 and the resampler 11
May be used.

Embodiment 7 FIG. The seventh embodiment is a modification of the third to sixth embodiments.

FIG. 15 is a block diagram showing a modification of the third embodiment of the seventh embodiment, and shows the configuration of clock phase error detecting section 51c. Clock phase error detector 51
c has a configuration in which the phase calculation unit 506 and the phase averaging unit 507 of the clock phase error detection unit 51a shown in FIG. The clock phase error detection unit 51c is also used in the orthogonal frequency division multiplex signal
1 and 102 can be employed as the clock phase error detection unit 51.

FIG. 16 is a block diagram showing a modification of the fourth embodiment of the seventh embodiment, and shows the configuration of clock phase error detecting section 51d. Clock phase error detector 51
“d” has a configuration in which the phase calculation unit 506 and the phase averaging unit 507 of the clock phase error detection unit 51b shown in FIG. The clock phase error detection unit 51d is also used in the orthogonal frequency division multiplex signal
1 and 102 can be employed as the clock phase error detection unit 51.

FIG. 17 is a block diagram showing a modification of the fifth embodiment of the seventh embodiment, and shows the configuration of clock phase error detection section 52b. Clock phase error detector 52
b is a clock phase error detector 52a shown in FIG.
In which the phase calculation unit 506 and the phase averaging unit 507 are replaced by a tangent averaging unit 508. The clock phase error detection unit 52b is also used in the orthogonal frequency division multiplexed signal receiving device 1
03 can be employed as the clock phase error detection unit 52 included in the third embodiment.

FIG. 18 is a block diagram showing a modification of the sixth embodiment of the seventh embodiment, and shows the configuration of clock phase error detecting section 53b. Clock phase error detector 5
3 'is a clock phase error detection unit 53 shown in FIG.
The configuration is such that the phase calculation unit 506 and the phase averaging unit 507 in FIG. The clock phase error detection unit 53b can also be employed as the clock phase error detection unit 53 included in the orthogonal frequency division multiplexed signal receiving device 104.

The tangent averaging unit 508 includes a tangent calculating unit 505
Is input, and the average value of the tangent of the phase information calculated within one symbol period is calculated. Since the result is a scalar quantity reflecting the phase error of the clock signal, this can be treated as the detection output y _i for the i-th symbol.

As described above, in this embodiment, the output y _i of the clock phase error detectors 51, 52, 53 is obtained by averaging the output of the tangent calculator 505 for one symbol period. Therefore, there is no need to determine the phase from the tangent, and the circuit scale can be reduced.

Embodiment 8 FIG. The eighth embodiment is a further modification of the seventh embodiment as a modification of the third embodiment.
FIG. 19 is a block diagram showing a configuration of the clock phase error detection unit 51e. The clock phase error detection unit 51e can be adopted as the clock phase error detection unit 51 included in the orthogonal frequency division multiplexed signal receiving apparatuses 101 and 102.

The clock phase error detecting section 51e is the tangent calculating section 5 of the clock phase error detecting section 51c shown in FIG.
05, the tangent averaging unit 508 is replaced with an imaginary part information extracting unit 509 and an imaginary part averaging unit 510, respectively.

The clock phase error detector 51e obtains the complex signal R ^′ _{i, k} from the coordinate converter in the same manner as the clock phase error detectors 51a and 51c. The imaginary part information extracting unit 509 outputs the complex signal R _^'i, the imaginary part Im [R of _{^k' i, k]} a. This clock phase error detector 51a, the complex signal at the output of the 51c of the tangent calculator 505 R _^'i, the real part of _k Re [R
^' _{i, k} ]. Imaginary part averaging section 510
Outputs the imaginary part Im [R ^′ _{i, k} ] by averaging the subcarrier number k. Since the result is a scalar quantity reflecting the phase error of the clock signal, this can be treated as the detection output y _i for the i-th symbol.

As described above, in the present embodiment, the average value of one symbol of the imaginary part information is used as the clock phase error detector 51.
Output. Therefore, there is no need to determine the tangent or phase, and the circuit scale can be reduced.

Embodiment 9 FIG. The ninth embodiment is a further modification of the seventh embodiment as a modification of the fourth embodiment.
FIG. 20 is a block diagram showing the configuration of the clock phase error detection section 51f. The clock phase error detection section 51f can be employed as the clock phase error detection section 51 provided in the orthogonal frequency division multiplexed signal receiving apparatuses 101 and 102.

The clock phase error detection section 51f uses the conjugate complex number conversion section 515, complex multiplication section 516, tangent calculation section 505, and tangent averaging section 508 of the clock phase error detection section 51d shown in FIG. It has a configuration in which the multiplication unit 517 and the imaginary part averaging unit 510 are replaced.

The clock phase error detecting section 51f, like the clock phase error detecting sections 51b and 51d, outputs the pilot first transmission path characteristic component c _{i, k} ^(p) and the pilot first transmission path characteristic component from the adjacent transmission path characteristic component separation section 514. Second transmission path characteristic component p
_{get i, k} ^(p) . The imaginary part information generation multiplication unit 517 receives these inputs, calculates imaginary part information q _{i, k} ^(p) based on Equation (9), and outputs the calculated imaginary part information q _{i, k} ^(p) .

[0137]

(Equation 9)

That is, the imaginary part information q _{i, k} ^(p) is converted into the tangent value obtained from the tangent calculation section 505 in the clock phase error detection sections 51b and 51d by (Re [c _{i, k} ^(p) ] · Re
A ^{_{[p i, k (p)}} ] The value obtained by multiplying ^{_{+ Im [c i, k (}} p)] · Im [p i, k (p)] to). The imaginary part averaging unit 510 calculates the imaginary part information q _{i, k} ^(p)
And outputs the average of the sub-carrier number k.
Since the result is a scalar quantity reflecting the phase error of the clock signal, this can be treated as the detection output y _i for the i-th symbol.

As described above, in the present embodiment, the average value of one symbol of the imaginary part information is used as the clock phase error detector 51.
Output. Therefore, like complex multiplication (Re [c _{i, k}
^(p) ] · Re [ _{pi, k} ^(p) ] + Im [ci _{, k} ^(p) ] · Im [ _{pi, k}
^(p) ]) is not required, and there is no need to determine the tangent or phase, and the circuit scale can be reduced.

Embodiment 10 FIG. The tenth embodiment is a further modification of the seventh embodiment as a modification of the fifth embodiment. FIG. 21 is a block diagram showing a configuration of the clock phase error detection unit 52c. The clock phase error detection unit 52c can be adopted as the clock phase error detection unit 52 included in the orthogonal frequency division multiplexed signal receiving device 103.

The clock phase error detection section 52c uses the conjugate complex number conversion section 515, complex multiplication section 516, tangent calculation section 505, and tangent averaging section 508 of the clock phase error detection section 52b shown in FIG. It has a configuration in which the multiplication unit 517 and the imaginary part averaging unit 510 are replaced.

The clock phase error detecting section 52c, like the clock phase error detecting sections 52a and 52b, outputs the first transmission path characteristic component c _{i, k} from the adjacent transmission path characteristic component separation section 514.
^(h) and the second transmission path characteristic component p _{i, k} ^(h) are obtained. Imaginary part information generator for multiplication unit 517, enter these imaginary part information q _i, to calculate the _k ^(h) to output based on Equation (10).

[0143]

(Equation 10)

That is, the imaginary part information q _{i, k} ^(h) is obtained by adding the tangent value obtained from the tangent calculation section 505 in the clock phase error detection sections 52a and 52b to (Re [c _{i, k} ^(h) ] · Re
[P _{i, k} ^(h) ] + Im [c _{i, k} ^(h) ] · Im [p _{i, k} ^(h) ]). The imaginary part averaging unit 510 calculates the imaginary part information q _{i, k} ^(h)
Is averaged for the subcarrier number k and output.
Since the result is a scalar quantity reflecting the phase error of the clock signal, this can be treated as the detection output y _i for the i-th symbol.

As described above, in the present embodiment, the average value of one symbol of the imaginary part information is used as the clock phase error detector 51.
Output. Therefore, like complex multiplication (Re [c _{i, k}
^(h) ] Re [ _{pi, k} ^(h) ] + Im [ci _{, k} ^(h) ] Im [ _{pi, k}
^(h) ]) does not need to be determined, and there is no need to determine the tangent or phase, and the circuit scale can be reduced.

Embodiment 11 FIG. The eleventh embodiment is a further modification of the seventh embodiment as a modification of the sixth embodiment. FIG. 22 is a block diagram showing the configuration of the clock phase error detection unit 53c. The clock phase error detection unit 53c can be adopted as the clock phase error detection unit 53 included in the orthogonal frequency division multiplexed signal receiving device 104.

The clock phase error detecting section 53c is a tangent calculating section 5 of the clock phase error detecting section 53b shown in FIG.
05, the tangent averaging unit 508 is replaced by an imaginary part information extracting unit 509 and an imaginary part averaging unit 510.

Therefore, when the signal selection section 522 outputs the output R ^′ _{i, k} of the coordinate conversion section 504 according to the modulation scheme identification signal D, Im as in the eighth embodiment.
[R ^′ _{i, k} ] is given to the imaginary part averaging section 510. Also, when the signal selection unit 522 outputs the output R _{i, k} ^(p) of the complex multiplication unit 516 according to the modulation scheme identification signal D, the imaginary part information q _{i, k} ^(p) as in the ninth embodiment. Is the imaginary part averaging unit 5
10 given.

As described above, in the present embodiment, the one-symbol average value of the imaginary part information is used as the output of the clock phase error detector 5. Therefore, a circuit for determining the tangent or phase is not required, and the circuit scale can be reduced.

[0150]

According to the orthogonal frequency division multiplexed signal receiving apparatus according to the first and second aspects of the present invention, a phase locked loop for the phase error of the clock signal is provided, so Accurate and stable clock reproduction can be performed. Further, the frequency error of the clock signal can also be locally regarded as a phase error. Therefore,
An error rate after data reproduction of the orthogonal frequency division multiplexed signal is reduced.

According to the orthogonal frequency division multiplexed signal receiving apparatus of the third and fourth aspects of the present invention, the number of subcarriers for obtaining the phase error of the clock signal can be increased, and A detection output reflecting a phase error of a signal is required with high accuracy.

According to the orthogonal frequency division multiplexing signal receiving apparatus of the present invention, since the magnitudes of the absolute values of the subcarrier components for data transmission are all equal, the phase error of the clock signal is reflected. When finding the detection output,
There is no need to normalize by the size of the subcarrier component for data transmission.

According to the orthogonal frequency division multiplexed signal receiving apparatus according to the sixth aspect of the present invention, correction according to the frequency interval is required, and the detected value varies with respect to the phase error of the same clock signal. Can be avoided.

According to the orthogonal frequency division multiplexing signal receiving apparatus of the present invention, the detection output reflecting the phase error of the clock signal is determined by the phase difference between the data of the subcarrier component for data transmission. You can ask without.

According to the orthogonal frequency division multiplex signal receiving apparatus of the present invention, the phase error of the clock signal can be obtained based on the result of the coordinate-transformed complex multiplication.

According to the orthogonal frequency division multiplexing signal receiving apparatus of the ninth aspect of the present invention, it is not necessary to determine the phase based on the subcarrier component for data transmission.

According to the orthogonal frequency division multiplexed signal receiving apparatus of the tenth aspect of the present invention, it is not necessary to determine the tangent or phase based on the subcarrier component for data transmission.

In the orthogonal frequency division multiplexing signal receiving apparatus according to the eleventh aspect of the present invention, the phase error of the clock signal is determined by using a pilot subcarrier whose frequency and time arrangement is regular for each symbol. Therefore, the phase error of the clock signal can be obtained with higher accuracy than in the case where the phase difference is detected using a pilot subcarrier having an irregular frequency / time arrangement.

According to the orthogonal frequency division multiplexing signal receiving apparatus of the twelfth aspect of the present invention, the detection output reflecting the phase error of the clock signal is obtained for each symbol using the pilot subcarrier. Therefore, the number of sub-carriers for obtaining the phase error can be increased.

According to the orthogonal frequency division multiplexed signal receiving apparatus of the present invention, the phase error of the clock signal can be obtained irrespective of the value of the pilot subcarrier component. .

According to the orthogonal frequency division multiplexed signal receiving apparatus of the present invention, there is no need to determine the phase based on the result of the complex multiplication.

According to the orthogonal frequency division multiplexing signal receiving apparatus of the present invention, the output of the transmission path estimating section usually used for demodulating the synchronously modulated subcarrier is employed. Then, a detection output reflecting the phase error of the clock signal is obtained. Further, the number of sub-carriers for obtaining the phase error of the clock signal can be employed in a large number, and a detection output reflecting the phase error of the clock signal can be obtained with high accuracy.

According to the orthogonal frequency division multiplexed signal receiving apparatus of the eighteenth aspect of the present invention, there is no need to determine the phase based on the result of the complex multiplication.

According to the orthogonal frequency division multiplexed signal receiving apparatus of the present invention, there is no need to obtain complex multiplication, tangent, and phase.

According to the orthogonal frequency division multiplexing signal receiving apparatus of the twentieth aspect of the present invention, when receiving an orthogonal frequency division multiplexing signal in which differential modulation and synchronous modulation are mixed, a highly accurate clock recovery is performed. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a graph showing an operation of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a third embodiment of the present invention.

FIG. 5 is a graph showing an operation of the third embodiment of the present invention.

FIG. 6 is a graph showing an operation of the third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 8 is a schematic diagram showing the operation of the fourth embodiment of the present invention.

FIG. 9 is a conceptual diagram showing the operation of the fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a sixth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a sixth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a seventh embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a seventh embodiment of the present invention.

FIG. 17 is a block diagram showing a configuration of a seventh embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration of a seventh embodiment of the present invention.

FIG. 19 is a block diagram showing a configuration of an eighth embodiment of the present invention.

FIG. 20 is a block diagram showing the configuration of a ninth embodiment of the present invention.

FIG. 21 is a block diagram showing a configuration of a tenth embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of the eleventh embodiment of the present invention.

FIG. 23 is a block diagram showing a configuration of a conventional technique.

[Explanation of symbols]

a _{i, k} ^(p) known pilot data, first sub-carrier component for transmitting c _{i, k} data _, second sub-carrier component for transmitting p _{i, k} data _, first transmission path for c _{i, k} ^(p) pilot Characteristic components,
p _{i, k} ^(p) pilot second channel characteristic component, c _{i, k} ^(h)
First subcarrier transmission path characteristic component, p _{i, k} ^(h) Second subcarrier transmission path characteristic component, R _{i, k} , R ^′ _{i, k} complex signal, x _{i, k}
Subcarrier component, y _i detection output, θ _{i, k} phase.

Claims (20)

[Claims] 1. An analog / digital converter for sampling a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal, and based on an output of the analog / digital converter. A quadrature frequency division comprising: a Fourier transform unit that calculates a plurality of subcarrier components by using a clock output unit that outputs a clock signal based on a detection output that reflects a phase error of the clock signal obtained from the plurality of subcarrier components. A multiplex signal receiving device. 2. An analog / digital converter for sampling a received signal demodulated to a predetermined frequency band from an orthogonal frequency division multiplexed signal at a timing based on a clock signal, and an output of the analog / digital converter. A resampling unit for sampling, and a Fourier transform unit for obtaining a plurality of subcarrier components based on an output of the resampling unit, a detection output reflecting a phase error of the clock signal obtained from the plurality of subcarrier components. An orthogonal frequency division multiplexed signal receiving apparatus for resampling the output of the analog / digital conversion unit based on the signal. 3. The quadrature frequency division multiplexed signal according to claim 1, further comprising a clock phase error detection unit for obtaining the detection output based on a phase between the plurality of subcarrier components in the same symbol. Receiving device. 4. A plurality of transmission path characteristics are obtained based on the plurality of subcarrier components of different symbols and having different frequencies, and the detection output is obtained based on a phase between the plurality of transmission path characteristics. 3. An apparatus for receiving an orthogonal frequency division multiplexed signal according to claim 1. 5. The data transmission subcarrier in which the plurality of subcarrier components in the same symbol used for obtaining the detection output are QPSK-based modulation as orthogonal frequency division multiplex modulation. 4. The receiving apparatus for orthogonal frequency division multiplexed signals according to 3. 6. The data transmission sub-carrier component of at least one pair is used to determine the detection output, and an interval between the data transmission sub-carrier components of the at least one pair is constant. Item 6. An orthogonal frequency division multiplexed signal receiving device according to item 5. 7. The data transmission sub-carrier component extraction unit for extracting a plurality of data transmission sub-carrier components for each symbol, the clock phase error detection unit; Adjacent data transmission sub-carrier component separation means for outputting one pair of data transmission sub-carrier components, and a conjugate complex number converter that outputs one conjugate complex signal of the at least one pair of data transmission sub-carrier components The other of the at least one pair of data transmission subcarrier components, and a complex multiplier that outputs a complex multiplication result of the one of the conjugate complex signals of the at least one pair of data transmission subcarrier components, A coordinate conversion unit for performing a coordinate conversion for limiting the absolute value of the phase component of the complex multiplication result to 0 to π / 4 radian on a complex coordinate plane and outputting the result. The receiving apparatus of an orthogonal frequency division multiplexing signal according to claim 6, wherein. 8. A tangent calculation unit for obtaining and outputting a tangent of an output of the coordinate transformation unit; and a phase between the at least one pair of data transmission subcarrier components in the symbol from the output of the tangent calculation unit. The receiving apparatus for an orthogonal frequency division multiplexed signal according to claim 7, further comprising: a phase calculation unit that obtains the following equation; and a phase averaging unit that obtains the detection output by obtaining an average value of the phase for each symbol. 9. A tangent calculating section for obtaining and outputting a tangent of an output of the coordinate transforming section; and a tangent averaging section for obtaining an average value of an output of the tangent calculating section for each symbol to obtain the detection output. further comprising,
An apparatus for receiving an orthogonal frequency division multiplexed signal according to claim 7. 10. An imaginary part information extraction unit for obtaining and outputting an imaginary part of an output of the coordinate transformation unit, and an imaginary part for obtaining the detection output by obtaining an average value of outputs of the imaginary part information extraction part for each symbol. The receiving device for an orthogonal frequency division multiplexed signal according to claim 7, further comprising a partial averaging unit. 11. The detection output is obtained for each symbol using a pilot subcarrier, wherein the pilot subcarrier has a constant frequency interval within the same symbol and a constant frequency arrangement for each symbol. The orthogonal frequency division multiplexed signal receiving apparatus according to claim 4, which has an offset of: 12. A clock phase error detection unit for obtaining the detection output based on a phase between at least one pair of the pilot subcarrier components different by the offset over a plurality of symbols. An apparatus for receiving an orthogonal frequency division multiplexed signal according to the above. 13. A pilot phase subcarrier component extracting section for extracting the pilot subcarrier component for each symbol, a clock phase error detecting section, and a transmission path for dividing the pilot subcarrier component by known pilot data. 13. A division unit that outputs a characteristic component, and an adjacent transmission line characteristic component separation unit that outputs at least one pair of the transmission line characteristic components that differs by the offset over the plurality of symbols. For receiving orthogonal frequency division multiplexed signals. 14. A conjugate complex number converter that outputs one conjugate complex number signal of the at least one pair of transmission path characteristic components; the other of the at least one pair of transmission path characteristic components; A complex multiplication unit that outputs a complex multiplication result of the one of the conjugate complex number signals of a transmission path characteristic component, a tangent calculation unit that calculates and outputs a tangent of the complex multiplication result, and an output of the tangent calculation unit. In a symbol, further comprising: a phase calculation unit that obtains a phase between the at least one pair of transmission path characteristic components; and a phase averaging unit that obtains the detection output by obtaining an average value of the phase for each symbol. Item 14. An orthogonal frequency division multiplexed signal receiving device according to item 13. 15. A conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission path characteristic components; and the other of the at least one pair of transmission path characteristic components and the at least one pair of the transmission path characteristic components. A complex multiplication unit that outputs a complex multiplication result of the one of the conjugate complex number signals of a transmission path characteristic component, a tangent calculation unit that calculates and outputs a tangent of the complex multiplication result, and a tangent calculation unit for each symbol. And a tangent averaging unit for obtaining the detection output by obtaining an average value of the output,
The receiving apparatus for an orthogonal frequency division multiplexed signal according to claim 13. 16. The plurality of subcarrier components for pilot, the plurality of subcarrier components having a plurality of pilot subcarrier components inserted into the received signal for demodulation of a synchronously modulated subcarrier, The quadrature frequency division according to claim 4, further comprising: a transmission path estimating unit that estimates the plurality of transmission path characteristics based on the clock signal; and a clock phase error detection unit that obtains the detection output based on the plurality of transmission path characteristics. A multiplex signal receiving device. 17. An adjacent transmission line characteristic component separation unit that outputs at least one pair of the transmission line characteristic components, and a conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission line characteristic components. A complex multiplying unit that outputs a result of complex multiplication of the other of the at least one pair of transmission path characteristic components and the one of the conjugate complex number signals of the at least one pair of transmission path characteristic components; A tangent calculation unit that calculates and outputs a tangent of the result; a phase calculation unit that obtains a phase between the at least one pair of transmission path characteristic components in the symbol from an output of the tangent calculation unit; 17. The apparatus for receiving an orthogonal frequency division multiplexed signal according to claim 16, further comprising: a phase averaging unit that obtains the detection output by obtaining an average value of a phase. 18. An adjacent transmission line characteristic component separation unit that outputs at least one pair of the transmission line characteristic components, and a conjugate complex number conversion unit that outputs one conjugate complex number signal of the at least one pair of transmission line characteristic components. A complex multiplication unit that outputs a complex multiplication result of the other of the at least one pair of transmission path characteristic components and one of the conjugate complex number signals of the at least one pair of transmission path characteristic components; and A tangent calculating unit that calculates and outputs a tangent of the tangent, and a tangent averaging unit that obtains the detection output by obtaining an average value of the output of the tangent calculating unit for each symbol.
An apparatus for receiving an orthogonal frequency division multiplexed signal according to claim 16. 19. The at least one pair of transmission path characteristic components is obtained from a product of one real part of the at least one pair of transmission path characteristic components and the other imaginary part of the at least one pair of transmission path characteristic components. An imaginary part information generation unit that generates imaginary part information by subtracting a product of the one imaginary part of the component and the other real part of the at least one pair of transmission path characteristic components; and the imaginary part for each symbol. 2. The imaginary part averaging unit that obtains the detection output by obtaining an average value of information.
An apparatus for receiving an orthogonal frequency division multiplexed signal according to claim 3 or claim 16. 20. When the plurality of subcarrier components are differentially modulated, the detection output is obtained based on a phase between the plurality of subcarrier components in the same symbol. If the sub-carrier component is a tuned modulation, the detection output is obtained based on the phase between at least one pair of specific pilot sub-carrier components that differ by a predetermined offset over a plurality of symbols, The orthogonal frequency according to any one of claims 1 and 2, wherein the specific pilot subcarrier has a constant frequency interval within the same symbol and the frequency arrangement has the predetermined offset for each symbol. A receiving device for a division multiplex signal.