JP2005039524A - Ofdm receiver - Google Patents

Ofdm receiver Download PDF

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JP2005039524A
JP2005039524A JP2003274529A JP2003274529A JP2005039524A JP 2005039524 A JP2005039524 A JP 2005039524A JP 2003274529 A JP2003274529 A JP 2003274529A JP 2003274529 A JP2003274529 A JP 2003274529A JP 2005039524 A JP2005039524 A JP 2005039524A
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circuit
carrier
phase difference
output
value
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Nobuaki Otaka
伸章 大鷹
Ryosuke Watanabe
亮介 渡辺
Toru Abe
徹 阿部
Kazuhisa Ikuiwa
量久 生岩
Takako Kanamori
香子 金森
Toshihiro Negishi
俊裕 根岸
Kenichi Tsuchida
健一 土田
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Fujitsu Ltd
Japan Broadcasting Corp
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Fujitsu Ltd
Nippon Hoso Kyokai NHK
Japan Broadcasting Corp
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<P>PROBLEM TO BE SOLVED: To provide an OFDM receiver capable of highly accurately detecting a CN value indicating receiving quality. <P>SOLUTION: An AC/TMCC carrier selection circuit 10 selects an AC/TMCC carrier from an output of an FFT circuit 5. A delay memory 11 delays the carrier outputted from the AC/TMCC carrier selection circuit 10 by one symbol. A phase difference detection circuit 12 detects a phase difference between the carrier outputted from the AC/TMCC carrier selection circuit 10 and the carrier of one symbol before which is outputted from the delay memory 11. A dispersion calculation circuit 15 calculates a phase error from a difference between the phase difference outputted from the phase difference calculation circuit 12 and a reference phase and calculates the dispersion of phase errors of the AC/TMCC carrier for one symbol. An average circuit 16 calculates an average value of symbol directions outputted from the dispersion calculation circuit 15 and outputs a CN value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、ＯＦＤＭ（Orthogonal Frequency Division Multiplexing：直交周波数分割多重）伝送方式のデジタル放送システム等で使用される受信装置、いわゆるＯＦＤＭ受信装置に関する。   The present invention relates to a receiving apparatus used in a digital broadcasting system or the like of an OFDM (Orthogonal Frequency Division Multiplexing) transmission system, a so-called OFDM receiving apparatus.

デジタル信号伝送方式の一種としてＯＦＤＭ伝送方式が知られている。ＯＦＤＭ伝送方式は、周波数軸上で直交する複数のキャリアにデータを割り当てて伝送する方式であり、送信側ではＩＦＦＴ（Inverse Fast Fourier Transform：逆高速フーリエ変換）による変調が行われ、受信側ではＦＦＴ（Fast Fourier Transform：高速フーリエ変換）による復調が行われる。   An OFDM transmission system is known as a kind of digital signal transmission system. The OFDM transmission method is a method in which data is assigned to a plurality of carriers orthogonal on the frequency axis and transmitted. The transmission side performs modulation by IFFT (Inverse Fast Fourier Transform), and the reception side performs FFT. Demodulation is performed by (Fast Fourier Transform).

ＯＦＤＭ伝送方式は、周波数利用効率が高いことから、地上波デジタル放送への適用が広く検討されており、例えば、ＤＶＢ−Ｔ（Digital Video Broadcasting-Terrestrial）やＩＳＤＢ−Ｔ（Integrated Services Digital Broadcasting-Terrestrial）では、ＯＦＤＭ伝送方式が採用されている。   Since the OFDM transmission system has high frequency utilization efficiency, its application to terrestrial digital broadcasting has been widely studied. For example, DVB-T (Digital Video Broadcasting-Terrestrial) and ISDB-T (Integrated Services Digital Broadcasting-Terrestrial ) Employs an OFDM transmission scheme.

ＯＦＤＭ伝送方式で伝送される各キャリアは異なる変調方式を用いることができ、同期検波を用いるＱＡＭ方式や、周波数同期を必要としない差動変調方式などが選択可能であり、ビットレート、伝送路の状態、伝送情報の重要性などから決定される。   Each carrier transmitted in the OFDM transmission scheme can use a different modulation scheme, and a QAM scheme using synchronous detection or a differential modulation scheme that does not require frequency synchronization can be selected. It is determined from the status and importance of transmission information.

ＩＳＤＢ−Ｔでは、データキャリアは６４ＱＡＭ、１６ＱＡＭ、ＱＰＳＫ、ＤＱＰＳＫによる変調が行われ、ＳＰ（Scattered Pilot：分散パイロット）キャリアとＣＰ（Continual Pilot：連続パイロット）キャリアはＢＰＳＫによる変調が行われ、ＡＣ（Auxiliary Channel：補助チャネル）キャリアやＴＭＣＣ（Transmission and Multiplexing Configuration Control：伝送多重制御）キャリアはＤＢＰＳＫによる変調が行われる。   In ISDB-T, data carriers are modulated by 64QAM, 16QAM, QPSK, and DQPSK, SP (Scattered Pilot) carriers and CP (Continual Pilot) carriers are modulated by BPSK, and AC ( Auxiliary channel (auxiliary channel) carriers and TMCC (Transmission and Multiplexing Configuration Control) carriers are modulated by DBPSK.

図８はＩＳＤＢ−ＴにおけるＳＰキャリア、ＡＣキャリア及びＴＭＣＣキャリアの挿入位置を示す図である。すなわち、ＩＳＤＢ−Ｔでは、ＳＰキャリアは、周波数方向に１２キャリア毎に、かつ、１シンボル毎に３キャリア分位置がシフトするように挿入され、ＡＣキャリアとＴＭＣＣキャリアは、周波数選択性の妨害への耐性が考慮され、周波数軸上にランダムに特定の位置に挿入される。   FIG. 8 is a diagram showing the insertion positions of SP carrier, AC carrier and TMCC carrier in ISDB-T. That is, in ISDB-T, SP carriers are inserted every 12 carriers in the frequency direction and 3 carriers are shifted for each symbol, and the AC carrier and the TMCC carrier cause interference with frequency selectivity. Is inserted at a specific position randomly on the frequency axis.

地上波デジタル放送においては、受信装置のアンテナ調整などの際には、受信品質を示す信号（ＣＮ［Carrier to Noise Ratio］値）が用いられる。ＣＮ値の検出方法として、例えば、受信電力レベルを用いる方法や、ＳＰキャリアの送信時の基準点からのずれを算出する方法が提案されている（例えば、特許文献１〜３参照）。
特開平１１−２５２０４０号公報 特開２００２−２６８６０号公報 特開２００２−１５８６３１号公報 In terrestrial digital broadcasting, a signal (CN [Carrier to Noise Ratio] value) indicating reception quality is used for antenna adjustment of a receiving device. As a CN value detection method, for example, a method using a received power level and a method of calculating a deviation from a reference point at the time of transmission of an SP carrier have been proposed (for example, see Patent Documents 1 to 3).
Japanese Patent Laid-Open No. 11-252040 Japanese Patent Laid-Open No. 2002-26860 JP 2002-158631 A

受信電力レベルを用いてＣＮ値を検出する方法は、受信信号にノイズが加算された場合でも、受信レベルが増加するため、正確なＣＮ値を検出することができないという問題点を有している。   The method of detecting the CN value using the received power level has a problem that even if noise is added to the received signal, the received level increases, and thus an accurate CN value cannot be detected. .

また、ＳＰキャリアの送信時の基準点からのずれを算出してＣＮ値を検出する方法は、マルチパス等、受信側で等化処理による補正が可能な妨害に対しても、受信品質に影響を与えるため、正確な受信品質を検出することができないという問題点を有している。   In addition, the method of detecting the CN value by calculating the deviation from the reference point at the time of transmission of the SP carrier affects the reception quality even for interference that can be corrected by equalization processing on the reception side, such as multipath. Therefore, there is a problem that accurate reception quality cannot be detected.

本発明は、かかる点に鑑み、受信品質を示すＣＮ値を高精度に検出することができるようにしたＯＦＤＭ受信装置を提供することを目的とする。   In view of this point, an object of the present invention is to provide an OFDM receiver capable of detecting a CN value indicating reception quality with high accuracy.

本発明のＯＦＤＭ受信装置は、受信信号内の同一キャリア番号の所定キャリアの所定シンボル期間間隔での位相差を検出する位相差検出回路と、該位相差検出回路の出力からＣＮ値を算出するＣＮ値算出回路を有するというものである。   An OFDM receiver of the present invention includes a phase difference detection circuit that detects a phase difference at a predetermined symbol period interval of a predetermined carrier having the same carrier number in a received signal, and a CN that calculates a CN value from the output of the phase difference detection circuit It has a value calculation circuit.

本発明によれば、受信信号内の同一キャリア番号の所定キャリアの所定シンボル期間間隔での位相差からＣＮ値を算出することができるので、マルチパス等の影響を取り除いた妨害成分のみの検出が可能であり、高精度のＣＮ値を得ることができる。   According to the present invention, since the CN value can be calculated from the phase difference of the predetermined carrier of the same carrier number in the received signal at the predetermined symbol period interval, it is possible to detect only the interference component without the influence of multipath or the like. This is possible, and a highly accurate CN value can be obtained.

（第１実施形態・・図１〜図５）
図１は本発明の第１実施形態の要部を示す回路図である。図１中、１はアンテナ、２はアンテナ１で受信された高周波信号を入力して、選択されたチャネルの高周波信号を中間周波数信号に変換して出力するチューナ、３はチューナ２の出力をアナログ信号からデジタル信号に変換するＡ／Ｄ変換回路である。 (First embodiment: FIGS. 1 to 5)
FIG. 1 is a circuit diagram showing the main part of the first embodiment of the present invention. In FIG. 1, 1 is an antenna, 2 is a tuner that inputs a high-frequency signal received by the antenna 1, converts a high-frequency signal of a selected channel into an intermediate frequency signal, and 3 is an analog output of the tuner 2. It is an A / D conversion circuit that converts a signal into a digital signal.

４はＡ／Ｄ変換回路３の出力を複素ベースバンド信号に変換する直交復調回路、５は直交復調回路４から出力される複素ベースバンド信号を時間領域信号から周波数領域信号に変換してキャリアデータを出力するＦＦＴ回路である。   4 is an orthogonal demodulation circuit that converts the output of the A / D conversion circuit 3 into a complex baseband signal, and 5 is a carrier data obtained by converting the complex baseband signal output from the orthogonal demodulation circuit 4 from a time domain signal to a frequency domain signal. Is an FFT circuit.

６はＦＦＴ回路５から出力されるキャリアの中のデータキャリアの等化処理をＳＰキャリアにより得られる伝送路の周波数応答に基づいて行い、復調データを出力する等化処理回路、７は等化処理回路６から出力される復調データについて誤り訂正処理を行い、受信データを出力する誤り訂正回路である。   6 is an equalization processing circuit for performing the equalization processing of the data carrier in the carrier output from the FFT circuit 5 based on the frequency response of the transmission path obtained by the SP carrier and outputting demodulated data, and 7 is the equalization processing This is an error correction circuit that performs error correction processing on the demodulated data output from the circuit 6 and outputs received data.

８はＡＣデータ及びＴＭＣＣデータを復調するＡＣ・ＴＭＣＣデータ復調回路、９はＣＮ値を検出するＣＮ値検出回路であり、１０はＦＦＴ回路５の出力からＡＣキャリアとＴＭＣＣキャリアを選択し、周波数の低いキャリアの順に出力するＡＣ・ＴＭＣＣキャリア選択回路、１１はＡＣ・ＴＭＣＣキャリア選択回路１０から出力されるキャリアを１シンボル期間遅延する遅延メモリである。   8 is an AC / TMCC data demodulating circuit for demodulating AC data and TMCC data, 9 is a CN value detecting circuit for detecting a CN value, 10 is an AC carrier and TMCC carrier selected from the output of the FFT circuit 5, An AC / TMCC carrier selection circuit 11 for outputting in the order of lower carriers is a delay memory 11 for delaying the carrier output from the AC / TMCC carrier selection circuit 10 by one symbol period.

１２はＡＣ・ＴＭＣＣキャリア選択回路１０から出力されるキャリアと遅延メモリ１１から出力される１シンボル前のキャリアとの位相差を検出する位相差検出回路、１３は位相差検出回路１２から出力されるＡＣキャリアの位相差データとＴＭＣＣキャリアの位相差データからＡＣデータとＴＭＣＣデータを復調するＡＣ・ＴＭＣＣ復調回路である。   Reference numeral 12 denotes a phase difference detection circuit that detects the phase difference between the carrier output from the AC / TMCC carrier selection circuit 10 and the carrier one symbol before output from the delay memory 11. Reference numeral 13 denotes the phase difference detection circuit 12. It is an AC / TMCC demodulation circuit that demodulates AC data and TMCC data from phase difference data of an AC carrier and phase difference data of a TMCC carrier.

１４はＣＮ値算出回路であり、１５は位相差検出回路１２から出力される位相差と基準位相との差から位相誤差を算出し、１シンボル分のＡＣキャリア及びＴＭＣＣキャリアの位相誤差の分散を算出する分散算出回路である。   Reference numeral 14 denotes a CN value calculation circuit. Reference numeral 15 denotes a phase error calculated from the difference between the phase difference output from the phase difference detection circuit 12 and the reference phase, and the variance of the phase error of the AC carrier and TMCC carrier for one symbol is calculated. It is a dispersion | distribution calculation circuit to calculate.

分散は、位相誤差の２乗を１シンボル内のキャリア数で平均したものであるが、ハードウェア化の容易性を考慮し、位相差の絶対値の１シンボル内での平均を取る方法もある。なお、分散は、１シンボル内のＡＣキャリア、ＴＭＣＣキャリアを全て読み込んだ時点で計算されて出力される。   The variance is obtained by averaging the square of the phase error by the number of carriers in one symbol, but there is also a method of taking the average of the absolute value of the phase difference within one symbol in consideration of ease of hardware implementation. . The variance is calculated and output when all the AC carrier and TMCC carrier in one symbol are read.

１６は分散算出回路１５から出力される分散のシンボル方向の平均値を算出して最終的なＣＮ値を出力する平均回路である。   Reference numeral 16 denotes an average circuit that calculates an average value in the symbol direction of the variance output from the variance calculation circuit 15 and outputs a final CN value.

図２は位相差検出回路１２の第１構成例を示す回路図である。図２中、１７はＡＣ・ＴＭＣＣキャリア選択回路１０から出力されるキャリアの位相を計算する位相計算回路、１８は遅延メモリ１１から出力されるキャリアの位相を計算する位相計算回路、１９は位相計算回路１７、１８の出力の差分を演算して位相差を出力する差分回路である。   FIG. 2 is a circuit diagram showing a first configuration example of the phase difference detection circuit 12. In FIG. 2, 17 is a phase calculation circuit for calculating the phase of the carrier output from the AC / TMCC carrier selection circuit 10, 18 is a phase calculation circuit for calculating the phase of the carrier output from the delay memory 11, and 19 is a phase calculation circuit. It is a difference circuit that calculates a difference between outputs of the circuits 17 and 18 and outputs a phase difference.

図３は位相差検出回路１２の第２構成例を示す回路図である。図３中、２０は遅延メモリ１１から出力されるキャリアの複素共役を求める複素共役回路、２１はＡＣ・ＴＭＣＣキャリア選択回路１０の出力と複素共役回路２０の出力とを乗算する乗算回路、２２は乗算回路２１の出力から、ＡＣ・ＴＭＣＣキャリア選択回路１０から出力されるキャリアと遅延メモリ１１から出力されるキャリアの位相差を計算する位相差計算回路である。   FIG. 3 is a circuit diagram showing a second configuration example of the phase difference detection circuit 12. In FIG. 3, 20 is a complex conjugate circuit for obtaining the complex conjugate of the carrier output from the delay memory 11, 21 is a multiplication circuit that multiplies the output of the AC / TMCC carrier selection circuit 10 and the output of the complex conjugate circuit 20, 22 This is a phase difference calculation circuit that calculates the phase difference between the carrier output from the AC / TMCC carrier selection circuit 10 and the carrier output from the delay memory 11 from the output of the multiplication circuit 21.

例えば、ＡＣ・ＴＭＣＣキャリア選択回路１０の出力をｒ1exp(jθ1)、遅延メモリ１１の出力をｒ2exp(jθ2)とすると、複素共役回路２０の出力はｒ2exp(-jθ2)となる。この結果、乗算回路２１の出力はｒ1ｒ2exp(j(θ1-θ2))となり、位相差計算回路２２の出力は、θ1−θ2となる。 For example, if the output of the AC / TMCC carrier selection circuit 10 is r 1 exp (jθ 1 ) and the output of the delay memory 11 is r 2 exp (jθ 2 ), the output of the complex conjugate circuit 20 is r 2 exp (−jθ 2). ). As a result, the output of the multiplication circuit 21 is r 1 r 2 exp (j (θ 1 −θ 2 )), and the output of the phase difference calculation circuit 22 is θ 1 −θ 2 .

ここで、ＡＣキャリア及びＴＭＣＣキャリアはＤＢＰＳＫ変調されており、“０”を伝送する場合には、前シンボルと同位相のデータが送信され、“１”を伝送する場合には前シンボルに対して１８０度の位相差をつけたデータが送信される。   Here, the AC carrier and the TMCC carrier are DBPSK modulated. When “0” is transmitted, data having the same phase as that of the previous symbol is transmitted, and when “1” is transmitted, the data is transmitted with respect to the previous symbol. Data with a phase difference of 180 degrees is transmitted.

したがって、位相差検出回路１２の出力は、伝送路特性による位相回転の影響が相殺され、図４に示すように理想的な位相差の値である０度又は１８０度（基準位相）から、妨害の影響により位相誤差が加算されたものとなる。   Therefore, the output of the phase difference detection circuit 12 cancels out the influence of the phase rotation due to the transmission line characteristics, and the interference from the ideal phase difference value of 0 degrees or 180 degrees (reference phase) as shown in FIG. The phase error is added due to the influence of.

図５は平均回路１６の構成を示す回路図である。２３は加算回路、２４は分散算出回路１５から出力される分散をＮシンボル分遅延するＮシンボル分遅延回路（但し、Ｎは任意の整数）、２５は加算回路２３の出力からＮシンボル分遅延回路２４の出力を減算する減算回路、２６は減算回路２５の出力を順次更新しながら格納するレジスタ、２７はレジスタ２６の出力をＮで除算する除算回路である。   FIG. 5 is a circuit diagram showing the configuration of the averaging circuit 16. 23 is an adder circuit, 24 is an N symbol delay circuit that delays the variance output from the variance calculation circuit 15 by N symbols (where N is an arbitrary integer), and 25 is an N symbol delay circuit from the output of the adder circuit 23. A subtracting circuit that subtracts the output of 24, a register 26 that stores the output of the subtracting circuit 25 while sequentially updating it, and a dividing circuit 27 that divides the output of the register 26 by N.

平均回路１６では、加算回路２３で分散算出回路１５の出力とレジスタ２６の出力が加算され、減算回路２５で加算回路２３の出力からＮシンボル分遅延回路２４の出力が減算され、減算回路２５の出力がレジスタ２６に格納される。   In the averaging circuit 16, the output of the variance calculation circuit 15 and the output of the register 26 are added by the adding circuit 23, and the output of the delay circuit 24 for N symbols is subtracted from the output of the adding circuit 23 by the subtracting circuit 25. The output is stored in register 26.

即ち、レジスタ２６には常に過去Ｎシンボル分の分散算出回路１５の出力の総和が保存される。そして、除算回路２７でレジスタ２６の出力値がＮを除数として除算されることにより、Ｎシンボル分についての分散算出回路１５の出力の移動平均値がＣＮ値として算出される。   That is, the register 26 always stores the total sum of the outputs of the variance calculation circuit 15 for the past N symbols. Then, the division circuit 27 divides the output value of the register 26 by using N as a divisor, whereby the moving average value of the output of the variance calculation circuit 15 for N symbols is calculated as the CN value.

以上のように、本発明の第１実施形態によれば、ＡＣ・ＴＭＣＣキャリア選択回路１０と遅延メモリ１１と位相差検出回路１２を設け、同一キャリア番号のＡＣキャリア、ＴＭＣＣキャリアの１シンボル期間間隔での位相差を算出し、この位相差からＣＮ値を算出するとしているので、マルチパス等の影響を取り除いた妨害成分のみの検出が可能となり、高精度のＣＮ値を得ることができる。   As described above, according to the first embodiment of the present invention, the AC / TMCC carrier selection circuit 10, the delay memory 11, and the phase difference detection circuit 12 are provided, and one symbol period interval between the AC carrier and the TMCC carrier of the same carrier number is provided. Since the phase difference is calculated and the CN value is calculated from this phase difference, it is possible to detect only the interference component from which the influence of multipath or the like is removed, and a highly accurate CN value can be obtained.

なお、本発明の第１実施形態では、ＣＮ値検出回路９はＡＣキャリア及びＴＭＣＣキャリアを用いているが、ＡＣキャリア及びＴＭＣＣキャリアのいずれか一方のみを用いるようにしても良い。   In the first embodiment of the present invention, the CN value detection circuit 9 uses an AC carrier and a TMCC carrier. However, only one of the AC carrier and the TMCC carrier may be used.

（第２実施形態・・図６、図７）
図６は本発明の第２実施形態の要部を示す回路図である。本発明の第２実施形態は、本発明の第１実施形態が備えるＣＮ値検出回路９と回路構成の異なるＣＮ値検出回路２８を設け、その他については、本発明の第１実施形態と同様に構成したものである。 (Second embodiment. FIG. 6 and FIG. 7)
FIG. 6 is a circuit diagram showing the main part of the second embodiment of the present invention. In the second embodiment of the present invention, a CN value detection circuit 28 having a circuit configuration different from that of the CN value detection circuit 9 provided in the first embodiment of the present invention is provided, and the others are the same as in the first embodiment of the present invention. It is composed.

ＣＮ値検出回路２８において、２９はＦＦＴ回路５の出力からＳＰキャリアを選択して出力するＳＰキャリア選択回路、３０はＳＰキャリア選択回路２９から出力されるＳＰキャリアを４シンボル分遅延する遅延メモリ、３１はＳＰキャリア選択回路２９から出力されるＳＰキャリアと遅延メモリ３０から出力される４シンボル前のＳＰキャリアの位相差を検出する位相差検出回路である。   In the CN value detection circuit 28, 29 is an SP carrier selection circuit that selects and outputs an SP carrier from the output of the FFT circuit 5, 30 is a delay memory that delays the SP carrier output from the SP carrier selection circuit 29 by 4 symbols, A phase difference detection circuit 31 detects the phase difference between the SP carrier output from the SP carrier selection circuit 29 and the SP carrier four symbols before output from the delay memory 30.

ここで、ＳＰキャリアは常に固定データを伝送するので、基準位相は０度のみである。即ち、位相差検出回路３１の出力は、伝送路特性による位相回転の影響が相殺され、図７に示すように理想的な位相差の値である０度（基準位相）から、妨害の影響により位相誤差が加算されたものとなる。   Here, since the SP carrier always transmits fixed data, the reference phase is only 0 degree. That is, the output of the phase difference detection circuit 31 is offset by the effect of phase rotation due to the transmission path characteristics, and from the ideal phase difference value of 0 degrees (reference phase) as shown in FIG. The phase error is added.

また、図６中、３２はＣＮ値算出回路であり、３３は位相差検出回路３１から出力される位相差と基準位相との差から位相誤差を算出し、１シンボル分のＳＰキャリアの位相誤差の分散を算出する分散算出回路である。   In FIG. 6, 32 is a CN value calculation circuit, 33 is a phase error calculated from the difference between the phase difference output from the phase difference detection circuit 31 and the reference phase, and the phase error of the SP carrier for one symbol. Is a variance calculation circuit for calculating the variance of

本実施形態でも、分散は、位相誤差の２乗を１シンボル内のキャリア数で平均したものであるが、ハードウェア化の容易性を考慮し、位相差の絶対値の１シンボル内での平均を取る方法もある。なお、分散は、１シンボル内のＳＰキャリアを全て読み込んだ時点で計算されて出力される。   Also in this embodiment, the variance is obtained by averaging the square of the phase error by the number of carriers in one symbol. However, in consideration of the ease of hardware implementation, the average of the absolute value of the phase difference within one symbol. There is also a way to take. The variance is calculated and output when all the SP carriers in one symbol are read.

３４は分散算出回路３３から出力される分散のシンボル方向の平均値を算出して最終的なＣＮ値を出力する平均回路であり、本発明の第１実施形態が備える平均回路１６と同様の構成を有するものである。   34 is an average circuit that calculates the average value in the symbol direction of the variance output from the variance calculation circuit 33 and outputs the final CN value, and has the same configuration as the average circuit 16 provided in the first embodiment of the present invention. It is what has.

以上のように、本発明の第２実施形態によれば、ＳＰキャリア選択回路２９と遅延メモリ３０と位相差検出回路３１を設け、同一キャリア番号のＳＰキャリアの４シンボル期間間隔での位相差を算出し、この位相差からＣＮ値を算出するとしているので、マルチパス等の影響を取り除いた妨害成分のみの検出が可能となり、高精度のＣＮ値を得ることができる。   As described above, according to the second embodiment of the present invention, the SP carrier selection circuit 29, the delay memory 30, and the phase difference detection circuit 31 are provided, and the phase difference between the four carrier periods of the SP carrier having the same carrier number is obtained. Since the CN value is calculated and calculated from this phase difference, it is possible to detect only the interference component from which the influence of multipath or the like is removed, and a highly accurate CN value can be obtained.

本発明の第１実施形態の要部を示す回路図である。It is a circuit diagram which shows the principal part of 1st Embodiment of this invention. 本発明の第１実施形態が備える位相差検出回路の第１構成例を示す回路図である。FIG. 3 is a circuit diagram illustrating a first configuration example of a phase difference detection circuit included in the first embodiment of the present invention. 本発明の第１実施形態が備える位相差検出回路の第２構成例を示す回路図である。It is a circuit diagram which shows the 2nd structural example of the phase difference detection circuit with which 1st Embodiment of this invention is provided. 本発明の第１実施形態が備える位相差検出回路の出力を説明するための図である。It is a figure for demonstrating the output of the phase difference detection circuit with which 1st Embodiment of this invention is provided. 本発明の第１実施形態が備える平均回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the average circuit with which 1st Embodiment of this invention is provided. 本発明の第２実施形態の要部を示す回路図である。It is a circuit diagram which shows the principal part of 2nd Embodiment of this invention. 本発明の第２実施形態が備える位相差検出回路の出力を説明するための図である。It is a figure for demonstrating the output of the phase difference detection circuit with which 2nd Embodiment of this invention is provided. ＩＳＤＢ−ＴにおけるＳＰキャリア、ＡＣキャリア及びＴＭＣＣキャリアの挿入位置を示す図である。It is a figure which shows the insertion position of SP carrier, AC carrier, and TMCC carrier in ISDB-T.

符号の説明Explanation of symbols

１…アンテナ
２…チューナ
３…Ａ／Ｄ変換器
４…直交復調回路
５…ＦＦＴ回路
６…等化処理回路
７…誤り訂正回路
８…ＡＣ・ＴＭＣＣデータ復調回路
９…ＣＮ値検出回路
１０…ＡＣ・ＴＭＣＣキャリア選択回路
１１…遅延メモリ
１２…位相差検出回路
１３…ＡＣ・ＴＭＣＣ復調回路
１４…ＣＮ値算出回路
１５…分散算出回路
１６…平均回路
１７、１８…位相計算回路
１９…差分回路
２０…複素共役回路
２１…乗算回路
２２…位相差計算回路
２３…加算回路
２４…Ｎシンボル分遅延回路
２５…減算回路
２６…レジスタ
２７…除算回路
２８…ＣＮ値検出回路
２９…ＳＰキャリア選択回路
３０…遅延メモリ
３１…位相差検出回路
３２…ＣＮ値算出回路
３３…分散算出回路
３４…平均回路
DESCRIPTION OF SYMBOLS 1 ... Antenna 2 ... Tuner 3 ... A / D converter 4 ... Orthogonal demodulation circuit 5 ... FFT circuit 6 ... Equalization processing circuit 7 ... Error correction circuit 8 ... AC / TMCC data demodulation circuit 9 ... CN value detection circuit 10 ... AC TMCC carrier selection circuit 11 ... delay memory 12 ... phase difference detection circuit 13 ... AC / TMCC demodulation circuit 14 ... CN value calculation circuit 15 ... dispersion calculation circuit 16 ... average circuit 17, 18 ... phase calculation circuit 19 ... difference circuit 20 ... Complex conjugate circuit 21 ... Multiplication circuit 22 ... Phase difference calculation circuit 23 ... Addition circuit 24 ... Delay circuit for N symbols 25 ... Subtraction circuit 26 ... Register 27 ... Division circuit 28 ... CN value detection circuit 29 ... SP carrier selection circuit 30 ... Delay Memory 31 ... Phase difference detection circuit 32 ... CN value calculation circuit 33 ... Dispersion calculation circuit 34 ... Average circuit

Claims (4)

受信信号内の同一キャリア番号の所定キャリアの所定シンボル期間間隔での位相差を検出する位相差検出回路と、該位相差検出回路の出力からＣＮ値を算出するＣＮ値算出回路を有することを特徴とするＯＦＤＭ受信装置。   A phase difference detection circuit that detects a phase difference at a predetermined symbol period interval of a predetermined carrier of the same carrier number in a received signal, and a CN value calculation circuit that calculates a CN value from an output of the phase difference detection circuit An OFDM receiver. 前記所定キャリアは、補助チャネルキャリア及び伝送多重制御キャリアのいずれか一方又は両方又は分散パイロットキャリアであることを特徴とする請求項１記載のＯＦＤＭ受信装置。   2. The OFDM receiver according to claim 1, wherein the predetermined carrier is one or both of an auxiliary channel carrier and a transmission multiplexing control carrier, or a distributed pilot carrier. 高速フーリエ変換回路の出力から前記所定キャリアを選択する選択回路と、該選択回路の出力を所定シンボル期間遅延する遅延回路を有し、
前記位相差検出回路は、前記選択回路の出力と前記遅延回路の出力から前記所定キャリアの所定シンボル期間間隔での位相差を検出することを特徴とする請求項１記載のＯＦＤＭ受信装置。 A selection circuit that selects the predetermined carrier from the output of the fast Fourier transform circuit, and a delay circuit that delays the output of the selection circuit for a predetermined symbol period,
2. The OFDM receiver according to claim 1, wherein the phase difference detection circuit detects a phase difference of the predetermined carrier at a predetermined symbol period interval from the output of the selection circuit and the output of the delay circuit. 前記ＣＮ値算出回路は、前記位相差検出回路から出力される位相差の分散を算出する分散算出回路と、該分散算出回路から出力される分散のシンボル方向の平均を算出する平均回路を有することを特徴とする請求項１記載のＯＦＤＭ受信装置。
The CN value calculating circuit includes a variance calculating circuit that calculates a variance of the phase difference output from the phase difference detecting circuit, and an averaging circuit that calculates an average of the symbol direction of the variance output from the variance calculating circuit. The OFDM receiver according to claim 1.
JP2003274529A 2003-07-15 2003-07-15 Ofdm receiver Pending JP2005039524A (en)

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098840A (en) * 2006-10-10 2008-04-24 Nippon Hoso Kyokai <Nhk> Pilot signal receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098840A (en) * 2006-10-10 2008-04-24 Nippon Hoso Kyokai <Nhk> Pilot signal receiver

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