JP4856523B2 - 半導体構造体及び半導体構造体を製造する方法 - Google Patents
半導体構造体及び半導体構造体を製造する方法 Download PDFInfo
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- 238000005229 chemical vapour deposition Methods 0.000 description 9
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
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- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
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- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
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- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
埋め込まれたeヒューズを含む少なくとも1つのヒューズ開口部を有する半導体基板が備わり、埋め込まれたeヒューズは、少なくとも1つのヒューズ開口部の側壁部分及び底壁部分上に配置され、かつ、側壁部分において半導体基板内に配置された隣接するドープ領域と電気接触した状態にある。
少なくとも1つのヒューズ開口部の側壁部分及び底壁部分の内側を少なくともヒューズ材料が覆うように、少なくとも1つのヒューズ開口部を半導体基板内に提供することと、
隣接する浅いトレンチ分離領域を半導体基板内に形成することであって、隣接する浅いトレンチ分離領域の形成中に、少なくとも1つの開口部内のヒューズ材料の外縁部分がトリミングされて、残りの半導体アイランドによって定められる少なくとも1つのヒューズ開口部の側壁部分に位置合わせされた埋め込まれたeヒューズが形成されるようにすることと、
埋め込まれたeヒューズと電気接触した状態のドープ領域を残りの半導体アイランド内に形成することと
を含む。
10A:下部半導体層
10B:埋込み絶縁層
10C:上部半導体層
12:誘電体キャップ
14:ヒューズ開口部
16:フォトレジト層
18:ヒューズ材料
20:浅いトレンチ分離(STI)領域
24:ゲート誘電体
26:ゲート導体
32:第1の導電性のイオン
36:第2の導電性のイオン
38:スペーサ
40:シリサイド領域
42:第1の相互接続レベル
44:層間誘電体
50:バルク半導体基板
Claims (8)
- 埋め込まれたeヒューズを含む少なくとも1つのヒューズ開口部を有する半導体基板を備え、
前記埋め込まれたeヒューズは、前記少なくとも1つのヒューズ開口部の側壁部分及び底壁部分上に配置され、かつ、前記側壁部分において前記半導体基板内に配置された隣接するドープ領域と電気接触した状態にあり、前記半導体基板が埋め込み絶縁層を含む半導体オン・インシュレータであり、
前記半導体オン・インシュレータの前記埋め込み絶縁層がヒューズ開口部の底壁部分を構成する、半導体構造体。 - 半導体構造体を製造する方法であって、
少なくとも1つのヒューズ開口部の側壁部分及び底壁部分の内側を少なくともヒューズ材料が覆うように、少なくとも1つのヒューズ開口部を半導体基板内に形成することと、 隣接する浅いトレンチ分離領域を前記半導体基板内に形成することであって、前記隣接する浅いトレン分離領域の形成中に、前記少なくとも1つの開口部内の前記ヒューズ材料の外縁部分がトリミングされて、残りの半導体アイランドによって定められる該少なくとも1つのヒューズ開口部の前記側壁部分に位置合わせされた埋め込まれたeヒューズが形成されるようにすることと、
前記埋め込まれたeヒューズと電気接触した状態のドープ領域を前記残りの半導体アイランド内に形成することと、
を含み、
前記少なくとも1つのヒューズ開口部を形成することは、リソグラフィ及びエッチングを含み、前記半導体基板は半導体オン・インシュレータ基板であり、前記エッチングを、前記半導体オン・インシュレータ基板の埋込み絶縁層の上で停止させる、前記の方法。 - 前記少なくとも1つのヒューズ開口部を形成することは、前記ヒューズ材料を形成する前に、少なくとも前記底壁上に電気絶縁材料又は熱絶縁材料を形成することを含む、請求項2に記載の方法。
- 前記隣接する浅いトレンチ分離領域を形成する間に、トレンチ誘電体材料が、前記少なくとも1つのヒューズ開口部内に充填される、請求項2に記載の方法。
- 前記eヒューズは、金属、金属合金、及び付着によって形成されたこれらの多層スタックからなる群から選択されるヒューズ材料からなる、請求項2に記載の方法。
- 前記ドープ領域を前記残りの半導体アイランド内に形成することは、イオン注入プロセスを用いる少なくとも1つの半導体デバイスの形成中に行われる、請求項2に記載の方法。
- 前記少なくとも1つの半導体デバイスは電界効果トランジスタを含む、請求項6に記載の方法。
- 前記半導体基板の上に、導電性に充填された接触開口部を有する層間誘電体を含む相互接続レベルを提供することをさらに含む、請求項2に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/290,890 US7381594B2 (en) | 2005-11-30 | 2005-11-30 | CMOS compatible shallow-trench efuse structure and method |
US11/290890 | 2005-11-30 |
Publications (2)
Publication Number | Publication Date |
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JP2007158330A JP2007158330A (ja) | 2007-06-21 |
JP4856523B2 true JP4856523B2 (ja) | 2012-01-18 |
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JP2006317786A Expired - Fee Related JP4856523B2 (ja) | 2005-11-30 | 2006-11-24 | 半導体構造体及び半導体構造体を製造する方法 |
Country Status (3)
Country | Link |
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US (1) | US7381594B2 (ja) |
JP (1) | JP4856523B2 (ja) |
CN (1) | CN100483715C (ja) |
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US7064409B2 (en) * | 2003-11-04 | 2006-06-20 | International Business Machines Corporation | Structure and programming of laser fuse |
US7986029B2 (en) * | 2005-11-08 | 2011-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual SOI structure |
US7491585B2 (en) * | 2006-10-19 | 2009-02-17 | International Business Machines Corporation | Electrical fuse and method of making |
US7960809B2 (en) * | 2009-01-16 | 2011-06-14 | International Business Machines Corporation | eFuse with partial SiGe layer and design structure therefor |
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US8816473B2 (en) | 2012-04-05 | 2014-08-26 | International Business Machines Corporation | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication |
US9293414B2 (en) | 2013-06-26 | 2016-03-22 | Globalfoundries Inc. | Electronic fuse having a substantially uniform thermal profile |
US9159667B2 (en) | 2013-07-26 | 2015-10-13 | Globalfoundries Inc. | Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure |
US9214567B2 (en) * | 2013-09-06 | 2015-12-15 | Globalfoundries Inc. | Nanowire compatible E-fuse |
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WO2015122870A1 (en) * | 2014-02-11 | 2015-08-20 | Intel Corporation | Antifuse with backfilled terminals |
US9431339B2 (en) | 2014-02-19 | 2016-08-30 | International Business Machines Corporation | Wiring structure for trench fuse component with methods of fabrication |
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US6828689B2 (en) * | 2002-07-08 | 2004-12-07 | Vi Ci Civ | Semiconductor latches and SRAM devices |
US7064018B2 (en) * | 2002-07-08 | 2006-06-20 | Viciciv Technology | Methods for fabricating three dimensional integrated circuits |
US7002829B2 (en) * | 2003-09-30 | 2006-02-21 | Agere Systems Inc. | Apparatus and method for programming a one-time programmable memory device |
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2005
- 2005-11-30 US US11/290,890 patent/US7381594B2/en not_active Expired - Fee Related
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2006
- 2006-10-26 CN CNB2006101429950A patent/CN100483715C/zh not_active Expired - Fee Related
- 2006-11-24 JP JP2006317786A patent/JP4856523B2/ja not_active Expired - Fee Related
Also Published As
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US20070120218A1 (en) | 2007-05-31 |
CN1976035A (zh) | 2007-06-06 |
CN100483715C (zh) | 2009-04-29 |
US7381594B2 (en) | 2008-06-03 |
JP2007158330A (ja) | 2007-06-21 |
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