JP4844042B2 - Flat panel display - Google Patents

Description

  The present invention relates to a flat display device that displays information such as characters and images, and more particularly, to a flat display device that is characterized by the arrangement of incorporated spacers.

  As an image display device that can replace the mainstream cathode ray tube (CRT), various types of flat display devices have been studied. Examples of such a flat display device include a liquid crystal display device (LCD), an electroluminescence display device (ELD), and a plasma display device (PDP). Development of a flat display device incorporating an electron-emitting device is also underway. Here, as the electron-emitting device, a cold cathode field electron-emitting device, a metal / insulating film / metal-type device (also called MIM device), and a surface conduction electron-emitting device are known. The flat display device incorporating the electron-emitting device is attracting attention from the viewpoint of high resolution, high luminance color display, and low power consumption.

  A cold cathode field emission display device (hereinafter sometimes abbreviated as a display device), which is a flat display device incorporating a cold cathode field emission device, generally corresponds to each pixel arranged in a two-dimensional matrix. The cathode panel having the electron emission region and the anode panel having a phosphor layer that emits light when excited by collision with electrons emitted from the electron emission region are arranged to face each other through a vacuum layer. The electron emission region is usually provided with one or a plurality of cold cathode field emission devices (hereinafter sometimes abbreviated as field emission devices). Examples of field emission devices include Spindt type, flat type, edge type, and planar type.

  As an example, a conceptual partial end view of a display device having a Spindt-type field emission device is shown in FIG. 8, and a schematic view of a part of the cathode panel CP and the anode panel AP when the cathode panel CP and the anode panel AP are disassembled. A simple exploded perspective view is shown in FIG. The Spindt-type field emission device constituting this display device was formed on the cathode 10 formed on the support 10, the insulating layer 12 formed on the support 10 and the cathode 11, and the insulating layer 12. A gate electrode 13 and an opening 14 provided in the gate electrode 13 and the insulating layer 12 (a first opening 14A provided in the gate electrode 13 and a second opening 14B provided in the insulating layer 12); It is composed of a conical electron emission portion 15 formed on the cathode electrode 11 located at the bottom of the opening 14.

  Alternatively, FIG. 9 shows a conceptual partial end view of a display device having a so-called flat type field emission device having a substantially planar electron emission portion 15A. The field emission device includes a cathode electrode 11 formed on a support 10, an insulating layer 12 formed on the support 10 and the cathode electrode 11, a gate electrode 13 formed on the insulating layer 12, a gate An opening 14 provided in the electrode 13 and the insulating layer 12 (a first opening 14A provided in the gate electrode 13 and a second opening 14B provided in the insulating layer 12) and a bottom of the opening 14 The electron emission portion 15A is formed on the cathode electrode 11 positioned. The electron emission portion 15A is composed of, for example, a large number of carbon nanotubes partially embedded in a matrix.

  In these display devices, the cathode electrode 11 has a strip shape extending in the Y direction, and the gate electrode 13 has a strip shape extending in the X direction different from the Y direction. In general, the cathode electrode 11 and the gate electrode 13 are each formed in a strip shape in a direction in which the projected images of both the electrodes 11 and 13 are orthogonal to each other. An overlapping region where the strip-shaped cathode electrode 11 and the strip-shaped gate electrode 13 overlap is an electron emission region EA, which corresponds to one subpixel. The electron emission areas EA are normally arranged in a two-dimensional matrix within the effective area of the cathode panel CP (area that functions as an actual display portion).

  On the other hand, the anode panel AP has a phosphor layer 22 (specifically, a red light-emitting phosphor layer 22R, a green light-emitting phosphor layer 22G, and a blue light-emitting phosphor layer 22B) having a predetermined pattern on the substrate 20. The phosphor layer 22 is formed and covered with the anode electrode 24. Between these phosphor layers 22, a light absorbing layer (black matrix) 23 made of a light absorbing material such as carbon is embedded to prevent display image color turbidity and optical crosstalk. ing. In the figure, reference numeral 21 represents a partition, reference numeral 40 represents a spacer, reference numeral 25 represents a spacer holding part, reference numeral 26 represents a frame, reference numeral 16 represents a focusing electrode, reference Reference numeral 17 represents an interlayer insulating layer. In FIG. 9 and FIG. 10, illustration of the partition walls, the spacers, the spacer holding portion, and the focusing electrode is omitted.

  The anode electrode 24 functions as a reflection film that reflects the light emitted from the phosphor layer 22, and rebounds from the phosphor layer 22 or secondary electrons emitted from the phosphor layer 22 (hereinafter referred to as these The electrons are collectively referred to as backscattered electrons) and have a function of preventing the phosphor layer 22 from being charged. The barrier rib 21 has a function of preventing so-called optical crosstalk (color turbidity) from occurring due to backscattered electrons colliding with another phosphor layer 22.

  One subpixel is composed of an electron emission area EA on the cathode panel side and a phosphor layer 22 on the anode panel side facing a group of these field emission elements. In the effective area, such pixels are arranged on the order of hundreds of thousands to millions, for example.

Then, the anode panel AP and the cathode panel CP are arranged so that the electron emission area EA and the phosphor layer 22 face each other, joined at the peripheral portion via the frame body 26, and then exhausted and sealed. Thus, a display device can be manufactured. A space surrounded by the anode panel AP, the cathode panel CP, and the frame body 26 is in a high vacuum (for example, 1 × 10 ⁻³ Pa or less).

Therefore, if the spacer 40 made of a high resistance material such as a ceramic material or glass is not disposed between the anode panel AP and the cathode panel CP, the display device is damaged by the atmospheric pressure. . Note that an antistatic film (not shown) made of, for example, CrO _x or CrAl _x O _y is usually formed on the surface of the spacer 40.

  A relatively negative voltage is applied to the cathode electrode 11 from the cathode electrode control circuit 31, a relatively positive voltage is applied to the gate electrode 13 from the gate electrode control circuit 32, and the anode electrode 24 is applied to the anode electrode 24 more than the gate electrode 13. Further, a higher positive voltage is applied from the anode electrode control circuit 33. When performing display in such a display device, for example, a scanning signal is input to the cathode electrode 11 from the cathode electrode control circuit 31, and a video signal is input to the gate electrode 13 from the gate electrode control circuit 32. Alternatively, a video signal is input from the cathode electrode control circuit 31 to the cathode electrode 11, and a scanning signal is input from the gate electrode control circuit 32 to the gate electrode 13. Electrons are emitted from the electron emission portions 15 and 15A based on the quantum tunnel effect due to an electric field generated when a voltage is applied between the cathode electrode 11 and the gate electrode 13, and the electrons are attracted to the anode electrode 24. It passes through 24 and collides with the phosphor layer 22. As a result, the phosphor layer 22 is excited to emit light, and a desired image can be obtained. That is, the operation of the cold cathode field emission display is basically controlled by the voltage applied to the gate electrode 13 and the voltage applied to the cathode electrode 11.

  17, 18, and 19 schematically show the trajectories of electrons or electron beams in one subpixel located in the vicinity of the spacer 40. In FIGS. 17, 18, and 19, the anode electrode, the light absorption layer (black matrix), the focusing electrode, and the like are not shown. Further, the gate electrode 13 extends in a direction perpendicular to the drawing sheet (X direction), and the cathode electrode 11 extends in a direction parallel to the drawing sheet (Y direction).

  As shown in FIG. 17, some of the electrons that have passed through an anode electrode (not shown) in the anode panel AP and collided with the phosphor layer 22 are back-scattered by the phosphor layer 22 as shown in FIG. Some of the backscattered electrons collide with the spacer 40.

  By the way, such backscattered electrons cause various problems.

  That is, some of the backscattered electrons collide with the spacer 40 in the vicinity of the spacer 40. In general, materials such as ceramic materials and glass having an excellent withstand voltage have a relatively high value of the total secondary electron emission coefficient (TSEEY), and the total secondary electron emission in a wide energy region where electrons collide with the spacer 40. The value of the coefficient is a value exceeding 1. Here, the total secondary electron emission coefficient (TSEEY) is represented by the sum of the secondary electron emission coefficient (SEEC) and the reflected electron coefficient (BC). As shown in FIG. 20, the total secondary electron emission coefficient is a function of the energy of the electron beam, and takes a maximum value in the vicinity of 450 eV in almost all substances. Further, the total secondary electron emission coefficient varies depending on the incident angle θ incident on the surface of the substance. Here, FIG. 20 shows the relationship between the energy of the electron beam and the total secondary electron emission coefficient (TSEEY) when the incident angle θ is 0 degree, 30 degrees, 60 degrees, and 80 degrees. FIG. 20 also shows that when the electrons enter the spacer 40 from an oblique direction, the value of the total secondary electron emission coefficient increases.

  FIG. 21A shows the energy distribution of electrons that collide with the spacer 40, and FIG. 21B shows the angular distribution of electrons that collide with the spacer 40. FIG. When the phosphor layer 22 is irradiated with an electron beam having an energy of 10 keV, the backscattered electrons are temporarily directed to the cathode panel CP side, but the electric field is positive on the anode panel AP side. take. Therefore, the electrons are incident (collised) with various energy distributions (see FIG. 21A) and various angles with respect to the spacer 40 (see FIG. 21B). Ideally, if the total secondary electron emission coefficient on the surface of the spacer 40 is 1, no charge-up occurs on the surface of the spacer 40. However, it is almost impossible to set the total secondary electron emission coefficient to 1 for electrons incident (collised) on the spacer 40 at various angles and various energies.

  As a result, a positive charge is generated on the surface of the spacer 40. Due to the positive charge, a parallel electric field is bent in the vicinity of the spacer 40, and the electron beam trajectory is curved. Further, the curvature of the electron beam trajectory further causes electrons to collide with the spacer 40. In the spacer 40, the charge-up is further increased, and the electron beam trajectory is further bent (see FIG. 19). In such a state, due to the disturbance of the electron beam trajectory in the vicinity of the spacer 40, the electron beam does not collide with the desired phosphor layer 22, and the formed image is distorted in the vicinity of the spacer 40, which seriously affects image formation. And the spacer 40 is visually recognized.

Further, when the electrons collide with the spacer 40, the resistance value of the spacer 40 varies. As described above, generally, the surface of the spacer 40 is coated with a transition metal oxide film made of CrO _x or CrAl _x O _y as an antistatic film. This transition metal oxide film is reduced by an electron beam. As a result, as shown in FIG. 2B, when the end surface of the spacer 40 in contact with the anode electrode 24 is set to z ₀ = ₀ mm, the portion of the spacer that occupies the region from z ₀ to z ₁ (mm) May become equipotential. Hereinafter, the spacer in which such a phenomenon has occurred may be referred to as “a spacer whose short-circuit region is z ₁ ” for convenience. Also, “z ₁ ” may be referred to as “the length of the short-circuit region in the z direction”. In FIG. 2B, the short-circuit region is hatched.

The result of examining how much the trajectory of the electron beam is disturbed by the presence of the spacer 40 is schematically shown in FIG. 22, and FIG. 22 is a view of the spacer 40 viewed from the cathode panel CP side. Here, FIG. 22 shows a state in which the equipotential lines change due to the presence of the spacer 40. Furthermore, the region of the anode electrode 24 to which the electron beam should originally collide is blackened with an elliptical region EB _R , and These are indicated by white oval regions EB _G and EB _B. Furthermore, the state in which the equipotential lines are changed due to the presence of the spacers 40 and the electron beam trajectory is shifted is represented by black arrows. Note that the numbers (3), (4),... (14) in FIG. 22 indicate the numbers of subpixels. Are adjacent to each other along the Y direction, while the subpixels of subpixel number (6) or less have no adjacent spacers 40. In addition, in the subpixel numbers (3), (4), (7) to (9), the black arrow indicating the state in which the electron beam trajectory is shifted is omitted.

In an isolated spacer 40 (see FIG. 22) having a short-circuit region of 100 μm, a deviation amount (movement amount) generated in the trajectory of the electron beam emitted from the electron emission region located adjacent to the spacer 40 and its extension line is obtained. The calculated results are shown in FIG. 23 (A) and (B). Here, the horizontal axes in FIGS. 23A and 23B indicate the subpixel numbers shown in FIG. 22, and the vertical axis in FIG. 23A indicates the Y direction generated in the trajectory of the electron beam ( The vertical axis of (B) in FIG. 23 is the shift amount (movement amount) in the X direction (see FIG. 22) generated in the trajectory of the electron beam. Note that the anode voltage V _A that is the voltage applied to the anode electrode 24 is 9 kilovolts, and the distance d ₀ between the cathode panel CP and the anode panel AP is 2.0 mm.

  It can be seen from FIGS. 23A and 23B that there is a large shift in the trajectory of the electron beam emitted from the electron emission region located in the vicinity of the end of the spacer 40. In particular, in the subpixel number (4) to the subpixel number (8), the light is emitted from the electron emission region corresponding to the subpixel number (i) (i = 4, 5,..., 8). The electron beam collides with the phosphor layer corresponding to the subpixel number (i + 1). It can also be seen that the deviation of the trajectory of the electron beam is larger in the X direction than in the Y direction.

JP 2004-127944 A

  By the way, in the effective area of the display device, one spacer may be disposed along the X direction, but a plurality of spacers may be disposed along the X direction. Note that the plurality of spacers in the latter case is referred to as a spacer group. In the latter case, a plurality of spacer groups are arranged at intervals along the Y direction. The distance between adjacent spacers constituting the spacer group is preferably 0 mm from the results shown in FIGS. 23A and 23B (for example, paragraph number [0175 of JP-A-2004-127944). ]).

  However, in practice, the distance between adjacent spacers constituting the spacer group is set to 0 mm due to dimensional variations in the manufacture of the spacers, variations caused when the spacers are attached to the display device, and the like. It is almost impossible to arrange the spacers without any gaps.

  Therefore, the object of the present invention is large in the trajectory of the electron beam emitted from the electron emission region located near the end of the spacer even when there is a gap between adjacent spacers constituting the spacer group. An object of the present invention is to provide a flat display device having a structure in which displacement is difficult to occur.

  The flat display device of the present invention includes a first panel in which a plurality of electron emission regions for emitting electrons are formed on a support, a phosphor layer and an anode electrode on which electrons emitted from the electron emission region collide, and a substrate. A flat panel display device in which a space sandwiched between the first panel and the second panel is held in a vacuum, and the second panel is formed in a vacuum. Between the two panels, a plurality of spacer groups composed of a plurality of spacers arranged on a straight line extending in the first direction are arranged along a second direction different from the first direction. ing.

In the flat display device according to the first aspect of the present invention for achieving the above object, when the distance between the first panel and the second panel is d ₀ (unit: mm), The distance d _S (unit: mm) between adjacent spacers constituting the spacer group is:
1/20 <d _S / d ₀ ≦ 1/4
It is characterized by satisfying. Note that the distance d ₀ between the first panel and the second panel is equivalent to the height of the spacer.

In the flat display device according to the second aspect of the present invention for achieving the above object, the distance d _S (unit: mm) between adjacent spacers constituting the spacer group is:
0.1 (mm) <d _S ≦ 0.5 (mm)
It is characterized by satisfying.

Furthermore, in the flat display device according to the third aspect of the present invention for achieving the above object, the distance d _S between adjacent spacers constituting the spacer group is:
(1) An orbit shift amount of the electron beam emitted from the electron emission region adjacent to the spacer (more specifically, adjacent along the second direction) due to the electric field formed by the spacer (first Each of the amount of deviation along the direction of and the amount of deviation along the second direction) is ± 5 μm or less, and
(2) A distance where no discharge occurs due to a difference in potential distribution in each spacer between adjacent spacers constituting the spacer group.
It is characterized by satisfying these two requirements.

  Note that the amount of orbital deviation of the electron beam emitted from the electron emission region is adjacent to the spacer (more specifically, adjacent to the second direction when no electric field is formed by the spacer). From the position of the phosphor layer where the electron beam emitted from the electron emitting region originally collides (position where the center of the potential beam collides) to the electric field formed by the spacer during the actual operation of the normal flat display device. Therefore, the position of the phosphor layer where the electron beam emitted from the electron emission region adjacent to the spacer (more specifically, along the second direction) collides (the position where the center of the potential beam collides). ) Along the first direction and the distance along the second direction.

  In the flat display device according to the first aspect, the second aspect or the third aspect of the present invention (hereinafter, these may be collectively referred to simply as the flat display device of the present invention). The flat display device can be a cold cathode field emission display device having an electron emission region composed of one or a plurality of cold cathode field emission devices, or a metal / insulating film / metal A flat display device having an electron emission region constituted by a type element (also referred to as an MIM element) and a flat display device having an electron emission region constituted by a surface conduction electron emission element can also be used.

  In the present invention, the spacer can be made of, for example, ceramics or glass. When the spacer is made of ceramics, the ceramics include mullite, alumina, barium titanate, lead zirconate titanate, zirconia, cordiolite, borosilicate barium, iron silicate, glass ceramic materials, titanium oxide and chromium oxide. Examples thereof include iron oxide, vanadium oxide, and nickel oxide added. In this case, the spacer can be manufactured by forming a so-called green sheet, firing the green sheet, and cutting the green sheet fired product. Moreover, soda-lime glass can be mentioned as glass which comprises a spacer. For example, the spacer may be fixed by being sandwiched between partition walls, which will be described later, provided on the second panel. Alternatively, for example, a spacer holding part may be formed on the second panel and fixed by the spacer holding part. That's fine.

An antistatic film may be provided on the surface of the spacer. The material constituting the antistatic film preferably has a secondary electron emission coefficient close to 1, and as the material constituting the antistatic film, a semimetal such as graphite, an oxide, a boride, a carbide, a sulfide, and A nitride or the like can be used. For example, compounds containing a metalloid element ₂ such as a semi-metal and MoSe such as _{graphite, CrO x, CrAl x O y} , Nd 2 O 3, La x Ba 2-x CuO 4, La x Ba 2-x CuO 4, Oxides such as La _x Y _1-x CrO ₃ , borides such as AlB ₂ and TiB ₂ , carbides such as SiC, sulfides such as MoS ₂ and WS ₂ , and nitrides such as BN, TiN and AlN In addition, for example, materials described in, for example, JP-T-2004-500688 can be used. The antistatic film may be composed of a single type of material, may be composed of a plurality of types of materials, may be a single layer structure, or may be a multilayer structure. May be. The antistatic film can be formed based on a known method such as a sputtering method, a vacuum deposition method, a chemical vapor deposition method (CVD method), or the like.

When the flat display device is a cold cathode field emission display device, the cold cathode field emission device (hereinafter referred to as field emission device) constituting the electron emission region is sometimes referred to as a first panel (hereinafter referred to as a cathode panel). Provided),
(A) a strip-shaped cathode electrode formed on the support and extending in the Y direction;
(B) an insulating layer formed on the cathode electrode and the support;
(C) a strip-shaped gate electrode formed on the insulating layer and extending in the X direction different from the Y direction;
(D) an opening provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and an exposed portion of the cathode electrode at the bottom; and
(E) an electron emission portion provided on the cathode electrode exposed at the bottom of the opening,
Consists of.

  The type of the field emission device is not particularly limited, and a Spindt-type field emission device (a field emission device in which a conical electron emission portion is provided on the cathode electrode positioned at the bottom of the opening) or a flat type field emission device An element (a field emission element in which a substantially planar electron emission portion is provided on a cathode electrode positioned at the bottom of an opening) can be given.

  It is preferable that the projected image of the cathode electrode and the projected image of the gate electrode are orthogonal, that is, the Y direction and the X direction are orthogonal from the viewpoint of simplifying the structure of the cold cathode field emission display. In the cathode panel, an overlapping region where the cathode electrode and the gate electrode overlap corresponds to an electron emission region, and the electron emission regions are arranged in a two-dimensional matrix, and each electron emission region includes one or more A field emission device is provided.

  In the cold cathode field emission display, a strong electric field generated by a voltage applied to the cathode electrode and the gate electrode is applied to the electron emission portion, and as a result, electrons are emitted from the electron emission portion by the quantum tunnel effect. The electrons are attracted to the second panel (anode panel) by the anode electrode provided on the second panel (sometimes referred to as an anode panel) and collide with the phosphor layer. As a result of the collision of electrons with the phosphor layer, the phosphor layer emits light and can be recognized as an image.

In the cold cathode field emission display, the cathode electrode is connected to the cathode electrode control circuit, the gate electrode is connected to the gate electrode control circuit, and the anode electrode is connected to the anode electrode control circuit. Note that these control circuits can be constituted by known circuits. During actual operation, the voltage (anode voltage) V _A applied to the anode electrode from the anode electrode control circuit is normally constant, and can be, for example, 5 to 15 kilovolts. Alternatively, when the distance between the anode panel and the cathode panel is d ₀ (where 0.5 mm ≦ d ₀ ≦ 10 mm), the value of V _A / d ₀ (unit: kilovolt / mm) is 0. It is desirable to satisfy 5 or more and 20 or less, preferably 1 or more and 10 or less, and more preferably 4 or more and 8 or less. In actual operation of the cold cathode field emission display, the voltage modulation method can be adopted as the gradation control method for the voltage V _C applied to the cathode electrode and the voltage V _G applied to the gate electrode.

A field emission device can be generally manufactured by the following method.
(1) forming a cathode electrode on a support;
(2) forming an insulating layer on the entire surface (on the support and the cathode electrode);
(3) forming a gate electrode on the insulating layer;
(4) forming an opening in a portion of the gate electrode and the insulating layer in a region where the cathode electrode and the gate electrode overlap, and exposing the cathode electrode at the bottom of the opening;
(5) A step of forming an electron emission portion on the cathode electrode located at the bottom of the opening.

Alternatively, the field emission device can be manufactured by the following method.
(1) forming a cathode electrode on a support;
(2) forming an electron emission portion on the cathode electrode;
(3) forming an insulating layer on the entire surface (on the support and the electron emission portion or on the support, the cathode electrode and the electron emission portion);
(4) forming a gate electrode on the insulating layer;
(5) A step of forming an opening in a portion of the gate electrode and the insulating layer in the overlapping region of the cathode electrode and the gate electrode, and exposing the electron emission portion at the bottom of the opening.

  The field emission device may be provided with a focusing electrode. That is, for example, a field emission element in which an interlayer insulating layer is further provided on the gate electrode and the insulating layer, and a focusing electrode is provided on the interlayer insulating layer, or a focusing electrode is provided above the gate electrode. It can also be a field emission device. Here, the focusing electrode is an electrode for converging the trajectory of emitted electrons that are emitted from the opening and directed toward the anode electrode, thereby improving the luminance and preventing optical crosstalk between adjacent pixels. It is. In a so-called high voltage type cold cathode field emission display, the potential difference between the anode electrode and the cathode electrode is on the order of several kilovolts or more and the distance between the anode electrode and the cathode electrode is relatively long. The electrode is particularly effective. A relative negative voltage (for example, 0 volts) is applied to the focusing electrode from the focusing electrode control circuit. The focusing electrode does not necessarily have to be individually formed so as to surround each of the electron emission portion or the electron emission region provided in the overlapping region where the cathode electrode and the gate electrode overlap, for example, the electron emission portion or The electron emission region may be extended along a predetermined arrangement direction, or the electron emission portion or the electron emission region may be surrounded by one focusing electrode (that is, the focusing electrode may be a cold cathode field electron). It may be a thin sheet-like structure covering the entire effective area, which is the central display area that performs a practical function as an emission display device), thereby providing a plurality of electron emission areas or electron emission areas. A common convergence effect can be exerted.

  In the Spindt-type field emission device, as the material constituting the electron emission portion, molybdenum, molybdenum alloy, tungsten, tungsten alloy, titanium, titanium alloy, niobium, niobium alloy, tantalum, tantalum alloy, chromium, chromium alloy, and And at least one material selected from the group consisting of silicon (polysilicon and amorphous silicon) containing impurities. The electron emission portion of the Spindt-type field emission device can be formed by, for example, a sputtering method or a CVD method in addition to the vacuum evaporation method.

In the flat field emission device, it is preferable that the material constituting the electron emission portion is composed of a material having a work function Φ smaller than that of the material constituting the cathode electrode. What is necessary is just to determine based on the work function of the material which comprises a cathode electrode, the electric potential difference between a gate electrode and a cathode electrode, the magnitude | size of the emission electron current density requested | required, etc. Alternatively, the material constituting the electron emission portion may be appropriately selected from materials in which the secondary electron gain δ of the material is larger than the secondary electron gain δ of the conductive material constituting the cathode electrode. In the flat type field emission device, carbon, more specifically, amorphous diamond or graphite, a carbon nanotube structure (carbon nanotube and / or graphite nanofiber), as a particularly preferable constituent material of the electron emission portion, Examples thereof include ZnO whiskers, MgO whiskers, SnO ₂ whiskers, MnO whiskers, Y ₂ O ₃ whiskers, NiO whiskers, ITO whiskers, In ₂ O ₃ whiskers, and Al ₂ O ₃ whiskers. In addition, the material which comprises an electron emission part does not necessarily need to be provided with electroconductivity.

The constituent materials of the cathode electrode, gate electrode, and focusing electrode are aluminum (Al), tungsten (W), niobium (Nb), tantalum (Ta), molybdenum (Mo), chromium (Cr), copper (Cu), gold ( Metals such as Au), silver (Ag), titanium (Ti), nickel (Ni), cobalt (Co), zirconium (Zr), iron (Fe), platinum (Pt), zinc (Zn); these metal elements Alloys (eg, MoW) or compounds (eg, nitrides such as TiN, silicides such as WSi ₂ , MoSi ₂ , TiSi ₂ , TaSi ₂ ); semiconductors such as silicon (Si); carbon thin films such as diamond; ITO ( Examples thereof include conductive metal oxides such as indium oxide-tin oxide, indium oxide, and zinc oxide. In addition, as a method for forming these electrodes, for example, a vapor deposition method such as an electron beam vapor deposition method or a hot filament vapor deposition method, a sputtering method, a combination of a CVD method, an ion plating method and an etching method; a screen printing method; Plating method and electroless plating method); lift-off method; laser ablation method; sol-gel method and the like. According to the screen printing method or the plating method, for example, a strip-like cathode electrode or gate electrode can be formed directly.

As a material for constituting the insulating layer and the interlayer insulating _{layer, SiO 2, BPSG, PSG,} BSG, AsSG, PbSG, SiON, SOG ( spin on glass), low-melting glass, SiO ₂ based materials such glass paste; SiN-based materials; polyimide These insulating resins can be used alone or in appropriate combination. For forming the insulating layer or the interlayer insulating layer, a known process such as a CVD method, a coating method, a sputtering method, or a screen printing method can be used.

  Planar shape of the first opening (opening formed in the gate electrode) or the second opening (opening formed in the insulating layer) (shape when the opening is cut in a virtual plane parallel to the support surface) ) Can be any shape such as a circle, an ellipse, a rectangle, a polygon, a rounded rectangle, a rounded polygon. The formation of the first opening can be performed by, for example, anisotropic etching, isotropic etching, a combination of anisotropic etching and isotropic etching, or, depending on the method of forming the gate electrode, The first opening can also be formed directly. The second opening can also be formed by, for example, anisotropic etching, isotropic etching, or a combination of anisotropic etching and isotropic etching.

  In the field emission device, depending on the structure of the field emission device, one electron emission portion may exist in one opening, or a plurality of electron emission portions may exist in one opening. In addition, a plurality of first openings are provided in the gate electrode, one second opening communicating with the first opening is provided in the insulating layer, and one or more are provided in one second opening provided in the insulating layer. There may be an electron emission portion.

In the field emission device, a resistor film may be provided between the cathode electrode and the electron emission portion. By providing the resistor film, the operation of the field emission device can be stabilized and the electron emission characteristics can be made uniform. As a material constituting the resistor film, a carbon-based material such as silicon carbide (SiC) or SiCN, a semiconductor material such as SiN or amorphous silicon, or a refractory metal oxide such as ruthenium oxide (RuO ₂ ), tantalum oxide, or tantalum nitride. It can be illustrated. Examples of the method for forming the resistor film include a sputtering method, a CVD method, and a screen printing method. The electrical resistance value per one electron emitting portion may be approximately 1 × 10 ⁶ to 1 × 10 ¹¹ Ω, preferably several tens of gigaΩ.

As a substrate constituting the first panel (or cathode panel) or as a substrate constituting the second panel (or anode panel), a glass substrate, a glass substrate having an insulating film formed on the surface, a quartz substrate, a surface Examples include a quartz substrate having an insulating film formed thereon, and a semiconductor substrate having an insulating film formed on the surface. From the viewpoint of reducing manufacturing costs, a glass substrate or a glass substrate having an insulating film formed on the surface Is preferably used. As a glass substrate, high strain point glass, soda glass (Na ₂ O · CaO · SiO ₂ ), borosilicate glass (Na ₂ O · B ₂ O ₃ · SiO ₂ ), forsterite (2MgO · SiO ₂ ), lead glass (Na ₂ O · PbO · SiO ₂ ) and alkali-free glass can be exemplified.

  In the flat display device, examples of the configuration of the anode electrode and the phosphor layer include (1) a configuration in which the anode electrode is formed on the substrate and the phosphor layer is formed on the anode electrode, and (2) on the substrate. The structure which forms a fluorescent substance layer and forms an anode electrode on a fluorescent substance layer can be mentioned. In the configuration (1), a so-called metal back film that is electrically connected to the anode electrode may be formed on the phosphor layer. In the configuration (2), a metal back film may be formed on the anode electrode.

The anode electrode may be composed of one anode electrode as a whole, or may be composed of a plurality of anode electrode units. In the latter case, the anode electrode unit and the anode electrode unit need to be electrically connected by a resistor layer. As the material constituting the resistor layer, carbon, carbon carbide (SiC), SiCN, and other carbon materials; SiN materials; ruthenium oxide (RuO ₂ ), tantalum oxide, tantalum nitride, chromium oxide, titanium oxide, and other high melting point metals Examples thereof include oxides; semiconductor materials such as amorphous silicon; ITO. It is also possible to realize a stable desired sheet resistance value by combining a plurality of films such as laminating a carbon thin film having a low resistance value on the SiC resistance film. Examples of the sheet resistance value of the resistor layer include 1 × 10 ⁻¹ Ω / □ to 1 × 10 ¹⁰ Ω / □, preferably 1 × 10 ³ Ω / □ to 1 × 10 ⁸ Ω / □. The number (Q) of anode electrode units may be two or more. For example, when the total number of rows of phosphor layers arranged in a straight line is q, Q = q or q = k · Q (K is an integer of 2 or more, preferably 10 ≦ k ≦ 100, more preferably 20 ≦ k ≦ 50), or a number obtained by adding 1 to the number of spacer groups arranged at a constant interval. Or a number that matches the number of pixels or subpixels, or an integer fraction of the number of pixels or subpixels. The size of each anode electrode unit may be the same regardless of the position of the anode electrode unit, or may vary depending on the position of the anode electrode unit. A resistor layer may be formed on one anode electrode as a whole.

The anode electrode (including the anode electrode unit) may be formed using a conductive material layer. Examples of the method of forming the conductive material layer include various physical vapor deposition methods (PVD methods) such as an evaporation method such as an electron beam evaporation method and a hot filament evaporation method, a sputtering method, an ion plating method, and a laser ablation method; Examples include CVD method; screen printing method; metal mask printing method; lift-off method; sol-gel method. That is, it is possible to form an anode electrode by forming a conductive material layer made of a conductive material and patterning the conductive material layer based on a lithography technique and an etching technique. Alternatively, the anode electrode can be obtained by forming a conductive material based on a PVD method or a screen printing method through a mask or screen having an anode electrode pattern. The resistor layer can also be formed by a similar method. That is, a resistor layer may be formed from a resistor material, and the resistor layer may be patterned based on a lithography technique and an etching technique, or the resistor material may be provided via a mask or screen having a resistor layer pattern. The resistor layer can be obtained by formation based on the PVD method or the screen printing method. 3 × 10 ⁻⁸ m (30 nm) to 5 as the average thickness of the anode electrode on the substrate (or above the substrate) (when the partition is provided as described later, the average thickness of the anode electrode on the top surface of the partition) Examples include x10 ⁻⁷ m (0.5 μm), preferably 5 × 10 ⁻⁸ m (50 nm) to 3 × 10 ⁻⁷ m (0.3 μm).

As the constituent material of the anode electrode, molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), niobium (Nb), tantalum (Ta), gold (Au), silver (Ag), titanium (Ti) ), Cobalt (Co), zirconium (Zr), iron (Fe), platinum (Pt), zinc (Zn), etc .; alloys or compounds containing these metal elements (for example, nitrides such as TiN, WSi ₂ Silicide such as MoSi ₂ , TiSi ₂ , TaSi ₂ ); Semiconductor such as silicon (Si); Carbon thin film such as diamond; Conductive metal oxide such as ITO (indium oxide-tin oxide), indium oxide, zinc oxide can do. When the resistor layer is formed, the anode electrode is preferably made of a conductive material that does not change the resistance value of the resistor layer. For example, when the resistor layer is made of silicon carbide (SiC), the anode electrode is It is preferable to comprise from molybdenum (Mo).

  The phosphor layer may be composed of single-color phosphor particles or may be composed of three primary color phosphor particles. The phosphor layer is arranged in a dot pattern. Specifically, when the flat display device is a color display, examples of the arrangement and arrangement of the phosphor layers include a delta arrangement, a stripe arrangement, a diagonal arrangement, and a rectangle arrangement. That is, one line of the phosphor layers arranged in a straight line is occupied by a line occupied by the red light emitting phosphor layer, a line occupied by the green light emitting phosphor layer, and a blue light emitting phosphor layer. It may be comprised from the row | line | column, and it may be comprised from the row | line | column in which the red light emission fluorescent substance layer, the green light emission fluorescent substance layer, and the blue light emission fluorescent substance layer were arrange | positioned in order. Here, the phosphor layer is defined as a phosphor region that generates one bright spot on the second panel (anode panel). Further, one pixel (one pixel) is composed of a set of one red light emitting phosphor layer, one green light emitting phosphor layer, and one blue light emitting phosphor layer, and one subpixel is one phosphor. It is composed of layers (one red-emitting phosphor layer, one green-emitting phosphor layer, or one blue-emitting phosphor layer). A gap between adjacent phosphor layers may be filled with a light absorption layer (black matrix) for the purpose of improving contrast.

  The phosphor layer uses a luminescent crystal particle composition prepared from luminescent crystal particles. For example, a red photosensitive luminescent crystal particle composition (red phosphor slurry) is applied to the entire surface, exposed, Development is performed to form a red light-emitting phosphor layer, and then a green photosensitive light-emitting crystal particle composition (green phosphor slurry) is applied to the entire surface, exposed, and developed to form a green light-emitting phosphor layer. Further, a blue light-emitting phosphor crystal particle composition (blue phosphor slurry) is coated on the entire surface, exposed and developed to form a blue light-emitting phosphor layer. . Alternatively, after sequentially applying the red light emitting phosphor slurry, the green light emitting phosphor slurry, and the blue light emitting phosphor slurry, each phosphor slurry may be sequentially exposed and developed to form each phosphor layer. Each phosphor layer may be formed by a screen printing method, an inkjet method, a float coating method, a sedimentation coating method, a phosphor film transfer method, or the like. The average thickness of the phosphor layer on the substrate is not limited, but is preferably 3 μm to 20 μm, preferably 5 μm to 10 μm. The phosphor material constituting the luminescent crystal particles can be appropriately selected from conventionally known phosphor materials. In the case of color display, a phosphor material whose color purity is close to the three primary colors specified by NTSC, white balance is achieved when the three primary colors are mixed, the afterglow time is short, and the afterglow time of the three primary colors is almost equal. It is preferable to combine them.

  The light absorption layer that absorbs light from the phosphor layer is preferably formed between adjacent phosphor layers or between the partition wall and the substrate from the viewpoint of improving the contrast of the display image. Here, the light absorption layer functions as a so-called black matrix. As the material constituting the light absorption layer, it is preferable to select a material that absorbs 90% or more of light from the phosphor layer. Such materials include carbon, metal thin films (eg, chromium, nickel, aluminum, molybdenum, etc., or alloys thereof), metal oxides (eg, chromium oxide), metal nitrides (eg, chromium nitride), heat resistance Materials such as photosensitive organic resins, glass pastes, glass pastes containing conductive particles such as black pigments and silver, and specifically, photosensitive polyimide resins, chromium oxides, and chromium oxide / chromium laminated films Can be illustrated. In the chromium oxide / chromium laminated film, the chromium film is in contact with the substrate. The light absorption layer depends on the material used, for example, a combination of a vacuum deposition method, a sputtering method and an etching method, a combination of a vacuum deposition method, a sputtering method, a spin coating method and a lift-off method, a screen printing method, a lithography technique, etc. Thus, it can be formed by an appropriately selected method.

  In order to prevent the electrons recoiled from the phosphor layer or the secondary electrons emitted from the phosphor layer from entering other phosphor layers, so-called optical crosstalk (color turbidity) is generated. Alternatively, it is preferable to provide a partition wall in order to prevent electrons recoiled from the phosphor layer or secondary electrons emitted from the phosphor layer from colliding with other phosphor layers.

  Examples of the partition wall forming method include a screen printing method, a dry film method, a photosensitive method, a casting method, and a sandblast forming method. Here, in the screen printing method, an opening is formed in a portion of the screen corresponding to a portion where a partition is to be formed, and the partition forming material on the screen is passed through the opening using a squeegee, and the partition is formed on the substrate. In this method, after the formation material layer is formed, the partition wall formation material layer is fired. The dry film method is a method of laminating a photosensitive film on a substrate, removing the photosensitive film at the part where the partition wall is to be formed by exposure and development, embedding the partition wall forming material in the opening generated by the removal, and baking. . The photosensitive film is burned and removed by baking, and the partition wall-forming material embedded in the openings remains to form partition walls. The photosensitive method is a method in which a barrier rib-forming material layer having photosensitivity is formed on a substrate, the barrier rib-forming material layer is patterned by exposure and development, and then fired (cured). The casting method (embossing molding method) refers to a method for forming a partition wall forming material layer by extruding a partition wall forming material layer made of a paste-like organic material or inorganic material onto a substrate from a mold (cast). In this method, the partition wall forming material layer is fired. The sand blast forming method is, for example, forming a partition wall forming material layer on a substrate using a screen printing or metal mask printing method, a roll coater, a doctor blade, a nozzle discharge type coater, etc. In this method, the part of the partition wall forming material layer to be covered is covered with a mask layer, and then the exposed part of the partition wall forming material layer is removed by sandblasting. After the partition wall is formed, the partition wall may be polished to flatten the top surface of the partition wall.

  As the planar shape of the part surrounding the phosphor layer in the partition wall (corresponding to the inner contour line of the projected image of the partition wall side surface, which is a kind of opening region), rectangular shape, circular shape, elliptical shape, oval shape, triangular shape, Examples include pentagonal or more polygonal shapes, rounded triangular shapes, rounded rectangular shapes, rounded polygons, and the like. By arranging these planar shapes (planar shapes of the opening regions) in a two-dimensional matrix, a grid-like partition is formed. This two-dimensional matrix-like arrangement may be arranged, for example, like a cross or like a zigzag.

Examples of the partition wall forming material include photosensitive polyimide resin, lead glass colored with a metal oxide such as cobalt oxide, SiO ₂ , and a low melting point glass paste. A protective layer (for example, made of SiO ₂ , SiON, or AlN) is provided on the surface (top surface and side surface) of the partition wall to prevent an electron beam from colliding with the partition wall and releasing gas from the partition wall. It may be formed.

The first panel and the second panel are joined at the periphery, but the joining may be performed using an adhesive layer, or a frame made of an insulating rigid material such as glass or ceramics and an adhesive layer are used in combination. You may go. When the frame and the adhesive layer are used in combination, the distance between the first panel and the second panel can be further increased by appropriately selecting the height of the frame as compared with the case where only the adhesive layer is used. It can be set longer. As a constituent material of the adhesive layer, frit glass is generally used, but a so-called low melting point metal material having a melting point of about 120 to 400 ° C. may be used. Such low melting point metal materials include In (indium: melting point 157 ° C.); indium-gold based low melting point alloy; Sn ₈₀ Ag ₂₀ (melting point 220 to 370 ° C.), Sn ₉₅ Cu ₅ (melting point 227 to 370 ° C.) C) tin (Sn) type high temperature solder such as Pb _97.5 Ag _2.5 (melting point 304 ° C.), Pb _94.5 Ag _5.5 (melting point 304 to 365 ° C.), Pb _97.5 Ag _1.5 Sn _1.0 (melting point 309 ° C.), etc. Lead (Pb) high temperature solder; zinc (Zn) high temperature solder such as Zn ₉₅ Al ₅ (melting point 380 ° C.); Sn ₅ Pb ₉₅ (melting point 300 to 314 ° C.), Sn ₂ Pb ₉₈ (melting point 316 to 322) Tin-lead standard solder such as ° C); brazing material such as Au ₈₈ Ga ₁₂ (melting point 381 ° C) (the above subscripts all represent atomic%).

  When joining the first panel, the second panel, and the frame, the three parties may be joined at the same time, or in the first stage, either the first panel or the second panel and the frame. And the other of the first panel or the second panel and the frame may be joined in the second stage. If the three-party simultaneous bonding or the second stage bonding is performed in a high vacuum atmosphere, the space surrounded by the first panel, the second panel, the frame body, and the adhesive layer becomes a vacuum simultaneously with the bonding. Or after completion | finish of joining of three parties, the space enclosed by the 1st panel, the 2nd panel, the frame, and the contact bonding layer can be exhausted, and it can also be set as a vacuum. When exhausting after joining, the pressure of the atmosphere at the time of joining may be normal pressure / depressurized, and the gas constituting the atmosphere may be air, or nitrogen gas or group 0 of the periodic table An inert gas containing a gas belonging to (for example, Ar gas) may be used.

  When exhaust is performed, exhaust can be performed through a tip tube connected in advance to the first panel and / or the second panel. The tip tube is typically a glass tube, or a metal or alloy having a low coefficient of thermal expansion [for example, an iron (Fe) alloy containing 42% by weight of nickel (Ni), 42% by weight of nickel (Ni), A hollow tube made of an iron (Fe) alloy containing 6% by weight of chromium (Cr)] and serving as an ineffective area of the first panel and / or the second panel (practical function as a flat display device) Around the penetrating part provided in the frame surrounding the effective area, which is the display area in the center, is joined using frit glass or the above-mentioned low melting point metal material, and the space reaches a predetermined degree of vacuum. After that, it is sealed by thermal fusion or sealed by pressure bonding. In addition, if the whole flat display device is once heated and then cooled before sealing, it is preferable because residual gas can be released into the space, and this residual gas can be removed out of the space by exhaust. .

In the flat display device of the present invention, by defining the relationship between the distance d ₀ between the first panel and the second panel and the distance d _S between adjacent spacers constituting the spacer group. , Alternatively, by defining the value of the distance d _S between spacers adjacent constituting a spacer group, or alternatively, the distance d _S between spacers adjacent constituting the spacer group satisfies the two requirements As a result, even if the distance d _S between adjacent spacers constituting the spacer group exceeds 0, there is a large shift in the trajectory of the electron beam emitted from the electron emission region located near the end of the spacer. It becomes difficult to occur. As a result, a flat display device capable of displaying a high-quality image with high uniformity can be provided.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to a flat display device according to the first, second, and third aspects of the present invention. Here, more specifically, the flat display device of Example 1 includes a cold cathode field emission display device (hereinafter, abbreviated as a display device). A schematic partial sectional view of the display device of Example 1 having a Spindt-type cold cathode field emission device (hereinafter referred to as a field emission device) is the same as that shown in FIG. 8, and has a flat type field emission device. A schematic partial cross-sectional view of the display device of Example 1 is the same as that shown in FIG. Further, the first panel (cathode panel CP) and the second panel (anode panel AP) when the first panel (hereinafter referred to as cathode panel CP) and the second panel (hereinafter referred to as anode panel AP) are disassembled. A schematic exploded perspective view of a part is the same as that shown in FIG.

  That is, in the display device of Example 1, the first panel (cathode panel CP) in which a plurality of electron emission areas EA that emit electrons are formed on the support 10 and the electrons emitted from the electron emission area EA collide with each other. A second panel (anode panel AP) formed by forming the phosphor layer 22 and the anode electrode 24 on the substrate 20 is joined at the peripheral edge thereof, and the first panel (cathode panel CP) and the second panel (anode). This is a display device in which the space between the panel AP) is held in a vacuum.

Here, in Example 1, the field emission device constituting the electron emission region is constituted by, for example, a Spindt type field emission device. Here, the Spindt-type field emission device, as shown in FIG.
(A) a cathode electrode 11 formed on the support 10;
(B) an insulating layer 12 formed on the support 10 and the cathode electrode 11;
(C) a gate electrode 13 formed on the insulating layer 12;
(D) the opening 14 provided in the gate electrode 13 and the insulating layer 12 (the first opening 14A provided in the gate electrode 13 and the second opening 14B provided in the insulating layer 12), and
(E) a conical electron emission portion 15 formed on the cathode electrode 11 located at the bottom of the opening 14;
It is composed of

Or in Example 1, the field emission element is comprised from the flat type field emission element, for example. Here, as shown in FIG.
(A) a cathode electrode 11 formed on the support 10;
(B) an insulating layer 12 formed on the support 10 and the cathode electrode 11;
(C) a gate electrode 13 formed on the insulating layer 12;
(D) the opening 14 provided in the gate electrode 13 and the insulating layer 12 (the first opening 14A provided in the gate electrode 13 and the second opening 14B provided in the insulating layer 12), and
(E) an electron emission portion 15A formed on the cathode electrode 11 located at the bottom of the opening 14;
It is composed of The electron emission portion 15A is composed of, for example, a large number of carbon nanotubes partially embedded in a matrix.

  In the cathode panel CP, the cathode electrode 11 has a strip shape extending in the Y direction, and the gate electrode 13 has a strip shape extending in the X direction different from the Y direction. The cathode electrode 11 and the gate electrode 13 are each formed in a strip shape in a direction in which the projected images of both the electrodes 11 and 13 are orthogonal to each other. A plurality of field emission elements are provided in the electron emission area EA corresponding to one subpixel. Further, the focusing electrode 16 is provided on the interlayer insulating layer 17 along a predetermined arrangement direction of the field emission elements, and a common convergence effect can be exerted on the plurality of field emission elements.

  In Example 1, the anode panel AP includes the substrate 20 and the phosphor layer 22 formed on the substrate 20 (in the case of color display, the red light-emitting phosphor layer 22R, the green light-emitting phosphor layer 22G, the blue light-emitting phosphor). A body layer 22B) and an anode electrode 24 covering the phosphor layer 22. That is, the anode panel AP is more specifically formed on the substrate 20 and the substrate 20 between the partition walls 21 formed on the substrate 20 and the phosphor layer 22 made of a large number of phosphor particles. (A red light emitting phosphor layer 22R, a green light emitting phosphor layer 22G, a blue light emitting phosphor layer 22B), and an anode electrode 24 formed on the phosphor layer 22. The anode electrode 24 is made of aluminum (Al) having a thickness of about 70 nm, is in the form of a thin sheet that covers the effective region, and is provided so as to cover the partition wall 21 and the phosphor layer 22. Between the phosphor layer 22 and the phosphor layer 22, and between the partition wall 21 and the substrate 20, a light absorption layer (black) is used to prevent the occurrence of color turbidity and optical crosstalk in the display image. Matrix) 23 is formed.

  An example of the arrangement | positioning state of the partition 21, the spacer 40, and the fluorescent substance layer 22 is typically shown in FIGS. The arrangement of the phosphor layers and the like in the display device shown in FIG. 8 or FIG. 9 is the configuration shown in FIG. 12 or FIG. Also, the anode electrode is not shown in FIGS. The planar shape of the partition wall 21 is a lattice shape (cross-beam shape), that is, a shape corresponding to one subpixel, for example, a shape surrounding the four sides of the phosphor layer 22 having a substantially rectangular planar shape (FIGS. 11, 12, 13, 14), or a belt-like shape extending in parallel with two opposing sides of the substantially rectangular (or belt-like) phosphor layer 22 (see FIGS. 15 and 16). In the phosphor layer 22 shown in FIG. 15, the phosphor layers 22R, 22G, and 22B can be formed in a strip shape extending in the vertical direction of FIG. A part of the partition wall 21 also functions as a spacer holding portion for holding the spacer 40.

In the first embodiment, the cathode electrode 11 is connected to the cathode electrode control circuit 31, the gate electrode 13 is connected to the gate electrode control circuit 32, the focusing electrode 16 is connected to the focusing electrode control circuit (not shown), and the anode electrode Reference numeral 24 denotes an anode electrode control circuit 33. These control circuits can be constituted by known circuits. During actual operation of the display device, the anode voltage V _A applied from the anode electrode control circuit 33 to the anode electrode 24 is normally constant, and can be set to, for example, 5 kilovolts to 15 kilovolts. On the other hand, regarding the voltage V _C applied to the cathode electrode 11 and the voltage V _G applied to the gate electrode 13 during actual operation of the display device,
(1) A method in which the voltage V _C applied to the cathode electrode 11 is constant and the voltage V _G applied to the gate electrode 13 is changed. (2) The voltage V _C applied to the cathode electrode 11 is changed and applied to the gate electrode 13. the voltage V _G for changing the voltage V _C applied to the method (3) a cathode electrode 11, constant, and may employ any method to change the voltage V _G applied to the gate electrode 13.

During actual operation of the display device, a relatively negative voltage (V _C ) is applied to the cathode electrode 11 from the cathode electrode control circuit 31, and a relatively positive voltage (V _G ) is applied to the gate electrode 13 in the gate electrode control circuit. For example, 0 V is applied to the focusing electrode 16 from the focusing electrode control circuit, and a positive voltage (anode voltage V _A ) higher than the gate electrode 13 is applied to the anode electrode 24 from the anode electrode control circuit 33. The When performing display in such a display device, for example, a scanning signal is input to the cathode electrode 11 from the cathode electrode control circuit 31, and a video signal is input to the gate electrode 13 from the gate electrode control circuit 32. Note that a video signal may be input to the cathode electrode 11 from the cathode electrode control circuit 31, and a scanning signal may be input to the gate electrode 13 from the gate electrode control circuit 32. Electrons are emitted from the electron emission portions 15 and 15A based on the quantum tunnel effect due to an electric field generated when a voltage is applied between the cathode electrode 11 and the gate electrode 13, and the electrons are attracted to the anode electrode 24. It passes through 24 and collides with the phosphor layer 22. As a result, the phosphor layer 22 is excited to emit light, and a desired image can be obtained. That is, the operation of this display device is basically controlled by the voltage V _G applied to the gate electrode 13 and the voltage V _C applied to the cathode electrode 11.

The space sandwiched between the first panel (cathode panel CP) and the second panel (anode panel AP) is in a vacuum state (pressure: for example, 10 ⁻³ Pa or less). Therefore, if the spacer 40 is not disposed between the anode panel AP and the cathode panel CP, the display device is damaged by the atmospheric pressure.

The material constituting the spacer 40 is selected from, for example, a material (a high resistance material such as ceramic material or glass) that can ensure a dielectric breakdown voltage of 12 kilovolts. More specifically, the spacer 40 is made of, for example, alumina (Al ₂ O ₃ , purity 99.8%). The spacer 40 has a length of 100 mm, a height of 2.0 mm, and a thickness of 50 μm. On the surface of the spacer 40, for example, an antistatic film (not shown) made of CrO _x or CrAl _x O _y is formed. Contact electrodes (not shown) may be provided on the top and bottom surfaces of the spacer 40. The contact electrode provided on the top surface of the spacer 40 is in contact with the anode electrode 24, and the contact electrode provided on the bottom surface of the spacer 40 is in contact with the focusing electrode 16, thereby holding the spacer 40 at a predetermined potential. Can do. That is, a predetermined potential gradient (for example, a potential gradient having the highest potential on the top surface of the spacer 40 and the lowest potential on the bottom surface of the spacer 40) can be applied to the spacer 40.

1A is a conceptual plan view, and FIG. 1B is a conceptual front view, arranged on a straight line extending in a first direction (corresponding to the X direction). A plurality of spacer groups 40 </ b> A composed of a plurality of spacers 40 are arranged along a second direction (matching the Y direction) different from the first direction. Here, the distance between the first panel and the second panel is d ₀ (unit: mm), and the distance between the adjacent spacers 40 constituting the spacer group 40A is d _S (unit: mm). Note that the distance d ₀ between the first panel and the second panel is equivalent to the height of the spacer 40.

And in the display device of Example 1,
1/20 <d _S / d ₀ ≦ 1/4
Is satisfied.

Alternatively, in the display device of Example 1,
0.1 (mm) <d _S ≦ 0.5 (mm)
Is satisfied.

Alternatively, in the display device of Example 1, the distance d _S between the adjacent spacers 40 constituting the spacer group 40A is
(1) An orbit shift amount of an electron beam emitted from the electron emission region EA adjacent to the spacer 40 (more specifically, adjacent to the second direction) due to the electric field formed by the spacer 40 (The amount of deviation along the first direction and the amount of deviation along the second direction) is a distance that is ± 5 μm or less, and
(2) The distance between the adjacent spacers 40 constituting the spacer group 40A is such that no discharge occurs due to the difference in potential distribution in each spacer 40.
The two requirements are satisfied.

Hereinafter, these points will be described in detail. However, in the following description, the distance d ₀ (unit: mm) between the first panel (cathode panel CP) and the second panel (anode panel AP) is 2.0 mm, and the anode voltage V _A is 9 kilovolts. And

  FIG. 2A schematically shows the result of examining how much the trajectory of the electron beam is disturbed by the presence of the adjacent spacer 40, and FIG. 2A shows the spacer 40 from the cathode panel CP side. It is the schematic diagram which looked at etc. Here, FIG. 2A shows a state in which the equipotential lines change due to the presence of the spacer 40, and the region of the anode electrode 24 to which the electron beam should originally collide is indicated by an ellipse. Furthermore, the state in which the equipotential lines change due to the presence of the spacers 40 and the electron beam trajectory is shifted is schematically represented by black arrows. Comparing FIG. 2A with FIG. 22, it can be seen that Example 1 has less change in equipotential lines and less deviation of the trajectory of the electron beam.

  In one spacer group 40A, it is assumed that the spacers 40 whose short-circuit regions are both 100 μm are adjacent to each other.

Then, adjacent to the spacer 40 along the second direction when the distance d _S (unit: mm) between the adjacent spacers 40 constituting the spacer group 40A is changed from 2.0 mm to 0.25 mm. 3A and 3B show the calculation results of the shift amount (movement amount) generated in the trajectory of the electron beam emitted from the electron emission region positioned at the same position. Here, the horizontal axes in FIGS. 3A and 3B indicate subpixel numbers in the same manner as shown in FIG. 22, and the vertical axis in FIG. 3A indicates the Y generated in the trajectory of the electron beam. 3 is a displacement amount (movement amount) in the direction (second direction), and the vertical axis in FIG. 3B represents the displacement amount (movement amount) in the X direction (first direction) generated in the trajectory of the electron beam. It is. 3A and 3B, the left end portion of one spacer 40 (spacer 40 located on the right side) is located at the subpixel number (7). The size (length) of the sub-pixel on the horizontal axis in FIGS. 3A and 3B is 0.166 mm. Therefore, for example, a distance d _S = 0.25 mm means that adjacent spacers 40 are separated from each other by 1.51 subpixels, and the other spacer is located at subpixel number (5). The right end of 40 (spacer 40 located on the left side) is located. For example, the distance d _S = 0.5 mm means that the adjacent spacers 40 are separated from each other by 3.01 subpixels, and the other spacer is located at the subpixel number (3). The right end of 40 (spacer 40 located on the left side) is located. Further, for example, the distance d _S = 2.0 mm means that the adjacent spacers 40 are separated from each other by 12.05 subpixels, and the other is located at the subpixel number (−6). The right end of the spacer 40 (the spacer 40 located on the left side) is located. 3A and 3B, data (A) shows d _S = 0.25 mm, data (B) shows d _S = 0.50 mm, and data (C) has d _S = 0. 75 mm is shown, data (D) shows d _S = 1.0 mm, data (E) shows d _S = 1.5 mm, and data (F) shows d _S = 2.0 mm.

  3A and 3B, in the portion of the spacer 40 sufficiently separated from the end portion of the spacer 40, the deviation of the electron beam in the X direction and the Y direction takes a substantially constant value. I understand that. This indicates that the electric field in the vicinity of the portion of the spacer 40 is not affected by the disturbance of the electric field at the end of the spacer 40 if it is sufficiently separated from the end of the spacer 40.

  From various experiments, the amount of deviation (the amount of deviation along the first direction and the amount of deviation along the second direction) generated in the trajectory of the electron beam emitted from the electron emission region located adjacent to the spacer 40 along the second direction. If each of the deviations along the direction) is within ± 5 μm, the image formation will not be seriously affected, and the formed image will be distorted in the vicinity of the spacer 40, It turned out that it was not visually recognized.

From the calculation results shown in FIGS. 3A and 3B, in one spacer group 40A, when the spacers 40 whose short-circuit regions are both 100 μm are adjacent to each other, the spacer group 40A is If the distance d _S (unit: mm) between the adjacent spacers 40 is 0.5 mm or less, the amount of deviation generated in the trajectory of the electron beam (the amount of deviation along the first direction and the second direction). It can be seen that there is no problem because each of the deviations along the line is within ± 5 μm.

That is, the orbit shift amount of the electron beam emitted from the electron emission region EA adjacent to the spacer 40 along the second direction due to the electric field formed by the spacer 40 (the shift amount along the first direction and the shift amount). If a distance d _S is selected such that each of the shift amounts along the second direction is ± 5 μm or less, the formed image is distorted in the vicinity of the spacer 40, or the image formation is seriously affected. In addition, the spacer 40 is not visually recognized.

By the way, in the spacers 40 adjacent to each other, the z-direction length z ₁ of the short circuit region is often different. Such a phenomenon occurs because the material constituting the spacer 40, the collision of electrons from the electron emission region with the spacer 40, and the collision of backscattered electrons with the spacer 40 are slightly different for each spacer 40. When the lengths ₁ of the short-circuit regions z in the adjacent spacers 40 are different from each other, the anode voltage V _A applied from the anode electrode 24 is constant, but the spacers 40 between the adjacent spacers 40 are constant. The potential difference is caused by the difference in potential distribution at. When such a potential difference occurs, distortion occurs in equipotential lines in the vicinity of the spacers 40 adjacent to each other. This state is schematically shown in FIGS. 4A and 4B. When the distance d _S between the adjacent spacers 40 is short, the equipotential distortion becomes steep, and the distance between the adjacent spacers 40 becomes steep. If the distance d _S is long, the equipotential line distortion becomes relatively gentle.

In adjacent spacers 40, the length of the short-circuit region in one spacer 40 in the z direction is Z ₁ (= 0.1 mm), the length of the short-circuit region in the other spacer 40 is z (Z ₁ + ΔZ ₁ ), FIG. 5 shows the calculation result of the amount of deviation in the X direction generated in the trajectory of the electron beam when ΔZ ₁ is 0.1 mm, 0.05 mm, 0.02 mm, and 0 mm. In FIG. 5, the calculation result of the shift amount when ΔZ ₁ = 0.1 mm is shown by (A), the calculation result of the shift amount when ΔZ ₁ = 0.05 mm is shown by (B), and ΔZ ₁ The calculation result of the shift amount when 0.02 mm is indicated by (C), and the calculation result of the shift amount when ΔZ ₁ = 0 mm is indicated by (D).

From FIG. 5, in the case of ΔZ ₁ = 0 mm, if the distance d _S (unit: mm) is 0.5 mm or less, the deviation amount (movement amount) in the X direction generated in the trajectory of the electron beam is within ± 5 μm. However, for example, in the case of ΔZ ₁ = 0.05 mm, even if the distance d _S (unit: mm) is 0.5 mm or less (see the curve (B)), the amount of deviation in the X direction generated in the trajectory of the electron beam ( The amount of movement is not within ± 5 μm.

Various experiments revealed that ΔZ ₁ is usually 0.02 mm or less. Therefore, in the adjacent spacers 40, the z-direction length z ₁ of the short-circuit region is often different, but the difference in the z-direction length z ₁ of the short-circuit region itself is almost the same as the amount of deviation caused in the trajectory of the electron beam. It turns out that it has no effect.

However, when there is a difference in the z-direction length of the short-circuit region between the adjacent spacers 40 in the adjacent spacers 40, a potential difference is generated due to a difference in potential distribution in each spacer 40 between the adjacent spacers 40 constituting the spacer group 40A. . Since the height of the spacer 40 is set to 2.0 mm and the anode voltage V _{A is set} to 9 kilovolts, a potential gradient of 4.5 volts / μm is generated in the height direction of the spacer 40 by simple calculation. Further, when a short-circuit region exists, a potential gradient exceeding 4.5 volts / μm is generated. Therefore, when ΔZ ₁ = 0.02 mm, a potential difference of about 100 volts is generated between the adjacent spacers 40.

  From various tests, it has been found that when the electric field strength exceeds 1 volt / μm between the adjacent spacers 40, discharge is likely to occur between the adjacent spacers 40.

Therefore, when ΔZ ₁ = 0.02 mm, a potential difference of about 100 volts is generated between the adjacent spacers 40. In order to prevent discharge between the adjacent spacers 40 in this state, the distance is set. d _S is
d _S > 0.1 mm
Need to be satisfied.

That is, if a distance d _S is selected between adjacent spacers 40 constituting the spacer group 40A so that no discharge occurs due to a difference in potential distribution in each spacer 40, the generation of discharge between the spacers 40 can be suppressed. .

Summarizing the above various test results and discussion, the distance d _S (unit: mm) between the adjacent spacers 40 constituting the spacer group 40A is:
0.1 (mm) <d _S ≦ 0.5 (mm) (1)
It is necessary to satisfy. On the other hand, since the distance d ₀ between the first panel (cathode panel CP) and the second panel (anode panel AP) is 2.0 mm, when the above equation (1) is normalized by d ₀ , the equation (1) ) Can be modified as follows.
1/20 <d _S / d ₀ ≦ 1/4 (2)

  Hereinafter, a method for assembling the display device according to the first embodiment will be described.

[Step-100]
A first panel (cathode panel CP) in which a plurality of field emission elements constituting an electron emission region for emitting electrons are formed on the support 10 and an electron emission region (from a Spindt type field emission device or a flat type field emission device). A second panel (anode panel AP) in which a phosphor layer 22 and an anode electrode 24 with which electrons emitted from the structure collide are formed on the substrate 20 is prepared. A spacer 40 is prepared.

[Step-110]
Then, the display device is assembled. Specifically, the spacer 40 is attached to the spacer holding part 25 provided in the effective area of the anode panel AP, and the anode panel AP and the cathode panel CP are arranged so that the phosphor layer 22 and the electron emission area EA face each other. Then, the anode panel AP and the cathode panel CP (more specifically, the substrate 20 and the support body 10) are joined together at the peripheral edge via a frame body 26 made of ceramics or glass. At the time of joining, frit glass is applied to the joining portion between the frame body 26 and the anode panel AP and the joining portion between the frame body 26 and the cathode panel CP, and the anode panel AP, the cathode panel CP, and the frame body 26 are pasted. In addition, the frit glass is dried by preliminary baking, and then main baking is performed at about 450 ° C. for 10 to 30 minutes.

[Step-120]
Thereafter, the space surrounded by the anode panel AP, the cathode panel CP, the frame, and the frit glass (not shown) is exhausted through a through hole (not shown) and a tip tube (not shown), and the pressure in the space is reduced. When the ^pressure reaches about 10 ⁻⁵ Pa, the tip tube is sealed by heating and melting. In this way, the space surrounded by the anode panel AP, the cathode panel CP, and the frame can be evacuated.

  Alternatively, for example, the frame, the anode panel AP, and the cathode panel CP may be bonded together in a high vacuum atmosphere. Alternatively, depending on the structure of the display device, the anode panel AP and the cathode panel CP may be bonded together by using only an adhesive layer without a frame. Thereafter, wiring connection with necessary external circuits is performed, and the display device of Example 1 is completed.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to this Example. The configurations and structures of the flat panel display device, cathode panel and anode panel, cold cathode field emission display device and cold cathode field emission device described in the embodiments are examples, and can be changed as appropriate. The method of assembling the field electron emission display device is also an example, and can be changed as appropriate. Furthermore, various materials used in the manufacture of anode panels and the like are also examples, and can be appropriately changed. The display device has been described by taking color display as an example, but it may also be a single color display. In some cases, it is not necessary to form a focusing electrode.

In the first embodiment, the shape of the spacer is an elongated plate, but the shape of the spacer is not limited to such a shape. As shown in the conceptual partial plan view of FIG. 6A, the cross-shaped spacer 41 and the plate-like spacer 40 may be combined, or the conceptual partial plan view of FIG. As shown in the figure, only the cross-shaped spacer 41 can be used. In these cases, the distance d ′ _S between the adjacent spacers along the second direction needs to satisfy the same requirements as the distance d _S.

In the first embodiment, the end portion of the spacer is a flat and vertical end portion. However, the spacer can be attached smoothly to the spacer holding portion 25 provided in the effective area of the anode panel AP. As shown in FIG. 7A, a conceptual front view may be provided so that a notch portion may be provided at the end of the spacer 42, or the end of the spacer 43 may be tapered. May be attached. In these cases, the portion of the shortest gap between the spacers needs to satisfy the requirement of the distance d _S. Moreover, it is preferable to chamfer the edge part of a spacer and to remove a projection part.

  In the field emission device, a mode in which one electron emission portion corresponds to one opening has been described. However, depending on the structure of the field emission device, a mode in which a plurality of electron emission portions correspond to one opening. Alternatively, one electron emission portion may correspond to a plurality of openings. Alternatively, a plurality of first openings may be provided in the gate electrode, a second opening connected to the plurality of first openings related to the insulating layer may be provided, and one or a plurality of electron emission portions may be provided. .

The electron emission region can also be constituted by an electron emission element commonly called a surface conduction electron emission element. This surface conduction electron-emitting device is formed on a support made of glass, for example, tin oxide (SnO ₂ ), gold (Au), indium oxide (In ₂ O ₃ ) / tin oxide (SnO ₂ ), carbon, palladium oxide ( A pair of electrodes made of a conductive material such as (PdO), having a small area and arranged with a predetermined gap (gap) are formed in a matrix. A carbon thin film is formed on each electrode. The row direction wiring is connected to one electrode of the pair of electrodes, and the column direction wiring is connected to the other electrode of the pair of electrodes. By applying a voltage to the pair of electrodes, an electric field is applied to the carbon thin films facing each other across the gap, and electrons are emitted from the carbon thin film. By causing the electrons to collide with the phosphor layer on the anode panel, the phosphor layer is excited to emit light, and a desired image can be obtained. Alternatively, the electron emission region can be formed from a metal / insulating film / metal type element.

FIG. 1 is a schematic diagram showing an arrangement state of a spacer group composed of a plurality of spacers. Specifically, FIG. 1A is a conceptual plan view of spacers, etc. (B) is a conceptual front view of a spacer and the like. FIG. 2A is a schematic diagram showing a state in which equipotential lines change due to the presence of adjacent spacers and a state in which the trajectory of the electron beam is disturbed in Example 1, and FIG. These are the schematic diagrams of a spacer which shows the state from the end surface which contact | connects the anode electrode of a spacer to a certain area | region by an electron collision from a certain area | region. 3 (A) and 3 (B) show, in the spacer of Example 1 in which the short-circuit region is 100 μm, the deviation caused in the trajectory of the electron beam emitted from the electron emission region located adjacent to the spacer, respectively. It is a graph which shows the result of having calculated quantity (movement amount). 4A and 4B are diagrams schematically showing distortion of equipotential lines in the vicinity of adjacent spacers when a difference is generated in the potential applied to each spacer. FIG. 5 shows an electron beam trajectory in the case where there is a difference between the z-direction length of the short-circuit region in one spacer and the z-direction length of the short-circuit region in the other spacer in adjacent spacers. 6 is a graph showing a calculation result of a deviation amount in the X direction generated in FIG. 6A and 6B are conceptual partial plan views showing modified examples of the shape of the spacer. FIGS. 7A and 7B are conceptual front views showing a modification of the shape of the end portion of the spacer. FIG. 8 is a conceptual partial end view of a flat display device including a cold cathode field emission display device having a Spindt-type cold cathode field emission device. FIG. 9 is a conceptual partial end view of a flat display device including a cold cathode field emission display device having a flat type cold cathode field emission device. FIG. 10 is a schematic exploded perspective view of a part of a cathode panel and an anode panel in a cold cathode field emission display. FIG. 11 is a layout diagram schematically showing the layout of the barrier ribs, spacers, and phosphor layers in the second panel constituting the flat display device. FIG. 12 is a layout diagram schematically showing the layout of the barrier ribs, spacers and phosphor layers in the second panel constituting the flat display device. FIG. 13 is a layout diagram schematically showing the layout of the barrier ribs, spacers, and phosphor layers in the second panel constituting the flat display device. FIG. 14 is a layout diagram schematically showing the layout of the barrier ribs, spacers, and phosphor layers in the second panel constituting the flat display device. FIG. 15 is a layout diagram schematically showing the layout of the barrier ribs, spacers, and phosphor layers in the second panel constituting the flat display device. FIG. 16 is a layout diagram schematically showing the layout of the barrier ribs, spacers and phosphor layers in the second panel constituting the flat display device. FIG. 17 is a diagram schematically showing the trajectory of the electron beam in the vicinity of the spacer. FIG. 18 is a diagram schematically showing the trajectory of the electron beam in the vicinity of the spacer. FIG. 19 is a diagram schematically showing the trajectory of the electron beam in the vicinity of the spacer. FIG. 20 is a graph showing the relationship between the energy of the electron beam and the total secondary electron emission coefficient (TSEEY). 21A and 21B are graphs showing the energy distribution of electrons that collide with the spacer and the angular distribution of electrons that collide with the spacer. FIG. 22 is a schematic diagram showing a state where the equipotential lines change due to the presence of the spacer and a state where the trajectory of the electron beam is disturbed. FIGS. 23A and 23B show an orbit of an electron beam emitted from an electron emission region located adjacent to the spacer and its extension line in an isolated spacer having a short-circuit region of 100 μm, respectively. It is a graph which shows the result of having calculated the amount of shift (movement amount).

Explanation of symbols

CP ... cathode panel (first panel), AP ... anode panel (second panel), EA ... electron emission region, 10 ... support, 11 ... cathode electrode, 12 ... Insulating layer, 13 ... gate electrode, 14 ... opening, 14A ... first opening, 14B ... second opening, 15, 15A ... electron emitting part, 16 ... convergence Electrode, 17... Interlayer insulating layer, 20... Substrate, 21 .. partition wall, 22, 22 R, 22 G, 22 B... Phosphor layer, 23. ... Anode electrode, 25 ... Spacer holding part, 26 ... Frame, 31 ... Cathode electrode control circuit, 32 ... Gate electrode control circuit, 33 ... Anode electrode control circuit, 40, 41, 42, 43 ... spacer, 40A ... spacer group

Claims (3)

A first panel in which a plurality of electron emission regions for emitting electrons are formed on a support; a second panel in which a phosphor layer and an anode electrode on which electrons emitted from the electron emission region collide are formed on a substrate; Is a flat display device in which the space sandwiched between the first panel and the second panel is held in a vacuum, and is joined at their peripheral edges.
Between the first panel and the second panel, there is a spacer group composed of a plurality of spacers arranged on a straight line extending in the first direction along a second direction different from the first direction. , Multiple, arranged,
When the distance between the first panel and the second panel is d ₀ (unit: mm), the distance d _S (unit: mm) between adjacent spacers constituting the spacer group is:
1/20 <d _S / d ₀ ≦ 1/4
Satisfied ,
A flat display device in which the voltage applied to the anode electrode is 5 kilovolts or more and 15 kilovolts or less . A first panel in which a plurality of electron emission regions for emitting electrons are formed on a support; a second panel in which a phosphor layer and an anode electrode on which electrons emitted from the electron emission region collide are formed on a substrate; Is a flat display device in which the space sandwiched between the first panel and the second panel is held in a vacuum, and is joined at their peripheral edges.
Between the first panel and the second panel, there is a spacer group composed of a plurality of spacers arranged on a straight line extending in the first direction along a second direction different from the first direction. , Multiple, arranged,
The distance d _S (unit: mm) between adjacent spacers constituting the spacer group is:
0.1 (mm) <d _S ≦ 0.5 (mm)
Satisfied ,
When the voltage applied to the anode electrode is V _A (unit: kilovolt) and the distance between the anode panel and the cathode panel is d ₀ (unit: mm), the value of V _A / d ₀ is 0.5 or more. A flat display device that is 20 or less . A first panel in which a plurality of electron emission regions for emitting electrons are formed on a support; a second panel in which a phosphor layer and an anode electrode on which electrons emitted from the electron emission region collide are formed on a substrate; Is a flat display device in which the space sandwiched between the first panel and the second panel is held in a vacuum, and is joined at their peripheral edges.
Between the first panel and the second panel, there is a spacer group composed of a plurality of spacers arranged on a straight line extending in the first direction along a second direction different from the first direction. , Multiple, arranged,
The distance d _S between adjacent spacers constituting the spacer group is
(1) a distance at which an orbit shift amount of an electron beam emitted from an electron emission region adjacent to the spacer caused by an electric field formed by the spacer is ± 5 μm or less; and
(2) A distance where no discharge occurs due to a difference in potential distribution in each spacer between adjacent spacers constituting the spacer group.
A flat display device that satisfies the following two requirements.

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