JP4833690B2 - Arithmetic circuit and arithmetic method - Google Patents

Description

  The present invention relates to an arithmetic circuit that performs various types of filter processing on data arranged in a two-dimensional space by a convolution operation and an arithmetic method thereof.

  A convolution operation is known as one of conventional techniques for performing digital processing on an original image and performing filter processing such as image quality improvement, noise removal, and edge enhancement. The convolution operation is mainly used to perform various kinds of filter processing on data arranged in a two-dimensional space consisting of x columns × y rows, such as an image. In general, the convolution operation is often used for the above-mentioned purpose, but by changing the coefficient value, a filter having various characteristics can be configured.

For example, when performing a filtering process of 5 columns × 5 rows, the column direction (horizontal direction) of the original image is x, the row direction (vertical direction) is y, and the pixel value of the x column y row of the original image is L _{x, If y is} the pixel value in the x column and y row after the filter processing is P _{x, y} , and the coefficient value in the i column j row of the 5 × 5 filter coefficients is C _{i, j} , the filtered pixel The value P _{x, y} is calculated by the following equation (1). As described above, the characteristics of the filter are determined by the coefficient values C _{i, j} and perform various functions such as image quality improvement, noise removal, and edge enhancement.

  Hereinafter, in order to simplify the description, a filter that performs a convolution operation for calculating a pixel value of one pixel after the filter processing from pixel values of four columns of 2 columns × 2 rows of the original image (before the filter processing) ( The arithmetic circuit will be described.

  Here, the pixel values L11, L12, L13,..., L21, L22, L23,..., L31, L32, L33,. Assume that pixel values P11, P12, P12,..., P21, P22, P23,.

FIG. 10 is a conceptual diagram illustrating an example of a relationship between a pixel value of each pixel of the original image and a pixel value of each pixel of the image after filtering. That is, in this example, the pixel values L _{i, j} , L _{i, j + 1} , L _{i + 1, j} , L _{i + 1} , _{j + 1} of 2 columns × 2 rows = 4 pixels of the original image are used. Thus, the pixel value P _{i, j} of one pixel after the filter processing is calculated. In the case of a filter of 2 columns × 2 rows, four (= 2 columns × 2 rows) filter coefficients C _1,1 , C _1,2 , C _2,1 , C _2,2 are required. The pixel value P _{i, j} of each pixel after the filter processing is calculated by the following equation (2).

P _{i, j} = C _1,1 L _{i, j} + C _1,2 L _{i, j + 1} + C _2,1 L _{i + 1, j} + C _2,2 L _{i + 1} , _{j + 1} (2)

  For example, the pixel value P11 of the first pixel of the image after filtering is, as shown in FIG. 11, the pixel values L11 and L21 for four pixels in the first and second columns of the original image surrounded by a thick square frame. , L12, L22. Further, when the filtering process is performed in the order shown in FIG. 13, the pixel value P12 of the second pixel of the image after the filtering process is 2 and 2 of the original image surrounded by a square thick frame as shown in FIG. Calculation is performed using pixel values L12, L22, L13, and L23 for four pixels in the third column.

Also, for example, when performing noise removal filtering, the average of the pixel values L _{i, j} , L _{i, j + 1} , L _{i + 1, j} , L _{i + 1} , _{j + 1} of the four pixels of the original image In order to calculate the values, the filter coefficients C _1,1 , C _1,2 , C _2,1 , C _2,2 are all set to ¼ of the same value as in the following equation (3). Thereby, the said Formula (2) becomes a format of following Formula (4). Thus, by calculating the average value of the pixel values L _{i, j} , L _{i, j + 1} , L _{i + 1, j} , L _{i + 1} , _{j + 1} for the four pixels of the original image, An effect of removing small noise in the image can be obtained.

_{C 1,1 = C 1,2 = C 2,1} = C 2,2 = 1/4 ... (3)
P _{i, j} = (L _{i, j} + L _{i, j + 1} + L _{i + 1, j} + L _{i + 1} , _{j + 1} ) / 4 (4)

Here, when the filter processing is performed in the order shown in FIG. 13 by the above equation (2), for example, in the calculation of adjacent pixels like the pixel values P11 and P12 of the pixels after the filter processing, FIG. 11 and FIG. As can be seen from the above, pixel values L12 and L22 for two pixels in one column are used in both the calculations of P11 and P12. Therefore, for example, Patent Document 1 proposes a technique for preventing the pixel value of the same pixel of the original image that is commonly used in calculation of adjacent pixels from being read twice from a memory or the like.

  Hereinafter, Patent Document 1 will be described.

  FIG. 14 is a schematic diagram illustrating an example of a configuration of an arithmetic circuit that performs filter processing using a conventional convolution operation. An arithmetic circuit 140 shown in the figure is configured by applying the technique proposed in Patent Document 1 as a filter of 2 columns × 2 rows in order to simplify the description. The arithmetic circuit 140 includes an image information storage device 141, an original image register 142, a coefficient shift register 144, a multiplexer (MUX) 145, a product-sum operation unit 146, an adder 148, and a multiplexer (MUX) 149. And an intermediate result register 154 composed of two flip-flops 150a and 150b, and a counter 156.

  15 and 16 conceptually show states of the arithmetic circuit 140 when the counter value 156 of the arithmetic circuit 140 shown in FIG. 14 is 0 and when the count value = 1. FIG. 17 is a conceptual diagram showing the configuration of the product-sum calculator 146 used in the arithmetic circuit 140. The multiplier 160a that multiplies the coefficient value C1 (C11 or C21) and the pixel value L1, The multiplier 160b that multiplies the coefficient value C2 (C12 or C22) and the pixel value L2 and the adder 162 that adds the operation results of the two multipliers 160a and 160b.

  The counter 156 repeatedly counts 0 and 1 after initialization. When the count value of the counter 156 is 0, pixel values for two pixels in one column to be processed are read from the original image stored in the image information storage device 141, and are stored in the original image register 142. Are held as L1 and L2, respectively. Further, as shown in FIG. 15, coefficient values C <b> 11 and C <b> 21 are output from the coefficient shift register 144 via the multiplexer 145.

  The product-sum operation unit 146 performs a product-sum operation C11L1 + C21L2 between the pixel values L1 and L2 for two pixels in one column input from the original image register 142 and the coefficient values C11 and C21 input from the coefficient shift register 144. Is done. The adder 148 adds the operation result of the product-sum operation unit 146 and 0, and the addition result C11L1 + C21L2 is input to the flip-flop 150a of the intermediate result register 154 via the multiplexer 149.

  The flip-flop 150a of the intermediate result register 154 holds the addition result input from the adder 148 in synchronization with the clock signal. Similarly, in synchronization with the clock signal, the output of the flip-flop 150a is held in the flip-flop 150b and is output as the pixel value of the pixel after the filter processing. That is, the value held in the flip-flop 150a before one cycle (one clock) is held in the flip-flop 150b.

  On the other hand, when the count value of the counter 156 = 1, no new pixel value is read from the image information storage device 141. Therefore, the original image register 142 holds pixel values L1 and L2 for two pixels when the count value of the counter 156 = 0. Coefficient values C12 and C22 are output from the coefficient shift register 144 as shown in FIG. The product-sum calculator 146 performs a product-sum operation C12L1 + C22L2 of the pixel values L1 and L2 for two pixels in one column and the coefficient values C12 and C22.

  The adder 148 adds the operation result of the product-sum operation unit 146 and the output of the flip-flop 150b. As a result, the calculation result C11L1 + C21L2 of the product-sum calculator 146 when the counter value of the counter 156 is 0 three cycles before and the calculation result C12L1 + C22L2 when the counter value = 1 are added. The flip-flop 150b holds the addition result of the adder 148 in synchronization with the clock signal and outputs it as the pixel value of the pixel after the filter processing. The flip-flop 150a holds (maintains) its own held value one cycle before.

  Next, the operation of the arithmetic circuit 140 will be specifically described with reference to Table 1 below.

  The first cycle is an initialization cycle. The holding values P1 and P2 of the two flip-flops 150a and 150b of the intermediate result register 154 are zero. Although omitted in Table 1, coefficient values C11, C21, C12, and C22 are set in the coefficient shift register 144.

  In cycle 1, the count value of the counter 156 = 0. Therefore, the pixel values L11 and L21 for the first two columns of pixels are read from the image information storage device 141 and are stored in the original image register 142 as L1 and L2, respectively. The coefficient values C11 and C21 are output from the coefficient shift register 144. Then, C11L11 + C21L21 is calculated by the product-sum calculator 146, and 0 is further added by the adder 148. The addition result C11L11 + C21L21 of the adder 148 is held as the hold value P1 in the flip-flop 150a of the intermediate result register 154 in synchronization with the clock signal. In the flip-flop 150b, 0, which is the value held in the flip-flop 150a one cycle before, is held as the hold value P2.

  In cycle 2, the count value of the counter 156 is 1. Therefore, L1 and L2 of the original image register 142 remain L11 and L21. On the other hand, coefficient values C12 and C22 are output from the coefficient shift register 144. The product-sum calculator 146 calculates C12L11 + C22L21, and the adder 148 further adds the output 0 of the flip-flop 150b of the intermediate result register 154. The addition result C12L11 + C22L21 of the adder 148 is held in the flip-flop 150b of the intermediate result register 154 in synchronization with the clock signal. The flip-flop 150a maintains C11L11 + C21L21, which is its own output.

  In cycle 3, the count value of the counter 156 becomes 0 again. Pixel values L12 and L22 for two pixels in the second one column are read and held in the original image register 142 as L1 and L2, respectively. Coefficient values C11 and C21 are output from the coefficient shift register 144. Then, C11L12 + C21L22 is calculated by the product-sum calculator 146, and 0 is further added by the adder 148. The addition result C11L12 + C21L22 of the adder 148 is held in the flip-flop 150a of the intermediate result register 154 in synchronization with the clock signal. The flip-flop 150b holds the output C11L11 + C21L21 of the flip-flop 150a.

  In cycle 4, the count value of the counter 156 becomes 1 again. Similarly, L1 and L2 of the original image register 142 remain L12 and L22. Coefficient values C12 and C22 are output from the coefficient shift register 144. The product-sum calculator 146 calculates C12L12 + C22L22, and the adder 148 further adds the output C11L11 + C21L21 of the flip-flop 150b of the intermediate result register 154. The addition result C11L11 + C21L21 + C12L12 + C22L22 of the adder 148 is held in the flip-flop 150b of the intermediate result register 154 in synchronization with the clock signal, and is output as the pixel value P11 of the pixel after filtering. The flip-flop 150a maintains its own output C11L12 + C21L22.

  The operations after cycle 5 are the same as described above. That is, in the arithmetic circuit 140, after initialization, the pixel value P11 of the first pixel after filtering is output in four cycles, and thereafter, the pixel value P12 of the second and subsequent pixels after filtering is processed every two cycles. P13,... Are sequentially output.

  As described above, Patent Document 1 has an advantage that it is not necessary to read out twice from the image information storage device the pixel value of the pixel of the original image that is commonly used in the calculation of adjacent pixels. However, in Patent Document 1, four cycles are required after the initialization until the pixel value P11 of the first pixel after the filtering process is output, and the pixel values P12, P13,... Of the second and subsequent pixels are output. Each time it takes two cycles, there is a problem that it takes too much processing time (number of cycles) for the filter processing.

JP 51-141536 A

  SUMMARY OF THE INVENTION An object of the present invention is to solve the problems based on the prior art and to perform an arithmetic circuit and an arithmetic circuit capable of performing filter processing by convolution operation on data arranged in a two-dimensional space with fewer cycles than in the past. It is to provide a method.

  Another object of the present invention is to provide an arithmetic circuit and an arithmetic method capable of appropriately reducing the circuit scale by giving priority to the circuit scale over the processing speed when high speed is not required for the filter processing by the convolution operation. It is to provide.

In order to achieve the above object , the present invention is an arithmetic circuit for performing a convolution operation of data arranged in a two-dimensional space,
A coefficient register for storing coefficients of N columns × N rows (N is an integer of 3 or more);
A data register holding N data values;
a pre-processing circuit including m (2 ≦ m <N) product-sum calculators;
And a post-processing circuit including 1st to Nth product-sum registers,
Initialize the 1-N-1 product-sum registers of the 1-Nth in the initialization cycle,
After that, in the order of 1 to N cycles, the data value of the 1st to Nth columns in the range of N columns × N rows of the two-dimensional space is held in the data register,
For each cycle,
In each of at least some of the m product-sum calculators of the preprocessing circuit, the product-sum between the N data values and the N coefficients of any column of the N columns × N rows. By calculating the product sum between the N data values and the coefficients of all the columns by repeating the operation of calculating N times less than N times,
A product-sum operation result between the N data values and the N coefficients in the first column calculated by the product-sum calculator is held in a first product-sum register of the post-processing circuit, and The product-sum operation result between the N data values and the coefficients of the n-th column (n = 2 to N), and the value held in the n−1th product-sum register of the post-processing circuit in the previous cycle Is held in the n-th product-sum register of the post-processing circuit,
Provided is an arithmetic circuit which outputs a convolution operation result of a first operation target point located at the center of the range of N columns × N rows in the two-dimensional space from the Nth product-sum register. .

Here, the post-processing circuit further includes a 1-Nth temporary register provided corresponding to each of the 1-Nth product-sum registers,
After each product-sum operation result calculated by the product-sum operation unit between the data value and the coefficients in the 1st to Nth columns is held in the 1st to Nth temporary registers for each cycle. The integrated value of the n-th product-sum operation result held in the temporary register and the value held in the (n−1) -th product-sum register in the previous cycle may be held in the n-th product-sum register. preferable.

The present invention is an arithmetic circuit for performing a convolution operation of data arranged in a two-dimensional space,
A coefficient register for holding coefficients of N columns × N rows (N is an integer of 2 or more);
N columns x N rows of data registers;
A preprocessing circuit having N product-sum calculators;
A post-processing circuit having N product-sum registers,
The data register holds the data of the 1st to Nth columns in the range of N columns × N rows of the two-dimensional space,
In the first cycle, the N data values held in the nth column of the data register of N columns × N rows in the nth (n = 1 to N) product-sum operation unit Calculate the sum of products with the N coefficients in the first column of the N columns × N rows, and store the respective operation results in the n th product sum register of the post-processing circuit,
Then, in order through the kth (k = 2 to N) cycle,
The data held in the data register is shifted by −1 column, and the N + k−1 column data adjacent to the N column × N row of the two-dimensional space in the column direction is shifted to the N column of the data register. Hold
In the nth product-sum operation unit, N data values held in the nth column of the N column × N row data register and N coefficients in the N column × N row k column The sum of the results of each operation and the value held in the nth product-sum register of the post-processing circuit in the previous cycle is calculated as the n-th product-sum register of the post-processing circuit. By repeating the operation to hold
From each of the N product-sum registers, a first calculation target point located in the center of a range of N columns × N rows of the two-dimensional space, and the first calculation target in the column direction of the two-dimensional space Provided is an arithmetic circuit characterized in that a convolution operation result of the 2nd to Nth operation target points that are adjacent to the point in order is output.

Further, the present invention is an arithmetic method for performing a convolution operation between data arranged in a two-dimensional space and coefficients of N columns × N rows (N is an integer of 2 or more),
A preprocessing circuit having N product-sum calculators;
Prepare a post-processing circuit with N product-sum registers,
In the first cycle, a data value in a range of N columns × N rows of the two-dimensional space and N coefficients of the first column of N columns × N rows are supplied to the preprocessing circuit, and the N pieces The product-sum calculator between the N data values in the n-th column of the two-dimensional space and the N coefficients is calculated by an nth (n = 1 to N) product-sum calculator The operation result is held in the nth product-sum register of the post-processing circuit,
Then, in order through the kth (k = 2 to N) cycle,
The data values from the Nth column × Nth row kth column to the N + k−1th column adjacent to the Nth column × Nth row in the column direction, and the Nth column × Nth row N coefficients in the k-th column are supplied to the pre-processing circuit, and the N-th product-sum calculator calculates the N data values in the (N + k−1) -th column in the two-dimensional space and the N The sum of products between the coefficients is calculated, and an integrated value of each operation result and the value held in the nth product-sum register of the post-processing circuit in the previous cycle is calculated as n of the post-processing circuit. By repeating the operation held in the th product-sum register,
From each of the N product-sum registers, a first calculation target point located in the center of a range of N columns × N rows of the two-dimensional space, and the first calculation target in the column direction of the two-dimensional space Provided is a calculation method characterized by outputting a convolution calculation result of 2nd to Nth calculation target points that are adjacent to a point in order.

The present invention is an arithmetic circuit for performing a convolution operation of data arranged in a two-dimensional space,
A coefficient register for holding coefficients of N columns × N rows (N is an integer of 2 or more);
N columns x N rows of data registers;
a pre-processing circuit including m (m <N) product-sum calculators;
A post-processing circuit having N product-sum registers,
The data register holds data in the 1st to Nth columns in the range of N columns × N rows in the two-dimensional space,
In the first cycle,
In each of at least some of the m product-sum calculators of the preprocessing circuit, N data values held in any column of the N columns × N rows of data registers, and the N columns × N By repeating the operation of calculating the product sum between the N coefficients in the first column of the row, the data values held in all the columns of the data register and the coefficients in the first column are The sum of products of
The pre-processing circuit calculates the product-sum operation result between the data value held in the n-th column (n = 1 to N) of the data register and the coefficient in the first column, which is calculated by the product-sum calculator. In the nth sum of products register
Then, in order through the kth (k = 2 to N) cycle,
The data held in the data register is shifted by −1 in the column direction, and the N + k−1th column adjacent to the N column × N row in the two-dimensional space in the column direction is shifted to the Nth column of the data register. Keep the data,
In each of at least some of the m product-sum calculators of the preprocessing circuit, N data values held in any column of the N columns × N rows of data registers, and the N columns × N By repeatedly performing the operation of calculating the sum of products between the N coefficients in the k-th column of the row, the data values held in all the columns of the data register and the coefficients in the k-th column are calculated. Perform product-sum operation between
The product-sum operation result between the data value held in the n-th column of the data register and the coefficient in the k-th column, calculated by the product-sum calculator, and the nth of the post-processing circuit in the previous cycle By repeating the operation of holding the integrated value with the value held in the product-sum register in the nth product-sum register of the post-processing circuit,
From each of the N product-sum registers, a first calculation target point located at the center of a range of N columns × N rows of the two-dimensional space, and the first calculation in the column direction of the two-dimensional space Provided is an arithmetic circuit that outputs a convolution calculation result of the 2nd to N-th calculation target points that are adjacent to the target point in order.

  According to the present invention, as in the prior art, there is an advantage that it is not necessary to read out twice from the storage device a data value that is commonly used in calculation of adjacent data. In the present invention, the processing speed is several times that of a conventional arithmetic circuit by performing arithmetic processing using a plurality of product-sum arithmetic units. On the other hand, if the processing speed is not required, the number of product-sum calculators to be used can be appropriately reduced, so that the circuit scale can be appropriately reduced.

  The arithmetic circuit and the arithmetic method of the present invention will be described below in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a schematic diagram of the first embodiment showing the configuration of the arithmetic circuit of the present invention. The arithmetic circuit 10 shown in the figure sequentially performs filter processing by convolution operation from pixel values of 4 pixels of 2 columns × 2 rows in an original image arranged in a two-dimensional space. The arithmetic circuit 10 includes an original image register 12, a coefficient register 14, a preprocessing circuit 22, and a postprocessing circuit 24.

  The original image register (data register of the present invention) 12 is synchronized with the clock signal and is processed in the order of processing from an image information storage device (not shown, see FIG. 14) in which the pixel value of each pixel of the original image is stored. The read pixel values of two pixels in one column to be processed are sequentially held as L1 and L2, respectively. The outputs L1 and L2 of the original image register 12 are commonly input to both the product-sum calculators 16a and 16b of the preprocessing circuit 22.

  The coefficient register 14 holds a coefficient value that determines the function (filter processing) of the arithmetic circuit 10. In the present embodiment, the coefficient register 14 holds four coefficient values C11, C21, C12, and C22 corresponding to 2 columns × 2 rows = 4 pixels of the original image. The coefficient values C11 and C21 in the first column are input to the product-sum calculator 16a, and the coefficient values C12 and C22 in the second column are input to the product-sum calculator 16b.

  The preprocessing circuit 22 is composed of two product-sum calculators 16a and 16b for the number of columns (for the number of rows).

  The product-sum calculator 16a performs a product-sum operation C11L1 + C21L2 of the pixel values L1 and L2 for two pixels in one column and the two coefficient values C11 and C21 in the first column from the left side in FIG.

  The product-sum operation unit 16b performs a product-sum operation C12L1 + C22L2 of the pixel values L1 and L2 for two pixels in one column and the two coefficient values C12 and C22 in the second column. The calculation result (b) output from the product-sum calculator 16 b is input to the adder 18.

  The product-sum calculators 16a and 16b can be configured as shown in FIG. 17, for example. The configuration of the product-sum calculators 16a and 16b is not limited at all, and any of various configurations capable of performing the same product-sum operation can be used.

  Subsequently, the post-processing circuit 24 includes two product-sum registers 21a and 21b corresponding to the number of columns.

  The product-sum register 21a is constituted by a flip-flop 20a. The flip-flop 20a holds the output T1 of the product-sum calculator 16a as the hold value P1 at the timing of the valid edge (clock edge) of the clock signal (not shown). In other words, the product-sum register 21a holds the addition result of the output of the product-sum calculator 16a and 0. For this reason, an adder is omitted as compared with a product-sum register 21b described below. The flip-flop 20a also outputs the value held in the previous cycle to the adder 18 as the output P1 'before holding P1.

  The product-sum register 21b includes an adder 18 and a flip-flop 20b. The adder 18 adds the output T2 of the product-sum calculator 16b and the output P1 ′ of the flip-flop 20a, and the addition result (o) is stored in the flip-flop 20b at the hold value P2 at the timing of the clock edge. Held as. As described above, the product-sum register 21b includes the adder 18 and the flip-flop 20b, thereby calculating an integrated value between the operation result of the product-sum operation unit 16b and the value held in the product-sum register 21a in the previous cycle. And hold. The value P2 held in the flip-flop 20b is output as the pixel value of each pixel of the image after filtering.

  The clock signal supplied to the flip-flops 20a and 20b for holding the calculation result can be the same as the clock signal supplied to the original pixel register 12 for holding the pixel value. The calculation result using the pixel value held in the original image register 12 at the timing of the first valid edge of the clock signal is held in the flip-flops 20a and 20b at the timing of the next valid edge of the same clock signal. can do. In this case, the period from the first valid edge of the clock signal to the next valid edge is one computation cycle of the computation circuit 10.

  Next, the basic operation of the arithmetic circuit 10 will be described.

  In the arithmetic circuit 10, at least the flip-flop 20a is initialized in the initialization cycle, and the held value becomes zero. Further, four coefficient values C11, C21, C12, and C22 are set (held) in the coefficient register 14.

  Subsequently, for each cycle, pixel values for two pixels in one column of the original image read in the processing order are held in the original image register 12 as L1 and L2. For example, when the pixel value of each pixel of the original image shown in FIG. 8 is stored in the image information storage device and the filtering process is sequentially performed in the order shown in FIG. For each cycle, the pixel values of two pixels in one column are held in the order of L11, L21 in the first column, L12, L22 in the second column, L13, L23 in the third column, and so on from the left side in FIG. .

  In the product-sum calculator 16 a of the pre-processing circuit 22, the pixel values L 1 and L 2 for two pixels in one column input from the original image register 12 and the coefficient value C 11 in the first column input from the coefficient register 14. , C21 and product-sum operation C11L1 + C21L2. Similarly, the product-sum calculator 16b performs a product-sum operation C12L1 + C22L2 of the pixel values L1 and L2 for two pixels in one column and the coefficient values C12 and C22 in the second column.

  The output T1 of the product-sum calculator 16a is held as the hold value P1 in the flip-flop 20a of the product-sum register 21a of the post-processing circuit 24 at the timing of the clock edge. Then, the adder 18 adds the output T2 of the product-sum calculator 16b and the output P1 'of the flip-flop 20a (= 1 output T1 of the product-sum calculator 16a before one cycle). The addition result (o) is held as the hold value P2 in the flip-flop 20b of the product-sum register 21b at the same clock edge timing, and sequentially output as the pixel value of each pixel of the image after the filter processing.

  Note that the pixel value (convolution operation result) of each pixel (calculation target point) of the image after the filter processing is as shown in FIG. 10 to FIG. 12 of the pixel to be processed of 2 columns × 2 rows in the two-dimensional space. Located at the center of the range.

  Next, the operation of the arithmetic circuit 10 will be specifically described with reference to Table 2 below. In the following description, it is assumed that the pixel value of each pixel of the original image shown in FIG. 8 is stored in the image information storage device, and the filter processing is sequentially performed in the order shown in FIG.

  Table 2 shows pixel values L1 and L2 held in the original image register 12 at the start of each cycle, and product-sum operation results T1 and T2 calculated by the product-sum operation units 16a and 16b using the pixel values. The values P1 and P2 held in the flip-flops 20a and 20b at the end of the same cycle are shown. The same applies to Tables 3 and 4 shown later.

  The first cycle is an initialization cycle. At least the hold value of the flip-flop 20a is initialized to zero.

  In cycle 1, the pixel values L11 and L21 for the two pixels in the first column from the left side in FIG. 8 are read from the image information storage device at the timing of the first edge of the clock signal, and are stored in the original image register 12 respectively. It is held as L1 and L2. As a result, the operation result T1 = C11L11 + C21L21 is output from the product-sum operation unit 16a, and the operation result T2 = C12L11 + C22L21 is output from the product-sum operation unit 16b.

  The flip-flop 20a holds the output T1 = C11L11 + C21L21 of the product-sum calculator 16a as the hold value P1 at the timing of the next edge of the clock signal. From the adder 18, the output P1 ′ of the flip-flop 20a (shown in Table 2 as the value of P1 in the previous cycle, that is, the initialization cycle) = 0 and the output T2 of the product-sum calculator 16b = Integration result with C12L11 + C22L21 (o) = C12L11 + C22L21 is output. In the flip-flop 20b, the integration result (o) is held as the hold value P2 at the timing of the clock edge.

  Subsequently, in cycle 2, pixel values L12 and L22 for two pixels in the second column are read from the image information storage device, and are stored in the original image register 12 as L1 and L2, respectively. As a result, the operation result T1 = C11L12 + C21L22 is output from the product-sum operation unit 16a, and the operation result T2 = C12L12 + C22L22 is output from the product-sum operation unit 16b.

  The flip-flop 20a holds the output T1 = C11L11 + C21L21 of the product-sum calculator 16a in synchronization with the clock edge. From the adder 18, the value P1 ′ held in the flip-flop 20a in the previous cycle (cycle 1) (shown in Table 2 as the value of P1 in the previous cycle, ie, cycle 1) = C11L11 + C21L21 Accumulation result (o) = C11L11 + C12L12 + C21L21 + C22L22 with the output T2 = C12L12 + C22L22 of the product-sum calculator 16b is output. In the flip-flop 20b, the integration result (o) is held as the hold value P2 at the timing of the clock edge. Then, the hold value is output from the flip-flop 20b as the pixel value P11 after the filter processing.

  Subsequently, in cycle 3, the pixel values L13 and L23 for the two pixels in the third column are read from the image information storage device and held in the original image register 12 as L1 and L2, respectively. As a result, the operation result T1 = C11L13 + C21L23 is output from the product-sum operation unit 16a, and the operation result T2 = C12L13 + C22L23 is output from the product-sum operation unit 16b.

  The flip-flop 20a holds the output T1 = C11L12 + C21L22 of the product-sum calculator 16a at the timing of the clock edge. The adder 18 outputs the addition result (o) = C11L12 + C12L13 + C21L22 + C22L23 of the value P1 ′ = C11L12 + C21L22 held in the flip-flop 20a in the previous cycle (cycle 2) and the output T2 = C12L13 + C22L23 of the product-sum calculator 16b. This addition result (o) is held in the flip-flop 20b at the timing of the clock edge, and is output as the pixel value P12 of the pixel after the filter processing.

  The subsequent operation is the same as described above. In the arithmetic circuit 10, the pixel value P11 of the first pixel after the filtering process is output in two cycles after the initialization. Thereafter, the pixel values P12, P13, ... are output sequentially.

  Table 2 shows a case where the hold value P2 of the flip-flop 20b is also initialized to 0 in the initialization cycle. However, in cycle 1, it is necessary to initialize the flip-flop 20a in which the value P1 'output before the clock signal is used for the operation, but the initialization is not essential for the flip-flop 20b. Further, after the output of the pixel values P11 to P15 of the pixels after the filter processing in the first row in the order shown in FIG. 13, the initialization cycle is performed again, and then the same cycle as the first row is repeated. To hold and output the pixel value of the pixel after the filter processing in the second row.

  In the arithmetic circuit 10 of the present embodiment, as in the conventional arithmetic circuit 140 shown in FIG. 14, it is necessary to read the pixel value of the pixel of the original image that is commonly used in the calculation of adjacent pixels from the image information storage device twice. There is an advantage that there is no. In addition, in the conventional arithmetic circuit 140, only one product-sum arithmetic unit is used, but in the arithmetic circuit 10 of the present embodiment, by using two product-sum arithmetic units, Twice the processing speed is realized. Further, unlike the conventional arithmetic circuit 140, complicated control using the counter 156 and the multiplexer 149 is not required. Therefore, it is possible to realize a high processing speed with a simple configuration.

  Next, as another example of the first embodiment, an arithmetic circuit that performs filter processing by convolution operation using pixel values for 25 pixels of 5 columns × 5 rows of the original image will be described.

  FIG. 2 is a conceptual diagram of the second embodiment showing the configuration of the arithmetic circuit of the present invention. The arithmetic circuit 30 shown in the figure is an abstract expression compared to the arithmetic circuit 10, but it is similar from the pixel values for 25 pixels of 5 columns × 5 rows of the original image arranged in the two-dimensional space. Filter processing by convolution operation. The arithmetic circuit 30 includes an original image register 32, a coefficient register 34, a preprocessing circuit 42, and a postprocessing circuit 44.

  Hereinafter, the difference between the arithmetic circuit 30 shown in FIG. 2 and the arithmetic circuit 10 shown in FIG. 1 will be mainly described.

In the arithmetic circuit 30, the original image register 32 and the coefficient register 34 have the same functions as the original image register 12 and the coefficient register 14 of the arithmetic circuit 10 in FIG. In FIG. 2, the original image register 32 is represented by a vertically long rectangle denoted by L _i . This is obtained by L _i and a simplified representation together pixel values L1i~L5i of five pixels of the i-th row of the original image to be processed. The same applies to C1 to C5 of the coefficient register 34.

The preprocessing circuit 42 includes five product-sum calculators 36a, 36b, 36c, 36d, and 36e corresponding to the number of columns. The preprocessing circuit 42 also has the same function as the preprocessing circuit 22 of the arithmetic circuit 10 in FIG. For example, in FIG. 2, the uppermost product-sum calculator 36a (first from the top) performs the calculation of C1L _i (= C11L1i + C21L2i + C31L3i + C41L4i + C51L5i) and outputs the calculation result T1. The same applies to the second to fifth product-sum calculators 36b, 36c, 36d, and 36e.

  The post-processing circuit 44 includes five product-sum registers 41a, 41b, 41c, 41d, and 41e corresponding to the number of columns. The post-processing circuit 44 is also configured similarly to the product-sum registers 21a and 21b of the arithmetic circuit 10 in FIG. 1, and has the same function. That is, the first product-sum register 41a is composed of only flip-flops, while the second to fifth product-sum registers 41b-41e are composed of adders and flip-flops.

  The uppermost (first from the top) product-sum register 41a holds the output T1 of the first product-sum calculator 36a as the hold value P1 at the timing of the clock edge.

  The second product-sum register 41b holds the addition result of the output P1 'of the product-sum register 41a and the calculation result T2 of the product-sum calculator 36b as the hold value P2 at the timing of the clock edge.

  The third to fifth product-sum registers 41c, 41d, and 41e operate in the same manner as the second product-sum register 41b. Then, the hold value P5 held in synchronization with the clock signal in the last (fifth) product-sum register 41e is output as the pixel value P of each pixel of the image after filtering.

  If the pixel value and the coefficient value are 8 bits, as shown in FIG. 2, 8 bits × 5 = 40 wires are connected from the original image register 32 to the preprocessing circuit 42, and the coefficient register From 34 to the pre-processing circuit 42, 8 bits × 5 × 5 = 200 wires are connected. Also, assuming that the calculation results T1 to T5 are 8 bits, 8 bits × 5 = 40 wires are connected from the preprocessing circuit 42 to the postprocessing circuit 44. When the pixel value of the pixel after the filter processing is 8 bits, 8 bits = 8 wires are connected from the post-processing circuit 44. Also in the subsequent embodiments, the number of wiring bits is shown in the figure as necessary.

  Since the basic operation of the arithmetic circuit 30 is the same as that of the arithmetic circuit 10 of FIG. 1, repeated description is omitted here.

  Similarly, when the pixel value of each pixel of the original image shown in FIG. 8 is stored in the image information storage device and the filtering process is sequentially performed in the order shown in FIG. 13, the specific operation of the arithmetic circuit 30 is as shown in the following table. As shown in 3 and 4.

In Tables 3 and 4, the output L _i of the original image register 32 is L1 in cycle 1, which means L1 = L11, L21, L31, L41, and L51. The same applies to L2 to L6 of cycles 2 to 6. The output T1 of the product-sum calculator 36a is C1L1 in cycle 1, which means C1L1 = C11L11 + C21L21 + C31L31 + C41L41 + C51L51. The same applies to the outputs T2 to T5 of the product-sum calculators 36b, 36c, 36d, and 36e, and the outputs P1 to P5 of the product-sum registers 41a, 41b, 41c, 41d, and 41e.

  In the arithmetic circuit 30, after initialization, the pixel value P of the first pixel after filtering is output in five cycles, and thereafter, the pixel value P of the second and subsequent pixels after filtering is sequentially output every cycle. Is done. Similarly, the arithmetic circuit 30 has the advantage that it is not necessary to read out the pixel value of the pixel of the original image that is commonly used in the calculation of adjacent pixels from the image information storage device twice. Since a product-sum operation unit is used, a processing speed five times that of the conventional one is realized.

  Note that the present invention is not limited to image data as in the first and second embodiments, and is an arithmetic circuit that filters data values of all types of data arranged in a two-dimensional space by a convolution operation. Is equally applicable. The same applies to the following embodiments. The arithmetic circuits 10 and 30 of the first and second embodiments are not limited to the filtering process of 2 columns × 2 rows or 5 columns × 5 rows, but N columns × N rows (N is an integer of 2 or more). The present invention can be applied to an arithmetic circuit that performs this filtering process.

  In the arithmetic circuits of the first and second embodiments, generally, after the initialization, the data values of the 1st to Nth columns in the range of N columns × N rows in the two-dimensional space are sequentially given from the 1st to Nth cycles. It is held in the data register and the operation result of the first product-sum operation unit is held in the first product-sum register. Also, the integrated value of the operation result of the nth (n = 2 to N) product-sum operation unit and the value held in the n−1th product-sum register in the previous cycle is held in the nth product-sum register. Is done. As a result, the convolution calculation result of the first calculation target point located at the center of the range of N columns × N rows in the two-dimensional space is output from the Nth product-sum register.

  Further, in the (N + 1) cycle following the 1st to Nth cycles, the data values after the (N + 1) th column adjacent to the range of N columns × N rows in the two-dimensional space are sequentially held in the data register. As a result, after N + M cycles (M is an integer equal to or greater than 1), the Nth product-sum register outputs the convolution calculation result of the Mth calculation target point adjacent in the column direction from the first calculation target point. .

  Next, a third embodiment of the present invention will be described.

  FIG. 3 is a conceptual diagram of the third embodiment showing the configuration of the arithmetic circuit of the present invention. Similar to the arithmetic circuit 30 in FIG. 2, the arithmetic circuit 50 shown in FIG. 2 also performs filter processing by convolution operation from pixel values for 25 pixels of 5 columns × 5 rows of the original image arranged in the two-dimensional space. . The arithmetic circuit 50 shown in FIG. 3 includes an original image register 52, a coefficient register 54, a preprocessing circuit 62, a postprocessing circuit 64, and a counter 66.

  FIG. 4 is a schematic diagram specifically showing the arithmetic circuit 50 of FIG. In FIG. 4, in order to avoid the complexity, the display of the counter 66 is omitted, and the count value is represented by j = 0-2. For example, the clock terminal of the flip-flop 60a1 is j = 0, which means that the clock signal is input to the flip-flop 60a1 during the period when the count value j = 0 of the counter 66. .

  Hereinafter, the difference between the arithmetic circuit 50 shown in FIGS. 3 and 4 and the arithmetic circuit 30 shown in FIG. 2 will be mainly described.

  In the arithmetic circuit 50, the original image register 52 and the coefficient register 54 have the same functions as the original image register 32 and the coefficient register 34 of the arithmetic circuit 30 in FIG.

  In the arithmetic circuit 30 of FIG. 2, coefficient values C1 to C5 respectively corresponding to the five product-sum calculators 36a, 36b, 36c, 36d, and 36e are output simultaneously (in parallel) from the coefficient register 34. On the other hand, in the arithmetic circuit 50 of FIG. 3, every time the count value j of the counter 66 changes, only one or two coefficient values are simultaneously sent from the coefficient register 54 to the two product-sum calculators 56a and 56b ( Output in parallel). The two are different in this respect.

  In the arithmetic circuit 30 shown in FIG. 2, if one coefficient value C is 8 bits, 8 bits × 5 × 5 = 200 wires are required. On the other hand, in the arithmetic circuit 50 shown in FIGS. 3 and 4, since the coefficient value output from the coefficient register 54 is two at the maximum, if one coefficient value is similarly 8 bits, 8 bits × 5 X2 = Only 80 wires are required, and the number of wires can be reduced to 2/5.

  That is, in the present embodiment, the output bit width of the coefficient register 54 can be reduced. As described above, by reducing the output bit width, it is possible to use a memory, FIFO, or the like having a smaller area in place of the register as the coefficient register 54. Further, this is not limited to the coefficient register 54, and the same applies to the original image register as shown in the following embodiment.

  Subsequently, the preprocessing circuit 62 is constituted by two product-sum calculators 56a and 56b which are smaller than the number of columns (5).

MAC unit 56a performs calculation of C _{2j + 1} L _i, and outputs the operation result T _{2j + 1.} Also, sum-of-products arithmetic unit 56b performs arithmetic operation of C _{2j + 2} L _i, and outputs the operation result T _{2j + 2.}

  The counter 66 repeatedly counts 0 to 2 in synchronization with the clock signal after initialization. In the present embodiment, when the count value j = 0 of the counter 66, the coefficient values C1 and C2 are output from the filter coefficient register 54 and input to the product-sum calculators 56a and 56b, respectively. When the count value j is 1, the coefficient values C3 and C4 are input to the product-sum calculators 56a and 56b, respectively. When the count value j is 2, the coefficient value C5 is input to the product-sum calculator 56a. .

  When the coefficient sum C1 is input to the product-sum calculator 56a, C11L1i + C21L2i + C31L3i + C41L4i + C51L5i is output as the calculation result T1. When C3 is input, C13L1i + C23L2i + C33L3i + C43L4i + C53L5i is output as T3, and when C5 is input, C15L1i + C25L2i + C35L3i + C45L4i + C55L5i is output as T5.

  When the coefficient sum C2 is input to the product-sum calculator 56b, C12L1i + C22L2i + C32L3i + C42L4i + C52L5i is output as the calculation result T2. When C4 is input, C14L1i + C24L2i + C34L3i + C44L4i + C54L5i is output as T4.

  Note that when the coefficient value C5 is input to the product-sum calculator 56a, the output of the product-sum calculator 56b is not used by the post-processing circuit 64, so the coefficient value input to the product-sum calculator 56b is not limited.

  Subsequently, the post-processing circuit 64 includes five product-sum registers 61a, 61b, 61c, 61d, and 61e corresponding to the number of columns.

  As shown in FIG. 4, the first product-sum register 61a is composed of two flip-flops 60a1 and 60a2. The flip-flop 60a1 in the first stage temporarily holds the output of the product-sum calculator 56a as the product-sum operation result T1 in the first column at the timing of the clock edge when the count value j = 0 of the counter 66. Specifically, for example, the counter 66 operates at the timing of the valid edge of the clock signal and the count value j changes to 0, and during one cycle of the clock signal, the coefficient value is input to the calculator 56a, and The product-sum operation result is output from the arithmetic unit 56a and held in the flip-flop 60a1 at the next effective edge timing. The product-sum operation result held in this first-stage flip-flop (hereinafter referred to as “temporary register”) 60a1 is the second-stage flip-flop at the clock edge timing in the period when the count value j = 0. Is held in the flip-flop 60a2 as the hold value P1. On the other hand, before P1 is held, the value P1 ′ held in the second flip-flop 60a2 during the period when the previous count value j = 0 is output from the flip-flop 60a2, and the second sum of products is output. The data is input to the adder 58b of the register 61b.

  The product-sum register 61b includes an adder 58b and two flip-flops 60b1 and 60b2. The first-stage flip-flop (temporary register) 60b1 outputs the output of the product-sum operation unit 56b to the second-column product-sum operation result T2 at the timing of the clock edge during the period when the count value j = 0 of the counter 66. Hold as. The adder 58b adds the product-sum operation result T2 held in the temporary register 60b1 and the output P1 'of the flip-flop 60a2. The flip-flop 60b2 holds the output P1 '+ T2 of the adder 58b at the timing of the clock edge in the period when the count value j = 0 of the counter 66 is next. P1 'used for the calculation here is a value held in the flip-flop 60a2 before P1 is held.

  The configuration and operation of the product-sum registers 61c, 61d, and 61e are the same as the configuration and operation of the product-sum register 61b. That is, the product-sum register 61c and the temporary registers 61c1 and 61d1 of the product-sum register 61d respectively output the outputs of the product-sum calculators 56a and 56b at the clock edge timing during the period when the count value j = 1 of the counter 66. The product-sum operation results T3 and T4 in the third and fourth columns are held. The temporary register 60e1 of the product-sum register 61e holds the output of the product-sum calculator 56a as the product-sum operation result T5 in the fifth column at the timing of the clock edge during the period when the count value j = 2 of the counter 66. Further, the adders 58c to 58e of the product-sum registers 61c to 61e respectively correspond to the values P2 ′ to P4 ′ held in the second-stage flip-flops 60b2 to 60d2 of the product-sum registers 61b to 61d and the corresponding temporary registers. The accumulated value of the product-sum operation results T3 to T5 held in is output to the second-stage flip-flops 60c2 to 60e2. Then, these integrated values P2 ′ + T3 to P4 ′ + T5 are held in the second-stage flip-flops 60c2 to 60e2 of the respective product-sum registers at the timing of the clock edge in the next period when the count value j = 0. Is done.

  Next, the basic operation of the arithmetic circuit 50 will be described.

  In the arithmetic circuit 50, five coefficient values C1 to C5 in five columns are held in the coefficient register 14 as initialization processing. At least the temporary registers of the product-sum registers 61a, 61b, 61c, and 61d and the holding values of the second-stage flip-flops are all initialized to zero.

  As described above, the counter 66 repeatedly counts in the order of 0 to 2 in synchronization with the clock signal, and outputs the count value j = 0 to 2. The count value j is input to the coefficient register 54, the original image register 52, the preprocessing circuit 62, and the postprocessing circuit 64. Each time the count value j = 0, the pixel values for five pixels in one column of the original image to be processed are held in the original image register 52 as Li.

  During the period of the count value j = 0 of the counter 66, the first and second coefficient values C1 and C2 are output from the coefficient value register 54 and input to the product-sum calculators 56a and 56b of the preprocessing circuit 62, respectively. .

  In the product-sum calculator 56a, the pixel values L1 for five pixels in the first column input from the original image register 52 and the five factors in the first column input from the coefficient register 54 are displayed. A product-sum operation C1L1 with the numerical value C1 is performed, and the operation result T1 is output. The product-sum calculator 56b performs a product-sum operation C2L1 of the pixel values L1 for five pixels in the first column and the five coefficient values C2 in the second column, and the calculation result T2 is Is output.

  The outputs T1 and T2 of the product-sum calculators 56a and 56b are held in the flip-flop 60a1 of the first product-sum register 61a and the flip-flop 60b1 of the second product-sum register 61b, respectively, at the timing of the clock edge.

  Subsequently, during the period of the count value j = 1 of the counter 66, the coefficient values C3 and C4 in the third and fourth columns are output from the coefficient register 54 and input to the product-sum calculators 56a and 56b, respectively.

  Similarly, the product-sum operation unit 56a performs a product-sum operation C3L1 of the pixel values L1 for five pixels in the first column and the five coefficient values C3 in the third column, and the calculation result T3 Is output. The product-sum calculator 56b performs a product-sum operation C4L1 of the pixel values L1 for five pixels in the first column and the five coefficient values C4 in the fourth column, and the calculation result T4 is Is output.

  The outputs T3 and T4 of the product-sum calculators 56a and 56b are held in the temporary register 60c1 of the third product-sum register 61c and the temporary register 60d1 of the fourth product-sum register 61d, respectively, at the timing of the clock edge.

  Subsequently, during the period of the count value j = 2 of the counter 66, the fifth coefficient value C5 is output from the coefficient register 54 and input to the product-sum calculator 56a of the preprocessing circuit 62.

  The product-sum operation unit 56a performs a product-sum operation C5L1 of the pixel values L1 for five pixels in the first column and the five coefficient values C5 in the fifth column, and outputs the calculation result T5. The

  The output T5 of the product-sum calculator 56a is held in the temporary register 60e1 of the fifth product-sum register 61e at the timing of the clock edge. As described above, in the arithmetic circuit 50, the count value of the counter 66 is changed to j = 0, 1, 2 by using the product-sum arithmetic units 56a, 56b which is smaller in number (two) than the number of columns (5). In the meantime, five product-sum operation results T1 to T5 are calculated and held in the temporary registers 60a1 to 60e1 of the respective product-sum registers 61a to 61e.

  Then, during the next count value j = 0, the product-sum operation results temporarily held in the temporary registers 60a1 to 60e1 are held as they are or in the second-stage flip-flops of the product-sum registers 61a to 61d. After being integrated with the value that has been set, it is held in the second-stage flip-flops 60a2 to 60e2.

  In the product-sum register 61a, the product-sum operation result T1 held in the temporary register 60a1 is held in the flip-flop 60a2 at the timing of the clock edge. In the product-sum register 61b, the adder 58b adds the product-sum operation result T2 held in the temporary register 60b1 and the output P1 ′ of the flip-flop 60a2, and the addition result P1 ′ + T1 is the clock edge. At the timing, it is held in the flip-flop 60b2 as the hold value P2. The output P1 'of the flip-flop 60a2 used for the addition operation here is the value held in the flip-flop 60a2 during the previous period when the count value j = 0 of the counter 66. In this case, the value after initialization, that is, 0.

  In the product-sum register 61c, the adder 58c adds the product-sum operation result T3 held in the temporary register 60c1 and the output P2 ′ of the flip-flop 60b2, and the addition result P2 ′ + T3 is obtained at the timing of the clock edge. It is held in the flip-flop 60c3 as a hold value P3. In the product-sum register 61d, the adder 58d adds the product-sum operation result T4 held in the temporary register 60d1 and the output P3 ′ of the flip-flop 60c2, and the addition result P3 ′ + T4 is added to the clock edge. At the timing, it is held in the flip-flop 60d2 as the hold value P4. The outputs P2 'and P3' of the flip-flops 60b2 and 60c2 used for the addition result here are values held in the flip-flops 60b2 and 60c2 during the previous period when the count value j = 0. In this case, the value after initialization, that is, 0.

  In the product-sum register 61e, the adder 58e adds the product-sum operation result T5 held in the temporary register 60e1 and the output P4 ′ of the flip-flop 60d2, and the addition result P4 ′ + T5 is obtained at the timing of the clock edge. The held value P5 is held in the flip-flop 60e2. The output P4 'of the flip-flop 60d2 used for the addition operation here is a value held last time during the period in which the count value j = 0. In this case, the value after initialization, that is, 0. Then, the output P5 of the flip-flop 60e2 is output as the pixel value P of each pixel of the image after filtering.

  As described above, the arithmetic circuit 50 performs the product-sum operations C1L1 to C5L1 using the two product-sum calculators 56a and 56b in the process in which the counter value j of the counter 66 changes to 0, 1, and 2. The calculation results T1 to T5 are held in the temporary registers 60a1 to 60e1 of the first to fifth product-sum registers 61a to 61e, respectively. Then, during the next period when the count value j = 0, the product-sum operation result T1 held in the temporary register 60a1 of the first product-sum register 61a is the second-stage flip-flop 60a2 of the same product-sum register 61a. Retained. At the same time, the product-sum operation results held in the temporary registers 60b1 to 60e1 of the same product-sum registers 61b to 61e are respectively stored in the second flip-flops 60b2 to 60e2 of the second to fifth product-sum registers 61b to 61e. T2 to T5 and the values P1 ′ to P4 ′ held in the period when the previous count value j = 0 was stored in the second flip-flops 60a2 to 60d2 of the first to fourth product-sum registers 61a to 61d. The integrated value is held.

  That is, in the arithmetic circuit 50, the arithmetic circuit 30 shown in FIG. 2 performs an operation performed in one cycle in the process in which the count value j of the counter 66 changes to 0, 1, 2 and returns to 0. Hereinafter, each period in which the count value j is 0, 1, and 2 is referred to as a step in order to distinguish it from a calculation cycle.

  In the arithmetic circuit 50, the counter 66 repeatedly performs counting in the order of 0 to 2, and the above operation is repeated. Similarly to the arithmetic circuit 30, the pixel value P of the first pixel subjected to the filter processing by the 5 column × 5 row convolution operation in the five cycles after the initialization is stored in the last product-sum register 61 e of the post-processing circuit 64. It is held in the flip-flop 60e2 and output.

  Similarly, when the pixel value of each pixel of the original image shown in FIG. 8 is stored in the image information storage device and the filter processing is sequentially performed in the order shown in FIG. 13, the specific operation of the arithmetic circuit 50 is as follows. As shown in FIGS.

  Tables 5 and 6 show the count value j in each step, the product-sum operation results T1 to T5 held in the temporary registers 60a1 to 60e1 of the product-sum registers 61a to 61e in synchronization with the clock edge, and The values P1 to P5 held in the second-stage flip-flops 60a2 to 60e2 are shown. Therefore, the value P1 supplied to the adders 58b to 58e of the product-sum registers 61b to 61e in order to calculate the value held in the second-stage flip-flops 60b2 to 60e2 in the step where the count value j = 0. “˜P4” is different from the values shown in Table 6 as the values of P1 to P4 in the same step. For example, Table 6 shows T11, T21, T31, and T41 as values of P1 to P4 in the fourth step, respectively. However, the values of P1 ′ to P4 ′ supplied to the adders 58b to 58e in the same step are held in the respective flip-flops 60a2 to 60d2 in the first step where j = 0 last time, and then the third step. The value that has been maintained until 0, that is, 0. In Tables 5 and 6, for example, T11 is the same as C1L1 in Table 4. The same applies to T12, T13,... And T21, T31,.

  Here, referring to Tables 4 and 5, in the process in which the count value j of the counter 66 changes to 0, 1, and 2 and further returns to 0, the arithmetic circuit 50 makes the arithmetic circuit 30 in FIG. A process for performing an operation to be performed will be described.

  For example, in the first cycle starting from the first step of Tables 5 and 6, first, the pixel value L1 of the first one column is held in the original image register 52 in the first step. Then, through the first to third steps, the first column of pixel values L1 held in the original image register 52 and the coefficient values held in the coefficient register 54 by the two product-sum calculators 56a and 56b. Multiply-and-accumulate operations are performed. The product-sum calculation results T11 to T51 are held in the temporary registers 60a1 to 60e1 of the product-sum registers 61a to 61e as the values of T1 to T5 shown in FIG. Subsequently, in a fourth step, the product-sum operation result T11 between the pixel value of the first column and the coefficient of the first column held in the temporary register 60a1 of the first product-sum register 61a is 1 The value of P1 in Table 6 is held in the second flip-flop 60a2 of the second product-sum register 61a. The product-sum operation result T21 between the pixel values of the first column and the coefficient values of the second to fifth columns held in the temporary registers 60b1 to 60e1 of the second to fifth product-sum registers 61b to 61e. To T51 are values P1 ′ to P4 ′ (values P1 to P4 held in the first step) supplied from the second-stage flip-flops 60a2 to 60d2 of the first to fourth product-sum registers 61a to 61d, respectively. And are held in the second flip-flops 60b2 to 60e2 of the second to fifth product-sum registers 61b to 61e. In this case, since the values held in the flip-flops 60a2 to 60d2 in the first step are all 0, the product-sum operation results T21 to T51 are held as they are as the values of P2 to P5 in Table 6. This completes the first processing cycle.

  In the fourth step, the second sum to the original image register 52 in the second cycle is held in parallel with the product-sum operation result or the accumulated value in the second-stage flip-flops 60a2 to 60e2 in the first cycle. The holding of the pixel value L2 of one column, the product-sum operation between the pixel value L2 and the coefficient value, and the holding of the result in the temporary register are started. That is, the values of T1 and T2 in Table 5 change to T12 and T22, respectively. Thus, in the arithmetic circuit 50, in the step where the count value j of the counter 66 becomes 0, part of the processing of two consecutive cycles is performed in parallel.

  The processing in the second cycle is further performed in the fifth to seventh steps. That is, following the fourth step, the product-sum operation is performed in the fifth and sixth steps and the result is stored in the temporary register. In the seventh step, the product-sum operation result to the second-stage flip-flops 60a2 to 60e2 is performed. Alternatively, the integrated value is held. Here, the values held in the second-stage flip-flops 60a to 60d of the first to fourth product-sum registers 61a to 61d used in the integration value calculation in the seventh step are the previous cycle, that is, the first cycle. It is held in four steps in synchronization with the clock signal.

  Here, at the end of the first cycle, values P1 ′ to P4 ′ used for integration performed in the fourth step are held in the second-stage flip-flops 60a to 60d in the first step following the initialization step. It is held as values P1 to P4. As described above, in the first step, the product-sum operation as the processing of the first cycle and the holding of the product-sum operation result in the temporary register are already started. However, as described above, in the arithmetic circuit 50, in the step where the count value j becomes 0, part of the processing of two consecutive cycles is performed in parallel. That is, the holding values P1 to P4 in the second-stage flip-flops 60a to 60d in the first step are performed as part of the initialization cycle that is the previous cycle. Accordingly, the holding values of the second-stage flip-flops 60a to 60d of the first to fourth product-sum registers 61a to 61d, which are used to calculate the integrated value in the last fourth step of the first cycle, are also the previous cycle. It is the retained value.

  Thereafter, the processes in the third and subsequent cycles are performed in the same manner, and the pixel value P of the pixel after the first filter process is output in the sixteenth step when the fifth cycle ends. Thereafter, every three cycles, the pixel value P of the pixel after the second and subsequent filter processing is sequentially output.

  The arithmetic circuit 50 of this embodiment also has an advantage that it is not necessary to read out the pixel value of the pixel of the original image that is commonly used in the calculation of adjacent pixels from the image information storage device twice. The arithmetic circuit 50 uses only two product-sum arithmetic units 56a and 56b. As a result, the processing speed is 1/3 times the conventional speed, but there is an advantage that the circuit scale can be reduced if the processing speed is not required.

  In the present embodiment, coefficient values are sequentially input to the product-sum calculator 56a in the order of coefficient values C1, C3, and C5, and coefficient values are sequentially input to the product-sum calculator 56b in the order of C2 and C4. Have been entered. However, the present invention is not limited to this, and the order in which the coefficient values are input to the product-sum operation unit may be any order. It is also arbitrary which coefficient value is input to which of the product-sum calculators 56a and 56b.

  The arithmetic circuit of the third embodiment is not limited to 5 columns × 5 rows, but can be applied to filter processing by convolution operation of N columns × N rows (N is an integer of 3 or more). At this time, the number m of product-sum calculators in the preprocessing circuit 52 is 2 ≦ m <N.

  In the arithmetic circuit of the present embodiment, generally, after initialization, data values in the 1st to Nth columns in the range of N columns × N rows in the two-dimensional space are sequentially stored in the data register over 1 to N cycles. For each cycle, between each of at least some of the m multiply-add calculators of the pre-processing circuit, between N data values and N coefficients in any column of N columns × N rows. The operation of calculating the sum of products is repeated less than N times (N steps), thereby calculating the sum of products between the N data values and the coefficients of all the columns. The product-sum operation result between the N data values and the N coefficients in the first column calculated by the product-sum calculator is held in the first product-sum register of the post-processing circuit, and N Of the product-sum operation between the data value of n and the coefficients of the n-th column (n = 2 to N) and the value held in the n−1th product-sum register of the post-processing circuit in the previous cycle Is held in the nth product-sum register of the post-processing circuit. As a result, the convolution calculation result of the first calculation target point located at the center of the range of N columns × N rows in the two-dimensional space is output from the Nth product-sum register.

  Further, as shown in FIG. 4, the post-processing circuit is further provided with 1-Nth temporary registers (flip-flops 60a1, 60b1, 60c1 of FIG. 4) provided corresponding to each of the 1-Nth product-sum registers. , 60d1, 60e1). In this case, after each product-sum operation result between the data value and the coefficient value in the 1st to Nth columns calculated by the product-sum operation unit is held in the 1st to Nth temporary registers for each cycle. The integrated value of the nth product-sum operation result held in the temporary register and the value held in the n−1th product-sum register in the previous cycle is held in the nth product-sum register.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 5 is a schematic diagram of the fourth embodiment showing the configuration of the arithmetic circuit of the present invention. The arithmetic circuit 70 shown in the figure performs a filtering process by a convolution operation from pixel values of 4 pixels of 2 columns × 2 rows of an original image arranged in a two-dimensional space. The arithmetic circuit 70 includes an original image shift register 72, a coefficient shift register 74, a preprocessing circuit 82, a postprocessing circuit 84, and a counter 86.

  The original image shift register 72 holds pixel values of 2 columns × 2 rows = 4 pixels of the original image to be processed. Then, for each cycle, the pixel values for the two pixels in the next column are shifted into the right column in FIG. 5, and the pixel values for the two pixels in each column are shifted one column to the left. .

That is, in the original image shift register 72, for each cycle, the pixel value L _i of two pixels in one column of the left (first column) are shifted out, two pixels in one column on the right (second row) The pixel value L _{i + 1 of the} minute is shifted to one column on the left side and held as L _i , and the pixel value for two pixels in the next one column to be processed is a new column on the right side as a new L _{i + 1} Retained. For each cycle, the pixel values L _i for two pixels in the left column are input to the product-sum calculator 76a, and the pixel values L _{i + 1 for} the two pixels in the right column are input to the product-sum calculator 76b. Entered.

  Subsequently, the coefficient shift register 74 determines the function (filtering process) of the arithmetic circuit 70, and the four coefficient values C11, C21, C12, corresponding to 2 columns × 2 rows = 4 pixels of the original image. Hold C22.

  In the coefficient shift register 74, two coefficient values C11 and C21 in one column on the left side and two coefficient values C12 and C22 in one column on the right side in FIG. 5 are alternately shifted (rotated) every cycle. Then, two coefficient values in one column on the left side are output. Two coefficient values C1 (= C11, C21) or C2 (= C12, C22) in one column are input in common to both the product-sum calculators 76a and 76b for each cycle.

  The counter 86 repeatedly counts 1 to 2 in synchronization with the clock signal after initialization. The count of the counter 86 and the shift of the coefficient shift register 74 are performed in synchronization with the same clock signal. In this embodiment, when the count value k = 1, the coefficient value C1 becomes the count value. When k = 2, the coefficient value C2 is commonly input to the product-sum calculators 76a and 76b.

  The preprocessing circuit 82 includes two product-sum calculators 76a and 76b corresponding to the number of columns.

The product-sum operation unit 76a includes, for each cycle, pixel values L _i (for example, L1 in cycle 1 and L2 in cycle 2) for two pixels in one column on the left side of the original image shift register 72, and a coefficient shift register. A product-sum operation T1 = C _{k Li} is performed with two coefficient values C _k (for example, C1 in cycle 1 and C2 in cycle 2) in the first column of 74 (left side in FIG. 5). The output T1 of the product-sum calculator 76a is input to the adder 78a.

On the other hand, the product-sum operation unit 76b includes pixel values L _{i + 1} (for example, L2 in cycle 1 and L3 in cycle 2) for two pixels in one column on the right side of the original image shift register 72, and a coefficient shift register. A product-sum operation T2 = C _k L _{i + 1} with the two coefficient values C _{k in} the first column of 74 is performed. The output T2 of the product-sum calculator 76b is input to the adder 78b.

  The post-processing circuit 84 includes two product-sum registers 81a and 81b corresponding to the number of columns.

  The product-sum register 81a includes an adder 78a, a selector 79a, and a flip-flop 80a. The adder 78a adds the output T1 of the product-sum calculator 76a and the output P1 'of the flip-flop 80a. The selector 79a selects and outputs the output T1 of the product-sum calculator 76a when the count value k = 1 of the counter 86 is 1. When the count value k = 2, the output P1 '+ T1 of the adder 78a is selected and output. The flip-flop 80a holds the output of the selector 79a at the timing of the clock edge. The held value P1 is output as the pixel value of each odd-numbered pixel of the image after filtering.

  The product-sum register 81b includes an adder 78b, a selector 79b, and a flip-flop 80b. The adder 78b adds the output T2 of the product-sum calculator 76b and the output P2 'of the flip-flop 80b. The selector 79b selects and outputs the output T1 of the product-sum calculator 76b when the count value k = 1 of the counter 86 is 1. When the count value k = 2, the output P2 '+ T2 of the adder 78b is selected and output. The flip-flop 80b holds the output of the selector 79b in synchronization with the clock signal. The held value P2 is output as the pixel value of each even-numbered pixel of the image after filtering.

  Next, referring to Table 7, the operation of the arithmetic circuit 70 when the pixel value of each pixel of the original image shown in FIG. 8 is stored in the image information storage device and the filter processing is sequentially performed in the order shown in FIG. Will be explained.

In the initialization cycle, the original image shift register 72, as shown in the upper side in FIG. 5, as the pixel value L _i of two pixels of one column to the left, the first column of the original image of two pixels Pixel values L11 and L21 are held, and pixel values L12 and L22 for two pixels in the second column of the original image are held as pixel values L _{i + 1} for the two pixels on the right side. The coefficient shift register 74 holds the coefficient values C1 (= C11, C21) and C2 (= C12, C22) in a state where C1 is first output.

  In cycle 1, the product-sum calculator 76 a receives the pixel values L 1 = L 11 and L 21 for two pixels in the left column input from the original image register 72 and the two relations input from the coefficient shift register 74. The product-sum operation C1L1 = C11L11 + C21L21 with the numerical values C1 = C11, C21 is performed.

  Similarly, the product-sum calculator 76b performs a product-sum operation C1L2 = C11L12 + C21L22 of the pixel values L2 = L12, L22 for two pixels in the right column and the two coefficient values C1 = C11, C21.

  In cycle 1, since the count value k of the counter 86 is 1, the output T1 = C11L11 + C21L21 of the product-sum calculator 76a is selected by the selector 79a and is held in the flip-flop 80a at the timing of the clock edge.

  Similarly, the selector 79b selects the output T2 = C11L12 + C21L22 of the product-sum calculator 76b and holds it in the flip-flop 80b at the timing of the clock edge.

In cycle 2, as shown in the lower side of FIG. 5, the pixel value L12 for the two pixels in the second column of the original image is used as the pixel value L _i for the two pixels in the first column on the left side of the shift register 72 for the original image. , L22 are held, and pixel values L13, L23 for the second pixel in the third column of the original image are held as pixel values Li _{+ 1} for the two pixels on the right side, and are respectively stored in the product-sum calculators 76a and 76b. Entered. Further, the coefficient value C2 (= C12, C22) is output from the coefficient shift register 74.

  Accordingly, the product-sum calculator 76a performs a product-sum operation C2L2 = C12L12 + C22L22 of the pixel values L2 = L12, L22 for the two pixels in the left column and the coefficient values C2 = C12, C22.

  Similarly, the product-sum calculator 76b performs a product-sum operation C2L3 = C12L13 + C22L23 of the pixel values L3 = L13, L23 for the two pixels in the right column and the coefficient values C2 = C12, C22.

  In the product-sum register 81a, the output T1 = C12L12 + C22L22 of the product-sum calculator 76a and the output P1 ′ = C11L11 + C21L21 of the flip-flop 80a are added by the adder 78a. In cycle 2, since the count value k of the counter 86 is 2, the selector 79a selects the output P1 '+ T1 = C11L11 + C12L12 + C21L21 + C22L22 of the adder 78a and holds it in the flip-flop 80a at the timing of the clock edge. The held value P1 is output as the pixel value P11 of the first pixel of the image after filtering.

  Similarly, in the product-sum register 81b, the adder 78b adds the output T2 = C12L13 + C22L23 of the product-sum calculator 76b and the output P2 '= C11L12 + C21L22 of the flip-flop 80b before the clock signal. Then, the output P2 '+ T2 = C11L12 + C12L13 + C21L22 + C22L23 of the adder 78b is selected by the selector 79b and held in the flip-flop 80b at the timing of the clock edge. The held value P2 is output as the pixel value P11 of the second pixel of the image after filtering.

  The subsequent operation is the same as described above. That is, in the arithmetic circuit 70, pixel values P11 and P12 for two pixels after the first and second filter processing in two cycles after initialization are output simultaneously (in parallel). Thereafter, pixel values for two pixels after the filter processing are simultaneously output every two cycles.

  The arithmetic circuit 70 of this embodiment also has an advantage that it is not necessary to read out the pixel value of the pixel of the original image that is commonly used in the calculation of adjacent pixels from the image information storage device. In the arithmetic circuit 70 of this embodiment, two product-sum calculators 76a and 76b and two product-sum registers 81a and 81b are used. As a result, the processing speed twice as high as that of the prior art is realized.

  Next, as another example of the fourth embodiment, an arithmetic circuit that performs filter processing by convolution operation using pixel values of 25 pixels of 5 columns × 5 rows of the original image will be described.

  FIG. 6 is a conceptual diagram of the fifth embodiment showing the configuration of the arithmetic circuit of the present invention. The arithmetic circuit 100 shown in the figure performs a filter process by a convolution operation from pixel values for 25 pixels of 5 columns × 5 rows of an original image arranged in a two-dimensional space. The arithmetic circuit 100 includes an original image shift register 102, a coefficient shift register 104, a pre-processing circuit 112, a post-processing circuit 114, and a counter 116.

  Hereinafter, the difference between the arithmetic circuit 100 shown in FIG. 6 and the arithmetic circuit 70 of FIG. 5 will be mainly described.

  In the arithmetic circuit 100, the original image shift register 102 and the coefficient shift register 104 have the same functions as the original image shift register 72 and the coefficient shift register 74 of the arithmetic circuit 70 in FIG.

  The pre-processing circuit 112 includes five product-sum calculators 106a, 106b, 106c, 106d, and 106e corresponding to the number of columns. The preprocessing circuit 112 also has the same function as the preprocessing circuit 82 in FIG.

  Further, the post-processing circuit 114 includes five product-sum registers 111a, 111b, 111c, 111d, and 111e corresponding to the number of columns. The post-processing circuit 114 also has the same function as the post-processing circuit 84 of the arithmetic circuit 70 in FIG.

  The counter 116 repeatedly counts 1 to 5 every cycle in synchronization with the clock signal after initialization. In the present embodiment, when the count value k = 1 of the counter 116, the coefficient value C1 (= C11, C21, C31, C41, C51) is output from the coefficient shift register 104, and all the product-sum calculators 106a, 106b, 106c, 106d, and 106e are input in common. Further, when the count value k = 2 to 5, coefficient values C2 to C5 are output, respectively.

  That is, when the count value k of the counter 116 is 1 to 5, the processing for the coefficient values C1 to C5 is performed.

  The operation of the arithmetic circuit 100 is the same as that of the arithmetic circuit 70 in FIG. In the pre-processing circuit 112, as described above, when the count value k of the counter 116 is 1 to 5, product-sum operation processing using the coefficient values C1 to C5 is performed, and product-sum operation results T1 to T5 are output. Is done. In the post-processing circuit 114, when k = 1, the product-sum operation results T1 to T5 input from the pre-processing circuit are held as they are. On the other hand, when k = 2 to 5, the integrated values of the values P1 'to P5' and T1 to T5 held in the previous cycle (that is, when k = 1 to 4 respectively) are held. Then, every five cycles, the post-processing circuit 114 outputs the pixel value P for five pixels of the image after filtering.

  Similarly, when the pixel value of each pixel of the original image shown in FIG. 8 is stored in the image information storage device and the filter processing is sequentially performed in the order shown in FIG. 13, the specific operation of the arithmetic circuit 100 is as follows. As shown in 8-10.

  That is, in the arithmetic circuit 100, pixel values P11 to P51 for five pixels after the first filter processing are output simultaneously in five cycles after initialization. Thereafter, pixel values for five pixels after the filter processing are simultaneously output every five cycles.

  The arithmetic circuit 100 of the present embodiment also has an advantage that it is not necessary to read out the pixel value of the pixel of the original image that is commonly used in the calculation of adjacent pixels from the image information storage device twice. In addition, the arithmetic circuit 100 according to the present embodiment uses five product-sum arithmetic units 106a, 106b, 106c, 106d, and 106e and five product-sum registers 111a, 111b, 111c, 111d, and 111e. 5 times the processing speed.

  The arithmetic circuits 70 and 100 of the fourth and fifth embodiments are not limited to 5 columns × 5 rows, and can be applied to filter processing by convolution operation of N columns × N rows (N is an integer of 2 or more). is there.

  In the arithmetic circuits of the fourth and fifth embodiments, generally, data in the 1st to Nth columns in the range of N columns × N rows in the two-dimensional space is held in the data register. Then, in the first cycle, the N data values held in the nth column of the data register of N columns × N rows are calculated by the nth (n = 1 to N) product-sum calculators out of N , N-column × N-row N-th coefficient of the first column is calculated, and each calculation result is held in the n-th product-sum register of the post-processing circuit. Thereafter, the data held in the data register is shifted by −1 column in order through the k-th (k = 2 to N) cycle, and the Nth column of the data register is shifted to the range of N columns × N rows in the two-dimensional space. N + k−1 columns of data adjacent in the column direction are held, and further, N pieces of data held in the nth column of the data register of N columns × N rows by the nth product-sum calculator. Is calculated and stored in the n-th product-sum register of the post-processing circuit in the previous cycle. The operation of holding the integrated value with the obtained value in the nth product-sum register of the post-processing circuit is repeated. Thereby, from each of the N product-sum registers, the first calculation target point located in the center of the range of N columns × N rows in the two-dimensional space, and the first calculation target point in the column direction of the two-dimensional space The results of the convolution calculation of the 2nd to Nth calculation target points that are adjacent to each other are output.

  Finally, a sixth embodiment of the present invention will be described.

  FIG. 7 is a conceptual diagram of the sixth embodiment showing the configuration of the arithmetic circuit of the present invention. The arithmetic circuit 120 shown in the figure also performs a filtering process by a convolution operation from pixel values for 25 pixels of 5 columns × 5 rows of the original image arranged in the two-dimensional space. 7 includes an original image shift register 122, a coefficient shift register 124, a pre-processing circuit 132, a post-processing circuit 134, and a counter 136.

  The arithmetic circuit 120 shown in FIG. 7 has a configuration in which the number of product-sum arithmetic units is reduced in the arithmetic circuit 100 shown in FIG. 6 and is used in time series (time division) like the arithmetic circuit 50 shown in FIG. belongs to. Therefore, the counter 136 has both the function of the counter 116 of the arithmetic circuit 100 shown in FIG. 6 and the function of the counter 66 of the arithmetic circuit 50 shown in FIG. That is, a count value k for controlling the processing cycle of the post-processing circuit 134 and a count value j for controlling the processing steps of the pre-processing circuit are generated. After the count value j is initialized to 0, the count of 0 to 4 is repeated in synchronization with the clock signal. After the count value k is initialized to 1, the count value j is incremented by one every time the count value j returns to 0, and the count of 1 to 5 is repeated.

  Hereinafter, the difference between the arithmetic circuit 120 in FIG. 7 and the arithmetic circuit 100 in FIG. 6 will be mainly described.

  In the arithmetic circuit 120, the original image shift register 122 and the coefficient shift register 124 have the same functions as the original image shift register 102 and the coefficient shift register 104 of the arithmetic circuit 100 in FIG.

In the arithmetic circuit 100 shown in FIG. 6, from the original image shift register 102 to the five product-sum arithmetic units 106a, 106b, 106c, 106d, and 106e of the preprocessing circuit 112, one pixel of each corresponding column. Pixel values L _{i to} L _{i + 4} are input simultaneously. On the other hand, in the arithmetic circuit 120 of FIG. 7, for each step, the pixel values L _{i + j} for five pixels in each column are sequentially transmitted to one product-sum arithmetic unit 126 in time series in accordance with the change in the count value j. Entered. The two are different in this respect. Then, after the process of 5 steps is performed in the process of the count value j changing from 0 to 4, the count value j returns to 0, and when proceeding to the next cycle, 5 of the next column to be processed is processed. Pixel values for pixels are shifted in.

  If the pixel value of one pixel is 8 bits, the arithmetic circuit 100 shown in FIG. 6 requires 8 bits × 5 × 5 = 200 wires. On the other hand, in the arithmetic circuit 120 shown in FIG. 7, since the pixel value output from the original image shift register 122 is only 5 pixels in one column, similarly, if one pixel value is 8 bits, 8 bits. X5 = Only 40 wires are required, and the number of wires can be reduced to 1/5.

Further, in the coefficient shift register 124, as in the coefficient shift register 104 in FIG. 6, the five coefficient values C1 to C5 in FIG. 6 are sequentially applied every cycle, that is, every time the count value k changes. It is shifted (rotated), and five coefficient values in the leftmost column in the figure are output. However, the supply of the same coefficient value C _k is continuously performed for a period of five steps in which the count value j changes between 0 and 4, and then the coefficient value is changed when the count value k changes and proceeds to the next cycle. 6 is different from the coefficient shift register 104 in FIG. 6 in that the shifts C1 to C5 are performed.

Subsequently, the preprocessing circuit 62 is configured by one product-sum calculator 126. The product-sum operation unit 126 performs a product-sum operation on C _k L _{i + j} and outputs the operation result T _{j + 1} .

  Further, the post-processing circuit 134 includes five product-sum registers 131a, 131b, 131c, 131d, and 131e corresponding to the number of columns. Each of the product-sum registers 131a to 131e of the post-processing circuit 134 has, for example, a configuration in which the temporary register 60a1 (or 60b1 to 60e1) of FIG. 4 is combined with the preceding stage of the product-sum register 81a (or 81b) of FIG. be able to. In this case, similarly to the arithmetic circuit 50 shown in FIG. 4, a clock signal is supplied to the temporary registers of the product-sum registers 131a to 131e during a period in which the count value j is a corresponding value. A clock signal is supplied to the flip-flop at the second stage during the period when the count value j returns to zero.

  Next, the operation of the arithmetic circuit 120 will be described.

  In the arithmetic circuit 120, in the initialization cycle, the pixel values L1 to L5 for the first to fifth columns are held in the original image shift register 122, and the coefficient values C1 to C5 for five columns are stored in the coefficient register 14. C5 is retained.

  In cycle 1, the pixel values L1 to L5 in the first to fifth columns are sequentially output from the original image shift register 122 according to the count value j = 0 to 4 of the counter 136, and the coefficient shift register 124 A numerical value C1 (that is, k = 1) is output.

In the sum-of-products calculator 126 of the pre-processing circuit 132, the pixel values L _{i + j} (= L1 to L5) in the first to fifth columns are obtained for each step in accordance with the count value j = 0 to 4 of the counter 136. The product-sum operation C1L _{i + j} is performed from the coefficient value C1, and the operation results T _{j + 1} (T1 to T5) are sequentially output. That is, the product-sum calculator 126 sequentially performs product-sum operations C1L1, C1L2, C1L3, C1L4, and C1L5 for each step according to the count value j = 0 to 4, and outputs the calculation results T1 to T5. Is done.

  Outputs T1 to T5 (= C1L1, C1L2, C1L3, C1L4, C1L5) of the product-sum operation unit 126 in steps 1 to 5 are respectively input to the product-sum registers 131a, 131b, 131c, 131d, and 131e of the post-processing circuit 134. , And held at the timing of the clock edge.

  In the next cycle 2, the pixel values L 6 for five pixels in the next column to be processed are shifted into the original image shift register 122, and the second to sixth columns are stored in the original image shift register 122. Pixel values L2 to L6 are held.

  In steps 1 to 5 in cycle 2, the pixel values L2 to L6 in the first to fifth columns are sequentially output from the original image shift register 122 according to the count value j = 0 to 4 of the counter 136, and the coefficient shift is performed. The coefficient value C2 (that is, k = 2) is output from the register 124.

Similarly, the product-sum calculator 126 calculates the product from the pixel values L _{i + j} (= L2 to L6) in the first to fifth columns and the coefficient value C2 in accordance with the count value j = 0 to 4 of the counter 136. The sum operation C2L _{i + j} is performed, and the operation results T _{j + 1} (T1 to T5) are sequentially output. That is, the product-sum calculator 132 sequentially performs the product-sum operations C2L2, C2L3, C2L4, C2L5, and C2L6 for each step according to the count value j = 0 to 4, and outputs the calculation results T1 to T5. Is done.

  Outputs T1 to T5 (= C2L2, C2L3, C2L4, C2L5, C2L6) of the product-sum calculator 126 in cycle 2 correspond to the product-sum registers 131a, 131b, 131c, 131d, and 131e respectively stored in cycle 1. P1 ′ to P5 ′ (= C1L1, C1L2, C1L3, C1L4, C1L5) to be added. The addition result is again held in the product-sum registers 131a, 131b, 131c, 131d, and 131e at the timing of the clock edge.

  That is, C1L1 + C2L2, C1L2 + C2L3, C1L3 + C2L4, C1L4 + C2L5, and C1L5 + C2L6 are held in the product-sum registers 131a, 131b, 131c, 131d, and 131e, respectively.

  As described above, the post-processing circuit 134 holds the product-sum operation result in the temporary register in the process of increasing the count value j as in the case of the arithmetic circuit 50 shown in FIGS. In the period when j returns to 0, it can be held in the flip-flop at the subsequent stage as it is, or integrated with the value held in the previous cycle. At this time, when the count value k is incremented at the timing when the count value j returns to 0, the product-sum operation result in the cycle 1 is actually held after the count value k = 2. The accumulated value of the product-sum operation result in cycle 2 and the value held in the previous cycle is held after the count value k changes to 3. Therefore, when control is performed using a selector as in the arithmetic circuit 70 shown in FIG. 5 to control whether the product-sum operation result is held as it is or after being integrated with the value held in the previous cycle, It can be controlled to select the output of the temporary register when the count value k = 2, and to select the output of the adder when the count value k is other than 2.

In the same manner, the pixel values for the next five pixels are shifted into the original image shift register 122 for each cycle, and the next coefficient value C _k is output from the coefficient shift register 124. The above operation is repeated. As a result, after initialization, the pixel value P for five pixels after the filter processing is simultaneously output every 25 cycles.

  The arithmetic circuit 120 of this embodiment also has an advantage that it is not necessary to read out the pixel value of the pixel of the original image that is commonly used in the calculation of adjacent pixels from the image information storage device. Further, in the arithmetic circuit 120, by using only one product-sum arithmetic unit 126 instead of five, the processing speed becomes 1/5 times that of the conventional one, but if the processing speed is not required, There is an advantage that the circuit scale can be reduced. Of course, like the arithmetic circuit 50 in FIG. 3, the pre-processing circuit 132 is provided with a plurality of product-sum arithmetic units, and the product-sum arithmetic results T1 to T5 using the pixel values of five columns are less than the number of columns (5). It is also possible to obtain the number of repetitions. This makes it possible to balance the processing speed and the circuit scale.

In the arithmetic circuit 120 of this embodiment, the pixel values are input to the product-sum calculator 126 in the order of L _i to L _{i + 4} , but the present invention is not limited to this, and the pixel values are input in any order. You may do it. Further, in the post-processing circuit 134, whether the product-sum operation results T1 to T4 are held as they are or whether the accumulated values of the values P1 ′ to P5 ′ held in the previous cycle and the product-sum operation results T1 to T5 are held. It is not essential to perform control using a selector. For example, even when the output of the adder is directly connected to the flip-flop constituting the product-sum register, after the output of the pixel value P after the filter processing from the flip-flop, During the period in which the product-sum operation results T1 to T5 are held in the temporary register, it is possible to initialize the flip-flop and perform the process of setting the hold values P1 to P5 to 0.

  In addition, the arithmetic circuit according to the present embodiment is not limited to 5 columns × 5 rows, and can be applied to filter processing based on N columns × N rows (N is an integer of 2 or more). In this case, the number m of product-sum calculators is 1 ≦ m <N.

  In the arithmetic circuit of this embodiment, generally, data in the 1st to Nth columns in the range of N columns × N rows in the two-dimensional space is held in the data register. In the first cycle, N data values held in any column of N columns × N rows of data registers in each of at least some of the m product-sum calculators of the preprocessing circuit, and N columns X By repeating the operation of calculating the sum of products with the N coefficients in the first column of N rows, the data values held in all the columns of the data register and the coefficients in the first column Perform product-sum operation. Then, the product-sum operation result between the data value held in the n-th column (n = 1 to N) of the data register and the coefficient in the first column, which is calculated by the product-sum calculator, is expressed as n in the preprocessing circuit. Hold in the th product-sum register. Thereafter, the data held in the data register is sequentially shifted by −1 in the column direction over the kth (k = 2 to N) cycle, and the range of N columns × N rows in the two-dimensional space is shifted to the Nth column of the data register. N + k−1 columns of data adjacent to each other in the column direction are held in at least one part of the m product-sum calculators of the pre-processing circuit, and stored in any column of N columns × N rows of data registers. By repeatedly performing the operation of calculating the sum of products between the held N data values and the N coefficients of the N columns × N rows and the kth column, the data values are held in all the columns of the data register. The product-sum operation is performed between the obtained data value and the coefficient in the k-th column. Subsequently, the product-sum operation result between the data value held in the nth column of the data register and the coefficient in the kth column calculated by the product-sum calculator and the nth product of the post-processing circuit in the previous cycle The operation of holding the integrated value with the value held in the sum register in the nth product-sum register of the post-processing circuit is repeated. Thereby, from each of the N product-sum registers, the first calculation target point located in the center of the range of N columns × N rows in the two-dimensional space, and the first calculation target in the column direction of the two-dimensional space A convolution calculation result of the 2nd to Nth calculation target points that are adjacent to the point in order is output.

  In the present invention, the data register may be configured to read data from a storage device (for example, the original image register is an image information storage device) via a buffer such as a line memory or FIFO. The preprocessing circuit may include components other than the product-sum operation unit, and the post-processing circuit may include components other than the product-sum register. Further, the specific configurations of the product-sum operation unit and the product-sum register are not limited at all, and various configurations having the same functions can be used.

The present invention is basically as described above.
Although the arithmetic circuit and the arithmetic method of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

It is the schematic of 1st Embodiment showing the structure of the arithmetic circuit of this invention. It is a conceptual diagram of 2nd Embodiment showing the structure of the arithmetic circuit of this invention. It is a conceptual diagram of 3rd Embodiment showing the structure of the arithmetic circuit of this invention. FIG. 4 is a schematic diagram illustrating a specific configuration of the arithmetic circuit illustrated in FIG. 3. It is the schematic of 4th Embodiment showing the structure of the arithmetic circuit of this invention. It is a conceptual diagram of 5th Embodiment showing the structure of the arithmetic circuit of this invention. It is a conceptual diagram of 6th Embodiment showing the structure of the arithmetic circuit of this invention. It is a conceptual diagram of an example showing the pixel value of each pixel of the original image arranged in the two-dimensional space. It is a conceptual diagram of an example showing the pixel value of each pixel of the image after the filter process of 2 columns × 2 rows. It is a conceptual diagram showing the relationship between the pixel value of each pixel of the original image shown in FIG. 8, and the pixel value of each pixel of the image after the filter process shown in FIG. In FIG. 10, it is a conceptual diagram showing the pixel value for 4 pixels of the original image of the 1st process target, and the pixel value of the pixel after a filter process. In FIG. 10, it is a conceptual diagram showing the pixel value for 4 pixels of the 2nd original image of a process target, and the pixel value of the pixel after a filter process. It is a conceptual diagram of an example showing the order of the filter process by a convolution operation. It is the schematic of an example showing the structure of the arithmetic circuit which performs the filter process by the conventional convolution operation. FIG. 15 is a conceptual diagram illustrating a state when the count value of the counter is 0 in the arithmetic circuit illustrated in FIG. 14. FIG. 15 is a conceptual diagram illustrating a state when the count value of the counter is 1 in the arithmetic circuit illustrated in FIG. 14. It is a conceptual diagram of an example showing the structure of a product-sum calculator.

Explanation of symbols

10, 30, 50, 70, 100, 120, 140 Arithmetic circuit 12, 32, 52, 102, 142 Original image register 14, 34, 54, 104 Coefficient register 22, 42, 62, 82, 112, 132 Previous Processing circuit 24, 44, 64, 84, 114, 134 Post-processing circuit 16a, 16b, 36a, 36b, 36c, 36d, 36e, 56a, 56b, 76a, 76b, 106a, 106b, 106c, 106d, 106e, 126, 146 Multiply-accumulator 21a, 21b, 41a, 41b, 41c, 41d, 41e, 61a, 61b, 61c, 61d, 61e, 81a, 81b, 111a, 111b, 111c, 111d, 111e, 131a, 131b, 131c, 131d 131e product-sum register 66, 116, 136, 156 counter 60a1, 60a2, 60b1, 60b2, 60c1, 60c2, 60d1, 60d2, 60e1, 60e2, 80a, 80b, 80c, 80d, 80e, 150a, 150b Flip-flops 58b, 58c, 58d, 58e, 78a, 78b, 78c, 78d 78e, 148, 162 Adder 72, 122 Original image shift register 74, 124, 144 Coefficient shift register 79a, 79b Selector 86 Counter 141 Image information storage device 145, 149 Multiplexer (MUX)
154 Intermediate result register 160a, 160b Multiplier

Claims (5)

An arithmetic circuit that performs a convolution operation of data arranged in a two-dimensional space,
A coefficient register for storing coefficients of N columns × N rows (N is an integer of 3 or more);
A data register holding N data values;
a pre-processing circuit including m (2 ≦ m <N) product-sum calculators;
And a post-processing circuit including 1st to Nth product-sum registers,
Initialize the 1-N-1 product-sum registers of the 1-Nth in the initialization cycle,
After that, in the order of 1 to N cycles, the data value of the 1st to Nth columns in the range of N columns × N rows of the two-dimensional space is held in the data register,
For each cycle,
In each of at least some of the m product-sum calculators of the preprocessing circuit, the product-sum between the N data values and the N coefficients of any column of the N columns × N rows. By calculating the product sum between the N data values and the coefficients of all the columns by repeating the operation of calculating N times less than N times,
A product-sum operation result between the N data values and the N coefficients in the first column calculated by the product-sum calculator is held in a first product-sum register of the post-processing circuit, and The product-sum operation result between the N data values and the coefficients of the n-th column (n = 2 to N), and the value held in the n−1th product-sum register of the post-processing circuit in the previous cycle Is held in the n-th product-sum register of the post-processing circuit,
An arithmetic circuit that outputs a convolution calculation result of a first calculation target point located in the center of the range of N columns × N rows in the two-dimensional space from the Nth product-sum register. The post-processing circuit further includes a 1-Nth temporary register provided corresponding to each of the 1-Nth product-sum registers;
After each product-sum operation result calculated by the product-sum operation unit between the data value and the coefficients in the 1st to Nth columns is held in the 1st to Nth temporary registers for each cycle. The accumulated value of the n-th product-sum operation result held in the temporary register and the value held in the (n-1) -th product-sum register in the previous cycle is held in the n-th product-sum register. The arithmetic circuit according to claim 1 , wherein: An arithmetic circuit that performs a convolution operation of data arranged in a two-dimensional space,
A coefficient register for holding coefficients of N columns × N rows (N is an integer of 2 or more);
N columns x N rows of data registers;
A preprocessing circuit having N product-sum calculators;
A post-processing circuit having N product-sum registers,
The data register holds the data of the 1st to Nth columns in the range of N columns × N rows of the two-dimensional space,
In the first cycle, the N data values held in the nth column of the data register of N columns × N rows in the nth (n = 1 to N) product-sum operation unit Calculate the sum of products with the N coefficients in the first column of the N columns × N rows, and store the respective operation results in the n th product sum register of the post-processing circuit,
Then, in order through the kth (k = 2 to N) cycle,
The data held in the data register is shifted by −1 column, and the N + k−1 column data adjacent to the N column × N row of the two-dimensional space in the column direction is shifted to the N column of the data register. Hold
In the nth product-sum operation unit, N data values held in the nth column of the N column × N row data register and N coefficients in the N column × N row k column The sum of the results of each operation and the value held in the nth product-sum register of the post-processing circuit in the previous cycle is calculated as the n-th product-sum register of the post-processing circuit. By repeating the operation to hold
From each of the N product-sum registers, a first calculation target point located in the center of a range of N columns × N rows of the two-dimensional space, and the first calculation target in the column direction of the two-dimensional space An arithmetic circuit which outputs a convolution operation result of the 2nd to Nth operation target points adjacent to each other in order. An arithmetic method for performing a convolution operation between data arranged in a two-dimensional space and coefficients of N columns × N rows (N is an integer of 2 or more),
A preprocessing circuit having N product-sum calculators;
Prepare a post-processing circuit with N product-sum registers,
In the first cycle, a data value in a range of N columns × N rows of the two-dimensional space and N coefficients of the first column of N columns × N rows are supplied to the preprocessing circuit, and the N pieces The product-sum calculator between the N data values in the n-th column of the two-dimensional space and the N coefficients is calculated by an nth (n = 1 to N) product-sum calculator The operation result is held in the nth product-sum register of the post-processing circuit,
Then, in order through the kth (k = 2 to N) cycle,
The data values from the Nth column × Nth row kth column to the N + k−1th column adjacent to the Nth column × Nth row in the column direction, and the Nth column × Nth row N coefficients in the k-th column are supplied to the pre-processing circuit, and the N-th product-sum calculator calculates the N data values in the (N + k−1) -th column in the two-dimensional space and the N The sum of products between the coefficients is calculated, and an integrated value of each operation result and the value held in the nth product-sum register of the post-processing circuit in the previous cycle is calculated as n of the post-processing circuit. By repeating the operation held in the th product-sum register,
From each of the N product-sum registers, a first calculation target point located in the center of a range of N columns × N rows of the two-dimensional space, and the first calculation target in the column direction of the two-dimensional space A calculation method that outputs a convolution calculation result of the 2nd to Nth calculation target points that are adjacent to each other in order. An arithmetic circuit that performs a convolution operation of data arranged in a two-dimensional space,
A coefficient register for holding coefficients of N columns × N rows (N is an integer of 2 or more);
N columns x N rows of data registers;
a pre-processing circuit including m (m <N) product-sum calculators;
A post-processing circuit having N product-sum registers,
The data register holds data in the 1st to Nth columns in the range of N columns × N rows in the two-dimensional space,
In the first cycle,
In each of at least some of the m product-sum calculators of the preprocessing circuit, N data values held in any column of the N columns × N rows of data registers, and the N columns × N By repeating the operation of calculating the product sum between the N coefficients in the first column of the row, the data values held in all the columns of the data register and the coefficients in the first column are The sum of products of
The pre-processing circuit calculates the product-sum operation result between the data value held in the n-th column (n = 1 to N) of the data register and the coefficient in the first column, which is calculated by the product-sum calculator. In the nth sum of products register
Then, in order through the kth (k = 2 to N) cycle,
The data held in the data register is shifted by −1 in the column direction, and the N + k−1th column adjacent to the N column × N row in the two-dimensional space in the column direction is shifted to the Nth column of the data register. Keep the data,
In each of at least some of the m product-sum calculators of the preprocessing circuit, N data values held in any column of the N columns × N rows of data registers, and the N columns × N By repeatedly performing the operation of calculating the sum of products between the N coefficients in the k-th column of the row, the data values held in all the columns of the data register and the coefficients in the k-th column are calculated. Perform product-sum operation between
The product-sum operation result between the data value held in the n-th column of the data register and the coefficient in the k-th column, calculated by the product-sum calculator, and the nth of the post-processing circuit in the previous cycle By repeating the operation of holding the integrated value with the value held in the product-sum register in the nth product-sum register of the post-processing circuit,
From each of the N product-sum registers, a first calculation target point located at the center of a range of N columns × N rows of the two-dimensional space, and the first calculation in the column direction of the two-dimensional space An arithmetic circuit which outputs a convolution calculation result of the 2nd to Nth calculation target points adjacent to the target point in order.

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