JP5493646B2 - Discrete Fourier transform apparatus and discrete Fourier transform / discrete inverse Fourier transform method - Google Patents

Description

  The present invention relates to a discrete Fourier transform apparatus and a discrete Fourier transform method, and more particularly to a discrete Fourier transform apparatus and a discrete Fourier transform method capable of executing discrete Fourier transform (DFT) with different points (point numbers).

  There is known a wireless communication signal processing device that performs modulation / demodulation processing including processing for converting a frequency domain signal into a time domain signal and processing for converting a time domain signal into a frequency domain signal. As an example of the modulation / demodulation processing, there is processing for performing discrete Fourier transform (DFT) and discrete inverse Fourier transform (IDFT) used in LTE (Long Term Evolution).

  In general, DFT is expressed by the following equation.

Here, X is an input, Y is an output, and N is a DFT score. Also,

It is.

  As a technique for executing DFT at high speed, there is a Winograd method in which a DFT with a certain score is processed as a combination of DFT processing with a score less than that score.

  FIG. 49 is a diagram showing a technique of processing a 15-point DFT by dividing it into 3-point and 5-point DFT using the Winograd method.

  According to the Winograd method, the 15-point DFT is derived from the 3-stage DFT pre-stage computation unit, the 5-point DFT pre-stage computation section, the multiplication stage, the 5-point DFT post-stage computation section, and the 3-point DFT post-stage computation section. Can be configured.

  First, the pre-stage calculation unit of the three-point DFT performs an addition process between the input data on the input data indicated by X (k).

  Next, the 3-stage DFT pre-stage calculation unit outputs the addition processing result to the 5-point DFT pre-stage calculation section, and the 5-point DFT pre-stage calculation section adds the addition process results from the 3-point DFT pre-stage calculation section. Process.

  Next, the 5-stage DFT pre-stage calculation unit sends the addition process result to the multiplication stage, and the multiplication stage calculates the addition process result from the 5-point DFT pre-stage calculation unit and the multiplication coefficient prepared in advance. Perform multiplication.

  Next, the multiplication stage sends the multiplication result to the subsequent stage calculation unit of the 5-point DFT, and the subsequent stage calculation unit of the 5-point DFT performs an addition process between the input data.

  Finally, the post-processing unit of the 5-point DFT sends the addition processing result to the post-processing unit of the 3-point DFT, and the post-processing unit of the 3-point DFT performs an addition process on the input data and outputs the result. .

  Several methods and architectures that modify the Winograd method have been proposed.

  Patent Document 1 proposes an architecture for efficiently processing a DFT used in a digital channelizer. In the method disclosed in Patent Document 1, the number of adders in the post-stage operation unit is reduced by reducing the number of DFT circuits that calculate unnecessary DFT output in the processing after DFT.

  In Patent Document 2, L FFT circuits having a specific number of points k are arranged in parallel, and k, 2 * k,. . , A variable-size discrete Fourier transform processing device capable of performing any FFT of L * k points is described.

JP 2000-252934 A JP 2000-123000 A

  The DFT processing method disclosed in Patent Document 1 is not versatile with respect to the number of points, and in order to support Fourier transformation of a plurality of types of points, a DFT circuit must be individually designed for each number of points. I must. For this reason, there is a problem that the number of adders and multipliers constituting the DFT circuit increases as the number of points increases, and the circuit scale increases. In addition, since the circuit must be individually designed for each DFT score, it takes time to design.

  The size-variable discrete Fourier transform processing device disclosed in Patent Document 2 uses L FFT circuits with k points, thereby supporting Fourier transformation with L types of points. For this reason, there is a problem that the number of adders and multipliers constituting the DFT circuit increases as the number of points increases, and the circuit scale increases.

  In other words, the techniques disclosed in Patent Documents 1 and 2 have a problem that the number of adders and multipliers constituting the DFT circuit increases as the number of points increases, resulting in an increase in circuit scale. .

  An object of the present invention is to provide a discrete Fourier transform apparatus and a discrete Fourier transform method capable of solving the above problems.

The discrete Fourier transform device of the present invention includes one of a plurality of types of points , a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, a plurality of data, A discrete Fourier transform device that executes discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal for the plurality of data,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform . Adding means;
Multiplication means for executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
Second addition means for performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing later than the second timing,
The first addition means outputs the result of the previous addition process to the multiplication means at the second timing regardless of the number of points indicated by the control signal,
The multiplication means performs the multiplication process on the result of the previous stage addition process, and the result of the multiplication process is determined at the third timing regardless of the number of points indicated by the control signal. Output to the adding means,
The second addition means performs the post-stage addition process on the result of the multiplication process, and outputs the result of the post-stage addition process as a result of executing the process on the plurality of data ,
The first adding means includes
When the plurality of data is received at the first timing, according to the control signal, the plurality of data is selectively added to each other, or first calculation means for outputting the plurality of data as they are;
Rearrangement means for selectively rearranging data input at a fourth timing later than the first timing and earlier than the second timing according to the control signal, or outputting the data as it is;
Data input at a fifth timing that is later than the fourth timing and earlier than the second timing, in accordance with the control signal, or a second calculation means that outputs the data as it is,
And third arithmetic means for selectively adding data input at a sixth timing later than the fifth timing and earlier than the second timing according to the control signal, or outputting the data as it is,
The first calculation means outputs its own output to the sorting means at the fourth timing regardless of the number of points indicated by the control signal,
The rearranging means outputs its own output to the second arithmetic means at the fifth timing regardless of the number of points indicated by the control signal,
The second calculation means outputs its own output to the third calculation means at the sixth timing regardless of the number of points indicated by the control signal,
The third calculation means outputs its own output to the multiplication means at the second timing regardless of the number of points indicated by the control signal. Also,
The discrete Fourier transform device of the present invention includes one of a plurality of types of points, a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, and a plurality of data. A discrete Fourier transform device that performs discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal for the plurality of data,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform. Adding means;
Multiplication means for executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
Second addition means for performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing later than the second timing,
The first addition means outputs the result of the previous addition process to the multiplication means at the second timing regardless of the number of points indicated by the control signal,
The multiplication means performs the multiplication process on the result of the previous stage addition process, and the result of the multiplication process is determined at the third timing regardless of the number of points indicated by the control signal. Output to the adding means,
The second addition means performs the post-stage addition process on the result of the multiplication process, and outputs the result of the post-stage addition process as a result of executing the process on the plurality of data,
The multiplication means is
Storage means for storing the multiplication coefficient for discrete Fourier transform corresponding to the number of points and the multiplication coefficient for discrete inverse Fourier transform corresponding to the number of points for each number of points;
Reading means for reading out the multiplication coefficient corresponding to the number of points and processing indicated by the control signal from the storage means;
First multiplication means for multiplying the output of the first addition means by the multiplication coefficient read by the reading means;
Second multiplication means for selectively multiplying the multiplication result of the first multiplication means by a pure imaginary number in accordance with the control signal. Also,
The discrete Fourier transform device of the present invention includes one of a plurality of types of points, a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, and a plurality of data. A discrete Fourier transform device that performs discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal for the plurality of data,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform. Adding means;
Multiplication means for executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
Second addition means for performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing later than the second timing,
The first addition means outputs the result of the previous addition process to the multiplication means at the second timing regardless of the number of points indicated by the control signal,
The multiplication means performs the multiplication process on the result of the previous stage addition process, and the result of the multiplication process is determined at the third timing regardless of the number of points indicated by the control signal. Output to the adding means,
The second addition means performs the post-stage addition process on the result of the multiplication process, and outputs the result of the post-stage addition process as a result of executing the process on the plurality of data,
The second adding means includes
When receiving the output of the multiplication means at the third timing, according to the control signal, selectively add the outputs of the multiplication means, or a fourth calculation means for outputting the output of the multiplication means as it is,
The data input at the seventh timing later than the third timing is selectively added according to the control signal, output as it is, or the addition result selectively added is selectively multiplied by a pure imaginary number. A fifth computing means;
Data rearranging means for selectively rearranging data inputted at an eighth timing later than the seventh timing according to the control signal, or outputting the data as it is,
Sixth arithmetic means for selectively adding the data input at the ninth timing later than the eighth timing according to the control signal, or outputting the data as it is,
The fourth calculation means outputs its own output to the fifth calculation means at the seventh timing regardless of the number of points indicated by the control signal,
The fifth computing means outputs its own output to the data rearranging means at the eighth timing regardless of the number of points indicated by the control signal,
The data rearranging means outputs its own output to the sixth arithmetic means at the ninth timing regardless of the number of points indicated by the control signal,
The sixth arithmetic means outputs its own output as a result of executing the processing of the number of points indicated by the control signal for the plurality of data.

The discrete Fourier transform / discrete inverse Fourier transform method of the present invention includes a control signal indicating one of a plurality of types of points and whether the process is a discrete Fourier transform or a discrete inverse Fourier transform . a plurality of data, the reception, the on multiple data, discrete Fourier transform and discrete inverse of the discrete Fourier transform unit for performing a discrete Fourier transform or inverse discrete Fourier transform of the number of points indicated by the control signal A Fourier transform method,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform . Adding step;
A multiplication step of executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
A second addition step of performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing that is later than the second timing,
In the first addition step, the result of the previous stage addition process is output at the second timing regardless of the number of points indicated by the control signal,
In the multiplication step, the result of the previous stage addition process is received at the second timing, the multiplication process is performed on the result of the previous stage addition process, and the result of the multiplication process is indicated by the control signal Regardless of the number of points, output at the third timing,
In the second addition step, the result of the multiplication process is received at the third timing, the post-stage addition process is performed on the result of the multiplication process, and the result of the post-stage addition process is applied to the plurality of data. Output as a result of executing the process ,
The first adding step includes
When receiving the plurality of data at the first timing, according to the control signal, selectively adding the plurality of data, or outputting the plurality of data as they are,
Rearrangement step of selectively rearranging data input at a fourth timing later than the first timing and earlier than the second timing according to the control signal, or outputting the data as it is;
A second calculation step of selectively adding data input at a fifth timing later than the fourth timing and earlier than the second timing according to the control signal, or outputting the data as it is;
A third operation step of selectively adding data inputted at a sixth timing later than the fifth timing and earlier than the second timing according to the control signal, or outputting the data as it is,
In the first calculation step, regardless of the number of points indicated by the control signal, the output of its own is output at the fourth timing,
In the rearrangement step, the output in the first calculation step is received at the fourth timing, and regardless of the number of points indicated by the control signal, the output of the self is output at the fifth timing,
In the second calculation step, the output in the rearrangement step is received at the fifth timing, and regardless of the number of points indicated by the control signal, its own output is output at the sixth timing,
The third calculation step accepts the output in the second calculation step at the sixth timing, and outputs its own output at the second timing regardless of the number of points indicated by the control signal,
In the multiplication step, the output in the third calculation step is received at the second timing as a result of the previous stage addition process, and the multiplication process is executed on the result of the previous stage addition process . Also,
The discrete Fourier transform / discrete inverse Fourier transform method of the present invention includes a control signal indicating one of a plurality of types of points, whether the processing is discrete Fourier transform or discrete inverse Fourier transform, and a plurality of points Discrete Fourier transform / discrete inverse Fourier in a discrete Fourier transform device that receives discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal for the plurality of data. A conversion method,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform. Adding step;
A multiplication step of executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
A second addition step of performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing that is later than the second timing,
In the first addition step, the result of the previous stage addition process is output at the second timing regardless of the number of points indicated by the control signal,
In the multiplication step, the result of the previous stage addition process is received at the second timing, the multiplication process is performed on the result of the previous stage addition process, and the result of the multiplication process is indicated by the control signal Regardless of the number of points, output at the third timing,
In the second addition step, the result of the multiplication process is received at the third timing, the post-stage addition process is performed on the result of the multiplication process, and the result of the post-stage addition process is applied to the plurality of data. Output as a result of executing the process,
The multiplication step includes
For each point number, a storage step of storing in the storage means the multiplication coefficient for discrete Fourier transform corresponding to the number of points and the multiplication coefficient for discrete inverse Fourier transform corresponding to the number of points;
A reading step of reading out the multiplication coefficient corresponding to the number of points and processing indicated by the control signal from the storage means;
A first multiplication step of multiplying the output in the first addition step by the read multiplication coefficient;
A second multiplication step of selectively multiplying a result of the multiplication by a pure imaginary number in accordance with the control signal. Also,
The discrete Fourier transform / discrete inverse Fourier transform method of the present invention includes a control signal indicating one of a plurality of types of points, whether the processing is discrete Fourier transform or discrete inverse Fourier transform, and a plurality of points Discrete Fourier transform / discrete inverse Fourier in a discrete Fourier transform device that receives discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal for the plurality of data. A conversion method,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform. Adding step;
A multiplication step of executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
A second addition step of performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing that is later than the second timing,
In the first addition step, the result of the previous stage addition process is output at the second timing regardless of the number of points indicated by the control signal,
In the multiplication step, the result of the previous stage addition process is received at the second timing, the multiplication process is performed on the result of the previous stage addition process, and the result of the multiplication process is indicated by the control signal Regardless of the number of points, output at the third timing,
In the second addition step, the result of the multiplication process is received at the third timing, the post-stage addition process is performed on the result of the multiplication process, and the result of the post-stage addition process is applied to the plurality of data. Output as a result of executing the process,
The second adding step includes
When the output at the multiplication step is received at the third timing, the outputs are selectively added according to the control signal, or a fourth calculation step for outputting the output as it is,
The data input at the seventh timing later than the third timing is selectively added according to the control signal, output as it is, or the addition result selectively added is selectively multiplied by a pure imaginary number. A fifth operation step;
A data rearrangement step of selectively rearranging data input at an eighth timing later than the seventh timing according to the control signal, or outputting the data as it is,
A sixth operation step of selectively adding data inputted at a ninth timing later than the eighth timing according to the control signal, or outputting the data as it is,
In the fourth calculation step, regardless of the number of points indicated by the control signal, the self output is output at the seventh timing,
In the fifth calculation step, the output in the fourth calculation step is accepted at the seventh timing, and regardless of the number of points indicated by the control signal, its own output is output at the eighth timing,
In the data rearrangement step, the output in the fifth calculation step is accepted at the eighth timing, and regardless of the number of points indicated by the control signal, its own output is output at the ninth timing,
In the sixth operation step, the output in the data rearrangement step is received at the ninth timing, and the output of itself is output as a result of executing the processing on the plurality of data.

  According to the present invention, it is possible to prevent the number of adders and multipliers from increasing as the number of points in the discrete Fourier transform increases.

2 is a diagram illustrating a configuration of a discrete Fourier transform apparatus 200. FIG. FIG. 4 is a diagram showing a configuration of a first-stage first addition unit 204. It is a figure which shows the structure of the front | former stage transposition unit 205. FIG. FIG. 4 is a diagram showing a configuration of a front-stage second addition unit 206. FIG. 6 is a diagram showing a configuration of a pre-stage third addition unit 207. FIG. 3 is a diagram illustrating a configuration of a multiplication unit 202. FIG. 4 is a diagram showing a configuration of a rear first addition unit 210. It is a figure which shows the structure of the back | latter stage 2nd addition unit 211. FIG. It is a figure which shows the structure of the back | latter stage transposition unit 212. FIG. It is a figure which shows the structure of the back | latter stage 3rd addition unit 213. FIG. It is a figure which shows the data flow of 3 point | piece DFT / IDFT. It is a figure which shows the data flow of 5-point DFT / IDFT. It is a figure which shows the data flow of 9 point | piece DFT / IDFT. It is a figure which shows the data flow of 15 points | pieces DFT / IDFT. It is a figure which shows the content of the control signal C_sig. It is a figure which shows the correspondence of a score signal and a DFT / IDFT score, and the correspondence of a DFT / IDFT selection signal, DFT, and IDFT. It is a figure which shows the content of the offset table 702. FIG. 4 is a diagram illustrating the contents of a DFT multiplication coefficient memory 704 and an IDFT multiplication coefficient memory 705. It is a figure which shows the input-output format to the discrete Fourier transform apparatus 200 of 3, 5, 9, 15-point DFT / IDFT. It is a time chart which shows the processing content in the front | former stage 1st addition unit 204 of 3 point | piece DFT / IDFT. It is a time chart which shows the processing content in the upstream transposition unit 205 of 3 point DFT / IDFT. It is a time chart which shows the processing content in the front | former stage 2nd addition unit 206 of 3 point | piece DFT / IDFT. It is a time chart which shows the processing content in the front | former stage 3rd addition unit 207 of 3 point | piece DFT / IDFT. It is a time chart which shows the processing content in the multiplication unit 202 of 3 point | piece DFT / IDFT. It is a time chart which shows the processing content in the latter 1st addition unit 210 of 3 point | piece DFT / IDFT. It is a time chart which shows the processing content in the back | latter stage 2nd addition unit 211 of 3 point | piece DFT / IDFT. It is a time chart which shows the processing content in the rear stage transposition unit 212 of 3 point DFT / IDFT. It is a time chart which shows the processing content in the latter stage 3rd addition unit 213 of 3 point | piece DFT / IDFT. It is a time chart which shows the processing content in the front | former stage 1st addition unit 204 of 5-point DFT / IDFT. It is a time chart which shows the processing content in the upstream transposition unit 205 of 5-point DFT / IDFT. It is a time chart which shows the processing content in the front | former stage 2nd addition unit 206 of 5-point DFT / IDFT. It is a time chart which shows the processing content in the front stage 3rd addition unit 207 of 5-point DFT / IDFT. It is a time chart which shows the processing content in the multiplication unit 202 of 5 point | piece DFT / IDFT. It is a time chart which shows the processing content in the latter 1st addition unit 210 of 5 point | piece DFT / IDFT. It is a time chart which shows the processing content in the latter stage 2nd addition unit 211 of 5-point DFT / IDFT. It is a time chart which shows the processing content in the rear stage transposition unit 212 of 5-point DFT / IDFT. It is a time chart which shows the processing content in the back | latter stage 3rd addition unit 213 of 5-point DFT / IDFT. It is a time chart which shows the processing content in the pre-stage 1st addition unit 204 of 9 points | pieces DFT / IDFT. It is a time chart which shows the processing content in the upstream transposition unit 205 of 9 points | piece DFT / IDFT. It is a time chart which shows the processing content in the front | former stage 2nd addition unit 206 of 9 points | piece DFT / IDFT. It is a time chart which shows the processing content in the pre-stage 3rd addition unit 207 of 9 points | piece DFT / IDFT. It is a time chart which shows the processing content in the multiplication unit 202 of 9 points | pieces DFT / IDFT. It is a time chart which shows the processing content in the latter 1st addition unit 210 of 9 points | pieces DFT / IDFT. It is a time chart which shows the processing content in the latter stage 2nd addition unit 211 of 9 points | pieces DFT / IDFT. It is a time chart which shows the processing content in the rear stage transposition unit 212 of 9 point DFT / IDFT. It is a time chart which shows the processing content in the latter stage 3rd addition unit 213 of 9 point | piece DFT / IDFT. It is a time chart which shows the processing content in the multiplication unit 202 of 15 points | pieces DFT / IDFT. It is a figure which shows the structure of 2nd embodiment of this invention. It is a figure which shows the processing method of 15 point | piece DFT using the method of Winograd.

  Next, a discrete Fourier transform apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a discrete Fourier transform apparatus (hereinafter also referred to as “arithmetic apparatus”) 200 according to the first embodiment of the present invention.

  In FIG. 1, the arithmetic device 200 includes a pre-addition unit 201, a multiplication unit 202, and a post-addition unit 203.

  The pre-addition unit 201 includes a pre-stage first addition unit 204, a pre-stage transposition unit 205, a pre-stage second addition unit 206, and a pre-stage third addition unit 207. The multiplication unit 202 includes a multiplier 208 and a control unit 209. The post-addition unit 203 includes a post-stage first addition unit 210, a post-stage second addition unit 211, a post-stage transposition unit 212, and a post-stage third addition unit 213.

  When the arithmetic device 200 receives a control signal indicating one of a plurality of types of points and a plurality of data, the arithmetic device 200 performs a discrete Fourier having the number of points indicated by the control signal with respect to the plurality of data. Perform conversion (DFT).

  In this embodiment, the number of points of a plurality of types is configured by 3, 5, 9, and 15 points. Each of the plurality of data is complex number data subjected to DFT.

  When receiving the control signal and the plurality of data, the arithmetic device 200 first performs a pre-stage addition process corresponding to the DFT having the number of points indicated by the control signal on the complex number data to generate a pre-stage addition process result. .

  Subsequently, the arithmetic device 200 performs a multiplication process corresponding to the DFT of the number of points indicated by the control signal on the previous stage addition process result, and generates a multiplication process result.

  Subsequently, the arithmetic device 200 performs post-stage addition processing according to the DFT having the number of points indicated by the control signal on the result of the multiplication processing, and outputs the result of the DFT having the number of points indicated by the control signal. To do.

  The pre-stage addition process is an addition process to be performed before the multiplication process, and the post-stage addition process is an addition process to be performed after the multiplication process.

It is known that the DFT processing is divided into the pre-stage addition process, the multiplication process, and the post-stage addition process by, for example, the Winograd method (see FIG. 49).
Pre-addition unit 201 can be generally referred to as first addition means.

  When a plurality of data is input at the first timing, the pre-addition unit 201 performs a pre-stage addition process corresponding to the discrete Fourier transform of the number of points indicated by the control signal on the plurality of data.

  Multiplication unit 202 can be generally referred to as multiplication means.

  The multiplication unit 202 performs a multiplication process corresponding to the discrete Fourier transform of the number of points indicated by the control signal on the data input at the second timing that is later than the first timing.

  Post addition unit 203 can be generally referred to as second addition means.

  The post-addition unit 203 performs post-stage addition processing corresponding to the discrete Fourier transform of the number of points indicated by the control signal on the data input at the third timing later than the second timing.

  The pre-addition unit 201 outputs the result of the pre-stage addition process to the multiplication unit 202 at the second timing regardless of the number of points indicated by the control signal.

  In addition, the multiplication unit 202 performs a multiplication process on the result of the previous stage addition process, and outputs the result of the multiplication process at the third timing regardless of the number of points indicated by the control signal. Output to.

  Further, the post-addition unit 203 performs post-stage addition processing on the result of the multiplication processing, and executes the discrete Fourier transform of the number of points indicated by the control signal on the plurality of data for the result of the post-stage addition processing Is output as a result.

  The first-stage first addition unit 204 can be generally referred to as first calculation means.

  When receiving the plurality of data at the first timing, the first-stage first addition unit 204 selectively adds the plurality of data to each other according to the control signal (addition process) or outputs the plurality of data as they are.

  The upstream transposition unit 205 can be generally referred to as rearrangement means.

  The upstream transposition unit 205 selectively rearranges the data input at the fourth timing later than the first timing and earlier than the second timing according to the control signal (transposition processing) or outputs the data as it is (through processing). To do.

  The pre-stage second addition unit 206 can be generally referred to as second calculation means.

  The pre-stage second addition unit 206 selectively adds the data input at the fifth timing later than the fourth timing and earlier than the second timing according to the control signal (addition processing) or outputs the data as it is.

  The pre-stage third addition unit 207 can be generally referred to as third calculation means.

  The pre-stage third addition unit 207 selectively adds the data input at the sixth timing later than the fifth timing and earlier than the second timing according to the control signal (addition processing) or outputs the data as it is.

  The first-stage first addition unit 204 outputs its own output to the first-stage transposition unit 205 at the fourth timing regardless of the number of points indicated by the control signal.

  The upstream transposition unit 205 outputs its output to the upstream second addition unit 206 at the fifth timing regardless of the number of points indicated by the control signal.

  The upstream second addition unit 206 outputs its own output to the upstream third addition unit 207 at the sixth timing regardless of the number of points indicated by the control signal.

  The pre-stage third addition unit 207 outputs its output to the multiplication unit 202 at the second timing regardless of the number of points indicated by the control signal.

  The multiplier 208 reads the multiplication coefficient from the control unit 209 and performs a multiplication process of multiplying the multiplication coefficient by the output of the pre-stage third addition unit 207.

  For each point number, the control unit 209 generates a memory (storage means) that stores a complex multiplication coefficient corresponding to the number of points, and an address for reading out the multiplication coefficient corresponding to the number of points indicated by the control signal from the memory. An address generation unit (reading means).

  The post-stage first addition unit 210 can be generally referred to as fourth arithmetic means.

  When the post-stage first addition unit 210 receives the output of the multiplication unit 202 at the third timing, the output of the multiplication unit 202 is selectively added according to the control signal (addition process), or the output of the multiplication unit 202 is output. Output as is.

  The post-secondary addition unit 211 can be generally referred to as fifth arithmetic means.

  The post-stage second addition unit 211 selectively adds the data input at the seventh timing later than the third timing according to the control signal (addition processing), outputs the data as it is, or the addition that is selectively added. The result is selectively multiplied by a pure imaginary number.

  The rear transposition unit 212 can be generally referred to as data rearranging means.

  The rear transposition unit 212 selectively rearranges the data input at the eighth timing later than the seventh timing (transposition processing) or outputs the data as it is (through processing).

  The post-stage third addition unit 213 can be generally referred to as sixth arithmetic means.

  The post-stage third addition unit 213 selectively adds the data input at the ninth timing later than the eighth timing according to the control signal (addition processing) or outputs the data as it is.

  The rear stage first addition unit 210 outputs its output to the rear stage second addition unit 211 at the seventh timing regardless of the number of points indicated by the control signal.

  The rear stage second addition unit 211 outputs its own output to the rear stage transposition unit 212 at the eighth timing regardless of the number of points indicated by the control signal.

  The rear transposition unit 212 outputs its own output to the rear third addition unit 213 at the ninth timing regardless of the number of points indicated by the control signal.

  The post-stage third addition unit 213 outputs its output as a result of executing the discrete Fourier transform of the number of points indicated by the control signal with respect to a plurality of data.

  FIG. 2 is a block diagram showing the first stage first addition unit 204.

  In FIG. 2, the first stage first addition unit 204 includes a delay circuit D, crossbars (Xbar) 31 and 37, adders 32, 33, 35 and 36, and a selector (Sel) 34.

  The pre-stage first addition unit 204 takes in the input control signal C_sig and outputs the control signal C_sig as C_out.

  The delay circuit D delays the complex number data in3 input to the arithmetic unit 200 by one clock.

  The crossbar 31 outputs each of the output regr from the delay circuit D and the complex data in1, in2, and in3 as one of sel1, sel2, sel3, sel4, sel6, sel7, and sel8 according to the control signal C_sig.

  The adder 32 performs an addition process for adding sel3 and sel4.

  The adder 33 performs an addition process of adding sel3 and sel4 with the sign inverted.

  The selector 34 selects and outputs either sel2 or the output add_o_3 of the adder 32 according to the control signal C_sig.

  The adder 35 performs an addition process of adding sel1 and the output sel5 of the selector 34.

  The adder 36 performs an addition process of adding sel1 and sel5 with the sign inverted.

  An output add_o_1 from the adder 35, an output add_o_2 from the adder 36, an output add_o_3 from the adder 32, an output add_o_4 from the adder 33, sel6, sel7, and sel8 can be input to the crossbar 37.

  The crossbar 37 outputs each of the input signals as out1, out2, out3, and out4 according to the control signal C_sig.

  FIG. 3 is a block diagram showing the upstream transposition unit 205.

  In FIG. 3, complex number data in1 is out1 from the first stage first addition unit 204, complex number data in2 is out2 from the first stage first addition unit 204, and complex number data in3 is sent from the first stage first addition unit 204. The complex number data in4 is out4 from the first-stage first addition unit 204, and the control signal C_sig is C_out from the first-stage first addition unit 204.

  In FIG. 3, the former transposition unit 205 includes a plurality of delay circuits D and crossbars (Xbar) 41, 42 and 43. Each delay circuit D in FIG. 3 delays input data by one clock.

  The pre-transposition unit 205 treats the input complex number data in1, in2, in3 and in4 and the input control signal C_sig as a pair. That is, the control signal C_sig is added to each complex number data input to the crossbar or the like in the preceding transposition unit 205.

  The upstream transposition unit 205 performs a process of pairing the control signal and the complex number data when the control signal and the complex number data are input. Hereinafter, this process is referred to as “integration”.

  The crossbar 41 outputs each of the complex number data in1 to in4 as one of Sel_1_1 to Sel_1_7 according to the control signal C_sig integrated with the respective complex number data.

  The crossbar 42 outputs the outputs D_Sel_1_1 to D_Sel_1_4 from the delay circuit D as one of Sel_2_1 to Sel_2_4 according to the control signal C_sig integrated with each data.

  The crossbar 43 outputs each signal from D_dt_1 to D_dt_11 as one of Sel_3_1 to Sel_3_4 according to the control signal integrated therein.

  Each signal of Sel_3_1 to Sel_3_4 is separated into a control signal and complex data. Of the separated signals, only complex data is output as outputs out1, out2, out3, and out4 from this unit. On the other hand, the control signal is input to the ground indicated by GND in FIG. 3 and is not used thereafter. The control signal C_sig is delayed by 10 clocks and output as C_out.

  FIG. 4 is a block diagram showing the pre-stage second addition unit 206.

  In FIG. 4, the complex number data in1 is out1 from the preceding transposition unit 205, the complex data in2 is out2 from the previous transposing unit 205, the complex data in3 is out3 from the preceding transposing unit 205, and is a complex number. Data in4 is out4 from the preceding transposition unit 205, and the control signal C_sig is C_out from the previous transposing unit 205.

  In FIG. 4, the front stage second addition unit 206 includes a plurality of delay circuits D, a crossbar (Xbar) & sign inverter 51, and adders 52, 53, 54 and 55.

  The crossbar (Xbar) & sign inverter 51 inverts the signs of the inputs in1 to in4 and the outputs regr1 to regr5 of the delay circuit D according to the control signal C_sig, and outputs each of them as one of sel1 to sel9 .

  The adder 52 performs an addition process of adding sel1, sel2, and sel3. The adder 53 performs an addition process of adding sel4 and sel5. The adder 54 performs an addition process of adding sel6 and sel7. The adder 55 performs an addition process of adding sel8 and sel9.

  The outputs of these adders are output from this unit as out1, out2, out3, and out4, respectively.

  Further, the control signal C_sig is delayed by one clock and output as C_out.

  FIG. 5 is a block diagram showing the pre-stage third addition unit 207.

  In FIG. 5, the complex number data in1 is out1 from the previous stage second addition unit 206, the complex number data in2 is out2 from the previous stage second addition unit 206, and the complex number data in3 is from the previous stage second addition unit 206. The complex number data in4 is out4 from the previous stage second addition unit 206, and the control signal C_sig is C_out from the previous stage second addition unit 206.

  The front third adder unit 207 includes a plurality of delay circuits D, a crossbar (Xbar) & sign inverter 61, and adders 62, 63, 64 and 65.

  The crossbar (Xbar) & sign inverter 61 inverts the signs of the inputs in1 to in4 and the outputs regr1 to regr4 of the delay circuit D according to the control signal C_sig, and outputs each of them as one of sel1 to sel10 .

  The adder 62 performs an addition process for adding sel1, sel2, and sel3. The adder 63 performs an addition process of adding sel4 and sel5. The adder 64 performs an addition process of adding sel6, sel7, and sel8. The adder 65 performs an addition process for adding sel9 and sel10.

  The outputs of these adders are output as out1, out2, out3, and out4, respectively.

  The control signal C_sig is output as C_out.

  FIG. 6 is a block diagram showing the control unit 209 and the multiplier 208.

  In FIG. 6, the complex number data in1 is out1 from the preceding stage third addition unit 207, the complex number data in2 is out2 from the preceding stage third addition unit 207, and the complex number data in3 is sent from the preceding stage third addition unit 207. The complex number data in4 is out4 from the preceding stage third addition unit 207, and the control signal C_sig is C_out from the preceding stage third addition unit 207.

  In FIG. 6, the control unit 209 includes an offset table 702 that stores an offset to be added to a clock number signal described later, multiplication coefficient memories 704 and 705, an adder 703, and a selector 706.

  The multiplier 208 includes a crossbar (Xbar) 701, parallel multipliers 707, 708, 709, and 710 that multiply the real part and the imaginary part of the input signal and the multiplication coefficient, respectively, and a pure imaginary multiplier 711 that multiplies the pure imaginary number. , 712, 713, and 714, and selectors 715, 716, 717, and 718.

  In the control unit 209, when the control signal C_sig is input, an offset is output from the offset table 702 according to C_sig. The adder 703 adds the offset and the clock number signal. According to the addition result, the multiplication coefficient is output from each of the multiplication coefficient memories 704 and 705. The selector 706 outputs either a multiplication coefficient from the multiplication coefficient memory 704 or a multiplication coefficient from the multiplication coefficient memory 705 as mult_cf1 to mult_cf4 in accordance with a DFT / IDFT selection signal described later.

  Details of the clock number signal, the DFT / IDFT selection signal, the configuration of the memory and table, and the access method thereof will be described later.

  In multiplier 208, crossbar (Xbar) 701 outputs each of inputs in1 to in4 as one of sel1 to sel5 in accordance with control signal C_sig.

  The parallel multipliers 707, 708, 709 and 710 multiply sel2 and mult_cf4, sel3 and mult_cf3, sel4 and mult_cf2, and sel5 and mult_cf1, respectively, and output the multiplication results as one of mult_sel1 to mult_sel4.

  Pure imaginary multipliers 711, 712, 713, and 714 respectively multiply mult_sel1 to mult_sel4 by pure imaginary numbers and output the multiplication results as one of mult_i_sel1 to mult_i_sel4.

  The selectors 715, 716, 717, and 718 selectively output mult_sel1 to mult_sel4 and mult_i_sel1 to mult_i_sel4 as out1 to out4, respectively, according to C_sig.

  The output sel1 of the crossbar (Xbar) 701 is output as out1. The control signal C_sig is output as C_out.

  FIG. 7 is a block diagram showing the post-stage first addition unit 210.

  In FIG. 7, the complex number data in1 is out1 from the multiplier 208, the complex number data in2 is out2 from the multiplier 208, the complex number data in3 is out3 from the multiplier 208, and the complex number data in4 is , Out4 from the multiplier 208, the complex number data in5 is out5 from the multiplier 208, and the control signal C_sig is C_out from the multiplier 208.

  In FIG. 7, the post-stage first addition unit 210 includes crossbars (Xbar) 81 and 85 and adders 82, 83 and 84.

  The crossbar (Xbar) 81 outputs each of the inputs in1 to in6 as one of sel1 to sel9 according to the control signal C_sig.

  The adder 82 adds sel4 and sel5 and outputs the addition result add_s1. The adder 83 adds sel6 and sel7 and outputs the addition result add_s2. The adder 84 adds sel8 and sel9 and outputs the addition result add_s3.

  The crossbar (Xbar) 85 can input sel1, sel2, sel3, add_s1, add_s2, and add_s3. The crossbar (Xbar) 85 outputs each of the input signals as one of out1 to out4 according to C_sig.

  The control signal C_sig is output as C_out.

  FIG. 8 is a block diagram showing the second-stage second addition unit 211.

  In FIG. 8, complex number data in1 is out1 from the post-stage first addition unit 210, complex number data in2 is out2 from the post-stage first addition unit 210, and complex number data in3 is from the post-stage first addition unit 210. The complex number data in4 is out4 from the post-stage first addition unit 210, and the control signal C_sig is C_out from the post-stage first addition unit 210.

  In FIG. 8, the second-stage second addition unit 211 includes a plurality of delay circuits D, a crossbar (Xbar) 901, adders 902, 903, 904, and 905, pure imaginary multipliers 906, 907, 908, and 909, Sel (selector) 910, 911, 912 and 913.

  The crossbar (Xbar) 901 outputs each of the inputs in1 to in4 and the outputs regr1 to regr10 of the delay circuit D as one of sel1 to sel12 according to the control signal C_sig.

  The adder 902 adds sel1, sel2, and sel3, and outputs an addition result add_s1. The adder 903 adds sel4, sel5, and sel6, and outputs an addition result add_s2. The adder 904 adds sel7, sel8, and sel9 and outputs an addition result add_s3. The adder 904 adds sel10, sel11, and sel12, and outputs an addition result add_s4.

  The pure imaginary multiplier 906 multiplies the addition result add_s1 by a pure imaginary number and outputs a multiplication result add_i_s1. The pure imaginary multiplier 907 multiplies the addition result add_s2 by the pure imaginary number and outputs the multiplication result add_i_s2. The pure imaginary multiplier 908 multiplies the addition result add_s3 by the pure imaginary number and outputs a multiplication result add_i_s3. The pure imaginary multiplier 909 multiplies the addition result add_s4 by the pure imaginary number and outputs a multiplication result add_i_s4.

  The selector Sel910 selects either the output of the adder 902 or the output of the pure imaginary multiplier 906 according to C_sig, and outputs the selection result as out1. The selector Sel 911 selects either the output of the adder 903 or the output of the pure imaginary multiplier 907 according to C_sig, and outputs the selection result as out2. The selector Sel 912 selects either the output of the adder 904 or the output of the pure imaginary multiplier 908 according to C_sig, and outputs the selection result as out3. The selector Sel 913 selects either the output of the adder 905 or the output of the pure imaginary multiplier 909 according to C_sig, and outputs the selection result as out4.

  C_sig is delayed by 2 clocks and output as C_out.

  FIG. 9 is a block diagram showing the rear stage transposition unit 212.

  In FIG. 9, the complex number data in1 is out1 from the second-stage second addition unit 211, the complex number data in2 is out2 from the second-stage second addition unit 211, and the complex number data in3 is sent from the second-stage second addition unit 211. The complex number data in4 is out4 from the second-stage second addition unit 211, and the control signal C_sig is C_out from the second-stage second addition unit 211.

  In FIG. 9, the rear transposition unit 212 includes a plurality of delay circuits D and crossbars (Xbar) 1001, 1002, 1003, and 1004.

  In the rear stage transposition unit 212, first, the inputs in1, in2, in3, and in4 are integrated with the control signal C_sig.

  The crossbar (Xbar) 1001 outputs these signals as one of Sel1_1 to Sel1_7, respectively.

  The crossbar (Xbar) 1002 distributes Sel1_1 and the outputs D_Sel1_1 to D_Sel1_3 of the delay circuit D to any of Sel2_1 to Sel2_4 according to the control signal of each.

  The crossbar (Xbar) 1003 distributes the outputs D_Sel2_1 to D_Sel2_3 of the delay circuit D to one of Sel3_1, Sel3_2, and Sel3_3 in accordance with the control signal of each.

  The crossbar (Xbar) 1004 distributes D_Sel3_1 to D_Sel3_3, D_Sel2_1 to D_Sel2_3, Sel2_4, Sel1_5, Sel1_6, and Sel1_7 to any one of Sel4_1 to Sel4_4.

  Sel4_1 to Sel4_4 are separated into a control signal and complex data. Each of the complex number data is output as one of out1, out2, out3, and out4. On the other hand, the control signal is output to the ground indicated by GND in FIG. 9 and is not used thereafter.

  Further, the control signal C_sig is delayed by 3 clocks by the delay circuit D and output as C_out.

  FIG. 10 is a block diagram showing the post-stage third addition unit 213.

  In FIG. 10, complex data in1 is out1 from the rear transposition unit 212, complex data in2 is out2 from the rear transposition unit 212, and complex data in3 is out3 from the rear transposition unit 212. Data in4 is out4 from the rear stage transposition unit 212, and the control signal C_sig is C_out from the rear stage transposition unit 212.

  In FIG. 10, the rear stage third addition unit 213 includes a plurality of delay circuits D, crossbars (Xbar) 1101 and 1108, adders 1102, 1103, 1106 and 1107, and Sel (selectors) 1104 and 1105. .

  The crossbar (Xbar) 1101 outputs each of the inputs in1 to in4 and the outputs regr1 to regr5 of the delay circuit D as one of sel1 to sel7 according to the control signal C_sig.

  The adder 1102 adds sel1 and sel2, and outputs an addition result add_o_1. The adder 1103 adds sel1 and sel2 whose sign is inverted, and outputs an addition result add_o_2.

  The selector Sel1104 selects either sel1 or add_o_2 according to the control signal C_sig, and outputs the selection result as add_sel1. The selector Sel1105 selects either sel3 or add_o_1 according to the control signal C_sig, and outputs the selection result as add_sel2.

  The adder 1106 adds add_sel2 and sel4, and outputs an addition result add_o_3. The adder 1107 adds add_sel2 and sel4 with the sign inverted, and outputs an addition result add_o_4.

  The crossbar (Xbar) 1108 can input add_sel1, add_o_1, add_o_3, add_o_4, sel5, sel6 and sel7. The crossbar (Xbar) 1108 outputs each of the input signals as one of out1 to out4 according to the control signal C_sig.

  Next, an example in which the arithmetic device 200 performs 3, 5, 9, 15-point DFT / IDFT according to the control signal will be described.

  First, the data flows of the 3-point DFT / IDFT, 5-point DFT / IDFT, 9-point DFT / IDFT, and 15-point DFT / IDFT processed by the arithmetic device 200 are shown in FIGS. 11, 12, 13, and 14, respectively. Show.

  Note that DFT and IDFT can be processed with the same data flow by simply changing the later-described multiplication coefficient. For this reason, in this description, DFT and IDFT for each score are shown in one diagram for each score, that is, three-point DFT / IDFT in FIG. 11, five-point DFT / IDFT in FIG. 12, and nine-point DFT / IDFT. 13 and 15 point DFT / IDFT will be described with reference to FIG.

  11, 12, 13, and 14, a portion where the arrows overlap indicates addition, and a box indicated by “−” indicates that the sign of the signal that has passed there is inverted, and is indicated by “i”. The box indicates that the signal passing there is multiplied by a pure imaginary number, and the symbol indicated by “x” multiplies the signal passing there by the multiplication factor indicated by the arrow above the × symbol. It shows that.

  Further, the 15-point DFT / IDFT needs to be rearranged in the middle of the process, but the process is performed at a location indicated as “reorder” in FIG.

  Also, the input X and output Y indexes of each DFT / IDFT correspond to the X and Y indexes of the equation shown in Equation 1.

  Next, input signals will be described.

  Data input to the arithmetic unit 200 is complex number data, and the real part and the imaginary part are data expressed in a floating-point format.

  The control signal C_sig input to this unit uses the format shown in FIG. As shown in FIG. 15, C_sig has passed since the start of the DFT / IDFT indicated by the point signal and the DFT / IDFT indicated by the point signal in any of 3, 5, 9, and 15 points of DFT / IDFT. A clock number signal indicating the number of clocks in 3 bits, and a DFT / IDFT selection signal indicating in 1 bit whether the process performed by the control signal is DFT or IDFT. The correspondence between the score signal and the DFT / IDFT score and the correspondence between the DFT / IDFT selection signal and the DFT / IDFT are as shown in FIG.

  Next, FIG. 17 shows the configuration of the offset table 702 shown in FIG.

  The offset table 702 uses the point signal shown in FIG. 15 as an address, and the contents indicated by each address store an offset for accessing the multiplication coefficient memories 704 and 705. That is, when a score signal is input from the outside to the offset table 702, the corresponding offset is read from the offset table 702 and output to the outside of the offset table 702.

  Next, the DFT multiplication coefficient memory 704 and the IDFT multiplication coefficient memory 705 will be described with reference to FIG.

  As shown in FIG. 18, the DFT multiplication coefficient memory 704 and the IDFT multiplication coefficient memory 705 each have four memories. When addresses are input to these four memories, the four values stored in each memory in the row corresponding to the value described in “Address” in FIG. 18 are read out, and mult_cf1, mult_cf2 in FIG. , mult_cf3 and mult_cf4, respectively.

  As an example, if the address “2” is input to the DFT multiplication coefficient memory 704, 0.559017 is read from the memory 1, 1.538842 is read from the memory 2, −0.36327 is read from the memory 3, and −0.58779 is read from the memory 4.

  In FIG. 18, the coefficient names of the multiplication coefficients shown in FIGS. 11, 12, 13, and 14 are also shown. A diagonal line in the table indicates that no value is stored at that location. Furthermore, the addresses input to the four memories, the DFT multiplication coefficient memory and the IDFT multiplication coefficient memory, are obtained by adding the clock number signal and the offset value read from the offset table 702.

  An input format of 3-point, 5-point, 9-point, and 15-point DFT / IDFT data to the arithmetic device 200 will be described with reference to FIG.

  FIG. 19 is a diagram illustrating a state where an input X of a 3-point, 5-point, 9-point, and 15-point DFT / IDFT is input to a DFT / IDFT circuit to obtain an output Y.

  Note that C shown at the top of the input X indicates a control signal, and has a format of C (DFT / IDFT selection signal value, number of clocks, point signal). In this description, DFT will be described as an example, but IDFT is the same processing as DFT except for a multiplication unit section described later, and thus description thereof is omitted.

  In addition, with respect to the 5-point DFT / IDFT, the arithmetic device 200 can simultaneously perform three sequences.

  Here, the series is a process for performing the process shown in FIG. 12 once. Therefore, the three series means that three processes shown in FIG. 12 are performed simultaneously.

  Hereinafter, each of the three series will be referred to as series 0, series 1, and series 2.

  The index in parentheses (X) in FIG. 19 indicates (index and sequence number assigned to each signal in FIG. 12). As an example, X (0,0) indicates X0 of the series 0.

(3-point DFT / IDFT)
Next, three-point DFT / IDFT processing by the arithmetic device 200 will be described.

  The process of the first-stage first addition unit 204 will be described with reference to FIG. In FIG. 20, it is assumed that the value of a part where nothing is described is 0, and the time charts shown below are the same.

  In the first-stage first addition unit 204, the process of calculating b0, b1, and b2 shown in FIG. 11 is performed in one cycle.

  Specifically, according to the input C_sig, the crossbar (Xbar) 31 outputs X (0) as sel1, X (1) as sel3, and X (2) as sel4.

  Next, the adder 35 outputs b0, the adder 32 outputs b1, and the adder 33 outputs b2.

  Finally, Xbar 37 outputs b0 to out1, outputs b1 to out2, and outputs b2 to out3 according to the control signal C_sig.

  In this way, the Xbar and the selector change the output destination of the input according to the input C_sig. In the following, detailed description of each Xbar and selector is omitted, and only the signal value output in the signal name is shown in the description.

  The process of the upstream transposition unit 205 will be described with reference to FIG.

  In the upstream transposition unit 205, first, the crossbar (Xbar) 41 outputs the input data in1, in2, and in3 as D_Sel_1_1, D_Sel_1_2, and D_Sel_1_3.

  Next, the crossbar (Xbar) 42 outputs D_Sel_1_1 to D_Sel_1_3 as Sel_2_1 to Sel_2_3, respectively, and the crossbar (Xbar) 43 outputs out1, out2, and out3.

  With reference to FIG. 22, the processing contents of the pre-stage second addition unit 206 are described.

  The upstream transposition unit 205 does not particularly perform addition processing, delays the input data by the delay circuit D, and outputs it to the next unit.

  The processing content of the pre-stage third addition unit 207 will be described with reference to FIG.

  The pre-stage third addition unit 207 passes through the input data without performing any particular addition processing, and outputs it to the next unit.

  The processing contents of the control unit 209 and the multiplier 208 will be described with reference to FIG.

  The control unit 209 reads the multiplication coefficients T_3_1 and T_3_2 in the first cycle, and the multiplier 208 multiplies them by b1 and b2, and outputs them to out2 and out3. Note that the multiplier 208 does not particularly multiply b0 by a coefficient and outputs it as out1.

  The processing content of the post-stage first addition unit 210 will be described with reference to FIG.

  The post-stage first addition unit 210 performs no particular processing and outputs the input data in1, in2, and in3 as sel1, sel2, and sel3, respectively, and outputs them as out1, out2, and out3.

  The processing contents of the second-stage second addition unit 211 will be described with reference to FIG.

  The post-secondary addition unit 211 does not particularly perform addition processing, but outputs the input data with a delay of two clocks. Specifically, the second-stage second addition unit 211 outputs the input data in1, in2, and in3 as regr2, regr5, and regr7, respectively, and further outputs them as sel1, sel4, and sel7. Thereafter, the adders 82 and 84 add 0 to sel4 and sel7, respectively, to output add_s1 and add_s2 having the same values as sel4 and sel7. Finally, out1, out2, and out3 are output.

  The processing content of the rear stage transposition unit 212 will be described with reference to FIG.

  In the rear transposition unit 212, the input data in1, in2, and in3 are output as Sel_1_1, Sel_1_2, and Sel_1_3, and then the signal delayed by the delay circuit D is sent to the crossbar (Xbar) 1002 by the Sel_2_1, Sel_2_2, Sel_2_3 Output as.

  At this time, the rear-stage transposition unit 212 does not perform a process of exchanging input data in particular. Thereafter, the respective signals are output as D_Sel_2_1, D_Sel_2_2, and D_Sel_2_3, and then output as out1, out2, and out3 through the crossbar (Xbar) 1004 and Sel_4_1, Sel_4_2, and Sel_4_3.

  The processing content of the post-stage third addition unit 213 will be described with reference to FIG.

  The post-stage third addition unit 213 performs addition processing after delaying the input data by one clock. Specifically, the input data in1, in2, and in3 are output as regr2, regr3, and reg4, respectively. Thereafter, the adder 1102 calculates m0 + m1, and the adder 1107 calculates m0 + m1-m2. M0 is output as sel5. Finally, three-point DFT / IDFT results y0, y1, and y2 are output from the crossbar (Xbar) 1108 as out1, out2, and out3, respectively.

  As described above, when the arithmetic device 200 receives the control signal instructing the three-point DFT / IDFT, the arithmetic device 200 executes the three-point DFT / IDFT.

(5-point DFT / IDFT)
Next, the 5-point DFT / IDFT processing by the arithmetic device 200 will be described.

  The processing contents of the first stage first addition unit 204 will be described with reference to FIG.

  The pre-stage first addition unit 204 does not perform the addition process and outputs the data through. Specifically, the pre-stage first addition unit 204 outputs the input data in1, in2, and in3 as sel6, sel7, and sel8, respectively. Further, the control signal is sequentially output by one clock from the first cycle.

  The processing contents of the upstream transposition unit 205 will be described with reference to FIG.

  The upstream transposition unit 205 performs transposition processing of 5-point DFT / IDFT data.

  Specifically, in the first cycle, the data X (0,0), X (0,1), X (0,2) input as in1, in2, and in3 are respectively Sel_1_5, Sel_1_6, and Sel_1_7 Is output and input to the delay circuit D.

  Next, in the second cycle, the data X (1,0), X (1,1), X (1,2) input as in1, in2, and in3 are output as Sel_1_1, Sel_1_2, and Sel_1_4, respectively And input to the delay circuit D.

  Next, in the third cycle, the data X (2,0), X (2,1), X (2,2) input as in1, in2, and in3 are output as Sel_1_1, Sel_1_2, and Sel_1_4, respectively And input to the delay circuit D.

  Next, in the fourth cycle, the data X (3,0), X (3,1), and X (3,2) input as in1, in2, and in3 are output as Sel_1_1, Sel_1_2, and Sel_1_4, respectively. And input to the delay circuit D.

  Next, in the fifth cycle, the data X (4,0), X (4,1), and X (4,2) input as in1, in2, and in3 are output as Sel_1_1, Sel_1_2, and Sel_1_4, respectively. And input to the delay circuit D. At the same time, X (1,0) integrated with C (0,01,1) is output as D_Sel_1_1, which is output as Sel_2_1.

  Next, in the sixth cycle, as D_Sel_1_1 and D_Sel_1_2, X (2,0) integrated with C (0,01,2) and X (1,1 integrated with C (0,01,1) ) Are respectively output. Among these, X (2,0) integrated with C (0,01,2) is output as Sel_2_2. On the other hand, X (1,1) integrated with C (0,01,1) is output as Sel_2_1. In this way, the upstream transposition unit 205 changes the order of the input data and outputs it.

  Next, in the seventh cycle, as D_Sel_1_1 and D_Sel_1_2, X (3,0) integrated with C (0,01,3) and X (2,1 integrated with C (0,01,1) ) Are respectively output. X (3,0) integrated with C (0,01,3) is output as Sel_2_3. X (2,1) integrated with C (0,01,1) is output as Sel_2_2.

  Next, in the eighth cycle, as D_Sel_1_1, D_Sel_1_2, and D_Sel_1_4, X (4,0) integrated with C (0,01,4), X (3 with C (0,01,1) integrated) , 1) and X (1,2) integrated with C (0,01,1) are output respectively. X (4,0) integrated with C (0,01,4) is output as Sel_2_4. X (3,1) integrated with C (0,01,1) is output as Sel_2_3. X (1,2) integrated with C (0,01,1) is output as Sel_2_1.

  Next, in the ninth cycle, X (4,1) integrated with C (0,01,1) and X (2,2 integrated with C (0,01,1) as D_Sel_1_2 and D_Sel_1_4 ) Are respectively output. Also, X (4,1) integrated with C (0,01,1) is output as Sel_2_4. X (2,2) integrated with C (0,01,1) is output as Sel_2_2.

  Next, in the tenth cycle, X (3,2) integrated with C (0,01,1) is output as D_Sel_1_4. Here, this data is also output as Sel_2_3.

  Next, in the eleventh cycle, X (4,2) integrated with C (0,01,1) is output as D_Sel_1_4. Here, this data is also output as Sel_2_4. At the same time, X (1,0) integrated with C (0,01,1) is output as Sel_3_1, and X (2,0) integrated with C (0,01,2) is output as Sel_3_2. Output, X (3,0) integrated with C (0,01,3) is output as Sel_3_3, and X (4,0) integrated with C (0,01,4) is output as Sel_3_4 Is output. The control signal is separated from these data, and only the data is output as out. That is, X (1,0) is output as out1, X (2,0) is output as out2, X (3,0) is output as out3, and X (4,0) is output as out4 . Further, C (0,01,0) is output as C_out.

  Next, in the twelfth cycle, X (1,1) integrated with C (0,01,1) is output as Sel_3_1. Further, X (2,1) integrated with C (0,01,2) is output as Sel_3_2. Further, X (3,1) integrated with C (0,01,3) is output as Sel_3_3. Further, X (4,1) integrated with C (0,01,4) is output as Sel_3_4. The control signal is separated from these data, and only the data is output as out. That is, X (1,1) is output as out1, X (2,1) is output as out2, X (3,1) is output as out3, and X (4,1) is output as out4 . Further, C (0,01,1) is output as C_out.

  Next, in the thirteenth cycle, X (0,0) integrated with C (0,01,0) is output as Sel_3_1. Further, X (0,1) integrated with C (0,01,1) is output as Sel_3_2. The control signal is separated from these data, and only the data is output as out. That is, X (0,0) is output as out1, and X (0,1) is output as out2. Furthermore, C (0,01,2) is output as C_out.

  Next, in the 14th cycle, X (1,2) integrated with C (0,01,1) is output as Sel_3_1. Further, X (2,2) integrated with C (0,01,2) is output as Sel_3_2. Also, X (3,2) integrated with C (0,01,3) is output as Sel_3_3, and X (4,2) integrated with C (0,01,4) as Sel_3_4 Is output. The control signal is separated from these data, and only the data is output as out. That is, X (1,2) is output as out1, X (2,2) is output as out2, X (3,2) is output as out3, and X (4,2) is output as out4 .

  Furthermore, C (0,01,3) is output as C_out.

  Finally, in the fifteenth cycle, X (0,2) integrated with C (0,01,0) is output as Sel_3_1. The control signal is separated from this data, and only the data is output as out. That is, X (0,2) is output as out1. Furthermore, C (0,01,4) is output as C_out.

  Further, one control signal is output every clock from the 11th cycle.

  With reference to FIG. 31, the processing content of the pre-stage second addition unit 206 is described.

  The pre-stage second addition unit 206 performs a process of calculating a0, a1, a2, a3, a4 shown in FIG.

  Specifically, as regr1, regr3, regr4, and regr5 in the second cycle in the 5-point DFT / IDFT processing in the second addition unit 206 at the preceding stage, X (1,0), X (2,0, respectively) ), X (3,0), and X (4,0) are output. The adder 52 calculates X (1,0) + X (2,0), and outputs the calculation result a1 (0) as out1. The adder 53 calculates X (1,0) -X (2,0), and outputs the calculation result a4 (0) as out2. The adder 54 calculates X (3,0) + X (4,0) and outputs the calculation result a2 (0) as out3. The adder 55 calculates X (3,0) −X (4,0), and outputs the calculation result a3 (0) as out4. Here, the numbers in parentheses attached to a indicate a sequence number. As an example, a1 (0) indicates the intermediate calculation result a1 of the input X of the series 0.

  In the third cycle, processing similar to that in the second cycle is performed, and a1 (1), a4 (1), a2 (1), and a3 (1) are output.

  In the fourth cycle, the front stage second addition unit 206 outputs a (0) and a (1). Specifically, X (0,0) and X (0,1) are output as regr1 and regr3, respectively. They are output as sel1 and sel4, respectively. The adder 52 and the adder 53 add 0 to sel1 and sel4, respectively, and output the added values as out1 and out2.

  In the fifth cycle, processing similar to that in the second and third cycles is performed, and a1 (2), a4 (2), a2 (2), and a3 (2) are output.

  In the sixth cycle, a (2) is output. Specifically, X (0,2) is output as regr1, X (0,2) is output as sel1, and the adder 52 adds 0 to sel1, and outputs the addition result as out1.

  Further, one control signal is output every clock from the second cycle.

  The processing contents of the pre-stage third addition unit 207 will be described with reference to FIG.

  The pre-stage third addition unit 207 performs a process of calculating c0 to c5 shown in FIG.

  Specifically, in the first cycle, the adder 62 performs a1 (0) -a2 (0) to obtain a calculation result c2 (0), and outputs c2 (0) as out1. Further, the adder 65 performs a3 (0) + a (4) to obtain a calculation result c5 (0), and outputs c5 (0) as out4. The crossbar 61 outputs a3 (0) and a4 (0) as sel4 and sel7, respectively. The adder 63 adds 0 to sel4 and outputs the addition result c3 (0) as out2. The adder 64 adds 0 to sel7 and outputs the addition result c4 (0) as out3.

  Next, in the second cycle, the same processing as in the first cycle is performed, and c2 (1), c3 (1), c4 (1), and c5 (1) are out1, out2, and out3, respectively. , Output as out4.

  Next, in the third cycle, data a0 (0) and a0 (1) of in1, in2 and a1 (0), a2 (0), a1 outputted as regr1, regr2, regr3, regr4, respectively. Using (1) and a2 (1), c0 (0), c1 (0), c0 (1), and c1 (1) are respectively calculated.

  Specifically, the adder 62 calculates a0 (0) + a1 (0) + a2 (0) to obtain a calculation result c0 (0), and outputs c0 (0) as out1. Further, the adder 63 calculates a1 (0) + a2 (0) to obtain a calculation result c1 (0), and outputs c1 (0) as out2. The adder 64 calculates a0 (1) + a1 (1) + a2 (1) to obtain a calculation result c0 (1), and outputs c0 (1) as out3. The adder 65 calculates a1 (1) + a2 (1) to obtain a calculation result c1 (1), and outputs c1 (1) as out4.

  Next, in the fourth cycle, the same processing as in the first and second cycles is performed, and c2 (2), c3 (2), c4 (2), and c5 (2) are out1, out2 respectively. , Out3, and out4.

  Finally, in the fifth cycle, substantially the same processing as in the third cycle is performed, and c0 (2) and c1 (2) are obtained.

  Further, one control signal is output every clock from the first cycle.

  The processing contents of the control unit 209 and the multiplier 208 will be described with reference to FIG. The control unit 209 and the multiplier 208 perform processing for obtaining coefficients m0 to m5 shown in FIG.

  Specifically, in the first cycle, the multiplier 208 converts the input c2 (0), c3 (0), c4 (0), and c5 (0) to T5_2, T5_3, T_5_4, and T5_5, respectively. Multiply by a coefficient. Further, the multiplier 208 multiplies pure imaginary numbers after multiplying the above coefficients for c3 (0), c4 (0), and c5 (0). As described above, m2 (0), m3 (0), m4 (0), and m5 (0) are calculated, and these are output as out1, out2, out3, and out4, respectively.

  In the second cycle, the same processing as in the first cycle is performed, and m2 (1), m3 (1), m4 (1), and m5 (1) are calculated, and these are out1, out2, out3 , Output as out4.

  In the third cycle, the multiplier 208 multiplies the input c0 (0), c1 (0), c0 (1), and c1 (1) by the coefficients of T5_0, T5_1, T5_0, and T5_1, respectively. Processing is performed to obtain m0 (0), m1 (0), m0 (1), and m1 (1). These are output as out1, out2, out3, and out4, respectively.

  In the fourth cycle, the same processing as in the first cycle is performed, and m2 (2), m3 (2), m4 (2), and m5 (2) are calculated, which are out1, out2, Output as out3 and out4.

  In the fifth cycle, processing similar to that in the third cycle is performed, and m0 (2) and m1 (2) are obtained. These are output as out1 and out2, respectively.

  Further, one control signal is output every clock from the first cycle.

  The processing contents of the post-stage first addition unit 210 will be described with reference to FIG. This unit performs the process of obtaining n0 to n4 shown in FIG.

  Specifically, in the first cycle, m2 (0) is output as sel1, more specifically, n2 (0). Further, the adder 82 calculates m3 (0) + m5 (0), and outputs the calculation result n3 (0) as add_s1. The adder 83 calculates m4 (0) + m5 (0) and outputs the calculation result n4 (0) as add_s2. The crossbar 85 outputs n2 (0), n3 (0), and n4 (0) as out1, out2, and out3, respectively.

  In the second cycle, processing similar to that in the first cycle is performed, and n2 (1), n3 (1), and n4 (1) are obtained. These are output as out1, out2, and out3, respectively.

  In the third cycle, m0 (0) and m0 (1) are output as sel1, sel2, and more specifically as n0 (0), n0 (1), respectively. Further, the adder 82 calculates m0 (0) + m1 (0), and outputs the calculation result n1 (0) as add_s1. The adder 83 calculates m0 (1) + m1 (1) and outputs the calculation result n1 (1) as add_s2. The crossbar 85 outputs n0 (0), n0 (1), n1 (0), and n1 (1) to out1, out2, out3, and out4, respectively.

  In the fourth cycle, the same processing as in the first and second cycles is performed, and n2 (2), n3 (2), and n4 (2) are obtained. These are output as out1, out2, and out3, respectively.

  In the fifth cycle, processing similar to that in the third cycle is performed, and n0 (2) and n1 (2) are obtained. These are output as out1 and out2, respectively.

  Further, one control signal is output for each clock from the first cycle.

  The processing contents of the second-stage second addition unit 211 will be described with reference to FIG.

  The latter second addition unit 211 calculates y0 to y4 shown in FIG.

  Specifically, the post-second addition unit 211 does not particularly perform addition processing in the first cycle and the second cycle, and the adder 902 performs n1 (0) + n2 (0) in the third cycle. + n4 (0) is calculated, and the calculation result y1 (0) is output as add_s1. The adder 903 calculates n1 (0) + n2 (0) −n4 (0), and outputs the calculation result y4 (0) as add_s2. The adder 904 calculates n1 (0) -n2 (0) + n3 (0), and outputs the calculation result y2 (0) as add_s3. The adder 905 calculates n1 (0) -n2 (0) -n3 (0) and outputs the calculation result y3 (0) as add_s4. These are output as out1, out2, out3, and out4, respectively.

  In the fourth cycle, processing similar to that in the third cycle is performed, and y (1,1), y (4,1), y (2,1), and y (3,1) are obtained. These are output as out1, out2, out3, and out4, respectively.

  In the fifth cycle, the same processing as in the third and fourth cycles is performed, and y (1,2), y (4,2), y (2,2), and y (3,2) are obtained. It is done. These are output as out1, out2, out3, and out4, respectively.

  In the sixth cycle, n0 (0), n0 (1), and n0 (2) are output as sel1, sel4, and sel7, respectively. The adder 902 adds 0 to sel1, and outputs the addition result y (0,0) as add_s1. The adder 903 adds 0 to sel4 and outputs the addition result y (0,1) as add_s2. The adder 904 adds 0 to sel7 and outputs the addition result y (0, 2) as add_s3. These are output as out1, out2, and out3, respectively.

  Also, one control signal is output every clock from the third cycle.

  The processing content of the rear stage transposition unit 212 is demonstrated using FIG.

  The rear transposition unit 212 performs a process of rearranging the input data.

  Specifically, in the first cycle, the input y (1,0), y (4,0), y (2,0), y (3,0) are respectively controlled by the control signal C (0 , 01,0) and output as Sel_1_1, Sel_1_2, Sel_1_3, and Sel_1_4. Moreover, y (1,0) is output as Sel_2_1.

  In the second cycle, the input y (1,1), y (4,1), y (2,1), y (3,1) are the control signals C (0,01,1), respectively. And are output as Sel_1_1, Sel_1_2, Sel_1_3, and Sel_1_4. Also, y (4,0) integrated with C (0,01,0) is output as D_Sel_1_1, and this data is also output as Sel_2_1. On the other hand, y (1,1) output as Sel_1_1 is also output as Sel_2_2.

  In the third cycle, the input y (1,2), y (4,2), y (2,2), y (3,2) are controlled by the control signal C (0,01,2), respectively. And are output as Sel_1_1, Sel_1_2, Sel_1_3, and Sel_1_4. Also, y (4,1) integrated with C (0,01,1) and y (2,0) integrated with C (0,01,0) are output as D_Sel_1_1 and D_Sel_1_2, respectively. . Furthermore, as Sel_2_1, Sel_2_2, and Sel_2_3, y (2,0) integrated with C (0,01,0), y (4,1), C combined with C (0,01,1), respectively Y (1,2) integrated with (0,01,2) is output.

  In the fourth cycle, the input y (0,0), y (0,1), y (0,2) are integrated with the control signal C (0,01,3), respectively, and Sel_1_5, Sel_1_6 , Sel_1_7, and then output as Sel_4_1, Sel_4_2, and Sel_4_3. In these signals, the control signal and data are separated and only the data is output as out. That is, y (0,0), y (0,1), and y (0,2) are output as out1, out2, and out3, respectively. On the other hand, as D_Sel_1_1, D_Sel_1_2, D_Sel_1_3, y (4,2) integrated with C (0,01,2), y (2,1) integrated with C (0,01,1), respectively Y (3,0) integrated with C (0,01,0) is output. These are output as Sel_2_3, Sel_2_2, and Sel_2_1, respectively. Furthermore, as D_Sel_2_1, D_Sel_2_2, D_Sel_2_3, y (1,0) integrated with C (0,01,0), y (1,1), C (0 integrated with C (0,01,1) , 01,2) and y (1,2) are output, which are output as Sel_3_1, Sel_3_2, and Sel_3_3, respectively.

  In the fifth cycle, as D_Sel_1_2 and D_Sel_1_3, y (2,2) integrated with C (0,01,2) and y (3,1) integrated with C (0,01,1), respectively Are output as Sel_2_3 and Sel_2_2, respectively. On the other hand, as D_Sel_2_1, D_Sel_2_2, and D_Sel_2_3, y (4,0) integrated with C (0,01,0), y (4,1), C ( 0 (01,2) and y (4,2) integrated are output, and these are output as Sel_3_1, Sel_3_2, and Sel_3_3, respectively. Furthermore, as Sel_4_1, Sel_4_2, and Sel_4_3, y (1,0) integrated with C (0,01,0), y (1,1) integrated with C (0,01,1), respectively. Y (1,2) integrated with C (0,01,2) is output. With these signals, the control signal and data are separated, and only the data is output as out. That is, y (1,0), y (1,1), and y (1,2) are output as out1, out2, and out3.

  In the sixth cycle, y (3,2) integrated with C (0,01,2) is output as D_Sel_1_3, which is output as Sel_2_3. D_Sel_2_1, D_Sel_2_2, and D_Sel_2_3 are y (2,0) integrated with C (0,01,0), y (2,1), C ( 0 (01,2) and y (2,2) integrated are output, and these are output as Sel_3_1, Sel_3_2, and Sel_3_3, respectively. Furthermore, as Sel_4_1, Sel_4_2, and Sel_4_3, y (4,0) integrated with C (0,01,0), y (4,1) integrated with C (0,01,1), respectively. Y (4,2) integrated with C (0,01,2) is output. In these signals, the control signal and data are separated and only the data is output as out. That is, y (4,0), y (4,1), and y (4,2) are output as out1, out2, and out3.

  In the 7th cycle, as D_Sel_2_1, D_Sel_2_2, D_Sel_2_3, y (3,0) integrated with C (0,01,0), y (3,1) integrated with C (0,01,1) , C (0,01,2) and y (3,2) are output, which are output as Sel_3_1, Sel_3_2, and Sel_3_3, respectively. Furthermore, as Sel_4_1, Sel_4_2, and Sel_4_3, y (2,0) integrated with C (0,01,0), y (2,1) integrated with C (0,01,1), respectively. Y (2,2) integrated with C (0,01,2) is output. In these signals, the control signal and data are separated and only the data is output as out. That is, y (2,0), y (2,1), and y (2,2) are output to out1, out2, and out3.

  In the eighth cycle, as Sel_4_1, Sel_4_2, and Sel_4_3, y (3,0) combined with C (0,01,0) and y (3,0,1) combined with C (0,01,1), respectively. 1), y (3,2) integrated with C (0,01,2) is output. In these signals, the control signal and data are separated and only the data is output as out. That is, y (3,0), y (3,1), and y (3,2) are output as out1, out2, and out3.

  Also, one control signal is output for each clock from the fourth cycle.

  The processing content of the post-stage third addition unit 213 will be described with reference to FIG.

  The post-stage third addition unit 213 simply outputs the input data with a delay of one clock, and does not perform any addition processing. Specifically, in1, in2, and in3 data delayed by one clock by the delay circuit D are output as sel5, sel6, and sel7, and then output as out1, out2, and out3.

  As described above, when the arithmetic device 200 receives the control signal instructing the 5-point DFT / IDFT, the arithmetic device 200 executes the 5-point DFT / IDFT.

(9 points DFT / IDFT)
Next, 9-point DFT / IDFT processing by the arithmetic device 200 will be described.

  The processing contents of the first-stage first addition unit 204 will be described with reference to FIG.

  The pre-stage first addition unit 204 performs processing for calculating coefficients a1 to a8 shown in FIG.

  Specifically, in the first cycle, the adder 35 and the adder 36 perform the processing of X (1) + X (8), X (1) −X (8), respectively, thereby a1, Calculate a2 and output them as out1 and out2.

  Next, in the second cycle, the adder 32, the adder 33, the adder 35, and the adder 36 are respectively X (4) + X (5), X (4) -X (5), By performing X (2) + X (7) and X (2) -X (7), a3, a4, a5, and a6 are calculated, respectively. These data are output as out1, out2, out3, and out4, respectively.

  Next, in the third cycle, the adder 35 and the adder 36 calculate X (3) + X (6) and X (3) −X (6), respectively, and obtain a7 and a8. These are output as out3 and out4. Further, X (0) is output as sel6 and then output as out1.

  The processing contents of the upstream transposition unit 205 will be described with reference to FIG.

  The upstream transposition unit 205 outputs the input data without particularly performing the data rearrangement process. Specifically, the data input as in1, in2, in3, in4 is output as Sel_1_1, Sel_1_2, Sel_1_3, Sel_1_4, respectively, and then output as Sel_2_1, Sel_2_2, Sel_2_3, Sel_2_4, and D_dt_1, Output as D_dt_2, D_dt3, D_dt_4, and finally output as out1, out2, out3, out4.

  With reference to FIG. 40, the processing contents of the second-stage second addition unit 206 will be described.

  The pre-stage second addition unit 206 performs processing for calculating a7 ′, a8 ′, and a9 to a16 shown in FIG.

  Specifically, the addition process is not performed in the first cycle, and in the second cycle, the adder 52, the adder 53, the adder 54, and the adder 55 are a1 + a3 + a5, a5- a1, a1-a3, a5-a3 are calculated, and calculation results a15, a9, a10, a11 are output. They are output as out1, out2, out3, out4.

  Next, in the third cycle, the adder 52, the adder 53, the adder 54, and the adder 55 calculate a6-a4 + a2, -a6-a4, a2-a6, a2-a4, respectively. The calculation results a16, a14, a12, and a13 are output. These are output as out1, out2, out3, and out4.

  Finally, in the fourth cycle, X0 ′, a7, and a8 are output as sel1, sel4, and sel6, respectively, and then 0 is added in the adder 52, adder 53, and adder 54, and then Output as out1, out2, and out3, respectively.

  The processing contents of the pre-stage third addition unit 207 will be described with reference to FIG. In this process, a17 shown in FIG. 13 is calculated.

  Specifically, in the first cycle, input data in1, in2, in3, and in4 are output as sel1, sel4, sel6, and sel9, respectively, and then adder 62, adder 63, and adder 64, 0 is added by the adder 65, and then output as out1, out2, out3, and out4, respectively.

  In the second cycle, the same processing as in the first cycle is performed.

  In the third cycle, the adder 62 performs a15 + x0 ″ + a7 ′ and outputs the addition result a17 as out1. Further, x0 ″, a7 ′, and a8 are output as out2, out3, and out4, respectively, in the same manner as in the first and second cycles.

  The processing contents of the control unit 209 and the multiplier 208 will be described with reference to FIG.

  The control unit 209 and the multiplier 208 perform processing for calculating a coefficient indicated by m in FIG.

  Specifically, in the first cycle, the multiplier 208 performs multiplication processing of a15 ′, a9 ′, a10 ′, a11 ′ and the multiplication coefficients T9_9, T9_1, T9_2, T9_3, and the calculation results m9, m1 respectively. , M2, and m3 are output. These are output as out2, out3, out4, and out5, respectively.

  In the second cycle, processing similar to that in the first cycle is performed, and coefficients m10, m6, m4, and m5 are obtained.

  In the third cycle, the same processing as in the first and second cycles is performed, and coefficients a7 ′ ″, m7, m8, and a17 ′ are obtained. Further, the X0 ′ ″ coefficient is output as sel1, and then output as out1.

  The processing contents of the post-stage first addition unit 210 will be described with reference to FIG.

  The post-stage first addition unit 210 performs processing for obtaining coefficients indicated by c and xa0 in FIG.

  Specifically, in the first cycle, m9 is output as sel1 and then output as out1. Further, the adder 82, the adder 83, and the adder 84 calculate m1 + m2, m2-m3, and m1 + m3, respectively, and obtain calculation results c4, c2, and c3, respectively. These are output as out2, out3, and out4, respectively.

  In the second cycle, m10 is output as sel1 and then output as out1. Further, the adder 82, the adder 83, and the adder 84 calculate m4-m6, m5-m6, and m4-m5, respectively, and obtain calculation results c8, c9, and c10, respectively. These are output as out2, out3, and out4, respectively.

  In the third cycle, m8 and a17 ′ are output as sel1 and sel2, respectively, and then output as out1 and out2. Further, the adder 82 and the adder 83 calculate x0 ″ ″ − m7 and x0 ″ ″ + a7 ′ ″, respectively, and obtain calculation results c1 and xa0, respectively. These are output as out3 and out4, respectively.

  The processing contents of the second-stage second addition unit 211 will be described with reference to FIG.

  The post-stage second addition unit 211 performs processing for calculating c7, c6, c5, c14, c11 * i, c12 * i, c13 * i, and m10 ″ * i shown in FIG.

  Specifically, no addition processing is particularly performed in the first cycle and the second cycle. In the third cycle, the adder 902 performs c1-c4-c2, and the adder 903 performs c1 + 4 + c3. The adder 904 performs c1 + c2-c3, and the adder 905 performs xa0-m9 ′ to obtain c7, c6, c5, and c14, respectively. These are output to out1, out2, out3, and out4, respectively.

  In the fourth cycle, the adder 902 calculates c8 + c9 + m8 ′, the adder 903 calculates c8 + c10−m8 ′, and the adder 904 calculates −c9 + c10 + m8 ′. Further, pure imaginary multipliers 906, 907, and 908 are multiplied by pure imaginary numbers, respectively, and the multiplication results are output as out1, out2, and ou3, respectively.

  In the fifth cycle, a17 ″ and m10 ′ are output as sel1 and sel4, respectively, and then 0 is added by the adders 902 and 903 and output. Further, pure imaginary multipliers 906 and 907 are multiplied by pure imaginary numbers, respectively, and the multiplication results are output as out1 and out2, respectively.

  The processing contents of the rear stage transposition unit 212 will be described with reference to FIG.

  The post-transposition unit 212 does not particularly perform input data rearrangement processing.

  Specifically, the data input as in1, in2, in3, in4 is output as Sel_1_1, Sel_1_2, Sel_1_3, Sel_1_4, respectively, and then output as Sel_2_1, Sel_2_2, Sel_2_3, Sel_2_4, and Sel_1_1, It is output as Sel_4_2, Sel_4_3, Sel_4_4, and finally output as out1, out2, out3, out4.

  The processing contents of the post-stage third addition unit 213 will be described with reference to FIG.

  The post-stage third addition unit 213 calculates an output indicated by y in FIG.

  Specifically, no particular addition processing is performed in the first cycle, and in the second cycle, the adder 1102, the adder 1103, the adder 1106, and the adder 1107 are respectively c5 + c11 * i, c5- c11 * i, c6 + c12 * i, and c6-c12 * i are calculated to obtain calculation results y8, y1, y7, and y2. These are output as out1, out2, out3, and out4, respectively.

  In the third cycle, processing similar to that in the second cycle is performed, and y5, y4, y6, and y3 are calculated and output as out1, out2, out3, and out4, respectively.

  In the fourth cycle, a17 ′ ″ is output as sel5 and then output as out1.

  As described above, when the arithmetic device 200 receives the control signal instructing the 9-point DFT / IDFT, it executes the 9-point DFT / IDFT.

(15 points DFT / IDFT)
Next, the 15-point DFT / IDFT processing content by the arithmetic device 200 will be described. Here, 15-point DFT / IDFT can be performed by a combination of 3-point DFT / IDFT processing and 5-point DFT / IDFT processing, except for the multiplication unit. Therefore, in the following, units other than the multiplication unit will be described as to which of 3 point DFT / IDFT and 5 point DFT / IDFT processing is performed, and detailed description thereof will be omitted.

  First, the first-stage first addition unit 204 performs a three-point DFT / IDFT process. Here, in the 3-point DFT / IDFT, input / output is completed in one cycle, whereas in the 15-point DFT / IDFT, calculation and output are performed by repeating the 3-point DFT / IDFT processing for 5 cycles.

  The upstream transposition unit 205 performs a 5-point DFT / IDFT process.

  The pre-stage second addition unit 206 performs 5-point DFT / IDFT processing.

  The pre-stage third addition unit 207 performs 5-point DFT / IDFT processing.

  The processing contents of the control unit 209 and the multiplier 208 will be described with reference to FIG.

  The control unit 209 and the multiplier 208 perform a process of multiplying the coefficient indicated by e in FIG. 14 by the multiplication coefficient and calculating the coefficient indicated by m.

  Specifically, in the first cycle, the multiplier 208 multiplies e2 by T15_2 to obtain an m2 coefficient. This is output as out1. At the same time, e3, e4, and e5 coefficients are input, and the multiplier 208 multiplies them by T15_3, T15_4, and T15_5. Further, regarding these coefficients, pure imaginary number multipliers 907, 908, and 909 perform processing for multiplying pure imaginary numbers to obtain m3, m4, and m5. These are output as out2, out3, and out4.

  In the second cycle, processing similar to that in the first cycle is performed, and m8, m9, m10, and m11 coefficients are obtained. These are output as out1, out2, out3, and out4, respectively.

  In the third cycle, e0, e1, e6, and e7 coefficients are input and multiplied by T15_0, T15_1, T15_6, and T15_7, respectively, and m0, m1, m6, and m7 are calculated. These are output as out1, out2, out3, and out4, respectively.

  In the fourth cycle, e15, e16, and e17 coefficients are input, and these are multiplied by T15_15, T15_16, and T15_17 to calculate m15, m16, and m17. These are output as out2, out3, and out4. At the same time, e14 is input, and this is multiplied by the T15_14 coefficient. Further, the pure imaginary multiplier 906 multiplies the multiplication result by a pure imaginary number and outputs the multiplication result as out1.

  In the fifth cycle, the e12 and e13 coefficients are input, and this is multiplied by the T15_12 and T15_13 coefficients. Further, pure imaginary multipliers 906 and 907 respectively multiply the multiplication results by pure imaginary numbers and output the multiplication results as out1 and out2.

  The latter first addition unit 210 performs a 5-point DFT / IDFT process.

  The rear stage second addition unit 211 performs a 5-point DFT / IDFT process.

  The rear transposition unit 212 performs a 5-point DFT / IDFT process.

  The post-stage third addition unit 213 performs 3-point DFT / IDFT processing.

  As described above, when the arithmetic device 200 receives the control signal instructing the 15-point DFT / IDFT, it executes the 15-point DFT / IDFT.

(Other embodiments)
FIG. 28 shows a second embodiment of the present invention. The present embodiment includes a discrete Fourier transform device (arithmetic device) 200, a CPU 1 that controls the discrete Fourier transform device 200, and a memory unit 2 that stores data.

  In this embodiment, when the CPU 1 issues an address for accessing the memory unit 2 by the CPU-memory unit address signal, the memory unit 2 corresponds to the issued address by the CPU-memory unit data signal. Data is output to CPU1.

  Next, the CPU 1 outputs data to the discrete Fourier transform device 200 together with the control signals of the above-mentioned 3, 5, 9, 15-point DFT / IDFT.

  When receiving a control signal and data from the CPU 1, the discrete Fourier transform apparatus 200 executes DFT / IDFT according to the control signal and returns the result to the CPU 1.

  In such an embodiment, the number of DFT points can be further increased by the CPU 1 performing DFT / IDFT of points other than 3, 5, 9, 15 points DFT / IDFT supported by the discrete Fourier transform apparatus 200. it can.

  According to each of the embodiments described above, 3, 5, 9, and 15 points of DFT / IDFT can be processed by a common circuit. For this reason, the number of multipliers and adders can be reduced as compared with the case where the DFT / IDFT circuits of 3, 5, 9, and 15 points are respectively configured by individual circuits.

  In addition, for a DFT / IDFT of 3, 5, 9, 15 points, only one circuit is required to design. For this reason, the time required for design and mounting can be shortened as compared with the case where the DFT / IDFT circuits of 3, 5, 9, and 15 points are each constituted by individual circuits.

Also, even if DFT / IDFT with different points such as 3, 5, 9, 15 is performed, the timing at which data is output to each unit is matched, so each unit is related to the number of points of DFT / IDFT. Instead, it can operate at a predetermined timing. For this reason, it is possible to perform DFT / IDFT with different points using a common circuit without performing control to change the operation start timing of each unit according to the number of points of DFT / IDFT.
[Industrial applicability]
As an application example of the present embodiment, a base station apparatus that executes radio signal processing required in LTE can be cited.

1 CPU
2 Memory unit 200 Discrete Fourier transform device (arithmetic unit)
201 Pre-adder unit 202 Multiply unit 203 Post-adder unit 204 Pre-stage first adder unit 205 Pre-stage transpose unit 206 Pre-stage second adder unit 207 Pre-stage third adder unit 208 Multiplier 209 Control unit 210 Post-stage first adder unit 211 Post-stage second adder Unit 212 Rear transposition unit 213 Rear third addition unit

Claims (10)

One of a plurality of types of points , and a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, and a plurality of data are received, and the plurality of data are received. A discrete Fourier transform device for performing discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform . Adding means;
Multiplication means for executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
Second addition means for performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing later than the second timing,
The first addition means outputs the result of the previous addition process to the multiplication means at the second timing regardless of the number of points indicated by the control signal,
The multiplication means performs the multiplication process on the result of the previous stage addition process, and the result of the multiplication process is determined at the third timing regardless of the number of points indicated by the control signal. Output to the adding means,
The second addition means performs the post-stage addition process on the result of the multiplication process, and outputs the result of the post-stage addition process as a result of executing the process on the plurality of data ,
The first adding means includes
When the plurality of data is received at the first timing, according to the control signal, the plurality of data is selectively added to each other, or first calculation means for outputting the plurality of data as they are;
Rearrangement means for selectively rearranging data input at a fourth timing later than the first timing and earlier than the second timing according to the control signal, or outputting the data as it is;
Data input at a fifth timing that is later than the fourth timing and earlier than the second timing, in accordance with the control signal, or a second calculation means that outputs the data as it is,
And third arithmetic means for selectively adding data input at a sixth timing later than the fifth timing and earlier than the second timing according to the control signal, or outputting the data as it is,
The first calculation means outputs its own output to the sorting means at the fourth timing regardless of the number of points indicated by the control signal,
The rearranging means outputs its own output to the second arithmetic means at the fifth timing regardless of the number of points indicated by the control signal,
The second calculation means outputs its own output to the third calculation means at the sixth timing regardless of the number of points indicated by the control signal,
The discrete Fourier transform device , wherein the third calculation means outputs its own output to the multiplication means at the second timing regardless of the number of points indicated by the control signal . The multiplication means is
Storage means for storing the multiplication coefficient for discrete Fourier transform corresponding to the number of points and the multiplication coefficient for discrete inverse Fourier transform corresponding to the number of points for each number of points ;
Reading means for reading out the multiplication coefficient corresponding to the number of points and processing indicated by the control signal from the storage means;
First multiplication means for multiplying the output of the first addition means by the multiplication coefficient read by the reading means;
The result of the multiplication to the first multiplication means, in accordance with said control signal comprises a second multiplying means for multiplying the selectively pure imaginary, the discrete Fourier transform device of claim 1. One of a plurality of types of points , and a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, and a plurality of data are received, and the plurality of data are received. A discrete Fourier transform device for performing discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform . Adding means;
Multiplication means for executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
Second addition means for performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing later than the second timing,
The first addition means outputs the result of the previous addition process to the multiplication means at the second timing regardless of the number of points indicated by the control signal,
The multiplication means performs the multiplication process on the result of the previous stage addition process, and the result of the multiplication process is determined at the third timing regardless of the number of points indicated by the control signal. Output to the adding means,
The second addition means performs the post-stage addition process on the result of the multiplication process, and outputs the result of the post-stage addition process as a result of executing the process on the plurality of data ,
The multiplication means is
Storage means for storing the multiplication coefficient for discrete Fourier transform corresponding to the number of points and the multiplication coefficient for discrete inverse Fourier transform corresponding to the number of points for each number of points;
Reading means for reading out the multiplication coefficient corresponding to the number of points and processing indicated by the control signal from the storage means;
First multiplication means for multiplying the output of the first addition means by the multiplication coefficient read by the reading means;
And a second multiplying unit that selectively multiplies the multiplication result of the first multiplying unit by a pure imaginary number in accordance with the control signal . The second adding means includes
When receiving the output of the multiplication means at the third timing, according to the control signal, selectively add the outputs of the multiplication means, or a fourth calculation means for outputting the output of the multiplication means as it is,
The data input at the seventh timing later than the third timing is selectively added according to the control signal, output as it is, or the addition result selectively added is selectively multiplied by a pure imaginary number. A fifth computing means;
Data rearranging means for selectively rearranging data inputted at an eighth timing later than the seventh timing according to the control signal, or outputting the data as it is,
Sixth arithmetic means for selectively adding the data input at the ninth timing later than the eighth timing according to the control signal, or outputting the data as it is,
The fourth calculation means outputs its own output to the fifth calculation means at the seventh timing regardless of the number of points indicated by the control signal,
The fifth computing means outputs its own output to the data rearranging means at the eighth timing regardless of the number of points indicated by the control signal,
The data rearranging means outputs its own output to the sixth arithmetic means at the ninth timing regardless of the number of points indicated by the control signal,
The said 6th calculating means outputs an output of self as a result of having performed the said process of the number of points shown by the said control signal with respect to these data. Discrete Fourier transform device described in 1. One of a plurality of types of points , and a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, and a plurality of data are received, and the plurality of data are received. A discrete Fourier transform device for performing discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform . Adding means;
Multiplication means for executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
Second addition means for performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing later than the second timing,
The first addition means outputs the result of the previous addition process to the multiplication means at the second timing regardless of the number of points indicated by the control signal,
The multiplication means performs the multiplication process on the result of the previous stage addition process, and the result of the multiplication process is determined at the third timing regardless of the number of points indicated by the control signal. Output to the adding means,
The second addition means performs the post-stage addition process on the result of the multiplication process, and outputs the result of the post-stage addition process as a result of executing the process on the plurality of data ,
The second adding means includes
When receiving the output of the multiplication means at the third timing, according to the control signal, selectively add the outputs of the multiplication means, or a fourth calculation means for outputting the output of the multiplication means as it is,
The data input at the seventh timing later than the third timing is selectively added according to the control signal, output as it is, or the addition result selectively added is selectively multiplied by a pure imaginary number. A fifth computing means;
Data rearranging means for selectively rearranging data inputted at an eighth timing later than the seventh timing according to the control signal, or outputting the data as it is,
Sixth arithmetic means for selectively adding the data input at the ninth timing later than the eighth timing according to the control signal, or outputting the data as it is,
The fourth calculation means outputs its own output to the fifth calculation means at the seventh timing regardless of the number of points indicated by the control signal,
The fifth computing means outputs its own output to the data rearranging means at the eighth timing regardless of the number of points indicated by the control signal,
The data rearranging means outputs its own output to the sixth arithmetic means at the ninth timing regardless of the number of points indicated by the control signal,
The sixth arithmetic means outputs a self-output as a result of executing the processing of the number of points indicated by the control signal with respect to the plurality of data . One of a plurality of types of points , and a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, and a plurality of data are received, and the plurality of data are received. A discrete Fourier transform / discrete inverse Fourier transform method in a discrete Fourier transform apparatus that performs discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform . Adding step;
A multiplication step of executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
A second addition step of performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing that is later than the second timing,
In the first addition step, the result of the previous stage addition process is output at the second timing regardless of the number of points indicated by the control signal,
In the multiplication step, the result of the previous stage addition process is received at the second timing, the multiplication process is performed on the result of the previous stage addition process, and the result of the multiplication process is indicated by the control signal Regardless of the number of points, output at the third timing,
In the second addition step, the result of the multiplication process is received at the third timing, the post-stage addition process is performed on the result of the multiplication process, and the result of the post-stage addition process is applied to the plurality of data. Output as a result of executing the process ,
The first adding step includes
When receiving the plurality of data at the first timing, according to the control signal, selectively adding the plurality of data, or outputting the plurality of data as they are,
Rearrangement step of selectively rearranging data input at a fourth timing later than the first timing and earlier than the second timing according to the control signal, or outputting the data as it is;
A second calculation step of selectively adding data input at a fifth timing later than the fourth timing and earlier than the second timing according to the control signal, or outputting the data as it is;
A third operation step of selectively adding data inputted at a sixth timing later than the fifth timing and earlier than the second timing according to the control signal, or outputting the data as it is,
In the first calculation step, regardless of the number of points indicated by the control signal, the output of its own is output at the fourth timing,
In the rearrangement step, the output in the first calculation step is received at the fourth timing, and regardless of the number of points indicated by the control signal, the output of the self is output at the fifth timing,
In the second calculation step, the output in the rearrangement step is received at the fifth timing, and regardless of the number of points indicated by the control signal, its own output is output at the sixth timing,
The third calculation step accepts the output in the second calculation step at the sixth timing, and outputs its own output at the second timing regardless of the number of points indicated by the control signal,
In the multiplication step, the output at the third operation step, accepted by the second timing as a result of the preceding addition process, performing said multiplication process on the result of the preceding addition process, discrete Fourier transform and discrete Inverse Fourier transform method. The multiplication step includes
For each point number, a storage step of storing in the storage means the multiplication coefficient for discrete Fourier transform corresponding to the number of points and the multiplication coefficient for discrete inverse Fourier transform corresponding to the number of points ;
A reading step of reading out the multiplication coefficient corresponding to the number of points and processing indicated by the control signal from the storage means;
A first multiplication step of multiplying the output in the first addition step by the read multiplication coefficient;
The discrete Fourier transform / discrete inverse Fourier transform method according to claim 6 , further comprising: a second multiplication step of selectively multiplying a result of the multiplication by a pure imaginary number in accordance with the control signal. One of a plurality of types of points , and a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, and a plurality of data are received, and the plurality of data are received. A discrete Fourier transform / discrete inverse Fourier transform method in a discrete Fourier transform apparatus that performs discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform . Adding step;
A multiplication step of executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
A second addition step of performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing that is later than the second timing,
In the first addition step, the result of the previous stage addition process is output at the second timing regardless of the number of points indicated by the control signal,
In the multiplication step, the result of the previous stage addition process is received at the second timing, the multiplication process is performed on the result of the previous stage addition process, and the result of the multiplication process is indicated by the control signal Regardless of the number of points, output at the third timing,
In the second addition step, the result of the multiplication process is received at the third timing, the post-stage addition process is performed on the result of the multiplication process, and the result of the post-stage addition process is applied to the plurality of data. Output as a result of executing the process ,
The multiplication step includes
For each point number, a storage step of storing in the storage means the multiplication coefficient for discrete Fourier transform corresponding to the number of points and the multiplication coefficient for discrete inverse Fourier transform corresponding to the number of points;
A reading step of reading out the multiplication coefficient corresponding to the number of points and processing indicated by the control signal from the storage means;
A first multiplication step of multiplying the output in the first addition step by the read multiplication coefficient;
A discrete Fourier transform / discrete inverse Fourier transform method comprising: a second multiplication step of selectively multiplying a result of the multiplication by a pure imaginary number according to the control signal . The second adding step includes
When the output at the multiplication step is received at the third timing, the outputs are selectively added according to the control signal, or a fourth calculation step for outputting the output as it is,
The data input at the seventh timing later than the third timing is selectively added according to the control signal, output as it is, or the addition result selectively added is selectively multiplied by a pure imaginary number. A fifth operation step;
A data rearrangement step of selectively rearranging data input at an eighth timing later than the seventh timing according to the control signal, or outputting the data as it is,
A sixth operation step of selectively adding data inputted at a ninth timing later than the eighth timing according to the control signal, or outputting the data as it is,
In the fourth calculation step, regardless of the number of points indicated by the control signal, the self output is output at the seventh timing,
In the fifth calculation step, the output in the fourth calculation step is accepted at the seventh timing, and regardless of the number of points indicated by the control signal, its own output is output at the eighth timing,
In the data rearrangement step, the output in the fifth calculation step is accepted at the eighth timing, and regardless of the number of points indicated by the control signal, its own output is output at the ninth timing,
And in the sixth operation step receives the output at the data rearrangement step in the ninth timing, and outputs its own output as a result of executing the processing to the plurality of data, from the claims 6 8 The discrete Fourier transform / discrete inverse Fourier transform method according to any one of the above items. One of a plurality of types of points , and a control signal indicating whether the process is a discrete Fourier transform or a discrete inverse Fourier transform, and a plurality of data are received, and the plurality of data are received. A discrete Fourier transform / discrete inverse Fourier transform method in a discrete Fourier transform apparatus that performs discrete Fourier transform or discrete inverse Fourier transform of the number of points indicated by the control signal,
When the plurality of data are input at a first timing defined by a clock, a first addition process is performed on the plurality of data according to the discrete Fourier transform and the discrete inverse Fourier transform . Adding step;
A multiplication step of executing multiplication processing according to the processing indicated by the control signal for data input at a second timing later than the first timing;
A second addition step of performing post-stage addition processing according to the discrete Fourier transform and the discrete inverse Fourier transform on data input at a third timing that is later than the second timing,
In the first addition step, the result of the previous stage addition process is output at the second timing regardless of the number of points indicated by the control signal,
In the multiplication step, the result of the previous stage addition process is received at the second timing, the multiplication process is performed on the result of the previous stage addition process, and the result of the multiplication process is indicated by the control signal Regardless of the number of points, output at the third timing,
In the second addition step, the result of the multiplication process is received at the third timing, the post-stage addition process is performed on the result of the multiplication process, and the result of the post-stage addition process is applied to the plurality of data. Output as a result of executing the process ,
The second adding step includes
When the output at the multiplication step is received at the third timing, the outputs are selectively added according to the control signal, or a fourth calculation step for outputting the output as it is,
The data input at the seventh timing later than the third timing is selectively added according to the control signal, output as it is, or the addition result selectively added is selectively multiplied by a pure imaginary number. A fifth operation step;
A data rearrangement step of selectively rearranging data input at an eighth timing later than the seventh timing according to the control signal, or outputting the data as it is,
A sixth operation step of selectively adding data inputted at a ninth timing later than the eighth timing according to the control signal, or outputting the data as it is,
In the fourth calculation step, regardless of the number of points indicated by the control signal, the self output is output at the seventh timing,
In the fifth calculation step, the output in the fourth calculation step is accepted at the seventh timing, and regardless of the number of points indicated by the control signal, its own output is output at the eighth timing,
In the data rearrangement step, the output in the fifth calculation step is accepted at the eighth timing, and regardless of the number of points indicated by the control signal, its own output is output at the ninth timing,
And in the sixth operation step, the reception output of the data rearrangement step in the ninth timing, and outputs as a result of its own output to perform the processing on the plurality of data, a discrete Fourier transform and inverse discrete Fourier transform method.

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