JP2016218528A - Data processing device and data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of times of data loading.SOLUTION: A conversion unit 111 accepts a matrix A which is a first matrix acquired from a memory 101 through an arithmetic instruction of an object. The conversion unit 111 outputs a matrix of an arithmetic object indicated by the arithmetic instruction out of the matrix A which is the first matrix and a matrix Awhich is a second matrix obtained by subjecting the matrix A to transposition. The second matrix is a matrix including the same element with a plurality of elements included in the first matrix and obtained by replacing the sequence of at least two elements among the plurality of elements included in the first matrix. An arithmetic unit 112 performs arithmetic indicated by the arithmetic instruction with respect to the matrix of the arithmetic object outputted by the conversion unit 111. The arithmetic includes, for example, addition, subtraction and estimation. The matrix conversion and arithmetic can be performed through one arithmetic instruction.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data processing apparatus and a data processing method.

  Conventionally, a large amount of matrix calculation processing may be performed in wireless communication baseband processing or the like. An array processing architecture is suitable for handling array type data such as matrix operation processing. As a processor that handles array-type data, for example, there is a SIMD (Single Instruction Multiple Data) method or a vector method processor.

  Further, in matrix operations in wireless communication baseband processing, many matrix transformation processes such as taking the transposed matrix or complex conjugate of the input matrix occur. For example, as one function of matrix calculation in SIMD, a technique for obtaining a transposed matrix of a plurality of matrices is known (for example, refer to Patent Document 1 below).

JP 2005-174292 A

  Conventionally, a processor that handles array type data supplies data continuously from a memory in order to perform the same operation on continuous unit data. Matrix operations in baseband processing often involve matrix transformation processing such as transposing an input matrix or taking complex conjugates, which increases the number of data loads from the data memory.

  In one aspect, an object of the present invention is to provide a data processing apparatus and a data processing method capable of reducing the number of data loads.

  According to an aspect of the present invention, the first matrix acquired from the memory according to the target operation instruction is received, and the received first matrix includes the same elements as the plurality of elements included in the first matrix. A second matrix in which the arrangement of at least any two of the plurality of elements included in the first matrix is exchanged; a conversion unit that outputs a matrix to be calculated indicated by the calculation instruction; and the conversion A data processing apparatus and a data processing method are proposed that include a calculation unit that performs a calculation instructed by the calculation command on the calculation target matrix output by the calculation unit.

  According to one embodiment of the present invention, the number of data loads can be reduced.

FIG. 1 is an explanatory diagram illustrating an operation example of the data processing apparatus. FIG. 2 is an explanatory diagram illustrating an application example of the data processing apparatus. FIG. 3 is an explanatory diagram illustrating a configuration example of the data processing device and peripheral circuits. FIG. 4 is an explanatory diagram illustrating a calculation example using a calculation data path. FIG. 5 is an explanatory diagram illustrating an example of conversion into a transposed matrix. FIG. 6 is an explanatory diagram illustrating a functional configuration example of the data processing device. FIG. 7 is an explanatory diagram illustrating an example of matrix transformation. FIG. 8 is an explanatory diagram illustrating an example of a data supply circuit. FIG. 9 is an explanatory diagram illustrating an example of an index table. FIG. 10 is an explanatory diagram illustrating an example of a conjugate circuit. FIG. 11 is an explanatory diagram illustrating an output example of the conjugate control signal. FIG. 12 is a flowchart illustrating an example of an instruction execution processing procedure. FIG. 13 is an explanatory diagram showing a configuration example of a data supply circuit including a wraparound processing circuit. FIG. 14 is an explanatory diagram showing an example of element selection by the WM processing circuit and the matrix conversion circuit. FIG. 15 is an explanatory diagram illustrating another configuration example of the data supply circuit including the wraparound processing circuit. FIG. 16 is an explanatory diagram showing an example of matrix conversion by the data supply circuit shown in FIG. FIG. 17 is a diagram (part 1) schematically illustrating processing of the memory access unit and the data supply circuit. FIG. 18 is a diagram (part 2) schematically illustrating processing of the memory access unit and the data supply circuit. FIG. 19 is a diagram illustrating a detailed example of the wrap-around processing circuit. FIG. 20 is a diagram illustrating an example of the selection operation by the WM control circuit. FIG. 21 is a diagram illustrating another example of the selection operation by the WM control circuit. FIG. 22 is a diagram showing still another example of the selection operation by the WM control circuit. FIG. 23 is a diagram illustrating an example of the configuration of the WM control circuit. FIG. 24 is a diagram illustrating an example of the configuration of the SEL_WRAP circuit. FIG. 25 is a diagram illustrating an example of the configuration of the ADD_OFFSET circuit. FIG. 26 is a diagram illustrating a generation algorithm of each signal when SLS ≦ M. FIG. 27 is a diagram illustrating a generation algorithm of each signal when SLS> M. FIG. 28 is a diagram illustrating another example of the configuration of the WM control circuit. FIG. 29 is a diagram illustrating an example of data in the SLS_MOD table. FIG. 30 is a diagram illustrating another example of the configuration of the data processing device.

  Exemplary embodiments of a data processing device and a data processing method according to the present invention will be explained below in detail with reference to the accompanying drawings.

  FIG. 1 is an explanatory diagram illustrating an operation example of the data processing apparatus. The data processing apparatus 100 is a computer that performs stream type processing. The stream type process is a process of sequentially reading a series of data (array type data) from the memory 101 and performing an operation, and sequentially writing a series of operation results to the data memory. An example of application of the data processing apparatus 100 is shown in FIG. The application target is, for example, a smartphone, a mobile phone, a tablet terminal device, a tablet PC (Personal Computer), a PHS (Personal Handy-phone System), and the like.

  Further, the data processing apparatus 100 has a command group that handles unit data as a command set. The unit data is, for example, data in a matrix format. The instruction is, for example, an operation instruction such as a multiplication instruction, an addition instruction, or an inverse matrix (division) instruction.

  Here, in wireless communication signal processing, a large amount of matrix calculation processing may be required. When it is required to execute a process with a large amount of calculation such as matrix calculation at high speed, a dedicated circuit for matrix calculation is provided. As described above, examples of processors that handle array type data include SIMD and vector processor processors.

  The SIMD processor handles, for example, 128-bit data as unit data. Here, each element included in the matrix is represented by 32-bit data. For example, when the unit data length UL of the 2 × 2 matrix is 128 bits and the SIMD width is 4, the data processing width P is 512 bits of UL × SIMD width.

  Conventionally, a processor that handles array type data supplies data continuously from the memory 101 in order to perform the same operation on continuous unit data. Matrix operations in baseband processing often involve matrix transformation processing such as transposing an input matrix or taking complex conjugates, which increases the number of loads from the data memory.

  Therefore, in the present embodiment, the calculation is performed by outputting any one of the input matrix and the transformation matrix in which the arrangement of a plurality of elements of the input matrix is replaced. Thereby, matrix conversion and calculation can be performed with one instruction, and the number of data loads can be reduced. Therefore, the time required for the matrix calculation process can be shortened.

  First, the data processing apparatus 100 includes a conversion unit 111 and a calculation unit 112. The memory 101 stores a plurality of elements included in the matrix in a specific sequence. The memory 101 is a data memory. The specific sequence is, for example, a sequence in which the rows are given priority to form a one-dimensional array in order. In the case of the matrix A in FIG. 1, the data are arranged and stored as {a, b, c, d}. In addition, when the data processing apparatus 100 acquires a matrix from the memory 101, the matrix is acquired in the order of {a, b, c, d}.

The conversion unit 111 receives the first matrix acquired from the memory 101 by the target calculation instruction. In other words, the first matrix is an input matrix. In the example of FIG. 1, the first matrix is the matrix A. The conversion unit 111 outputs a matrix to be calculated, which is designated by the calculation instruction, out of the first matrix and the second matrix. The second matrix is a matrix including the same elements as the plurality of elements included in the first matrix, and is a matrix in which the arrangement of at least any two of the plurality of elements included in the first matrix is replaced. is there. In other words, the second matrix is, for example, a conversion matrix obtained by converting the first matrix. The second matrix is, for example, a transposed matrix of the first matrix or a complex conjugate matrix. In the example of FIG. 1, the second matrix is the matrix ^AT and is a transposed matrix of the matrix A.

  For example, in order to obtain a transposed matrix of 2 × 2 matrix, the data processing apparatus 100 provides a selection circuit for each of the second element and the third element in the data of the one-dimensional array of the matrix, so that the second element And the third element may be controlled. A specific example of the conversion method will be described later. The selection circuit is also referred to as a multiplexer.

  The calculation unit 112 performs a calculation instructed by a calculation command on the calculation target matrix output by the conversion unit 111. Examples of the calculation include addition, subtraction, and integration, but are not particularly limited. Specifically, the calculation unit 112 performs, for example, integration of the output calculation target matrix with another matrix. Specifically, for example, the calculation unit 112 multiplies the output matrix to be calculated by an integer.

  As a result, matrix transformation and computation can be performed simultaneously with one computation instruction, so that the number of data loads can be reduced.

(Application example of data processing apparatus 100)
Here, a case where the data processing apparatus 100 according to the present embodiment is applied to a baseband processing LSI (Large Scale Integrated circuit) of a mobile phone will be described.

  FIG. 2 is an explanatory diagram illustrating an application example of the data processing apparatus. 2, the baseband processing LSI 200 includes an RF (Radio Frequency) unit 201, dedicated hardware 202, and DSPs (Digital Signal Processors) 203-1 to 203-3.

  The RF unit 201 down-converts the frequency of the radio signal received via the antenna 205, converts it to a digital signal, and outputs it to the bus 204. The RF unit 201 converts the digital signal output to the bus 204 into an analog signal, up-converts the signal to a radio frequency, and outputs the converted signal to the antenna 205.

  The dedicated hardware 202 includes, for example, a turbo that handles an error correction code, a viterbi that executes a Viterbi algorithm, a MIMO (Multi Input Multi Output) that transmits and receives data with a plurality of antennas, and the like.

  The DSPs 203-1 to 203-3 (hereinafter simply referred to as “DSP203”) include a processor 211, an instruction memory 213, a peripheral circuit 212, and a data memory 214. The processor 211 includes a CPU 221 and the data processing device 100. Each DSP 203 is assigned with each element processing of radio communication signal processing such as Searcher (synchronization), Demodulator (demodulation), Decoder (decoding), Codec (encoding), Modulator (modulation).

  The instruction memory 213 is a memory that stores instructions such as programs. The data memory 214 is a memory 101 that stores data to be calculated, calculation results, and the like.

  FIG. 3 is an explanatory diagram illustrating a configuration example of the data processing device and peripheral circuits. FIG. 3 shows a simple connection example between the data processing device 100 and the instruction memory 213 and the data memory 214 around the data processing device 100.

  The data processing apparatus 100 includes an instruction decoder 304, a data supply circuit 301, an operation data path 302, and a data store circuit 303. The data supply circuit 301 is connected to the data memory 214 and reads data from the data memory 214. The operation data path 302 is an operation unit 112 that is connected to the data supply circuit 301 and performs an operation instructed by an operation instruction on a plurality of elements of the matrix supplied from the data supply circuit 301. Examples of the calculation include integration, addition, and subtraction.

  The data store circuit 303 is connected to the calculation data path 302 and the data memory 214, and writes the calculation result supplied from the calculation data path 302 to the data memory 214. The instruction memory 213 stores an instruction sequence having a plurality of instructions, and each instruction in the instruction sequence is sequentially supplied to the instruction decoder 304. The instruction decoder 304 decodes each supplied instruction and controls the data supply circuit 301, the operation data path 302, and the data store circuit 303 according to the decoding result. As a result, the instruction decoder 304 executes access processing to the data memory 214 and arithmetic processing by the arithmetic data path 302.

  In consideration of versatility, SIMD type architecture is suitable for handling array data such as matrix operations. In the SIMD type architecture, for example, 32-bit scalar data, a matrix, a vector, and the like are handled as unit data. For example, if the system has a SIMD width of 4, a vector having a length of 4 in which four pieces of data are arranged is processed, and each of the four elements of the vector is processed in parallel, thereby executing a calculation at high speed. In such a SIMD type architecture, for example, the unit data length UL is fixed to 32 bits, the SIMD width is 4, the data processing width P is fixed to 128 (= 4 × 32) bits, and the like.

  In the present embodiment, the processor of the stream processing architecture has a hardware configuration in which unit data length, SIMD width, and the like are variable parameters. As a result, commands having various unit data lengths can be defined. In such a hardware configuration, the data processing width P = UL × SIMD determined by the unit data length UL and the SIMD width differs depending on the operation instruction.

  FIG. 4 is an explanatory diagram illustrating a calculation example using a calculation data path. For example, when a plurality of elements included in a matrix are received from the data supply circuit 301, the calculation data path 302 performs a matrix calculation based on the received plurality of elements. The plurality of elements received from the data supply circuit 301 are, for example, the first source data src0 and the second source data src1. As shown in FIG. 4, the wraparound circuit 401 and the matrix conversion circuit 402 in the data supply circuit 301 may be prepared for each source data. In the example of FIG. 4, each of the first source data src0 and the second source data src1 is a 2 × 2 matrix. Each element of the matrix is, for example, 16 bits for a real matrix and 32 bits for a complex matrix, but is not particularly limited.

  The operation data path 302 performs an operation between matrices in accordance with the decoding result of the operation instruction by the instruction decoder 304. In the example of FIG. 4, the calculation is integration. The operation data path 302 is a SIMD type architecture, and executes an operation by one instruction for a plurality of matrices. The arithmetic data path 302 shown in FIG. 4 can perform arithmetic processing in four parallel.

  As described above, for example, when the transposed matrix of the input matrix is obtained by the operation data path 302 and used for the operation, an instruction for obtaining a transposed matrix for the input matrix, an instruction for performing an operation using the transposed matrix, and the like. As described above, the final operation result is obtained by executing a plurality of instructions. Specifically, for example, after an input matrix is loaded from the data memory 214 by an instruction for obtaining a transposed matrix to obtain a transposed matrix, the transposed matrix is stored in the data memory 214. Then, a transposition matrix is loaded from the data memory 214 by an instruction for performing an operation using the transposed matrix, and an operation using the transposed matrix is performed. As described above, there is a problem that when the operation and the matrix conversion are different instruction executions, the number of loads increases and the entire processing takes time.

FIG. 5 is an explanatory diagram illustrating an example of conversion into a transposed matrix. In the present embodiment, as described above, for example, when a matrix is represented by a one-dimensional array, the rows are preferentially represented. Here, an example is shown in which a transposed matrix is obtained from a 2 × 2 input matrix. As shown in FIG. 5A, in order to obtain the transposed matrix A ^T {a, c, b, d} from the input matrix A {a, b, c, d}, the element “b” and the element “c” What is necessary is just to swap the position of.

  Therefore, as shown in FIG. 5 (2), the matrix conversion circuit 402 shown in FIG. 4 provides a 2 × 2 by providing a multiplexer that outputs by replacing the elements of “b” and “c” by a transposed matrix on / off signal. The transpose matrix or the input matrix itself can be obtained from the input matrix.

For example, both the multiplexer 501-1 and the multiplexer 501-2 have b and c as inputs. For example, when the transposed matrix ON / OFF signal indicates ON, the multiplexer 501-1 selects and outputs c, and the multiplexer 501-2 selects and outputs b. Thereby, the transposed matrix ^AT can be obtained. On the other hand, for example, when the transposed matrix ON / OFF signal indicates OFF, the multiplexer 501-1 selects and outputs b, and the multiplexer 501-2 selects and outputs c. Thereby, the input matrix A can be obtained as it is.

(Functional configuration example of the data processing apparatus 100)
FIG. 6 is an explanatory diagram illustrating a functional configuration example of the data processing device. The data processing apparatus 100 includes, for example, a buffer 601, a conversion unit 111, and a calculation unit 112.

  Each unit may be formed by an element such as an AND circuit that is a logical product circuit, an INVERTER that is a negative logic circuit, an OR that is a logical sum circuit, or an FF (Flip Flop) that is a latch circuit. Each unit may be realized by an application-specific IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device) such as an FPGA. Specifically, for example, the functions of the respective units described above may be defined in a netlist using a hardware description language or the like, and the netlist may be logically synthesized and provided to the ASIC or PLD to implement each unit.

  The conversion unit 111 receives the first matrix acquired from the memory 101 by the target calculation instruction. The memory 101 is, for example, the data memory 214 described above. And the conversion part 111 outputs the matrix of the calculation object which a calculation command instruct | indicates among the received 1st matrix and 2nd matrix. The second matrix is a matrix including the same elements as the plurality of elements included in the first matrix, and is a matrix in which the arrangement of at least any two of the plurality of elements included in the first matrix is replaced. is there.

  The calculation unit 112 performs a calculation instructed by a calculation command on the calculation target matrix output by the conversion unit 111. Specifically, the calculation unit 112 is, for example, the calculation data path 302 described above.

  The conversion unit 111 includes a selection unit 611, a selection control unit 612, and a conjugate unit 613. The selection unit 611 outputs either the first matrix or the second matrix. The selection control unit 612 performs control to cause the selection unit 611 to output either the first matrix or the second matrix in accordance with an arithmetic instruction.

  The selection control unit 612 includes a storage unit 621. The storage unit 621 includes a plurality of elements included in the first matrix that are output to the selection unit 611 for a plurality of elements in a specific array included in the first matrix corresponding to the number of row elements and the number of column elements. The value of the control signal instructing is stored. The selection control unit 612 reads out the value of the control signal from the storage unit 621 and outputs it to the selection unit 611 based on the number of row elements and the number of column elements for the calculation target matrix indicated by the calculation instruction. The storage unit 621 is, for example, an index table shown in FIG.

  The selection unit 611 outputs a matrix to be calculated including a plurality of elements in which the control signal output from the selection control unit 612 indicates a plurality of elements included in the first matrix.

  For example, the buffer 601 can store a predetermined number of elements equal to or greater than the number of elements included in the first matrix. Further, the buffer 601 stores a plurality of elements included in the first matrix acquired from the memory 101 by a target arithmetic instruction in a specific arrangement. In the present embodiment, the row elements of the first matrix are preferentially stored.

  The selection unit 611 selects one of a plurality of elements included in the first matrix stored in the buffer 601 by each of a predetermined number of selection circuits capable of inputting the predetermined number of elements stored in the buffer 601. And output. The selection control unit 612 instructs an element to be selected by each selection circuit among a predetermined number of elements stored in the buffer 601.

  In addition, the conjugate unit 613 adds the sign of the imaginary part of each of the plurality of elements included in the calculation target matrix when each of the plurality of elements included in the calculation target matrix has an imaginary part and a real part. The matrix to be calculated is output after replacement.

  The first matrix that is an input matrix may be a plurality of first matrices having the same number of row and column elements. In addition, the second matrix that is the matrix after conversion may be a plurality of second matrices having the same number of row and column elements. Each of the plurality of second matrices includes an arrangement of at least any two of the plurality of elements included in the first matrix for each of the plurality of first matrices corresponding to each of the plurality of second matrices. This is the replaced matrix.

  Based on the above, the operation will be described in detail using a circuit corresponding to each part.

  FIG. 7 is an explanatory diagram illustrating an example of matrix transformation. Here, one or a plurality of input matrices can be handled, a matrix having an arbitrary number of elements can be input as long as the number of elements can be stored in the buffer, and various matrix transformations can be performed. Here, a case where the number of elements that can be processed at one time is 16 is taken as an example. The left side of FIG. 7 is an example in which four 2 × 2 first matrices are input and four second matrices that are 2 × 2 transposed matrices are obtained. The right side of FIG. 7 is an example in which two 2 × 3 first matrices are input to obtain two second matrices that are 3 × 2 transposed matrices. Even if there are a plurality of input matrices and transformed matrices, the number of elements in the rows and columns is the same.

(Example of data supply circuit 301)
FIG. 8 is an explanatory diagram illustrating an example of a data supply circuit. The data supply circuit 301 includes, for example, an input buffer 801, a multiplexer 802, a matrix conversion control circuit 803, and a conjugate circuit 804.

  Here, the input buffer 801 is a register capable of storing elements included in the input matrix. The size of the input buffer 801 is determined according to, for example, the size of the matrix to be calculated in the calculation data path 302, the configuration of the calculation data path 302, and the like. Here, the input buffer 801 can store 16 elements. The input buffer 801 is provided, for example, for performing pipeline processing in the matrix conversion processor. One element is 32-bit data.

  The output buffer 805 is a register capable of storing elements included in the converted matrix. The number of elements that can be stored in the output buffer 805 is a number corresponding to the number of elements that can be stored in the input buffer 801, and is the same as the number of elements that can be stored in the input buffer 801, for example.

  The multiplexer 802 and the matrix conversion control circuit 803 are the conversion unit 111. The multiplexer 802 outputs either the first matrix or the second matrix in which the arrangement of at least two elements among the plurality of elements included in the first matrix is exchanged. The multiplexer 802 is a selection unit 611 that outputs by exchanging a plurality of elements stored in the input buffer 801.

  The multiplexer 802 has a predetermined number of multiplexers MUX. The predetermined number is the number of elements that can be stored in the input buffer 801 as described above. Here, the multiplexer 802 includes 16 multiplexers MUX from multiplexers MUX_0 to MUX_15. Each of the multiplexers MUX_0 to MUX_15 can input all 16 elements stored in the input buffer 801. Each of the multiplexers MUX_0 to MUX_15 selects one element according to the data selection control signals sel0 to sel15 corresponding to each of the multiplexers MUX_0 to MUX_15, and outputs the selected element to the corresponding output buffer 805.

  For example, the multiplexer MUX_0 selects and outputs one of the 16 elements stored in the input buffer 801 based on the data selection control signal sel0. In the example of FIG. 8, each of the multiplexers MUX_0 to MUX_15 outputs to the conjugate circuit 804. However, when the conjugate circuit 804 is in the OFF state, each element selected by the multiplexers MUX_0 to MUX_15 is output to the output buffer 805 corresponding to each of the multiplexers MUX_0 to MUX_15. For example, the element selected by the multiplexer MUX_0 is stored in the output buffer 805-0.

  The matrix conversion control circuit 803 includes, for example, an index table 811 and a conjugate control circuit 812. The index table 811 is a data selection control capable of selecting an element corresponding to the number of elements in the specified row and the number of elements in the column when the number of elements in the converted row and the number of elements in the column are specified. Signals sel0 to sel15 are output.

  FIG. 9 is an explanatory diagram illustrating an example of an index table. In the index table 811 shown in FIG. 9, values of data selection signals for obtaining a transposed matrix from a plurality of elements included in the input matrix are set. M is the number of elements in the row after conversion, and N is the number of elements in the column after conversion. It is also possible to perform other matrix transformations together with the transposed matrix by adding a row of the index table 811 by adding a matrix transformation mode to be described later.

  For example, among the 16 elements stored in the input buffer 801, the elements stored in the input buffer 801 corresponding to each of the data selection control signals sel0 to sel15 are output. For example, the data selection control signal sel0 is a control signal for the multiplexer MUX_0 shown in FIG.

  Here, the conjugate circuit 804 will be omitted. When the data selection control signal sel0 is 0, the multiplexer MUX_0 outputs the element stored in the register provided with the input buffer 801-0 to the output buffer 805-0. In the index table 811, “x” indicates don't care. The input buffer 801-0 is a register in which 0 is added to the Index of the input buffer 801 in FIG. The output buffer 805-0 is a register in which 0 is added to the Index of the output buffer 805 in FIG.

  For example, when M = 1 and N = 1, according to the index table 811, elements are output to the output buffer 805 in the order of elements input to the input buffer 801.

  In order to obtain two 3 × 2 transposed matrices from the two 2 × 3 matrices shown on the right side of FIG. 7, M = 3 and N = 2. When M = 3 and N = 2, the data selection control signal sel0 is 0 and the data selection control signal sel1 is 3. The data selection control signal sel2 is 1, the data selection control signal sel3 is 4, the data selection control signal sel4 is 2, and the data selection control signal sel5 is 5. Further, the data selection control signal sel6 is 6, the data selection control signal sel7 is 9, the data selection control signal sel8 is 7, the data selection control signal sel9 is 10, and the data selection control signal sel10 is 8. is there. The data selection control signal sel11 is 11, and the data selection control signals sel12 to sel15 are don't cares.

  As shown on the right side of FIG. 7, in the case of two 2 × 3 matrices, the number of elements is 12, and four of the 16 elements stored in the input buffer 801 are not used. Therefore, the data selection control signals sel12 to sel15 are don't care. In this way, the input matrix can be converted into a matrix to be calculated by a simple control process.

  Returning to the description of FIG. 8, the conjugate circuit 804 is a conjugate unit 613 that exchanges the signs of the imaginary parts of the elements output from the multiplexer 802 in accordance with the conjugate control signal. Replacing the sign of the imaginary part is also referred to as replacing it with a conjugate complex number.

  FIG. 10 is an explanatory diagram illustrating an example of a conjugate circuit. Here, one element is, for example, 32-bit data. Among the 32-bit data, upper 16-bit data is a real part, and lower 16-bit data is an imaginary part. The conjugate circuit 804 inputs the 16-bit data of the imaginary part of the 32-bit data to the circuit comp2 that replaces the sign of the imaginary part. The circuit comp2 is a circuit that calculates a 2's complement according to the value of the conjugate control signal.

  For example, if the value of the conjugate control signal is 0, the circuit comp2 outputs the input 16-bit data as it is without calculating the 2's complement, and if the value of the conjugate control signal is 1, the 2's complement is output. The calculated 16-bit data is output.

  FIG. 11 is an explanatory diagram illustrating an output example of the conjugate control signal. Here, for example, if the value of TFmode input from the instruction decoder 304 to the conjugate control circuit 812 is 0, for example, it indicates that conversion is not performed, and if it is 1, it indicates that it is converted into a transposed matrix. Indicates conversion to Hermitian matrix. For example, if the value of TFmode is 0 or 1, the conjugate control circuit 812 sets the value of the conjugate control signal to 0 and outputs it to the conjugate circuit 804.

  For example, if the value of TFmode is 2, the conjugate control circuit 812 sets the value of the conjugate control signal to 1 and outputs it to the conjugate circuit 804. As a result, the conjugate circuit 804 is turned on when obtaining the Hermitian matrix of the input matrix, and the conjugate circuit 804 is turned off when there is no conversion or a transposed matrix.

  FIG. 12 is a flowchart illustrating an example of an instruction execution processing procedure. When instruction execution is started, the instruction decoder 304 acquires an instruction from the instruction memory 213 and decodes it (step S1201). Next, the data supply circuit 301 loads data based on the decoding result (step S1202). The data supply circuit 301 outputs or converts the input matrix as it is based on the decoding result and outputs it (step S1203).

  The operation data path 302 performs the operation, and the data store circuit 303 writes the operation result back to the memory 101 (step S1204). Then, the data supply circuit 301 determines whether or not processing of all the data of the stream has been completed (step S1205). If it is determined that the processing of all the data of the stream has not been completed (step S1205: No), the data supply circuit 301 returns to step S1202 and loads the data. If it is determined that the processing of all the data in the stream has been completed (step S1205: Yes), the command execution ends.

  FIG. 13 is an explanatory diagram showing a configuration example of a data supply circuit including a wraparound processing circuit. The input FIFO 1301 is a buffer queue capable of storing a plurality of data having a width M. M is a positive integer. Here, the input buffer 801 can store two 16 elements. In the example of FIG. 13, the data width of one element is up to 32 bits.

  Although not shown, the memory access unit reads the data having the data length of the source data stored in the data memory 214 and stores it in the input FIFO 1301 as one or a plurality of widths M. The data length of the source data, that is, the entire length of the source data to be calculated is also referred to as a stream length SLS. For example, when the arithmetic unit is a 2 × 2 real number matrix (arithmetic unit length UL = 4short) and 1000 matrices are to be operated, the stream length SLS is 4000 shorts.

  Specifically, the memory access unit reads M data equal to one line of the data memory 214 from the head of the data having the data length SLS stored in the data memory 214. One line of the data memory 214 is equal to the width of the bus between the data memory 214 and the data supply circuit 301. The memory access unit writes the data of width M received via the bus of width M between the data memory 214 and the data supply circuit 301 to the input FIFO 1301. The input FIFO 1301 can sequentially store the data of the width M, and can sequentially read from the data of the width M stored previously.

  The wrap-around processing circuit 401 repeats the operation of reading out data of width P by selecting P (≦ M) consecutive unit data from the input FIFO 1301 a plurality of times, thereby performing a plurality of operations from the input FIFO 1301. Read data of width P in order without gaps. Specifically, the wrap-around processing circuit 401 first has P (≦ M) consecutive units from the beginning among the M unit data of the data of the width M stored first in the input FIFO 1301. Select data. The wraparound processing circuit 401 may supply the selected P unit data to the matrix conversion circuit 402. However, when the data transfer width between the wraparound processing circuit 401 and the matrix conversion circuit 402 is fixed (for example, width M), the wraparound processing circuit 401 includes, for example, width M including the selected P unit data. May be supplied to the matrix conversion circuit 402. At this time, the MP unit data other than the selected P unit data may have any value.

  After selecting P consecutive unit data, the wraparound processing circuit 401 selects P consecutive unit data from the next unit data after the last selected unit data, and selects the selected P unit data. May be supplied to the operation data path 302. By repeating this, the wrap-around processing circuit 401 reads a plurality of data of width P from the input FIFO 1301 in order without any gaps. Note that when the unit data selected by the wraparound processing circuit 401 becomes the unit data at the end of the data of width M, the wraparound processing circuit 401 reads the data of the next width M from the input FIFO 1301. Then, the wrap-around processing circuit 401 may continue to select the head unit data and the subsequent unit data of the new width M data.

  Specifically, the multiplexer 1311 has 16 multiplexers 802. The multiplexer 802 selects P consecutive unit data designated by the WM control signal supplied from the WM control circuit 1312 from the data BUFOUT having a width of 64 output from the input buffer 801.

  The multiplexer 802 is a selection unit included in the matrix conversion circuit 402 described above. The matrix conversion control circuit 803 is a selection control unit included in the matrix conversion circuit 402.

  FIG. 14 is an explanatory diagram showing an example of element selection by the WM processing circuit and the matrix conversion circuit. The WM control circuit 1312 outputs a WM control signal so as to select elements stored in the input buffer 801-4 to the input buffer 801-19.

  The matrix conversion control circuit 803 outputs a TF control signal for obtaining a 2 × 2 transposed matrix. Specifically, for example, when obtaining a 2 × 2 transposed matrix, the matrix transformation control circuit 803 sequentially starts with 0, 2, 1, 3, 4, 6, 5, 7, 8, 10, 9 from the left multiplexer 802. , 11, 12, 14, 13, 15 are output so as to select a TF control signal.

  Here, since each multiplexer 802 has a large circuit scale, the scale of the data processing apparatus 100 increases. Therefore, in this embodiment, the multiplexer 1311 in the wrap-around processing circuit 401 and the multiplexer 802 in the matrix conversion circuit 402 are shared to merge element selection processing. As a result, the circuit scale can be reduced.

  The selection unit 611 selects the second control signal based on the position data storing a plurality of elements included in the first matrix among the predetermined number of elements stored in the input buffer 801 and the first control signal. Generate. The first control signal is a signal output by the matrix transformation control circuit 803. The second control signal is a signal indicating an element to be selected by each selection circuit among a predetermined number of elements stored in the input buffer 801. Then, the selection unit 611 selects and outputs one of a predetermined number of elements stored in the buffer based on the second control signal generated by each of the selection circuits.

  FIG. 15 is an explanatory diagram illustrating another configuration example of the data supply circuit including the wraparound processing circuit. The data supply circuit 301 includes an input FIFO 1301, an input buffer 801, a WM control circuit 1312, a matrix conversion control circuit 803, an index selection multiplexer 1501, a data selection multiplexer 1502, and a conjugate circuit 804.

  The index selection multiplexer 1501 and the data selection multiplexer 1502 are the selection unit 611. The index selection multiplexer 1501 receives the second control signal based on the position data storing a plurality of elements included in the first matrix among the predetermined number of elements stored in the buffer 601 and the first control signal. Generate. The second control signal is a signal indicating an element to be selected by each of the selection circuits among a predetermined number of elements stored in the buffer 601.

  Specifically, the index selection multiplexer 1501 has, for example, 16 multiplexers. Each of the 16 multiplexers receives a WM control signal that is position data, and outputs any data selection control signal based on a TF control signal that is a first control signal. The data selection control signal output from the index selection multiplexer 1501 is the second control signal.

  The data selection multiplexer 1502 selects and outputs one of the elements stored in the input buffer 801 based on the data selection control signal output by the index selection multiplexer 1501. Specifically, the index selection multiplexer 1501 selects and outputs 16 elements from 32 elements stored in the input buffer 801 based on the data selection control signal.

  In contrast to the multiplexer 1311 and the multiplexer 802 shown in FIG. 13, the index selection multiplexer 1501 and the data selection multiplexer 1502 shown in FIG. 15 are reduced from a 32-bit multiplexer to a 5-bit multiplexer. Comparing FIG. 13 with FIG. 15, the index selection multiplexer 1501 and the data selection multiplexer 1502 can reduce the circuit scale to about 1/6.

  FIG. 16 is an explanatory diagram showing an example of matrix conversion by the data supply circuit shown in FIG. Here, as shown in FIG. 7, an example of conversion from four 2 × 2 input matrices to two 2 × 2 transposed matrices is shown. In addition, here, elements included in four 2 × 2 input matrices are stored in the input buffer 801-4 to the input buffer 801-19.

  The matrix conversion control circuit 803 selects 0, 2, 1, 3, 4, 6, 5, 7, 8, 10, 9, 11, 12, 14, 13, 15 in order from the left data multiplexer 1501. A TF control signal is output. The WM control circuit 1312 outputs a WM control signal so as to select the input buffer 801-4 to the input buffer 801-19.

<Wrap-around processing circuit 401>
Here, a configuration and an operation example of the wraparound processing circuit 401 will be described in detail.

  FIG. 17 is a diagram (part 1) schematically illustrating processing of the memory access unit and the data supply circuit. The process shown in FIG. 17 is a process executed when SLS> M.

  As shown in FIG. 17A, the data memory 214 stores data having a stream length SLS. The stream length SLS is longer than the width M. Data of this stream length SLS is read for each width M by the memory access unit and stored in the input FIFO 1301. FIG. 17B shows data 51 stored in the input FIFO 1301. By selecting P (≦ M) continuous unit data from the data stored in the input FIFO 1301 and repeating the operation of reading the data of the width P a plurality of times, the input FIFO 1301 has a plurality of widths P. Data 61 to 64 are read sequentially without any gaps. Since the data 65 of the width P is applied to the end portion of the data 51, the data of the stream length SLS is read from the data memory 214 by the memory access unit before the data 65 of the width P is read, and the data is input to the input FIFO 1301. Stored as 52. As a result, the data 61 to 69 having a plurality of widths P can be sequentially read from the input FIFO 1301 without gaps. As shown in FIG. 17C, each of the data 61 to 69 having the width P is read out every calculation cycle, that is, one in each calculation cycle.

  In the operation example of FIG. 17, the data of the stream length SLS is read from the data memory 214 and stored as data 51 in the input FIFO 1301. After that, data having the same stream length SLS is read from the data memory 214 and stored as data 52 in the input FIFO 1301. Instead of such a configuration, the data 51 already stored in the input FIFO 1301 may be reused, and the data portion corresponding to the data 52 may be arranged in the input FIFO 1301.

  FIG. 18 is a diagram (part 2) schematically illustrating processing of the memory access unit and the data supply circuit. The process shown in FIG. 18 is a process executed when SLS ≦ M.

  As shown in FIG. 18A, the data memory 214 stores data having a stream length SLS. The stream length SLS is shorter than the width M. This stream length SLS data is loaded as data of width M by the memory access unit and stored in the input FIFO 1301. FIG. 18B shows data 70 stored in the input FIFO 1301. By selecting P (≦ M) continuous unit data from the data stored in the input FIFO 1301 and repeating the operation of reading the data of the width P a plurality of times, the input FIFO 1301 has a plurality of widths P. Data 71 to 75 are read sequentially without any gaps. However, in the case of the data 73 having the width P, the data 70 is applied to the end portion of the data 70, so that the data is returned to the front end portion of the data 70, and data is selected and read continuously from the front end portion. The same applies to the data 75 of the width P. In this way, the data 71 to 75 having a plurality of widths P can be sequentially read from the input FIFO 1301 without a gap. Each of the data 71 to 75 having the width P is read out every calculation cycle, that is, one in each calculation cycle.

  Here, the wrap-around processing circuit will be described in detail. In FIG. 19 and subsequent figures, illustration of the matrix conversion circuit 402 is omitted to describe the wraparound processing circuit.

  FIG. 19 is a diagram illustrating a detailed example of the wrap-around processing circuit. The wraparound processing circuit includes a data selection unit 1901 and a WM control circuit 1312. The data selection unit 1901 includes a selector circuit 1911, a buffer circuit 1912, a coupling circuit 1913, a multiplexer 1311, and a coupling circuit 1914. The multiplexer 1311 includes selectors 84-1 to 84-32.

  The data of the width M (32 short in this example) stored first in the input FIFO 1301 is read from the input FIFO 1301 in response to the POP signal “1” from the WM control circuit 1312, and passes through the selector circuit 1911. And stored in the buffer circuit 1912. In this example, the width M is 32short. At this time, the selector circuit 1911 selects the input on the right side of FIG. 19 according to “1” of the POP signal. In the state where the data of width 32 is stored in the buffer circuit 1912, the data of width 32 output from the input FIFO 1301 is the next data after the data stored in the buffer circuit 1912. The data of width 32 output from the input FIFO 1301 is the data of width 32 stored first at the present time.

  In response to “1” of the POP signal, the memory access unit reads the remaining data not yet stored in the input FIFO 1301 from the data of the stream length SLS from the data memory 214 and stores it in the input FIFO 1301 as subsequent data. May be stored. At this time, when the data read from the data memory 214 reaches the end of the data of the stream length SLS, the reading is resumed from the start of the data of the stream length SLS in response to “1” of the next POP signal. You can do it. In this case, as shown in FIG. 18B, the data may be stored in the input FIFO 1301 so that the start of the data of the stream length SLS continues without a gap from the end of the data of the stream length SLS read out before.

  The combining circuit 1913 outputs data BUFOUT having a width of 64, which is formed by arranging the data having one width 32 stored in the buffer circuit 1912 and the data having the next width 32 output from the input FIFO 1301. The length of the data BUFOUT is 1024 bits of 64 shorts × 16 bits.

  The multiplexer 1311 selects P consecutive unit data designated by the WM control signals SEL00 to SEL31 supplied from the WM control circuit 1312 from the data BUFOUT having a width of 64 output from the combining circuit 1913. Actually, since the output of the data selection unit 1901 has a width 32 (short), the selected P consecutive unit data may be arranged in a continuous part of the output data having the width 32. Specifically, the continuous part is, for example, a continuous part at the left end. Since the operation data path 302 targets only data having the data processing width P, the operation is performed on, for example, P unit data at the left end among the data of the width 32 output from the data selection unit 1901. do it.

  Specifically, the selector 84-1 selects and outputs 1 short unit data at the position indicated by the WM control signal SEL00 from the data BUFOUT having a width of 64. Further, the selector 84-2 selects and outputs 1 short unit data at the position indicated by the WM control signal SEL01 from the data BUFOUT having a width of 64. The same applies to the following, and the selector 84-32 selects and outputs 1 short unit data at the position indicated by the WM control signal SEL31 from the data BUFOUT having a width of 64.

  FIG. 20 is a diagram illustrating an example of the selection operation by the WM control circuit. In the example shown in FIG. 20, the width M is 32 (short), the stream length SLS is 34 (short), and the data processing width P is 8 (short). SLS_MOD and OFFSET shown in the table of FIG. 20 will be described later. Since the data processing width P is 8, only the WM control signals SEL00 to SEL07 supplied to the eight leftmost selectors 84-1 to 84-8 shown in FIG.

  First, the 32 unit data at the head of the data whose stream length SLS is 34 is stored in the buffer circuit 1912 in FIG. 19, and the remaining two unit data are stored at the left end of the data output from the input FIFO 1301. It is assumed that it is in a state that has been done. As described above, in the data output from the input FIFO 1301, following the above two unit data at the left end, on the right side, the head portion of the data having the stream length SLS of 34 is displayed. Data (first 30 unit data) is stored. In this way, the memory access unit continuously reads the data of the stream length SLS from the data memory 214 and stores it as subsequent data in the input FIFO 1301 continuously.

  In the first cycle (cycle = 0), the WM control signals SEL00 to SEL07 are “0” to “7”, and the unit data of 0th (leftmost) of the data BUFOUT of width 64 is 7th (from the leftmost). Up to the 8th unit data is selected. In the next cycle (cycle = 1), the WM control signals SEL00 to SEL07 are “8” to “15”, and 15 from the unit data of the eighth data BUFOUT having the width 64 (9th counting from the left end). Up to the unit data of the number (16th counting from the left end) is selected. Thereafter, the process proceeds in the same manner, and while using the buffer circuit 1912, data of a plurality of widths P are sequentially selected from the input FIFO 1301 and read out.

  In the fifth cycle (cycle = 4), the WM control signals SEL00 to SEL07 are “32” to “39”, and the unit data from the 32nd unit data to the 39th unit data of the data BUFOUT having a width of 64 are selected. The At this time, the POP signal becomes “1”. Therefore, in the next cycle, the two unit data at the end of the data whose stream length SLS is 34 and the next 30 unit data at the head are stored in the buffer circuit 1912 of FIG. Further, the following four unit data at the end of the data with the stream length SLS of 34 and the data at the head of the data with the stream length SLS of 34 (the head 28 unit data) are stored in the input FIFO 1301. Stored side by side in the output data part.

  In the sixth cycle (cycle = 5), the WM control signals SEL00 to SEL07 are “8” to “15”, and from the unit data of the eighth data BUFOUT of width 64 (the ninth counted from the left end). Up to 15th unit data (16th counting from the left end) is selected. Thereafter, the process proceeds in the same manner, and data of a plurality of widths P are sequentially selected and read from the input FIFO 1301 without gaps.

  FIG. 21 is a diagram illustrating another example of the selection operation by the WM control circuit. In the example shown in FIG. 21, the width M is 32 (short), the stream length SLS is 34 (short), and the data processing width P is 32 (short). SLS_MOD and OFFSET shown in the table of FIG. 21 will be described later. Since the data processing width P is 32, the following description focuses on the WM control signals SEL00 to SEL31 supplied to the 32 selectors 84-1 to 84-32 shown in FIG.

  First, the 32 unit data at the head of the data whose stream length SLS is 34 is stored in the buffer circuit 1912 in FIG. 19, and the remaining two unit data are stored at the left end of the data output from the input FIFO 1301. It is assumed that it is in a state that has been done. As described above, in the data output from the input FIFO 1301, following the above two unit data at the left end, on the right side, the head portion of the data having the stream length SLS of 34 is displayed. Data (first 30 unit data) is stored. In this way, the memory access unit continuously reads the data of the stream length SLS from the data memory 214 and stores it as subsequent data in the input FIFO 1301 continuously.

  In the first cycle (cycle = 0), the WM control signals SEL00 to SEL31 are “0” to “31”, and the unit data from the 0th (leftmost) unit data of the data BUFOUT having a width of 64 is the 31st (first). Up to the rightmost unit data is selected. At this time, the POP signal becomes “1”. Therefore, in the next cycle, the two unit data at the end of the data whose stream length SLS is 34 and the next 30 unit data at the head are stored in the buffer circuit 1912 of FIG. Further, the following four unit data at the end of the data with the stream length SLS of 34 and the data at the head of the data with the stream length SLS of 34 (the head 28 unit data) are stored in the input FIFO 1301. Stored side by side in the output data part.

  Also in the next cycle (cycle = 1), the WM control signals SEL00 to SEL31 are “0” to “31”, and the unit data from the 0th (leftmost) unit data of the data BUFOUT having a width of 64 is the 31st (first). Up to the rightmost unit data is selected. At this time, the POP signal becomes “1”. Accordingly, in the next cycle, the four unit data at the end of the data having the stream length SLS of 34 and the following 28 unit data at the head are stored in the buffer circuit 1912 of FIG. Further, the following 6 unit data at the end of the data having the stream length SLS of 34 and the data at the head of the data having the stream length SLS of 34 (the 26 unit data at the head) are input to the input FIFO 1301. Stored side by side in the output data part. Thereafter, the process proceeds in the same manner. While using the buffer circuit 1912, data of a plurality of widths P are sequentially selected and read from the input FIFO 1301 without any gaps.

  FIG. 22 is a diagram showing still another example of the selection operation by the WM control circuit. In the example shown in FIG. 22, the width M is 32 (short), the stream length SLS is 12 (short), and the data processing width P is 8 (short). The SLS_MOD and OFFSET shown in the table of FIG. 22 will be described later. Since the data processing width P is 8, only the WM control signals SEL00 to SEL07 supplied to the eight leftmost selectors 84-1 to 84-8 shown in FIG.

  First, it is assumed that twelve unit data of data having a stream length SLS of 12 are packed and stored on the left end side of the buffer circuit 1912 in FIG.

  In the first cycle (cycle = 0), the WM control signals SEL00 to SEL07 are any one of “0” to “7”, and the number 7 from the 0th (leftmost) unit data of the data BUFOUT having a width of 64. Up to the unit data (eighth counting from the left end) are selected. In the next cycle (cycle = 1), the WM control signals SEL00 to SEL07 are “8, 9, 10, 11, 0, 1, 2, 3”. Therefore, the unit data from the 8th (9th counted from the left end) to the 11th (12th counted from the left end) unit data of the data BUFOUT 64 of width 64, and then the 0th (leftmost end) unit data. From the unit data to the third unit data (fourth from the left end) is selected. Thereafter, the process proceeds in the same manner, and while using the buffer circuit 1912, data of a plurality of widths P are sequentially selected from the input FIFO 1301 and read out. In this read operation, since the stream length SLS is shorter than the width M, the POP signal does not become “1”.

  FIG. 23 is a diagram illustrating an example of the configuration of the WM control circuit. The WM control circuit 1312 illustrated in FIG. 23 includes an SLS_MOD circuit 2301, an SLS register 2302, and SEL_WRAP circuits 2303-1 to 2303-32. The WM control circuit 1312 includes an OFFSET register 2304, an ADD_OFFSET circuit 2305, a P subtraction circuit 2306, and a selector circuit 2307.

  FIG. 24 is a diagram illustrating an example of the configuration of the SEL_WRAP circuit. The SEL_WRAP circuit 2303 illustrated in FIG. 24 includes an SLS determination circuit 2401, an SLS subtraction circuit 2402, an N addition circuit 2403, a selector circuit 2404, a comparison circuit 2405, a 1 addition circuit 2406, and a selector circuit 2407. . In the case of the SEL_WRAP circuit 2303-1, the applied SLS_MOD signal is equal to the value stored in the SLS_MOD circuit 2301. In the subsequent SEL_WRAP circuits 2303-2 to 2303-32, the applied SLS_MOD signal is equal to the SLS_MOD_NEXT signal output from the preceding SEL_WRAP circuit 2303.

  FIG. 25 is a diagram illustrating an example of the configuration of the ADD_OFFSET circuit. An ADD_OFFSET circuit 2305 illustrated in FIG. 25 includes an adder circuit 2501, an OFFSET register 2502, an OFFSET register 2503, a selector circuit 2504, and a selector circuit 2505.

  Here, an example of the operation of the WM control circuit 1312 will be described with reference to FIGS. 20 and 23 to 25. In the initial state, the SLS_MOD signal stored in the SLS_MOD circuit 2301 is “0”. The OFFSET signal stored in the OFFSET register 2304 is “0”.

  In the example of FIG. 20, when SLS> M, the selector circuit 2404 shown in FIG. 24 selects a value obtained by adding N to the value of the OFFSET signal. This value N is a value indicating what number the SEL_WRAP circuit 2303 is, and is “0” in the case of the 0th SEL_WRAP circuit 2303-1 with “0” as the start number. Therefore, in the case of the SEL_WRAP circuit 2303-1, “0” obtained by adding “0” to the value of the OFFSET signal is the value of the output WM control signal SEL. Also, “1”, which is a value obtained by adding “1” to the SLS_MOD signal that is “0” by the 1 addition circuit 2406, is output as the SLS_MOD_NEXT signal.

  In the case of the next SEL_WRAP circuit 2303-2, “1” obtained by adding “1” to the value of the OFFSET signal is the value of the output WM control signal SEL. In the case of the SEL_WRAP circuit 2303-2, since the SLS_MOD signal to be applied is the SLS_MOD_NEXT signal having the value “1” from the previous stage, the value of the SLS_MOD_NEXT signal to be output is “2”. Similarly, in the case of the SEL_WRAP circuit 2303-n, the WM control signal SEL to be output is “n−1”, and the SLS_MOD_NEXT signal to be output is “n”. Here, n is a natural number. As a result, WM control signals SEL00 to SEL31 as shown in cycle 0 of FIG. 20 are generated.

  The selector circuit 2307 receives SLS_MOD_NEXT output from each of the SEL_WRAP circuits 2303-1 to 2303-32. The selector circuit 2307 further receives a value obtained by subtracting 1 from the data processing width P, in this example, “7” as a selection control signal. The selector circuit 2307 selects the SLS_MOD_NEXT signal that is the value “8” output from the 7th (that is, 8th) SEL_WRAP circuit 2303-8 when the 0th is the start number, and supplies the SLS_MOD_230 signal to the SLS_MOD circuit 2301. As a result, in the next cycle, the SLS_MOD signal stored in the SLS_MOD circuit 2301 becomes “8”.

  In SADD> M in the ADD_OFFSET circuit 2305 shown in FIG. 25, the selector circuit 2505 selects a value obtained by adding the value of the OFFSET signal to the data processing width P, and outputs it as an OFFSET_NEXT signal. This OFFSET_NEXT signal is stored in the OFFSET register 2304 shown in FIG. 23, and becomes the OFFSET signal in the next cycle. Therefore, the value of the OFFSET signal increases by P every cycle. However, in the cycle in which the value obtained by adding P to the value of the OFFSET signal by the addition circuit 2501 is “32”, the value stored in the OFFSET register 2502 is 1, and the POP_NEXT signal is “1”.

  This POP_NEXT signal is output from the WM control circuit 1312 as a POP signal. Further, only the lower 5 bits of the value obtained by adding P to the value of the OFFSET signal by the addition circuit 2501 are stored in the OFFSET register 2503, so that the value of the OFFSET_NEXT signal takes only a value in the range of “0” to “31”. It will be. That is, the OFFSET value stored in the OFFSET register 2304 repeats a value in the range of “0” to “31”. In this way, an OFFSET signal and a POP signal are generated as shown in the operation example of FIG. In FIG. 20, since the OFFSET value includes a value including the sixth bit, the value “32” is shown.

  Another example of the operation of the WM control circuit 1312 will be described with reference to FIGS. In the initial state, the SLS_MOD signal stored in the SLS_MOD circuit 2301 is “0”. The OFFSET signal stored in the OFFSET register 2304 is “0”.

  In the example of FIG. 22, since SLS ≦ M, the selector circuit 2404 shown in FIG. 24 selects the SLS_MOD signal. Therefore, in the case of the SEL_WRAP circuit 2303-1, the output WM control signal SEL is “0”. Also, “1”, which is a value obtained by adding “1” to the SLS_MOD signal that is “0”, is output as the SLS_MOD_NEXT signal. In the case of the next SEL_WRAP circuit 2303-2, since the SLS_MOD signal to be applied is the SLS_MOD_NEXT signal with the value “1” from the previous stage, the output WM control signal SEL is “1” and the SLS_MOD_NEXT signal to be output The value is “2”. Similarly, in the case of the SEL_WRAP circuit 2303-n, the WM control signal SEL to be output is “n−1”, and the SLS_MOD_NEXT signal to be output is “n”. Here, n is a natural number smaller than SLS.

  In the example of FIG. 22, since the stream length SLS is 12, in the case of the SEL_WRAP circuit 2303-12, the output of the comparison circuit 2405 shown in FIG. Then, “0” is selected by the selector circuit 2407, and the value of the SLS_MOD_NEXT signal to be output becomes “0”. Therefore, as shown in cycle 0 of FIG. 22, the WM control signals SEL00 to SEL31 are signals that repeat from “0” to “11”.

  The selector circuit 2307 receives SLS_MOD_NEXT output from each of the SEL_WRAP circuits 2303-1 to 2303-32. The selector circuit 2307 further receives a value obtained by subtracting 1 from the data processing width P as a selection control signal. In this example, the selector circuit 2307 receives “7” as a selection control signal. The selector circuit 2307 selects the SLS_MOD_NEXT signal that is the value “8” output from the 7th (that is, 8th) SEL_WRAP circuit 2303-8 when the 0th is the start number, and supplies the SLS_MOD_230 signal to the SLS_MOD circuit 2301. As a result, in the next cycle, the SLS_MOD signal stored in the SLS_MOD circuit 2301 becomes “8”.

  In the ADD_OFFSET circuit 2305 shown in FIG. 25, since SLS ≦ M, the selector circuit 2504 and the selector circuit 2505 select the value “0” and the POP_NEXT signal having the value “0” and the OFFSET_NEXT signal having the value “0”. Is output. Thereby, as shown in the operation example of FIG. 22, both the OFFSET signal and the POP signal are always “0”.

  FIG. 26 is a diagram illustrating a generation algorithm of each signal when SLS ≦ M. In the case of SLS ≦ M, the SLS_MOD_NEXT signal, the WM control signal SEL, and the POP signal are generated by the generation algorithm shown in FIG.

  FIG. 27 is a diagram illustrating a generation algorithm of each signal when SLS> M. In the case of SLS> M, the POP signal, the OFFSET signal, and the WM control signal SEL are generated by the generation algorithm shown in FIG.

  FIG. 28 is a diagram illustrating another example of the configuration of the WM control circuit. The WM control circuit 1312 shown in FIG. 28 includes an SLS determination circuit 2801, a selector circuit 2802, an SLS_MOD circuit 2803, a selector circuit 2804, a 1-adder circuit 2805, an SLS_MOD table (SLS_MOD_TBL) 2806, and a shifter circuit (shifter 384). 2807. The WM control circuit 1312 further includes an OFFSET register 2304, an ADD_OFFSET circuit 2305, a P subtraction circuit 2306, and a selector circuit 2307. 28, the same or corresponding elements as those of FIG. 23 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate.

  FIG. 29 is a diagram illustrating an example of data in the SLS_MOD table. As shown in FIG. 29, the SLS_MOD table 2806 stores 64 pieces of position data for 33 rows from No. 1 to No. 33. For example, as the position data having the value “0”, the unit data of the 0th (leftmost) unit is selected from the 64 unit data of the data BUFOUT output from the coupling circuit 1913 in FIG. Similarly, as the position data having a value n (n: integer from 0 to 63), the nth unit data is selected from the 64 unit data of the data BUFOUT output from the coupling circuit 1913 in FIG. As described above, the SLS_MOD table 2806 is a table that stores position data indicating the selection position of each unit data selected from data having a width of 2M.

  The shifter circuit 2807 shown in FIG. 28 receives position data from the SLS_MOD table 2806, shifts the received position data, and supplies the shifted position data to the multiplexer 1311 as the WM control signals SEL00 to SEL31. With this configuration, appropriate unit data can be selected by the multiplexer 1311 of the data selection unit 1901.

  In FIG. 28, the SLS determination circuit 2801 determines whether or not the stream length SLS is M or less. When SLS> M, the output of the SLS determination circuit 2801 is “0”, and the selector circuit 2802 selects and outputs the value “33”. Therefore, in this case, the 33rd row of the SLS_MOD table 2806 is selected, and 64 pieces of position data “0” to “63” are output as shown in the 33rd row of FIG. At this time, the selector circuit 2804 selects the value of the OFFSET signal stored in the OFFSET register 2304, the 1 addition circuit 2805 adds “1” to the value selected by the selector circuit 2804, and the value after the addition is shifted. This is supplied to the circuit 2807. The shifter circuit 2807 shifts the 64 position data supplied from the SLS_MOD table 2806 according to the value of the OFFSET signal, and outputs the shifted 64 position data as the WM control signal SEL. As a result, the WM control signal SEL described above is generated.

  When SLS ≦ M, the output of the SLS determination circuit 2801 is “1”, and the selector circuit 2802 selects and outputs the value of the stream length SLS. As a result, for example, as shown in FIG. 22, when the stream length SLS is 12, the 12th row of the SLS_MOD table 2806 is selected. That is, as shown in the twelfth line in FIG. 29, 64 pieces of position data that repeat values “0” to “11” are output from the SLS_MOD table 2806. At this time, the selector circuit 2804 selects the value of the SLS_MOD signal stored in the SLS_MOD circuit 2803, the 1 addition circuit 2805 adds “1” to the value selected by the selector circuit 2804, and the value after the addition is shifted. This is supplied to the circuit 2807. The shifter circuit 2807 shifts the 64 position data supplied from the SLS_MOD table 2806 according to the value of the SLS_MOD signal, and outputs the shifted 64 position data as the WM control signal SEL. As a result, a WM control signal SEL as shown in FIG. 13 is generated.

  In the WM control circuit 1312 of FIG. 23, the SEL_WRAP circuits 2303-1 to 2303-32 are cascaded in 32 stages. Therefore, it takes time for the SLS_MOD_NEXT signal to propagate through each stage, and there is a possibility that the selection operation by the data supply circuit 301 cannot be performed sufficiently fast. On the other hand, in the WM control circuit 1312 shown in FIG. 28, only a few stages of delay are generated by the shifter circuit 2807, and the selection operation by the data supply circuit 301 can be executed sufficiently fast.

  FIG. 30 is a diagram illustrating another example of the configuration of the data processing device. In FIG. 30, the same or corresponding elements as those of FIG. 3 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate.

  30 includes a plurality of data supply circuits 301-1 to 301-n, an operation data path 302, and a data store circuit 303. The data supply circuits 301-1 to 301-n respectively read a plurality of n source data (operands) stored in the data memory 214 and supply them to the operation data path 302. When two source data src0 and src1 are to be operated as in the example shown in FIG. 4, the data supply circuit 301-1 may read the source data src0, and the data supply circuit 301-2 may read the source data src1. . The configuration and operation of each of the data supply circuits 301-1 to 301-n may be basically the same as the configuration and operation of the data memory 214 described above. In the data processing apparatus of FIG. 30, it is possible to correspond to a plurality of n source data (operands).

  As described above, the data processing apparatus 100 performs an operation by outputting one of the matrices to be calculated from the input matrix and the transformation matrix obtained by replacing the arrangement of a plurality of elements of the input matrix. Thereby, matrix conversion and matrix operation can be performed with one instruction, and the number of data loads can be reduced. Therefore, it is possible to shorten the time required from loading of matrix data to matrix calculation.

  In addition, the data processing apparatus 100 may select one of the first matrix and the second matrix by a selection unit that outputs one of the first matrix and the second matrix, and an arithmetic instruction. A selection control unit that performs control to be output to the selection unit. As a result, the input matrix can be converted into a matrix to be calculated by a simple control process.

  In addition, the data processing apparatus 100 uses the index table that stores a control signal instructing the arrangement of a plurality of elements to be output to the selection unit corresponding to the number of row elements and the number of column elements after conversion. Instruct. As a result, the input matrix can be converted into a matrix to be calculated by simple processing.

  Further, in the data processing device 100, each of a predetermined number of selection circuits to which the selection unit can input a predetermined number of elements stored in the buffer is selected from among a plurality of elements included in the input matrix stored in the buffer. Select or output. Thereby, even if the number of each element of an input matrix is arbitrary, it can convert into the matrix of calculation object.

  In addition, the data processing device 100 stores the position information of the elements of the first matrix among the elements stored in the buffer, and the first control signal that indicates the position after replacement of the elements of the first matrix. A second control signal indicating each position after replacement is generated from the stored elements. As a result, the circuit scale of the multiplexer can be reduced. If the area of the data processing device which is a semiconductor integrated circuit can be reduced, the number of semiconductor integrated circuits obtained from one semiconductor wafer can be increased, so that the unit price of the semiconductor integrated circuit can be reduced. .

  Further, the first matrix and the second matrix may be a plurality of matrices. Thereby, a conversion matrix can be obtained for a plurality of matrices at once, and the time required from the data load to the arithmetic processing can be shortened.

  The data processing method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The program is recorded on a computer-readable recording medium such as a magnetic disk, an optical disk, or a USB (Universal Serial Bus) flash memory, and is executed by being read from the recording medium by the computer.

  Further, as described above, the data processing apparatus 100 described in the present embodiment can also be realized by an ASIC such as a standard cell or a structured ASIC, or a PLD such as an FPGA. Specifically, for example, the data processing apparatus 100 can be manufactured by defining the functions of the data processing apparatus 100 described above by HDL description, logically synthesizing the HDL description, and giving the ASIC or PLD.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary Note 1) A first matrix acquired from a memory by a target operation instruction is received, and the received first matrix includes the same elements as the plurality of elements included in the first matrix and is included in the first matrix A second matrix in which the arrangement of at least any two of the plurality of elements is exchanged, and a conversion unit that outputs a matrix to be calculated indicated by the calculation instruction,
An arithmetic unit that performs an operation instructed by the arithmetic instruction on the matrix to be calculated output by the conversion unit;
A data processing apparatus comprising:

(Supplementary note 2)
A selection unit that outputs one of the first matrix and the second matrix;
A selection control unit that performs control to cause the selection unit to output one of the first matrix and the second matrix in accordance with the arithmetic instruction;
The data processing apparatus according to claim 1, further comprising:

(Supplementary Note 3) The selection control unit
Instructing the arrangement of a plurality of elements included in the first matrix to be output to the selection unit for a plurality of elements in a specific arrangement included in the first matrix corresponding to the number of elements in a row and the number of elements in a column Based on the number of elements in a row and the number of elements in a column for the matrix to be calculated indicated by the calculation instruction from the storage unit that stores the value of the control signal, the value of the control signal is read out and the selection unit Output to
The selection unit includes:
Outputting a plurality of elements included in the first matrix, the calculation target matrix including a plurality of elements instructed by the control signal output from the selection control unit;
The data processing apparatus according to appendix 2, characterized in that:

(Supplementary Note 4) A buffer capable of storing a predetermined number of elements equal to or greater than the number of elements included in the first matrix, wherein the elements included in the first matrix acquired from the memory are arranged in a specific sequence. Has a buffer to store in,
The selection unit includes:
Each of the predetermined number of selection circuits capable of inputting the predetermined number of elements stored in the buffer uses any one of a plurality of elements included in the first matrix stored in the buffer as a control signal. Select and output based on
The selection control unit
Outputting a control signal indicating an element to be selected by each of the selection circuits among a plurality of elements included in the first matrix stored in the buffer;
The data processing apparatus according to appendix 2 or 3, characterized by the above.

(Supplementary note 5)
Position data storing a plurality of elements included in the first matrix among the predetermined number of elements stored in the buffer, and the control signal (hereinafter referred to as “first control signal”). Based on the predetermined number of elements stored in the buffer, a second control signal is generated to indicate an element to be selected by each of the selection circuits, and the second control signal generated by each of the selection circuits is generated. The data processing apparatus according to appendix 4, wherein any one of the predetermined number of elements stored in the buffer is selected and output based on the selection.

(Supplementary Note 6) The first matrix is a plurality of first matrices having the same number of row and column elements,
The second matrix is a plurality of second matrices having the same number of row and column elements,
Each of the plurality of second matrices includes at least any two elements of the plurality of elements included in the first matrix for each of the plurality of first matrices corresponding to each of the plurality of second matrices. The data processing device according to any one of appendices 1 to 5, wherein the data processing device is a matrix in which the arrangement of

(Supplementary note 7) When each of a plurality of elements included in the calculation target matrix has an imaginary part and a real part,
The converter is
Any one of Supplementary notes 1 to 6, further comprising: a conjugate part that outputs the matrix of the operation target after replacing the sign of the imaginary part of each of the plurality of elements included in the operation target matrix A data processing device according to any one of the above.

(Supplementary note 8) The data processing device according to any one of supplementary notes 1 to 7, wherein the second matrix is a transposed matrix of the first matrix.

(Supplementary note 9)
The first matrix acquired from the memory by the target operation instruction is received, and the received first matrix and the plurality of elements included in the first matrix including the same elements as the plurality of elements included in the first matrix Out of the second matrix in which the arrangement of at least any two of the elements is replaced, and outputs a matrix to be calculated indicated by the calculation instruction,
Performing the operation indicated by the operation instruction on the output matrix to be operated;
A data processing method.

DESCRIPTION OF SYMBOLS 100 Data processing apparatus 101 Memory 111 Conversion part 112 Operation part 200 Baseband processing LSI
201 RF unit 202 Dedicated hardware 203 DSP
205 Antenna 211 Processor 212 Peripheral Circuit 213 Instruction Memory 214 Data Memory 221 CPU
DESCRIPTION OF SYMBOLS 301 Data supply circuit 302 Operation data path 303 Data store circuit 304 Instruction decoder 401 Wraparound processing circuit 402 Matrix conversion circuit 501, 802, 1311 Multiplexer 601 Buffer 611 Selection part 612 Selection control part 621 Storage part 801 Input buffer 803 Matrix conversion control circuit 804 Conjugate circuit 805 Output buffer 811 Index table 812 Conjugate control circuit 1301 Input FIFO
1312 WM control circuit 1501 Index selection multiplexer 1502 Data selection multiplexer src0, src1 Source data sel0 to sel15 Data selection control signal, TF control signal SEL00 to SEL31 WM control signal

Claims (8)

The first matrix acquired from the memory by the target operation instruction is received, and the received first matrix and the plurality of elements included in the first matrix including the same elements as the plurality of elements included in the first matrix A second matrix in which the arrangement of at least any two of the elements is replaced, and a conversion unit that outputs a matrix to be calculated indicated by the calculation instruction;
An arithmetic unit that performs an operation instructed by the arithmetic instruction on the matrix to be calculated output by the conversion unit;
A data processing apparatus comprising: The converter is
A selection unit that outputs one of the first matrix and the second matrix;
A selection control unit that performs control to cause the selection unit to output one of the first matrix and the second matrix in accordance with the arithmetic instruction;
The data processing apparatus according to claim 1, further comprising: The selection control unit
Instructing the arrangement of a plurality of elements included in the first matrix to be output to the selection unit for a plurality of elements in a specific arrangement included in the first matrix corresponding to the number of elements in a row and the number of elements in a column Based on the number of elements in a row and the number of elements in a column for the matrix to be calculated indicated by the calculation instruction from the storage unit that stores the value of the control signal, the value of the control signal is read out and the selection unit Output to
The selection unit includes:
Outputting a plurality of elements included in the first matrix, the calculation target matrix including a plurality of elements instructed by the control signal output from the selection control unit;
The data processing apparatus according to claim 2. A buffer capable of storing a predetermined number of elements equal to or greater than the number of elements included in the first matrix, the buffer storing a plurality of elements included in the first matrix acquired from the memory in a specific sequence Have
The selection unit includes:
Each of the predetermined number of selection circuits capable of inputting the predetermined number of elements stored in the buffer uses any one of a plurality of elements included in the first matrix stored in the buffer as a control signal. Select and output based on
The selection control unit
Outputting a control signal indicating an element to be selected by each of the selection circuits among a plurality of elements included in the first matrix stored in the buffer;
The data processing apparatus according to claim 2 or 3, wherein The selection unit includes:
Position data storing a plurality of elements included in the first matrix among the predetermined number of elements stored in the buffer, and the control signal (hereinafter referred to as “first control signal”). Based on the predetermined number of elements stored in the buffer, a second control signal is generated to indicate an element to be selected by each of the selection circuits, and the second control signal generated by each of the selection circuits is generated. 5. The data processing apparatus according to claim 4, wherein one of the predetermined number of elements stored in the buffer is selected and output based on the selected element. The first matrix is a plurality of first matrices having the same number of row and column elements,
The second matrix is a plurality of second matrices having the same number of row and column elements,
Each of the plurality of second matrices includes at least any two elements of the plurality of elements included in the first matrix for each of the plurality of first matrices corresponding to each of the plurality of second matrices. The data processing apparatus according to claim 1, wherein the data processing apparatus is a matrix in which the arrangement of the above is exchanged. When each of the plurality of elements included in the matrix to be operated has an imaginary part and a real part,
The converter is
The imaginary part of each of a plurality of elements included in the matrix to be calculated is replaced with a sign, and a conjugate part that outputs the matrix to be calculated after the replacement is provided. The data processing device according to any one of the above. Computer
The first matrix acquired from the memory by the target operation instruction is received, and the received first matrix and the plurality of elements included in the first matrix including the same elements as the plurality of elements included in the first matrix Out of the second matrix in which the arrangement of at least any two of the elements is replaced, and outputs a matrix to be calculated indicated by the calculation instruction,
Performing the operation indicated by the operation instruction on the output matrix to be operated;
A data processing method.

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