JPH11110370A - Fast fourier transforming device and method, variable bit reverse circuit, inverse fast fourier transforming device and method and ofdm receiving and transmitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce needed storage capacity in a fast Fourier transforming device. SOLUTION: An even number symbol stored in a RAM 101 and an odd number symbol stored in a RAM 102 are undergone fast Fourier transform according to a RAM address that is produced by a RAM address generating part 105. A RAM address converting part 131 converts a dummy address DAD for input- output into a real address RDAD for input-output by performing bit reverse processing as many as the number of instructions of a bit reverse signal BBR for input-output and also converts a dummy address BAD for butterfly computation into a real address RDAD for butterfly computation by performing bit reverse processing as many as the number of instructions of a bit reverse signal BBR for butterfly computation. Data which make an index that represents an order among symbols common can be stored at the same address of the RAM 101 or the RAM 102, and the overlap of a symbol input and a symbol output is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fast Fourier transform (FFT) apparatus and method for performing a fast Fourier transform (FFT).

[0002]

2. Description of the Related Art In recent years, digitalization of television and radio broadcasting has been promoted with the progress of digital communication technology and semiconductor integrated technology. In digital broadcasting using terrestrial waves, OFDM (Orthogonal Fr
equency Division Multiplex). OFDM is a method for efficiently transmitting various information in a limited frequency band, and has a feature for terrestrial broadcasting that is resistant to multipath interference.
However, in OFDM, it is necessary to perform a large-scale fast Fourier transform of thousands of samples, and reducing the cost of the fast Fourier transform apparatus is an important issue for practical use.

As an example of a conventional fast Fourier transform device, A. Delaruelle et al. “A Channel Demodulator IC
for Digital Audio Broadcasting ”(IEEE Custom In
integrated Circuit Conference, May 1994). This fast Fourier transform device has three RAMs (Random Access Memory) as storage devices, and one of them is an input buffer RA for storing input data.
M and two are used as fast Fourier transform RAMs for storing intermediate data and output data at the time of calculation. If the data for the number of samples to be Fourier-transformed is one symbol,
In the processing of a plurality of consecutive symbols, the processing for the current symbol is performed using two fast Fourier transform RAMs, and the input data of the next symbol is stored in the input buffer RAM.

As another example of a conventional fast Fourier transform apparatus, E. Bidet et al.
entation of 8192 Complex Points FFT ”(IEEE Custom
Integrated Circuit Conference, May 1994). This fast Fourier transform device includes a predetermined number of pipeline registers between arithmetic units as a storage device, and performs processing by operating each arithmetic unit in a pipeline. When a pipeline register is used, the storage capacity is equivalent to the case where two RAMs are used. is there. In the fast Fourier transform device used for modulation and demodulation, it is preferable that the order of the input data and the output data is equal in order to reduce the processing after the fast Fourier transform. Do. As a result, the storage capacity is equivalent to the fast Fourier transform device using the three RAMs.

[0005]

The fast Fourier transform apparatus has one symbol of input data, intermediate data for calculation,
And a storage device for storing output data. Further, in the fast Fourier transform device used for modulation and demodulation, since it is necessary to process a plurality of continuous symbols, a storage device for storing input data of the next symbol in parallel with the process for the current symbol is further required. .
Since these storage devices occupy most of the fast Fourier transform device, the cost of the fast Fourier transform device can be reduced by reducing the required storage capacity.

[0006] The two examples shown as conventional fast Fourier transform devices are equivalent in terms of storage capacity. But A
In the case of realization with an SIC or the like, the former configuration in which a RAM library can be used as a storage device is more advantageous for cost reduction, and thus the former configuration is often used in an ASIC or the like.

However, in the former configuration using a RAM, one RAM having a storage capacity capable of storing data for one symbol is provided as one RAM for an input buffer,
Since a total of three RAMs are required for the fast Fourier transform RAM, there is a problem that the circuit scale of the fast Fourier transform apparatus increases. This problem becomes more pronounced as the number of samples per symbol increases.

Accordingly, in the present invention, R for fast Fourier transform is used.
If the input data of the next symbol can be written to the fast Fourier transform RAM after reading the output data stored in the AM, the function of the input buffer RAM can be provided to the fast Fourier transform RAM. We have newly focused on the point that the buffer RAM can be omitted.

When the input buffer RAM is omitted, the fast Fourier transform is performed as follows. First, the input data is stored in the fast Fourier transform RAM, the butterfly operation is performed while the intermediate data is stored in the fast Fourier transform RAM, and finally, the data stored in the fast Fourier transform RAM is read out as output data. .

However, in this case, a new problem arises.
Focusing on the input / output data stored in the fast Fourier transform RAM, the input and output data having a common index indicating the order in the symbol are stored in the same address of the fast Fourier transform RAM due to the feature of the fast Fourier transform algorithm. Not stored. Therefore, in a normal configuration, the input data of the next symbol is written in the order of the address from which the output data stored in the RAM is read, so that the order of the input data and the output data is different. In order to make the order of the input data and the output data equal, the data may be rearranged after storing the input data or the output data in the RAM.
It is necessary to add a data rearranging RAM having a storage capacity capable of storing data for symbols, and therefore, the storage capacity cannot be reduced as a result.

In view of the above problems, an object of the present invention is to realize a cost reduction by reducing a required storage capacity in a fast Fourier transform.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a method for storing data having a common index indicating the order in a symbol between output data of one symbol and input data of the next symbol in a RAM. In order to enable storage at the same address, the address for accessing the RAM is converted for each symbol. In other words, an operation equivalent to data rearrangement is realized by address conversion. In addition, address conversion is performed by using a bit reverse process for address conversion and changing the number of bit reverses for a reference address for each symbol.

Further, the present invention has been implemented in order to make it possible to store data having a common index indicating the order in a symbol between output data of one symbol and input data of the next symbol at the same address of the RAM. The fast Fourier transform process is changed for each symbol. For example, the butterfly operation by the time thinning method and the butterfly operation by the frequency thinning method are alternately performed for each symbol. The time thinning method and the frequency thinning method are equivalent as fast Fourier transforms, but the relationship between the order of input data and the order of output data becomes symmetric. By taking advantage of this, the data thinning method is unnecessary by alternately performing the time thinning method and the frequency thinning method.

With such a configuration, the empty area of the RAM after reading the output data can be used as an input buffer for storing the input data of the next symbol.
The input buffer RAM can be omitted. RAM
Reads the stored output data of one symbol and then writes the input data of the next symbol to the same address. Thus, by performing the processing of the even-numbered symbols using the first RAM and the processing of the odd-numbered symbols using the second RAM among the plurality of consecutive symbols, the configuration using two RAMs is realized. Will be possible.

[0015] Specifically, a solution taken by the invention of claim 1 is a fast Fourier transform (FFT).
m), a random access memory (RAM) that stores input data for each symbol, which is a group of data to be subjected to the fast Fourier transform, and a butterfly operation for the input data stored in the RAM. F that performs fast Fourier transform processing (FFT processing)
An FT processing unit, wherein the RAM stores, as output data of the one symbol, data obtained as a result of FFT processing by the FFT processing unit on input data of one symbol stored in the RAM. , Said F
In the FT processing unit, the output data of one symbol and the input data of another symbol stored in the RAM next to the output data of the one symbol have the same index indicating the order in the symbol. The FFT processing is performed so that the FFT processing is stored in the address.

According to the first aspect of the present invention, by the FFT processing of the FFT processing unit, in the output data of one symbol and the input data of the next symbol, data having a common index indicating the order in the symbol is the same in the RAM. It can be stored at the address. For this reason, the empty area of the RAM after reading the output data can be used as an input buffer for storing the input data of the next symbol,
The input buffer RAM can be omitted without adding a data rearranging RAM. This makes it possible to reduce the storage capacity required for the fast Fourier transform.

According to a second aspect of the present invention, in the fast Fourier transform apparatus according to the first aspect, the FFT processing section includes a RAM address generating section for generating an address for accessing the RAM, and the FFT processing section generates the address by the RAM address generating section. The RAM is accessed in accordance with the given address, and the RAM address generation unit outputs the output data of one symbol and the input data of another symbol stored in the RAM after the output data of the one symbol. The generated address is converted for each symbol so that data having a common index indicating the order in the symbol is stored at the same address in the RAM.

According to the second aspect of the present invention, the RAM address generation unit converts the address for accessing the RAM for each symbol, so that the output data of one symbol and the input data of the next symbol have the same order in the symbol. Can be stored at the same address in the RAM. In other words, an operation equivalent to data rearrangement can be realized by address conversion.

Further, in the invention according to claim 3, the RAM address generator in the fast Fourier transform apparatus according to claim 2 groups the bits of the address on the basis of the radix of the butterfly operation and changes the bit order on a group basis. It is assumed that the generated address is converted for each symbol by using the processing.

Further, in the invention according to claim 4, the RAM address generation unit in the fast Fourier transform apparatus according to claim 3 generates an address by repeatedly performing a bit reverse process on a reference address a predetermined number of times. If the number obtained by subtracting 1 from the number of times to return to the original address when the bit reverse process is repeatedly performed is defined as a maximum bit reverse number Rmax (Rmax is a positive integer), the RAM address generation unit performs It is assumed that the generated address is converted for each symbol by incrementing the number of times of the bit reverse process for each symbol from 0 to Rmax.

According to a fifth aspect of the present invention, in the fast Fourier transform apparatus of the fourth aspect, the FFT processing unit performs the FFT processing by preferentially using a radix-4 butterfly operation, and The number of times Rmax is 1
1 when the number of samples, which is the number of symbol data, is 4 ^m (m is a positive integer) and 2 ^m when the number of samples is 4 ^m · 2
It is assumed that

According to the sixth aspect of the present invention, the fourth aspect is provided.
The RAM address generation unit in the fast Fourier transform device of the present invention includes a variable bit reverse unit that repeats a bit reverse process a specified number of times, and the variable bit reverse units each perform a single bit reverse process, and are connected in series. It is assumed that one of the plurality of bit reverse circuits has a number corresponding to the designated number of bit reverses and performs the bit reverse, and the remaining ones pass through the data.

According to a seventh aspect of the present invention, in the fast Fourier transform apparatus according to the sixth aspect, the variable bit reverse section performs a bit reverse in accordance with a plurality of sample numbers. Bit shift means for bit shifting data bit-reversed by the plurality of bit reverse circuits so as to match valid bit positions with data is provided.

Further, in the invention of claim 8, the variable bit reverse section in the fast Fourier transform apparatus of claim 7 is provided with bit exchange means for exchanging bits at a stage preceding any of the plurality of bit reverse circuits. It is assumed that

According to the ninth aspect of the present invention, the first aspect of the present invention is provided.
The FFT processing unit in the fast Fourier transform device includes a butterfly operation unit that performs an FFT process using a butterfly operation on the input data stored in the RAM, wherein the butterfly operation unit uses different butterfly operations and is substantially And a plurality of types of FFT processing which are equivalent to the above, and in the output data of one symbol and the input data of another symbol stored in the RAM after the output data of this one symbol, The type of FFT processing to be executed is changed for each symbol so that data having a common index indicating the order is stored at the same address in the RAM.

According to the ninth aspect of the present invention, the butterfly operation unit changes the type of the FFT processing to be executed for each symbol, so that the output data of one symbol and the input data of the next symbol have the same order in the symbol. Can be stored at the same address in the RAM.

In a tenth aspect of the present invention, the butterfly operation unit in the fast Fourier transform apparatus according to the ninth aspect is characterized in that the butterfly operation unit uses a butterfly operation by a frequency decimation method.
The FT processing and the FFT processing using the butterfly operation based on the time thinning method are alternately performed for each symbol.

According to another aspect of the present invention, there is provided a fast Fourier transform apparatus for performing a fast Fourier transform, which stores input data for each symbol which is a set of data to be subjected to the fast Fourier transform. 2 RAM
And an FFT processing unit that performs fast Fourier transform processing (FFT processing) using butterfly operation on the input data stored in the first or second RAM.
And the second RAM stores data obtained as a result of the FFT processing by the FFT processing unit on the input data of one symbol stored in the RAM as output data of the one symbol. The fast Fourier transform apparatus performs FFT processing on even-numbered symbols using one of the first and second RAMs, and performs FFT processing on odd-numbered symbols using the other. The processing unit determines that the output data of the i-th (i is a positive integer) symbol and the input data of the (i + 2) -th symbol have the same index indicating the order in the symbol in the same data in the first or second RAM. FFT processing is performed so as to be stored in the address.

According to the eleventh aspect of the present invention, by the FFT processing of the FFT processing unit, in the output data of the i-th symbol and the input data of the (i + 2) -th symbol, data having a common index indicating the order in the symbol is obtained. , Can be stored at the same address in the first or second RAM. Therefore, the free area of the first or second RAM after reading the output data can be used as an input buffer for storing the input data of the next symbol, and the input data can be input without adding a data rearranging RAM. The buffer RAM can be omitted. Therefore, by performing the processing of the even-numbered symbols using the first RAM and the processing of the odd-numbered symbols using the second RAM among a plurality of consecutive symbols, a configuration using two RAMs is possible. And the storage capacity required for the fast Fourier transform can be reduced.

According to a twelfth aspect of the present invention, in the fast Fourier transform apparatus of the eleventh aspect, data input of the (i + 2) -th symbol is performed during the data output period of the i-th (i is a positive integer) symbol. Together with the (i + 1) -th symbol butterfly operation.

According to the thirteenth aspect of the present invention, in the fast Fourier transform apparatus according to the eleventh aspect, the FFT processing unit comprises:
A RAM address generation unit for generating an address for accessing the first and second RAMs, and the first or second R
A butterfly operation unit for performing a butterfly operation based on data stored in the AM, and selectively inputting and outputting the input data of the fast Fourier transform device or the operation result data of the butterfly operation unit to the first or second RAM; First
A data selection unit, a second data selection unit that receives output data of the first or second RAM as input, and selectively outputs the output data of the fast Fourier transform device or to the butterfly operation unit, and the RAM address generation. And a control unit for controlling the first and second data selection units, wherein the RAM address generation unit includes i (i is a positive integer)
In the output data of the symbol and the input data of the (i + 2) th symbol, data having a common index indicating the order in the symbol is stored in the first or second RAM.
The generated address is converted for each symbol so that the address is stored at the same address.

According to a fourteenth aspect of the present invention, in the fast Fourier transform apparatus according to the thirteenth aspect, the RAM address generating unit is configured to store the input data and the output data of one symbol in the first or second RAM. An input / output address generation unit for generating an input / output temporary address serving as a reference, and a butterfly operation temporary address serving as a reference for an address for storing intermediate data during butterfly operation of one symbol in the first or second RAM. A butterfly address generating unit for generating an address, and converting the temporary address for input / output generated by the input / output address generating unit into a real address for input / output and the temporary address for butterfly operation generated by the butterfly address generating unit. It is converted into a real address for butterfly operation, and the real address for input / output and the Of the address, while outputs one in the first RAM, it is assumed that a RAM address conversion unit for outputting the other to the second RAM.

Further, in the invention of claim 15, the RAM address conversion unit in the fast Fourier transform apparatus of claim 14 performs a bit reverse process on the input / output temporary address generated by the input / output address generation unit. A first variable bit reverse section for generating an input / output real address by performing the number of times indicated by the input / output bit reverse signal output from the control section, and a butterfly operation generated by the butterfly address generation section A second variable bit reverse unit that generates a real address for butterfly operation by performing a bit reverse process on the temporary address for the number of times indicated by the bit reverse signal for butterfly operation output from the control unit; The real address for input / output generated by the first variable bit reverse section And as input said second real address for the butterfly operation which is generated by the variable bit reverse unit, according to RAM selection signal outputted from the control unit, one to the address of the first RAM,
And an address selector for selecting and outputting the other as the address of the second RAM.

According to a sixteenth aspect of the present invention, in the fast Fourier transform apparatus according to the fifteenth aspect, when the bit reverse process is repeatedly performed, the number of times obtained by subtracting 1 from the number of times of returning to the original address is determined as the maximum number of bit reverse times Rmax ( R
max is a positive integer), and assuming that the data input period for one symbol is a symbol period, the control unit specifies the input / output bit reverse signal and the butterfly operation bit reverse signal every two symbol periods. It is assumed that the processing is updated so that the number of repetitions of the processing goes from 0 to Rmax in order.

According to the seventeenth aspect of the present invention, in the fast Fourier transform apparatus according to the fourteenth aspect, the RAM address conversion unit includes a temporary input / output address generated by the input / output address generation unit and the butterfly address generation unit. The generated temporary address for butterfly operation is input, and one is selected as a temporary address of the first RAM and the other is selected and output as a temporary address of the second RAM according to a RAM selection signal output from the control unit. An address selection unit for performing a bit reverse process on the temporary address of the first RAM selected and output by the address selection unit, and a first RAM output from the control unit
By performing the number of times specified by the use bit reverse signal, a first variable bit reverse unit for generating an address of the first RAM and a temporary address of the second RAM selectively output by the address selection unit are provided. On the other hand, the bit reverse processing is performed by the second R output from the control unit.
By performing the number of times specified by the AM bit reverse signal, the second RAM generates the second RAM address.
And a variable bit reverse section.

According to the eighteenth aspect of the present invention, in the fast Fourier transform apparatus according to the seventeenth aspect, when the bit reverse processing is repeatedly performed, the number of times 1 is subtracted from the number of times of returning to the original address is the maximum number of bit reverse times Rmax ( R
max is a positive integer) and assuming that the data input period for one symbol is one symbol period, the control unit transmits the first RAM bit reverse signal and the second RAM bit reverse signal for two symbol periods. Each time, the number of times of the designated bit reverse process is updated from 0 to Rmax in order.

According to a nineteenth aspect of the present invention, in the fast Fourier transform apparatus of the sixteenth or eighteenth aspect, the FFT processing section performs the FFT processing by preferentially using a radix-4 butterfly operation. The number of bit reverses Rmax is 4 when the number of samples, which is the number of data of one symbol, is 4.
^m (m is a positive integer) is 1 and the number of samples is 4 ^m
In the case of 2, it is assumed that it is 2 m.

In the twentieth aspect, the FFT processing unit in the fast Fourier transform apparatus according to the eleventh aspect is characterized in that:
A RAM address generation unit for generating an address for accessing the first and second RAMs, and the first or second R
A butterfly operation unit for performing a butterfly operation based on the data stored in the AM, and input data of the fast Fourier transform device or operation result data of the butterfly operation unit, the first RAM or the second RAM; A first data selection unit for selectively outputting to the RAM, and second data for selectively receiving and outputting the output data of the first or second RAM as output data of the fast Fourier transform device or to the butterfly operation unit. A selector for controlling the RAM address generator and the first and second data selectors, wherein the butterfly operation unit uses different butterfly operations and is substantially equivalent to a plurality of types. FFT processing can be performed, and the output data of the i-th (i is a positive integer) symbol and the input data of the (i + 2) -th symbol Index is common to represent the order in symbol Te data, to be stored in the same address of said first or second RAM, and shall change the type of FFT processing to be performed for each symbol.

According to a twenty-first aspect of the present invention, in the fast Fourier transform apparatus according to the twentieth aspect, the butterfly operation unit performs a butterfly decimation method on the symbol input data stored in the first or second RAM. A frequency decimation operation unit for performing an FFT process using an operation;
It is provided with a time thinning-out operation unit for performing FFT processing using a butterfly operation by a time thinning-out method on the input data of the symbols stored in the first or second RAM.

According to a twenty-second aspect of the present invention, there is provided a fast Fourier transform method for performing a fast Fourier transform using a RAM. The RAM
And a fast Fourier transform (FFT process) using a butterfly operation on the data to be transformed stored in the RAM in the first step, and the process result data is stored in the RAM. A second step of storing, and the RA in the second step.
And a third step of reading out the processing result data stored in the M from the RAM. The second step is a processing in which the processing stored in the RAM is performed in the Nth (N is a positive integer) iteration. Result data and (N +
1) The address for accessing the RAM is changed each time the data to be converted stored in the RAM in the first iteration is stored at the same address in the RAM so that the data having the same index indicating the order in the symbol is stored in the RAM. Is converted to

According to the twenty-second aspect, by converting the address for accessing the RAM at each repetition, the index indicating the order in the symbol is common to the output data of one symbol and the input data of the next symbol. Data to be stored can be stored at the same address in the RAM. In other words, an operation equivalent to data rearrangement is realized by address conversion. Therefore, the empty area of the RAM after reading the output data can be used as an input buffer for storing the input data of the next symbol, and the input buffer RAM is omitted without adding a data rearranging RAM. be able to. This makes it possible to reduce the storage capacity required for the fast Fourier transform.

According to a twenty-third aspect of the present invention, the second step in the fast Fourier transform method according to the twenty-second aspect is the step of grouping bits of an address based on a radix of a butterfly operation, and changing the order of bits in groups. It is assumed that the address for accessing the RAM is converted each time the repetition is performed by using a reverse process.

According to a twenty-fourth aspect of the present invention, in the fast Fourier transform method according to the twenty-third aspect, the step of repeating the bit reverse process for the address for accessing the RAM for a reference address a predetermined number of times is repeated. The number of times that one bit is subtracted from the number of times of returning to the original address when the bit reverse processing is repeatedly performed is the maximum bit reverse number Rmax
(Rmax is a positive integer), the second step is to increment the number of repetitions of the bit reverse processing for the reference address from 0 to Rmax by repeating the RA at each repetition.
The address for accessing M is converted each time it is repeated.

According to a twenty-fifth aspect of the present invention, in the fast Fourier transform method of the twenty-fourth aspect, the second step preferentially uses a radix-4 butterfly operation.
T processing, and the maximum number of bit reverse times Rma
x is the number of samples of 4 ^m (m
Is a positive integer) and 2 ^m when the number of samples is 4 ^m · 2.

A solution according to the twenty-sixth aspect of the present invention is a fast Fourier transform method for performing a fast Fourier transform using a RAM. And RA
M, and a fast Fourier transform (FFT) using butterfly operation on the data to be transformed stored in the RAM in the first step.
Processing), and storing the processing result data in the RAM. In the second step, the R
And a third step of reading out the processing result data stored in the AM from the RAM. The second step is to perform a plurality of types of FFT processing that use different butterfly operations and are substantially equivalent. And at the Nth (N is a positive integer) iteration the R
The processing is performed so that data having the same index indicating the order in the symbol in the processing result data stored in the AM and the data to be converted stored in the RAM in the (N + 1) -th repetition are stored at the same address in the RAM. The type of FFT processing to be performed is changed every time the processing is repeated.

According to the twenty-sixth aspect, the FF to be executed
By changing the type of T processing for each iteration,
In the output data of one symbol and the input data of the next symbol, data having a common index indicating the order in the symbol can be stored at the same address of the RAM. For this reason, the empty area of the RAM after reading the output data can be used as an input buffer for storing the input data of the next symbol.
The input buffer RAM can be omitted without adding M. This makes it possible to reduce the storage capacity required for the fast Fourier transform.

According to a twenty-seventh aspect of the present invention, in the fast Fourier transform method according to the twenty-sixth aspect, the second step is an F-th using a butterfly operation by a frequency decimation method.
It is assumed that the FT processing and the FFT processing using the butterfly operation based on the time thinning method are alternately performed at each repetition.

[0048] The solution means adopted in the invention of claim 28 is a variable bit reverse circuit for repeating a bit reverse process for a butterfly operation a designated number of times, each of which performs a single bit reverse process. A plurality of connected bit reverse circuits are provided, and among the plurality of bit reverse circuits, a number corresponding to the designated number of bit reverses performs bit reverse, and the remaining ones pass data.

According to a twenty-ninth aspect of the present invention, the variable bit reverse circuit of the twenty-eighth aspect performs a bit reverse in accordance with a plurality of sample numbers, and is effective for input data and output data. Bit shift means for bit shifting data bit-reversed by the plurality of bit reverse circuits so that the positions of the bits match are provided.

According to a thirtieth aspect of the present invention, in the variable bit reverse circuit of the thirty-ninth aspect, a bit exchange means for exchanging bits is provided at a stage preceding any one of the plurality of bit reverse circuits. I do.

Further, a solution taken by the invention of claim 31 is that the invention of claim 1 is applied to an inverse fast Fourier transform, and as an inverse fast Fourier transform device for performing an inverse fast Fourier transform, the input data is RAM for storing for each symbol which is a set of data to be subjected to inverse fast Fourier transform
And an IFFT processing unit for performing an inverse fast Fourier transform process (IFFT process) using a butterfly operation on the input data stored in the RAM, wherein the RAM stores one symbol of one symbol stored in the RAM. The data obtained as a result of the IFFT processing on the input data by the IFFT processing section is stored as the output data of the one symbol. The IFFT processing section outputs the output data of one symbol and the next data of the one symbol. In the input data of another symbol stored in the RAM, an IFFT process is performed so that data having a common index indicating the order in the symbol is stored at the same address of the RAM.

In the invention of claim 32, in the inverse fast Fourier transform apparatus of claim 31, the IFF
The T processing unit includes a RAM address generation unit that generates an address for accessing the RAM, and accesses the RAM in accordance with the address generated by the RAM address generation unit. The output data of the symbol and the output data of the one symbol, next to the input data of the other symbol stored in the RAM, are stored at the same address of the RAM with the same index indicating the order in the symbol. Thus, the generated address is converted for each symbol.

According to a thirty-third aspect, in the inverse fast Fourier transform apparatus according to the thirty-first aspect, the IFFT
A processing unit for input data stored in the RAM;
A butterfly operation unit that performs an IFFT process using a butterfly operation is provided. The butterfly operation unit can execute a plurality of types of IFFT processes that use different butterfly operations and are substantially equivalent to each other. And the input data of another symbol stored in the RAM next to the output data of this one symbol, data having a common index indicating the order in the symbol is stored at the same address of the RAM. Thus, the type of IFFT processing to be executed is changed for each symbol.

Further, a solution taken by the invention of claim 34 is an application of the invention of claim 22 to an inverse fast Fourier transform, and is an inverse fast Fourier transform method for performing an inverse fast Fourier transform using a RAM. A first step of storing data to be converted for one symbol, which is a group of data to be subjected to inverse fast Fourier transform, in a RAM;
A second step of performing an inverse fast Fourier transform process using a butterfly operation on the data to be converted stored in the RAM in the step, and storing processing result data in the RAM; and R
And a third step of reading the processing result data stored in the AM from the RAM. The second step includes processing the processing result data stored in the RAM in the Nth (N is a positive integer) iteration. Data and (N +
1) In the data to be converted stored in the RAM in the first repetition, the address for accessing the RAM is repeated so that data having a common index indicating the order in the symbol is stored at the same address in the RAM. It is converted into degrees.

Further, a solution taken by the invention of claim 35 is the application of the invention of claim 26 to an inverse fast Fourier transform, and is an inverse fast Fourier transform method for performing an inverse fast Fourier transform using a RAM. A first step of storing data to be converted for one symbol, which is a group of data to be subjected to inverse fast Fourier transform, in a RAM;
A second step of performing an inverse fast Fourier transform process (IFFT process) using a butterfly operation on the data to be converted stored in the RAM in the step of, and storing the processing result data in the RAM; And the third step of reading out the processing result data stored in the RAM from the RAM in the step (b) is repeated. The second step uses a plurality of kinds of butterfly operations which are different and are substantially equivalent. IFFT processing can be executed, and in the processing result data stored in the RAM in the Nth (N is a positive integer) iteration and the data to be converted stored in the RAM in the (N + 1) th iteration, Data having a common index indicating the order is stored at the same address in the RAM. As it is intended to change every time the repeated type of FFT processing to be executed.

Further, according to the invention of claim 36, the received OF
As an OFDM receiver for demodulating a DM signal into received data, a digital demodulation unit for demodulating an OFDM signal to a baseband signal, and performing a fast Fourier transform on the baseband signal demodulated by the digital demodulation unit;
A fast Fourier transform unit for decoding the complex data of the carrier wave, and generating the received data based on the complex data of the carrier wave, wherein the fast Fourier transform unit comprises the fast Fourier transform device according to claim 1. Things.

According to the 37th aspect of the present invention, as an OFDM transmitting apparatus for modulating transmission data into an OFDM signal, an inverse fast Fourier transform unit for performing an inverse fast Fourier transform on complex data of a carrier generated from the transmission data is provided. A digital modulation unit that performs frequency conversion on an output of the inverse fast Fourier transform unit to generate an OFDM signal, wherein the inverse fast Fourier transform unit is configured to perform
1 is an inverse fast Fourier transform device.

[0058]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A fast Fourier transform apparatus according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the fast Fourier transform apparatus according to the first embodiment of the present invention. FIG.
, 101 and 102 are first and second RAMs for storing input / output data and intermediate data at the time of butterfly operation.
(In FIG. 1, RAM # 0 and RAM # 1 are described.)
03, a butterfly operation unit for performing butterfly operation, 104
Is a rotator generator for generating a rotator used in butterfly computation, 105 is a RAM address generator for generating addresses for accessing the first and second RAMs 101 and 102, and 106 is a control for the RAM address generator 105 and the like. It is a control unit to perform.

As constituent elements of the RAM address generation unit 105, an input / output address generation unit 111 generates an input / output temporary address DAD which is a reference of a RAM address at the time of data input / output, and a reference numeral 112 denotes a RAM at the time of butterfly operation. Temporary address BAD for butterfly operation as a reference for address
The address generator 113 generates an input / output bit reverse signal DBR for the input / output temporary address DAD generated by the input / output address generator 111.
Performs a bit reverse process (details will be described later) the number of times specified by
The first variable bit reverse unit 114 that generates the AD performs bit reverse processing on the temporary address BAD for butterfly operation generated by the butterfly address generation unit 112 for the number of times indicated by the butterfly operation bit reverse signal BBR. The second variable bit reverse unit 115 that generates the real address RBAD for the butterfly operation by this means outputs the input / output real address RDAD output from the first variable bit reverse unit 113 and the output from the second variable bit reverse unit 114 The input of the real address RBAD for butterfly operation, which is input to the first RA
An address selection unit that selects and outputs the address of M101 and the other as the address of the second RAM 102. The first and second variable bit reverse units 113 and 114 and the address selection unit 115 constitute a RAM address conversion unit 131.

Reference numeral 121 denotes input of the input data of the fast Fourier transform device and the operation result data of the butterfly operation unit 103, one of which is selected as input data of the first RAM 101 and the other is selected as input data of the second RAM 102. A first data selection unit 122 for output receives the output data of the first and second RAMs 101 and 102 as input, selects one as output data of the fast Fourier transform device, and selects the other as input data of the butterfly operation unit 103. This is a second data selection unit to be output.

Butterfly operation section 103, rotor generation section 1
04, the RAM address generation unit 105, the control unit 106, and the first and second data selection units 121 and 122 constitute an FFT processing unit.

The operation of the fast Fourier transform apparatus according to the present embodiment configured as described above will be described below. In the following description, it is assumed that data for the number of samples to be subjected to Fourier transform is one symbol.

FIG. 2 is a timing chart showing processing timing in the fast Fourier transform apparatus according to the present embodiment. In the present embodiment, as shown in FIG.
Is an integer), after inputting the symbol,
A butterfly operation is performed during the (i + 1) -th symbol input period, and a symbol output after Fourier transform is performed during the (i + 2) -th symbol input period (hatched portion in FIG. 2). That is, in the present embodiment, assuming that one symbol input period is one symbol period, the symbol input, the butterfly operation of the immediately preceding symbol, and the two previous symbol outputs are performed in one symbol period. . In other words, during the i-th symbol input period,
(I-1) -th symbol butterfly operation and (i-
The 2) th symbol output is performed in parallel.

In the present embodiment, the operation described above is
This is realized by switching the two RAMs 101 and 102 as appropriate.

FIG. 3 is a timing chart showing the RAM switching timing in the fast Fourier transform apparatus according to the present embodiment. FIG. 3 shows the RAM switching timing when performing the fast Fourier transform of the number of samples N (N is a positive integer), and x (0) to x (N-1) represent input data (before conversion) in each symbol. Data), X (0)-X (N
-1) is output data (data after conversion) in each symbol. The FFT processing (i) (i is an integer) indicates the fast Fourier transform processing of the ith symbol.

In this embodiment, two RAMs 101 and 10
2 (RAM # 0, RAM # 1) is used to perform fast Fourier transform on even-numbered symbols, and use the other to perform fast Fourier transform on odd-numbered symbols. FIG.
As shown in (1), in the FFT processing (i), the input data x (0) to x (N-1) are converted to the first RA during the i-th symbol input period.
The data is stored in M101 (symbol input (i)), and during the period of the (i + 1) -th symbol input, a butterfly operation is performed while storing intermediate data in the first RAM 101 (butterfly operation (i)). The data stored in the first RAM 101 during the symbol input period is output data X
(0) to X (N-1) (symbol output (i)).
Similarly, the FFT processing (i-2) and the FFT processing (i + 2)
Of the FFT process (i.
-1) and FFT processing (i + 1) are executed using the second RAM 102.

The symbol input (i) and the symbol output (i-
2) is performed by using the same RAM and overlapping within one symbol period. As a result, two RAMs 1
01 and 102 are alternately used for each symbol period for symbol input / output or butterfly operation. Switching between the two RAMs 101 and 102 is performed by the data selection units 121 and 122.

Due to the overlap between the symbol input and the symbol output, one symbol period can be allocated as an operation period of the butterfly operation which requires a lot of RAM access and operation. This means that the first and second RAMs 1
It is possible to reduce the operation speed required for the first and the second arithmetic operation units 102 and 102 and to reduce the circuit scale of the butterfly operation unit 103.

FIG. 4 is a signal flow graph showing a radix 4 × 2 time thinning method as an example of the fast Fourier transform algorithm. FIG. 5 is a diagram showing operation elements in the signal flow graph. FIG. 4 is a signal flow graph when the number of samples N = 32, and x
(0) to x (N-1) are input data before conversion, and X (0) to X (N-
1) is output data after conversion, and Wi is a coefficient of rotator multiplication. Radix 4 × 2 means radix-4 butterfly operation and radix-2
Indicates that the operation is a combination of the butterfly operation.

As shown in FIG. 4, in the fast Fourier transform algorithm, a butterfly operation for several stages and rotator multiplication between stages are performed on input data x (0) to x (N-1). , And output data X (0) to X (N-1). In the radix 4 × 2 time thinning method shown in FIG. 4, a radix 4 butterfly operation is performed in the first two stages (stage 0, stage 1), and a radix 2 butterfly operation is performed in the final stage (stage 2).

As shown in FIG. 5, each operation is performed in accordance with the following operation formula. <Radix 4 butterfly operation> X0 = x0 + x1 + x2 + x3 X1 = x0-j.x1-x2 + j.x3 X2 = x0-x1 + x2-x3 X3 = x0 + j.x1-x2-j2-x3 <Radix 2 butterfly operation> X0 = x0 + x1 X1 = x0 −x1 <rotator multiplication> Y = y · W ⁱ W = e ^{−j · 2π / N}

In the fast Fourier transform algorithm, input data x (0) to x (N-1) and output data X (0) to X (N-1)
And the order is different. Base 4 shown in FIG.
In the × 2 hour thinning method, the output data X (j) is j
= 0, 1, 2, 3..., While the input data x (j) has discrete values of j = 0, 8, 16, 24.

In order to overlap the symbol input and the symbol output, it is necessary to perform the reading of the output data and the writing of the input data in parallel. For this purpose, the output data of one symbol and the next symbol are output. It is necessary to store the data having the same index indicating the order in the symbol between the input data and the input data at the same address in the RAM. Therefore, conventionally, in order to match the order in which the input data and the output data are stored in the RAM, for example, the order of the input data x (j) in the fast Fourier transform algorithm shown in FIG. It is necessary to rearrange the data such that j = 0, 1, 2, 3,... From the top.

On the other hand, in the present embodiment, processing equivalent to data rearrangement is realized by converting addresses accessing the RAM for each symbol by using bit reverse processing, thereby eliminating the need for data rearrangement. Is what you do. More specifically, by changing the number of repetitions of the bit reverse process for the reference address for each symbol (this is referred to as “variable bit reverse”), R
The address for accessing the AM is converted for each symbol.

FIGS. 6 and 7 are diagrams for showing the effect of the variable bit reverse of the address in the present embodiment, and FIG. 6 shows the RAM without the variable bit reverse of the address.
FIG. 7 is a diagram showing data transfer between RAMs, and FIG. 7 is a diagram showing data transfer between RAMs with variable bit reverse of addresses. FIG.
7 and FIG. 7 both show data transfer between RAMs when the number of samples N = 8, and show only one of the two RAMs provided in the fast Fourier transform apparatus. The one RAM stores input / output data of one of the even-numbered and odd-numbered symbols and intermediate data in the butterfly operation of the input data of the symbol.

In the FFT process [i], which is a fast Fourier transform for the i-th symbol, after input data x (0) to x (7) are stored in the RAM as symbol inputs,
Performs a butterfly operation while storing intermediate data at the time of the operation, reads out output data X (0) to X (7) stored in the RAM, and outputs a symbol.

In this case, in the inter-RAM data transfer without variable bit reverse of the address as shown in FIG.
The output data X (k) of the T processing [i] and the input data x (k) of the FFT processing [i + 2] are not always stored at the same address in the RAM. Therefore, after reading the output data X (k) of the FFT processing [i], the FFT processing [i] is performed at the same address.
+2] needs to be rearranged in order to store the input data x (k).

On the other hand, in the inter-RAM data transfer with variable bit reverse of the address according to the present embodiment as shown in FIG. 7, the input / output address and the butterfly operation address are changed for each FFT process by the bit reverse. , The RAM address at which the output data X (k) of the FFT process [i] is stored and the RAM address at which the input data x (k) of the FFT process [i + 2] are stored can be the same address. Thus, after reading the output data X (k) of the FFT processing [i], the FFT processing is performed on the same address.
The input data x (k) of [i + 2] can be stored, and the overlap between the symbol input and the output of the previous symbol can be realized.

Changes in the input / output address and the butterfly operation address are controlled by the number of bit reverses. The number of bit reverses is incremented for each FFT process, and is initialized to 0 after reaching the maximum number of bit reverses Rmax (Rmax is a positive integer). The maximum bit reverse number Rmax is a number obtained by subtracting 1 from the number of times of returning to the original address when the bit reverse processing is repeatedly performed, and is determined by the number of samples, the type of butterfly operation used for the FFT processing, and the like. In the example shown in FIG. 7, the maximum number of bit reverses Rmax is two, and the number of bit reverses is updated for each FFT process so as to cycle from 0 to 2.

FIG. 8 is a diagram showing an outline of bit reverse. Bit reverse is a method for calculating the order of data required for fast Fourier transform from the input order of data. Specifically, as shown in FIG. 8, first, binary bits indicating the data input order are grouped in order from the LSB in correspondence with each stage in the butterfly operation. Assuming that the number of bits corresponding to the stage s is r (s), r (s) = log ₂ (radix of the stage s) (1) (s = 0, 1,..., M-1: M is the number of stages) Becomes
Next, the bit reverse is performed by exchanging the upper and lower bits of the grouped bits while maintaining the bit positions in the group.

FIG. 9 is a diagram showing an example of the bit reverse, and is a diagram showing the bit reverse in the radix 4 × 2 time thinning-out method when the number of samples N = 32 as shown in FIG. When the number of samples N = 32, the binary number representing the data input order is 5 bits from N = 32 = ²⁵ . First, the binary numbers are grouped in order from the LSB corresponding to each stage in the butterfly operation. As shown in FIG. 4, a radix-4 butterfly operation is performed in stages 0 and 1, and a radix-2 butterfly operation is performed in stage 2.
From equation (1), r (0) = r (1) = log 2 4 = 2 r (2) = log 2 2 = 1 , and the thus the binary number representing the input order of the data L
SB is grouped into 2 bits, 2 bits, and 1 bit. After grouping, bit reverse is performed by exchanging upper and lower bits while maintaining the bit position in the group. As a result, as shown in FIG. 9, the bit sequence a4 a3 a2 a1 a0 before the bit reverse is converted into the bit sequence a1 a0 a3 a2 a4 by the bit reverse.

In the present embodiment, a variable bit reverse for repeating the bit reverse as shown in FIGS.
The M address is appropriately converted.

FIG. 10 is a diagram showing an example of an address change due to variable bit reverse, corresponding to the data transfer between RAMs shown in FIG. FIG. 7 shows the number of samples N =
Since the data transfer between RAMs in the radix 4 × 2 time thinning method in the case of 8 is shown, the number of bits of the address is changed from N = 8 = 2 ³ to 3 bits, and the address of 3 bits is LS.
The bits are grouped into 2 bits and 1 bit in order from B and bit-reversed. Therefore, from the tentative address a2 a1 a0 before the bit reverse, a real address a2 a1
1 a0 (bit reverse count = 0), a1 a0 a2 (bit reverse count = 1), and a0 a2 a1 (bit reverse count = 2) are generated by bit reverse. In addition, the sequence of numbers attached to the right of each address bit represents the order of addresses by each address bit in decimal.

FIG. 11 is a diagram showing a change in address due to variable bit reverse, and is a diagram corresponding to data transfer between RAMs in the radix 4 × 2 hour thinning method when the number of samples N = 32. In FIG. 11, since the number of samples N is 32 (= 2 ⁵ ), the number of bits of the address is 5, and
Assuming that a radix-4 butterfly operation is performed in stages 0 and 1 and a radix-2 butterfly operation is performed in stage 2,
The bit addresses are grouped into 2 bits, 2 bits, and 1 bit in order from the LSB and are bit-reversed. Therefore, the temporary address a4 a before the bit reverse
3 From a2 a1 a0, as a real address, a4 a3 a2
a1 a0 (bit reverse count = 0), a1 a0 a3 a2
a4 (number of bit reverse = 1), a2 a4 a0 a3
a1 (bit reverse frequency = 2), a3 a1 a4 a0 a
2 (the number of bit reverses = 3), and a0 a2 a1 a4
a3 (bit reverse count = 4) is generated by bit reverse.

FIG. 12 is a diagram showing an address change due to variable bit reverse, and is a diagram corresponding to data transfer between RAMs in the radix 4 × 2 hour thinning method when the number of samples N = 16. In FIG. 12, since the number of samples N is 16 (= 2 ⁴ ), the number of bits of the address is 4, and
Assuming that the radix-4 butterfly operation is performed in both stages 0 and 1, the bits of the address are grouped into 2 bits and 2 bits in order from the LSB, and the bits are reversed. Therefore, the temporary address a3 a before the bit reverse
2 From a1 a0, as a real address, a3 a2 a1 a0
(Number of bit reverses = 0) and a1 a0 a3 a2 (number of bit reverses = 1) are generated by bit reverse.

As is apparent from FIGS. 10 to 12, when the bit reverse of the address is repeated, the address always returns to the original address. Accordingly, the number of required real addresses is finite. Can be generated.

The maximum number of bit reverses Rmax is 2 in FIG. 10 because the bit reverse is repeated three times to return to the original address. Similarly, in the case of FIG. 11, the maximum bit reverse frequency Rmax is 4, and in the case of FIG. 12, the maximum bit reverse frequency Rmax is 1. When the radix 4 × 2 time thinning method is used with priority given to the radix 4 butterfly operation, the relationship between the number N of samples and the maximum number of bit reverses Rmax can be expressed by the following equation. When N = 4 ^m (m is a positive integer): Rmax = 1 When N = 4 ^m · 2 (m is a positive integer): Rmax = log ₂ N−1 = 2 m (2)

The detailed configuration and operation of each part of the fast Fourier transform apparatus according to the present embodiment shown in FIG.

FIG. 13 is a signal flow graph in the case where the number of samples N = 32, and shows the calculation order of the butterfly calculation in this embodiment. In FIG.
The number given to the part corresponding to the butterfly operation is the order of the butterfly operation in the present embodiment. In order to reduce the power consumption of the device, the butterfly operation is performed every 4 s (s is a stage number: s = 0, 1,...) From the top in the radix-4 stage so that the change in the coefficient of the rotor operation is reduced. In the radix-2 stage, butterfly computation is performed in order from the top.

The configuration and operation of each unit of the fast Fourier transform apparatus according to the present embodiment will be described assuming that processing is performed in the order of operation shown in FIG.

FIGS. 14 and 15 are timing charts showing signals for controlling the RAM address generation unit 105 generated and output by the control unit 106. FIG. In FIG.
DCN is an input / output timing signal for controlling the operation timing of the input / output address generation unit 111, and BCN and BST are a butterfly operation timing signal and a butterfly operation stage signal for controlling the operation timing of the butterfly address generation unit 112. Assuming that the number of samples is N,
The input / output timing signal DCN is a signal of log ₂ (N) bits, and its value is changed from 0 to (N
-1), and circulates every symbol period. Here, since N = 32, the input / output timing signal DCN is a signal of 5 (= log ₂ 32) bits. Further, if the number of stages of the butterfly operation is M, the value of the butterfly operation stage signal BST changes in order from 0 to (M−1) during one symbol period, and the butterfly operation timing signal BCN is changed to the butterfly operation stage. Signal B
During a period in which the value of ST is constant, it changes in order from 0 to (N-1).

In FIG. 15, DBR is an input / output bit reverse signal for controlling the first variable bit reverse section 113, BBR is a butterfly operation bit reverse signal for controlling the second variable bit reverse section, and RSL is an address. This is a RAM selection signal that controls the selection operation of the selection unit 115. Bit reverse signal BBR for butterfly operation
Are updated so as to circulate in order from 0 to the maximum number of bit reverses Rmax, and the input / output bit reverse signal DBR
Is 1 more than the bit-reverse signal BBR for butterfly operation.
It is updated so as to circulate sequentially from 0 to Rmax with a delay of the symbol period. Further, the RAM selection signal RSL switches between “H” level and “L” level every symbol period.

FIG. 16 is a timing chart showing the operation timing of the butterfly operation unit 103. The butterfly operation unit 103 performs three rotator multiplications and one radix-4 butterfly operation at a stage performing a radix-4 butterfly operation, and performs two rotator multiplications and two radix-2 operations at a stage performing a radix-2 butterfly operation. Perform butterfly operation. That is, an operation of four inputs and four outputs is performed. Therefore, as shown in FIG. 16, the butterfly operation unit 103 outputs the input data D0 read out from the first RAM 101 or the second RAM 102 via the second data selection unit 122.
ＤD3 are subjected to rotator multiplication and a radix-4 or radix-2 butterfly operation to output data X0 to X3. Data input / output is performed in each update cycle of the butterfly operation timing signal BCN generated by the control unit 106, and the output timing of the output data X0 to X3 is delayed by four cycles with respect to the input timing of the input data D0 to D3. Will be.

The input / output address generation unit 111 includes the control unit 1
The input / output timing signal DCN generated in step 06 is input to generate an input / output temporary address DAD. The input / output temporary address DAD is determined regardless of the number of bit reverses, and the input address generation unit 111 outputs the input / output timing signal DCN, which is a 5-bit signal, as it is as the input / output temporary address DAD.

The butterfly address generation unit 112 receives the butterfly operation timing signal BCN generated by the control unit 106 as an input, and outputs the butterfly operation temporary address B.
Generate AD. The temporary address BAD for the butterfly operation is determined by the stage number and the radix of the butterfly operation regardless of the number of bit reverses, and the butterfly address generator 112 uses a part or all of the bits of the butterfly operation timing signal BCN to perform the butterfly operation. A temporary address BAD for butterfly operation is generated according to the stage signal BST.

The first variable bit reverse section 113 receives the input / output temporary address DAD generated by the input / output address generation section 111 as an input, and receives the input / output temporary address DAD.
The bit reverse processing is performed on the AD the number of times specified by the input / output bit reverse signal DBR generated by the control unit 106, and an input / output real address RDAD is generated. Similarly, the second variable bit reverse unit 114
Receives the butterfly operation provisional address BAD generated by the butterfly address generation unit 112 and inputs the butterfly operation provisional address BAD to the control unit 106.
The bit reverse processing is performed the number of times specified by the butterfly operation bit reverse signal BBR generated by the above operation, and a butterfly operation real address RBAD is generated.

FIG. 17 is a diagram showing an example of the configuration of the first and second variable bit reverse units 113 and 114.

FIG. 17A shows an example of the configuration of the selector format, in which an address without bit reverse and a one-time bit reverse section 5 are applied to an input temporary address DAD (BAD).
01, the address resulting from performing the bit reverse once, the twice the address resulting from performing the bit reverse twice by the bit reverse section 502,..., The address resulting from performing the bit reverse Rmax times using the Rmax times bit reverse section 503. Are generated, and the selector 504 selects a bit reverse signal DBR from the generated addresses.
(BBR) to selectively output the real address RDAD (RBAD).

FIG. 17 (b) shows an example of a table format configuration in which each address obtained as a result of bit-reversing a temporary address DAD (BAD) is stored in a table (ROM) in advance.
505 and the input temporary address DAD
A bit connection circuit 506 is provided at the upper (or lower) of (BAD).
The real address RDAD (RBAD) is read from the table 505 using the data to which the bit reverse signal DBR (BBR) is connected as a reference address.

FIG. 18 shows an input / output address generator 111 and a first variable bit reverser 113 according to this embodiment.
FIG. 4 is a diagram showing an operation of generating an input / output address according to an embodiment of the present invention, showing a correspondence between an input / output timing signal DCN and an input / output bit reverse signal DBR, an input / output tentative address DAD, and an input / output real address RDAD. . As shown in FIG. 18, the input / output temporary address DAD is always equal to the input / output timing signal DCN regardless of the value of the input / output bit reverse signal DBR. The input / output real address RDAD is LS
B is grouped into 2 bits, 2 bits, and 1 bit from B, and the bit reverse is repeated the number of times of the value of the input / output bit reverse signal DBR.

FIG. 19 shows the butterfly address generator 112 and the second variable bit reverser 1 in this embodiment.
14 is a diagram showing the operation of generating a butterfly operation address by the B.14, and includes a butterfly operation timing signal BCN, a butterfly operation stage signal BST, a butterfly operation bit reverse signal BBR, a butterfly operation temporary address BAD, and a butterfly operation real address RBAD. FIG. As shown in FIG. 19, the butterfly operation temporary address BAD is determined according to the butterfly operation stage signal BST with reference to the butterfly operation timing signal BCN, regardless of the value of the butterfly operation bit reverse signal BBR. Also, the real address RBAD for butterfly operation is 2 bits, 2 bits, from LSB with respect to the temporary address BAD for butterfly operation.
Bit reverse is repeated as many times as the value of the butterfly operation bit reverse signal BBR, grouped as one bit.

The address selection unit 115 outputs the input / output real address R output from the first bit reverse circuit 113.
The DAD and the real address RBAD for butterfly operation output from the second bit reverse circuit 114 are input, and the RAM selection signal RSL input from the control unit 106 is input.
, One is selected as the address of the first RAM 101 and the other is selectively output as the address of the second RAM 102.

FIG. 20 is a diagram showing a configuration of the address selection unit 115. As shown in FIG. In FIG. 20, reference numerals 601 to 603 denote selection circuits, and 611 to 614 denote registers. The address selection unit 11 of the first and second RAMs 101 and 102
5 outputs the real address RDAD for input / output.
After reading the output data stored at the specified address RDAD, M writes the input data to the same address. On the other hand, the RAM to which the real address for butterfly operation RBAD is output by the address selection unit 115 is similarly
After reading the data stored at the specified address RBAD as input data of the butterfly operation unit 103,
The output data of the butterfly operation unit 103 is written to the same address.

However, as shown in FIG. 16, the data output from the butterfly operation unit 103 is delayed in timing with respect to the data input, so that the address selection unit 115 sets the butterfly operation address RBAD for a predetermined period as shown in FIG. Registers 611 to 614 for holding are provided. The registers 611 to 614 operate in synchronization with the update cycle of the butterfly operation timing signal BCN. By serially connecting such registers in four stages, the address selection unit 115 allows the data output of the butterfly operation unit 113 to be input to the data input. The real address RBAD for butterfly operation can be held for four cycles that are delayed with respect to the above. The selection circuit 603 includes a real address RBAD for butterfly operation.
And the real address R for butterfly operation delayed by four periods
One of the BADs is selectively output in accordance with the butterfly operation address selection signal BADSL. Selection circuit 6
01 and 602 are, according to the RAM selection signal RSL, one of the input / output real address RDAD and the butterfly calculation real address RBAD output from the selection circuit 603 as the address of the first RAM 101 and the other as the second RAM. Selectively output as an address of the RAM 102.

FIGS. 21 and 22 show the address selector 115.
6 is a timing chart showing a RAM access timing using a RAM address output from the RAM, that is, a RAM address generated by the RAM address generation unit 105. FIG.
1 is a diagram showing the access timing of the RAM in data input / output, and FIG.
FIG. 3 is a diagram illustrating access timing of AM. 21 and 22, hatched portions indicate RAs of the same address.
M access.

As shown in FIG. 21, in data input / output,
The update cycle of the input / output timing signal DCN is divided into halves, and the RAM access is performed with the first half as a read cycle and the second half as a write cycle. At this time, data reading and data writing in one update cycle of the input / output timing signal DCN are performed on the same address.

On the other hand, in the butterfly operation, as shown in FIG. 22, the update cycle of the butterfly operation timing signal BCN is divided into halves, and the first half is a read cycle and the second half is a write cycle, and RAM access is performed. At this time,
Data reading in one update cycle of the butterfly operation timing signal BCN and data writing in an update cycle four cycles delayed from the one update cycle are performed on the same address.

As described above, the present embodiment employs the RA
The address for accessing M is converted for each symbol by changing the number of bit reverses with respect to the reference address for each symbol, whereby the output data of one symbol and the input data of the next symbol are converted. , Data having a common index indicating the order in the symbol can be stored at the same address in the RAM. That is, the input data of the next symbol can be written to the same address after reading the output data of one symbol from the RAM, and the empty area of the RAM after reading the output data stores the input data of the next symbol. Since it can be used as an input buffer, an input buffer RAM is not required. Accordingly, by performing the processing of the even-numbered symbols of the plurality of consecutive symbols using the first RAM and appropriately switching the RAMs to perform the processing of the odd-numbered symbols using the second RAM, A configuration with one RAM becomes possible.

The configuration of variable bit reverse sections 113 and 114 shown in FIG. 17 is for a case where the number of samples is fixed. On the other hand, when a fast Fourier transform device is used for a communication device, it must be possible to execute fast Fourier transform of several types of samples according to the communication standard. In order for the fast Fourier transform apparatus according to the present embodiment to handle a plurality of samples, it is necessary to configure the variable bit reverse units 113 and 114 so that addresses can be generated for each number of samples. In other words,
A variable bit reverse circuit capable of executing a plurality of variable bit reverses having different conversion patterns is required.

For example, by providing a configuration as shown in FIG. 17A for each number of samples, it is possible to configure a variable bit reverse circuit capable of generating an address for each number of samples. However, in this case, the circuit scale becomes enormous, which leads to an increase in the circuit scale of the RAM address generation unit 105, which is not preferable.

Therefore, in the present embodiment, a configuration of a variable bit reverse circuit that realizes a plurality of variable bit reverses having different conversion patterns by a small-scale circuit will be described.

FIG. 23 is a diagram showing another example of the structure of the first and second variable bit reverse units 113 and 114.
FIG. 9 is a circuit diagram showing a variable bit reverse circuit that realizes a plurality of variable bit reverses having different conversion patterns with a small-scale circuit. Specifically, the variable bit reverse circuit shown in FIG. 23 is configured to be able to execute the variable bit reverse for the number of samples N = 4, 8, 16, and 32, respectively. In FIG. 23, 701 to 704 are bit reverse circuits (BR), 711 is a bit exchange circuit (BC) as bit exchange means, and 721 is a barrel shifter (BS) as bit shift means.

FIG. 24 is a circuit diagram showing the configuration of each circuit constituting the variable bit reverse circuit shown in FIG. 23. In FIG. 24, (a) shows the configuration of the bit reverse circuit BR, and (b)
Shows the configuration of the bit exchange circuit BC, and (c) shows the configuration of the barrel shifter BS.

As shown in FIG. 23, each of the bit reverse circuits 701 to 704 has a bit reverse control signal BRSEL.
Is controlled by each bit. Then, as shown in FIG. 24A, each of the bit reverse circuits 701 to 704
When the corresponding bit of the bit reverse control signal BRSEL is "0", the input data is passed through and output as it is. × Perform bit reverse in a 2-hour thinning method. Switching of the operation is performed by the selector 801 according to the bit reverse control signal BRSEL.

The bit exchange circuit 711 is controlled by a bit exchange control signal BCSEL. And FIG.
As shown in (b), when the bit exchange control signal BCSEL is "0", the input data is passed through and output as it is. On the other hand, when the bit exchange control signal BCSEL is "1", the bits of the input data are inverted and output. The operation is switched by the bit exchange control signal BC.
This is performed by the selector 802 according to SEL.

Further, the barrel shifter 721 is controlled by a shift control signal BSSEL (2 bits).
As shown in (c), a selector 803 switched and controlled by a lower bit of a shift control signal BSSEL and a selector 804 switched and controlled by an upper bit are connected in series. The selector 803 outputs the shift control signal BS
When the lower bit of SEL is “0”, the input data is passed through and output as it is, and when it is “1”, the input data is set to 1
Shift right by bits. When the upper bit of the shift control signal BSSEL is “0”, the selector 804 passes through the input data and outputs it as it is, and when the upper bit is “1”, shifts the input data to the right by 2 bits. With such an operation, the data input to the barrel shifter 721 remains “01” when the shift control signal BSSEL is “00”.
Is shifted right by one bit, is shifted right by two bits when is "10", is shifted right by three bits when is "11", and is output.

FIG. 25 is a diagram showing set values of respective control signals of the variable bit reverse circuit shown in FIG.
(A) is the number of samples N = 32, (b) is the number of samples N =
16, (c) shows the set value of each control signal when the number of samples N = 8, and (d) shows the set value of each control signal when the number of samples N = 4.

The bit reverse control signal BRSEL changes according to the number of bit reverses, and the bit reverse circuit 7
The value is set so that only the number of bit reverses from the input side among 01 to 704 performs the bit reverse. For example, when the number of samples N = 32, FIG.
As shown in the following, the bit reverse control signal BRSEL is
When the number of bit reverses is 1, the bit reverse circuit 7
Only “01” is set to “0001” so that the bit reverse is performed, and when the number of bit reverses is 3, “0111” is set so that only the bit reverse circuits 701 to 703 perform the bit reverse.

The bit exchange control signal BCSEL changes according to the number of bit reverses only when the number of samples N = 8, and is set to “1” only when the bit reverse circuit 701 performs the bit reverse. That is, the bit exchange circuit 711 performs bit exchange only when the number of samples N = 8 and the number of bit reverses is 1 or 2.

The shift control signal BSSEL has the number of samples N
In the case other than = 32, the value becomes a value other than "00" when the number of bit reverses is an odd number. The value is set according to the number of samples. When the number of samples N = 16, it becomes “01” as shown in FIG. 25B, and when the number of samples N = 8, it becomes “10” as shown in FIG. In the case of 4, it becomes "11" as shown in FIG. That is, the barrel shifter 721 shifts the data right by one bit when the number of bit reverses is 1 when the number of samples N = 16, and shifts the data right by 2 bits when the number of bit reverses is 1 when the number of samples N = 8. When the number of samples N = 4, the data is shifted right by 3 bits when the number of bit reverses is 1.

The operation of the variable bit reverse circuit shown in FIG. 23 will be described by taking a case where the number of samples N = 8 as an example. In this case, as shown in FIG. 10, the variable bit reverse starts from the tentative address a2 a1 a0 before the bit reverse, and a2 a1 a0 (bit reverse count = 0), a1 a0 a2 (bit reverse count =
1), a0 a2 a1 (the number of bit reverses = 2).

FIG. 26 shows a case where the number of samples N = 8.
It is a diagram showing the operation of the variable bit reverse circuit shown in FIG.
In the figure, (a) shows that when the number of bit reverses is 1,
(B) shows the operation when the number of bit reverses is 2.

When the number of bit reverses is one,
As shown in (a), bit exchange, bit reverse, and 2-bit shift are performed. That is, since the bit exchange control signal BCSEL becomes "1", bit exchange is performed by the bit exchange circuit 711, and the bit reverse control signal BRSEL becomes "0001", so that only the bit reverse circuit 701 performs bit reverse.
Further, since the bit shift control signal BSSEL becomes “10”, the barrel shifter 721 performs a bit shift of 2 bits. The lower three bits of the bit string generated by such an operation become an effective address, and a1 a0 a2 is generated as an actual address from address a2 a1 a0.

When the number of bit reverses is 2, FIG.
As shown in (b), bit exchange and two bit reverses are performed. That is, the bit exchange control signal B
Since CSEL becomes “1”, bit exchange is performed by the bit exchange circuit 711 and the bit reverse control signal BR
Since SEL becomes “0011”, the bit reverse circuit 7
Bit reverse is performed by 01 and 702. On the other hand, since the bit shift control signal BSSEL becomes “00”, the bit shift by the barrel shifter 721 is not performed. The lower three bits of the bit string generated by such an operation become the effective address, and the tentative address a2 a1 a
From 0, a0 a2 a1 is generated as a real address.

If the number of bit reverses is 1 or 2 when the number of samples N = 8, an erroneous real address will be generated unless bit exchange is performed. FIG. 27 is a diagram showing the operation in the case of no bit exchange. When the number of bit reverses is 1, a1 a0 a3 is generated as a real address as shown in FIG. As shown in (b), a0, a3, and a1 are generated as real addresses, and both malfunction.

A configuration method and a control method when the variable bit reverse circuit according to the present embodiment is generally extended will be described. In the description here, the following variables are used. N (i) ... number of corresponding samples, where N (i) = 2 ⁱ (i is a positive integer: Mmin ≤ i ≤ Mmax) Rmax (i) ... maximum number of bit reverses AD [0 in sample number N (i) ] To AD [Mmax -1] ... address for performing variable bit reverse

<Structure> Bit Reverse Circuit BR The number of stages is set to enable variable bit reverse of the number of samples N (Mbr). Here, it is assumed that Mbr = Mmax (when Mmax is an odd number) and Mbr = Mmax + 1 (when Mmax is an even number). That is, Mbr is always an odd number. Therefore, Becomes -Bit exchange circuits BC At the bit positions of AD [m] and AD [m-1] (m is an odd number other than Mbr), ((m-1) / 2) bit exchange circuits are bit-input from the input side. It is inserted every two stages of the reverse circuit BR. Barrel shifter BS A barrel shifter BS having the maximum shift number (Mmax-Mmin) is provided next to the last stage of the bit reverse circuit BR.

FIG. 28 shows the number of samples N = 2 ⁱ (2 ≦ 2) according to the present embodiment, which is configured by the above configuration method.
FIG. 14 is a configuration diagram of a variable bit reverse circuit that can support i ≦ 11).

<Control Method> Bit Reverse Circuit BR The bit reverse circuits BR for the number of bit reverse operations from the input side are operated. -Bit exchange circuit BC In the case of the number of samples N (m) (m is an odd number other than Mbr), when the number of bit reverses is other than 0, AD [m],
The bit exchange circuit BC at the bit position of AD [m-1]
Only those on the input side of the operating bit reverse circuit BR are operated. Barrel shifter BS In the case of the number of samples N (n), when the number of bit reverses is an odd number, a right shift operation is performed by (Mmax-n) bits.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 29 is a block diagram showing the configuration of the fast Fourier transform device according to the second embodiment of the present invention. The fast Fourier transform apparatus according to the present embodiment differs from the fast Fourier transform apparatus according to the first embodiment shown in FIG. 1 only in the internal configuration of the RAM address generation unit and a part of the control signal. Only the generation unit 205 and the control unit 206 are shown. In the fast Fourier transform apparatus according to the present embodiment, the RAM address generation unit 105 and the control unit 106 in the configuration of FIG.
The address generator 205 and the controller 206 are replaced. Butterfly operation unit 103, rotor generation unit 10
4. The FFT processing unit includes the RAM address generation unit 205, the control unit 206, and the first and second data selection units 121 and 122.

The RAM address generation unit 205 according to the present embodiment shown in FIG.
The difference from the AM address generation unit 105 is that the first and second
Is provided with an address selection section 215 in the preceding stage of the variable bit reverse sections 113 and 114.

The input / output address generation unit 111 receives the input / output timing signal DCN and inputs / outputs the temporary input / output address D.
Generate and output AD. On the other hand, the butterfly address generation unit 112 receives the butterfly operation timing signal BCN and the butterfly operation stage signal BST, and generates and outputs a butterfly operation temporary address BAD. These operations are the same as in the first embodiment.

The address selection unit 215 receives the input / output temporary address DAD output from the input / output address generation unit 111 and the butterfly operation temporary address BAD output from the butterfly address generation unit 112, and inputs the address according to the RAM selection signal RSL. , One as a temporary address in the first RAM 101 and the other as a temporary address in the second RAM 102.

The first variable bit reverse section 113 is instructed by the first RAM bit reverse signal RBR0 output from the control section 206 with respect to the temporary address of the first RAM 101 output from the address selection section 215. The bit reverse is performed the number of times, and the result is output as the real address of the first RAM 101. On the other hand, the second variable bit reverse unit 114 applies the control unit 206 to the temporary address of the second RAM 102 output from the address selection unit 215.
RAM bit reverse signal RB output from
Perform bit reverse the number of times indicated by R1,
It is output as the real address of the second RAM 102.

Therefore, in the fast Fourier transform apparatus according to the present embodiment, the RAM address is specified substantially in the same manner as in the first embodiment.

FIG. 30 shows the first R generated by the control unit 206.
AM bit reverse signal RBR0, second RAM bit reverse signal RBR1, and first and second RAM1
6 is a timing chart showing a relationship with operations of the RAMs 01 and 102 (RAM # 0, RAM # 1). Assuming that the maximum number of bit reverses is Rmax as in the first embodiment, the second RAM bit reverse signal RBR1 is updated so as to circulate from 0 to Rmax, and the first RAM bit reverse signal RBR0 is the second RAM bit reverse signal RBR. The bit reverse signal RBR1 for the RAM is updated so as to circulate from 0 to Rmax one symbol period later. Also, first and second RAMs
101 and 102 alternately and repeatedly perform data input / output and butterfly operation.

With the above configuration, the same operation as that of the first embodiment can be realized, and the same effect as that of the first embodiment can be obtained.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 31 is a block diagram showing a configuration of a fast Fourier transform apparatus according to a third embodiment of the present invention. The difference from the fast Fourier transform apparatus according to the first embodiment shown in FIG. 1 is that the RAM address generation unit 305 does not include a variable bit reverse unit, and instead the butterfly operation unit 303 performs a butterfly operation by a time thinning method. In addition, it also has a function of performing a butterfly operation by a frequency thinning method.

In this embodiment, the fast Fourier transform using the butterfly operation by the time thinning method and the fast Fourier transform using the butterfly operation by the frequency thinning method are alternately performed for each symbol. The time thinning method and the frequency thinning method are equivalent as a fast Fourier transform,
The relationship between the order of the input data and the order of the output data becomes symmetric. The present embodiment makes use of this fact to eliminate the need for data rearrangement by alternately performing the time thinning method and the frequency thinning method.

In FIG. 31, reference numeral 303 denotes a butterfly operation unit, which is supplied from a frequency decimation unit 341 for performing a butterfly operation by a frequency decimation method, a time decimation unit 342 for performing a butterfly operation by a time decimation method, and a control unit 306. A selection circuit 343 for selecting and outputting one of the calculation results of the frequency thinning calculation unit 341 and the time thinning calculation unit 342 in accordance with the thinning method switching signal TSL. Reference numeral 304 denotes a rotator generation unit that generates a rotator used in a butterfly operation using a time thinning method or a frequency thinning method. Reference numeral 305 denotes a RAM address generation unit that generates an address for controlling the first and second RAMs 101 and 102. 31, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The butterfly operation unit 303, the rotator generation unit 304, the RAM address generation unit 305, the control unit 306, and the first and second data selection units 121 and 122 constitute an FFT processing unit.

The fast Fourier transform apparatus according to the present embodiment configured as described above performs fast Fourier transform of even-numbered symbols using one of the two RAMs 101 and 102, as in the first embodiment. And odd-numbered Fast Fourier Transform using the other.

In the first and second embodiments, the RAM address is updated for each symbol by the variable bit reverse in order to realize the overlap between the symbol input and the previous symbol output without rearranging the data. However, in the present embodiment, the butterfly operation unit is controlled so that the butterfly operation by the time thinning method and the butterfly operation by the frequency thinning method are alternately performed for each symbol.

FIG. 32 is a signal flow graph showing a radix-2 time thinning method and a frequency thinning method as an example of the fast Fourier transform algorithm. In the figure,
(A) shows a radix-2 time thinning-out method, and (b) shows a radix-2 frequency thinning-out method, both of which are signal flow graphs when the number of samples N = 8. As shown in FIG. 32 (a), in the radix-2 hour thinning method, when the index of input data x (j) is j = 0, 4, 2, 6,... From the top, the index of output data X (j) increases. J = 0,1,
2, 3, ... in ascending order. On the other hand, in the frequency thinning method as shown in FIG. 32B, the index of the input data x (j) is set to j = 0, 1, 2, j from the top according to the output data in the time thinning method shown in FIG. , 3 ... in ascending order, the index of the output data X (j) is j =
0, 4, 2, 6,..., Which match the input data in the time thinning method shown in FIG. That is, the order of the input data and the output data in the frequency thinning method matches the order of the output data and the input data in the time thinning method.

FIG. 33 is a diagram showing an example of data transfer between RAMs according to the present embodiment, and shows data transfer between RAMs when the time thinning method and the frequency thinning method are alternately performed for each symbol. The example shown in FIG. 33 is for the case where the number of samples N = 8, and two RAMs 101,
One of the RAMs 102 is shown.

In FIG. 33, in the FFT processing [i], a butterfly operation is performed by the time thinning method, and the FFT processing [i] is performed.
In [+2], butterfly computation is performed by the frequency thinning method. As shown in FIG. 33, the order of the output data X (J) of the butterfly operation (FFT processing [i]) by the time thinning method is performed by alternately performing the butterfly operation by the time thinning method and the butterfly operation by the frequency thinning method. And butterfly operation (FFT processing [i
+2]) and the order of the input data x (j)
Butterfly operation (FFT processing [i
+2]) The input data x of the butterfly operation (FFT processing [i]) by the order of the output data X (j) and the time thinning method
Since the order of (J) matches, the order of the output data of each FFT process and the input data of the next FFT process match.
Therefore, the read address of the output data X (k) of each FFT process is the same as the write address of the input data x (k) of the next FFT process. Thus, after reading the output data X (k) of the FFT processing, the input data x (k) of the next FFT processing can be stored at the same address, so that the symbol input and the symbol output of the immediately preceding symbol can be stored. Overlap can be achieved.

As described above, according to the present embodiment, the butterfly operation by the time thinning method and the butterfly operation by the frequency thinning method are alternately performed for each symbol, so that the output data of one symbol and the next symbol are output. Data having a common index indicating the order in the symbol between the input data and the input data can be stored at the same address in the RAM. That is, the input data of the next symbol can be written to the same address after reading the output data of one symbol from the RAM, and the empty area of the RAM after reading the output data stores the input data of the next symbol. Since it can be used as an input buffer, an input buffer RAM is not required. Accordingly, the RAM is configured to process even-numbered symbols of the plurality of consecutive symbols using the first RAM and perform processing of odd-numbered symbols using the second RAM.
Can be configured by two RAMs.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 34 is a diagram showing the configuration of the fast Fourier transform device according to the fourth embodiment of the present invention. In FIG. 34, reference numeral 401 denotes a RAM for storing input / output data and intermediate data at the time of butterfly operation, 402 denotes a CPU for performing butterfly operation and address calculation of the RAM 401, 403,
404, a bus for connecting the RAM 401 and the CPU 402; 403, an address bus; and 404, a data bus.

In this embodiment, the storage area of the RAM 401 is divided into two storage areas 405 and 406, and one of the two storage areas 405 and 406 is used to perform the fast Fourier transform of the even-numbered symbol, To perform an odd-numbered Fast Fourier Transform. CPU 402 is RAM 40
An address for storing input / output data and intermediate data at the time of butterfly operation is generated in the two storage areas 405 and 406. Further, the CPU 402 performs a butterfly operation using the data read from the RAM 401 as an input, and outputs the operation result to the RAM 401.

With the above configuration, the same operation as that of the fast Fourier transform device according to the first embodiment can be realized. In the present embodiment, the storage areas of the RAM are the first and second storage areas.
, And performing the even-numbered and odd-numbered fast Fourier transforms of the continuous symbols using the first and second storage areas, respectively, thereby reducing the storage capacity of the RAM.

In the first to third embodiments, two RAMs are provided for storing input / output data and intermediate data at the time of operation. However, as in the fourth embodiment, one RAM is provided.
The AM may be divided into two storage areas and used.

Further, in the first and second embodiments, the time thinning method is used as the fast Fourier transform algorithm, but the frequency thinning method may be used. When the frequency thinning method is used, the calculation by the butterfly calculation unit may be changed, and the grouping of the address bits in the bit reverse by the variable bit reverse unit may be changed.

In the first and second embodiments, R
Although the AM address generation unit has two variable bit reverse units, one variable bit reverse unit may be provided, and the bit reverse process of the input / output address and the butterfly operation address may be time-division-processed.

Further, in the first to third embodiments, two RAMs are provided for storing input / output data and intermediate data at the time of calculation, but the number of RAMs in the present invention is two.
The number is not limited to one and may be one or three or more.

(Application to Inverse Fast Fourier Transform) The present invention can be implemented in the inverse fast Fourier transform in the same manner as in the fast Fourier transform described in each embodiment.

The algorithm of the inverse fast Fourier transform can be realized only by converting a part of operations in the algorithm of the fast Fourier transform. For example, a radix 4 × 2 time decimation method as an example of an inverse fast Fourier transform algorithm is shown by a signal flow graph similar to the fast Fourier transform algorithm as shown in FIG. However, a part of the arithmetic expression of the arithmetic element is different from the fast Fourier transform algorithm.

FIG. 35 is a diagram showing operation elements when the signal flow graph of FIG. 4 shows an inverse fast Fourier transform algorithm. In the inverse fast Fourier transform algorithm, as shown in FIG. 35, each operation is performed according to the following expression. Note that the arithmetic elements in the fast Fourier transform shown in FIG. 5 which are different from the arithmetic expressions are underlined. <Radix 4 butterfly operation> X0 = x0 + x1 + x2 + x3 X1 = x0 + j.x1-x2-j.x3 X2 = x0-x1 + x2-x3 X3 = x0-j.x1-x2 + j.x3 <Radix 2 butterfly operation> X0 = x0 + x1 X1 = x0 −x1 <rotator multiplication> Y = y · W ⁱ W = e ^{j · 2π / N}

Therefore, in the first and second embodiments, the calculation in the butterfly operation unit 103 and the rotator generation unit 104 is changed. In the third embodiment, the butterfly operation unit 303 and the rotator generation unit 304 are changed.
In the fourth embodiment, the change in the calculation in
By performing the change of the butterfly operation and the rotator multiplication by U402, it becomes possible to perform the fast Fourier inverse transform according to the present invention. In this case, for example, in the first embodiment, the butterfly operation unit 103, the rotator generation unit 104, the RAM address generation unit 105, and the control unit 1
06, and the first and second data selection units 121, 1
The IFFT processing unit 22 performs an inverse fast Fourier transform process using a butterfly operation.

(Application to OFDM Receiving / Transmitting Apparatus) Note that the fast Fourier transform apparatus according to the present invention
Used in the receiving device. FIG. 36 is a block diagram showing the configuration of an OFDM receiving apparatus provided with the fast Fourier transform apparatus according to the present invention. In this OFDM receiving apparatus, the fast Fourier transform apparatus according to the present invention employs a fast Fourier transform unit 1
2 is used. The digital demodulation unit 11 converts the input OFDM signal into a baseband signal by digital demodulation, and the fast Fourier transform unit 12 performs fast Fourier transform on the baseband signal output from the digital demodulation unit 11. An OFDM signal is a modulated signal using a large number of carriers that are orthogonal to each other, and complex data of each carrier is decoded by fast Fourier transform. That is, the output of the fast Fourier transform unit 12 corresponds to the decoded complex data of each carrier. The error correction / deinterleave / demapping unit 13 performs a predetermined error correction / deinterleave / demapping process on the output of the fast Fourier transform unit 12 to decode the received data. By applying the fast Fourier transform device according to the present invention as the fast Fourier transform unit 12, the fast Fourier transform unit 12
Requires less storage space, thereby reducing OFD
Cost reduction of the entire M receiving apparatus can be realized.

Similarly, the inverse fast Fourier transform device according to the present invention is used, for example, in an OFDM transmission device.
FIG. 37 is a block diagram showing the configuration of an OFDM transmission device provided with the inverse fast Fourier transform device according to the present invention. In this OFDM transmitter, the inverse fast Fourier transform device according to the present invention is used as the inverse fast Fourier transform unit 22. Have been. The OFDM transmitting apparatus shown in FIG. 37 performs a process reverse to that of the OFDM receiving apparatus shown in FIG. 36 to generate an OFDM signal. That is, the encoding / interleave mapping unit 21 adds a predetermined error correction encoding /
An interleave mapping process is performed to generate complex data of each carrier. The inverse fast Fourier transform unit 22 performs an inverse fast Fourier transform process on the complex data of each carrier, and the digital modulation unit performs frequency conversion on the output of the inverse fast Fourier transform unit 22 to generate an OFDM signal. By applying the inverse fast Fourier transform device according to the present invention as the inverse fast Fourier transform unit 22, the storage capacity required for the inverse fast Fourier transform unit 22 is reduced, thereby realizing cost reduction of the entire OFDM transmission device. can do.

[0164]

According to the present invention, the RAM access is performed by changing the number of bit reverses of the address for each symbol, so that the output data of one symbol and the input data of the next symbol indicate the order in the symbol. Since the data having the same index can be stored at the same address in the RAM, it is possible to realize the overlap between the symbol input and the symbol output without the necessity of rearranging the data.

According to the present invention, the butterfly operation by the time thinning method and the butterfly operation by the frequency thinning method are alternately performed for each symbol, so that the output data of one symbol and the input data of the next symbol have the same Since the data having the same index indicating the order can be stored at the same address in the RAM, it is possible to realize the overlap between the symbol input and the symbol output without the necessity of rearranging the data.

For this reason, the input buffer RAM, which has been conventionally required, becomes unnecessary, and the cost of the fast Fourier transform apparatus can be reduced by reducing the storage capacity. RA
M occupies most of the fast Fourier transform device, and the effect of cost reduction by reducing the storage capacity is great.

Further, since it is not necessary to rearrange the data, the storage capacity can be reduced, and the processing after the fast Fourier transform can be reduced in the fast Fourier transform apparatus used for modulation and demodulation.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a fast Fourier transform device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing processing timing in the fast Fourier transform device according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing a RAM switching timing in the fast Fourier transform device according to the first embodiment of the present invention.

FIG. 4 is a signal flow graph illustrating a radix 4 × 2 time thinning method as an example of a fast Fourier transform algorithm.

FIG. 5 is a diagram showing operation elements in a signal flow.

FIG. 6 shows R in the case without variable bit reverse of an address.
It is a figure which shows data transfer between AM.

FIG. 7 shows R in a case where there is a variable bit reverse of an address.
It is a figure which shows data transfer between AM.

FIG. 8 is a diagram showing an outline of bit reverse.

FIG. 9 is a diagram illustrating an example of bit reverse, and is a diagram illustrating bit reverse in a radix 4 × 2 time thinning-out method when the number of samples N = 32;

FIG. 10 is a diagram showing an example of an address change due to variable bit reverse, corresponding to the data transfer between RAMs shown in FIG. 7;

FIG. 11 is a diagram showing a change in an address due to variable bit reverse, which is a radix of 4 × 2 when the number of samples N = 32;
It is a figure corresponding to data transfer between RAM in the time thinning method.

FIG. 12 is a diagram showing a change in an address due to variable bit reverse, which is a radix 4 × 2 when the number of samples N = 16;
It is a figure corresponding to data transfer between RAM in the time thinning method.

FIG. 13 is a signal flow graph in the case where the number of samples N = 32, and is a diagram showing the calculation order of butterfly calculation in the first embodiment of the present invention.

14 is a timing chart showing signals for controlling the RAM address generation unit 105 generated and output by the control unit 106 in the fast Fourier transform apparatus according to the first embodiment of the present invention shown in FIG.

15 is a timing chart showing signals for controlling the RAM address generation unit 105 generated and output by the control unit 106 in the fast Fourier transform apparatus according to the first embodiment of the present invention shown in FIG.

FIG. 16 is a timing chart showing the operation timing of the butterfly operation unit 103 in the fast Fourier transform apparatus according to the first embodiment of the present invention shown in FIG.

FIG. 17 is a diagram illustrating an example of a configuration of first and second variable bit reverse units 113 and 114 in the fast Fourier transform apparatus according to the first embodiment of the present invention illustrated in FIG. 1; A configuration example of a selector format, and (b) is a configuration example of a table format.

FIG. 18 shows an input / output address generation unit 111 and a first input / output address generation unit 111 in the fast Fourier transform apparatus according to the first embodiment of the present invention.
FIG. 11 is a diagram showing an operation of generating an input / output address by the variable bit reverse unit 113 of FIG.
It is a figure which shows correspondence of CN and the input / output bit reverse signal DBR, the input / output temporary address DAD, and the input / output real address RDAD.

FIG. 19 is a diagram illustrating an operation of generating a butterfly operation address by the butterfly address generation unit 112 and the second variable bit reverse unit 114 in the fast Fourier transform device according to the first embodiment of the present invention, Timing signal BCN, butterfly operation stage signal BST, and butterfly operation bit reverse signal B
It is a figure which shows correspondence of BR with the temporary address BAD for butterfly operations, and the real address RBAD for butterfly operations.

FIG. 20 is a diagram showing a configuration of an address selection unit 115 in the fast Fourier transform device according to the first embodiment of the present invention.

FIG. 21 is a diagram showing access timing of a RAM in data input / output in the fast Fourier transform device according to the first embodiment of the present invention.

FIG. 22 is a diagram showing access timing of a RAM in a butterfly operation in the fast Fourier transform device according to the first embodiment of the present invention.

FIG. 23 shows first and second variable bit reverse units 11;
FIG. 3 is a circuit diagram showing another example of the configuration of 3,114, and showing a variable bit reverse circuit configured to be able to execute variable bit reverse for the number of samples N = 4, 8, 16, and 32, respectively. It is.

24 is a circuit diagram showing a configuration of each circuit constituting the variable bit reverse circuit shown in FIG. 23, (a) showing a configuration of the bit reverse circuit BR, and (b) showing a bit exchange circuit B;
FIG. 3C is a diagram illustrating a configuration of C, and FIG. 3C is a diagram illustrating a configuration of a barrel shifter BS.

25A and 25B are diagrams illustrating set values of respective control signals of the variable bit reverse circuit illustrated in FIG. 23. FIG.
FIG. 13B is a diagram illustrating set values of control signals when the number of samples is N = 16, (c) is a sample number N = 8, and (d) is a sample number N = 4.

26A and 26B are diagrams showing the operation of the variable bit reverse circuit shown in FIG. 23 when the number of samples N = 8, where FIG. 26A shows a case where the number of bit reverses is 1, and FIG. FIG. 9 is a diagram showing the operation at the time.

FIG. 27 is a diagram illustrating an operation of the variable bit reverse circuit illustrated in FIG. 23 when the number of samples is N = 8 in the case where no bit exchange is performed.
(B) is a diagram showing the operation when the number of bit reverses is 2.

FIG. 28 shows the number of samples N = 2 ⁱ (2 ≦ 2) according to the present embodiment.
FIG. 9 is a configuration diagram of a variable bit reverse circuit that can support N ≦ 11).

FIG. 29 is a block diagram illustrating a configuration of a fast Fourier transform device according to a second embodiment of the present invention.

FIG. 30 is a block diagram of the fast Fourier transform apparatus according to the second embodiment of the present invention, in which a first RAM bit reverse signal RBR0 and a second RAM bit reverse signal RBR are provided;
1 and the first and second RAMs 101 and 102 (RAM #
0, RAM # 1) is a timing chart showing the relationship with the operation.

FIG. 31 is a block diagram illustrating a configuration of a fast Fourier transform device according to a third embodiment of the present invention.

FIGS. 32A and 32B are signal flow graphs showing an example of a fast Fourier transform algorithm, wherein FIG. 32A is a signal flow graph showing a radix-2 time thinning method, and FIG. 32B is a signal flow graph showing a radix-2 frequency thinning method.

FIG. 33 is a diagram illustrating an example of data transfer between RAMs according to the third embodiment of the present invention, in which a time thinning method and a frequency thinning method are alternately performed for each symbol;
It is a figure which shows data transfer between.

FIG. 34 is a diagram illustrating a configuration of a fast Fourier transform device according to a fourth embodiment of the present invention.

FIG. 35 is a diagram showing operation elements in a signal flow showing an inverse fast Fourier transform.

FIG. 36 is a diagram showing a configuration of an OFDM receiver using the fast Fourier transform device according to the present invention.

FIG. 37 is a diagram showing a configuration of an OFDM transmission device using the inverse fast Fourier transform device according to the present invention.

[Explanation of symbols]

 101 first RAM 102 second RAM 103 butterfly operation unit 105 RAM address generation unit 106 control unit 111 input / output address generation unit 112 butterfly address generation unit 113 first variable bit reverse unit 114 second variable bit reverse unit 115 Address selection unit 121 First data selection unit 122 Second data selection unit 131 RAM address conversion unit 205 RAM address generation unit 206 Control unit 215 Address selection unit 231 RAM address conversion unit 303 Butterfly operation unit 305 RAM address generation unit 306 Control Unit 341 Frequency thinning operation unit 342 Time thinning operation unit DAD I / O temporary address BAD Butterfly operation temporary address RDAD I / O real address RBAD Butterfly operation real address DBR I / O Bit reverse signal BBR butterfly operation bit reverse signal RSL RAM selection signal RBR0 first RAM bit reverse signal RBR1 second RAM bit reverse signal 701-704 bit reverse circuit 711 bit exchange circuit (bit exchange means) 721 barrel shifter (bit Shift means) 11 digital demodulation unit 12 fast Fourier transform unit 22 inverse fast Fourier transform unit 23 digital modulation unit

Claims (37)

[Claims] 1. Fast Fourier Transform (FFT)
e Transform), a random access memory (RAM) that stores input data for each symbol, which is a group of data to be subjected to fast Fourier transform.
And an FFT processing unit that performs a fast Fourier transform process (FFT process) using butterfly operation on the input data stored in the RAM. The RAM includes one symbol stored in the RAM. Storing the data obtained as a result of the FFT processing by the FFT processing section on the input data of the first symbol as output data of the one symbol, wherein the FFT processing section outputs the output data of one symbol and the one symbol In the input data of the other symbols stored in the RAM next to the output data of R, data having a common index indicating the order in the symbol is the R data.
A fast Fourier transform apparatus for performing an FFT process so as to be stored at the same address of an AM. 2. The fast Fourier transform apparatus according to claim 1, wherein the FFT processing unit includes a RAM address generating unit that generates an address for accessing the RAM.
The RAM is accessed in accordance with the address generated by the address generation unit. The RAM address generation unit outputs one symbol output data and the RA output next to the one symbol output data.
In the input data of other symbols stored in M, the generated address is converted for each symbol so that data having a common index indicating the order in the symbol is stored at the same address in the RAM. A fast Fourier transform device. 3. The fast Fourier transform apparatus according to claim 2, wherein the RAM address generation unit uses a bit reverse process of grouping bits of the address based on a radix of a butterfly operation, and changing a bit order in a group unit. A fast Fourier transform apparatus for converting an address to be generated for each symbol. 4. The fast Fourier transform apparatus according to claim 3, wherein the RAM address generation unit generates an address by repeatedly performing a bit reverse process on a reference address a predetermined number of times. Assuming that the maximum number of bit reverses Rmax (Rmax is a positive integer) is the number obtained by subtracting 1 from the number of times of returning to the original address when the bit reverse processing is repeatedly performed, the RAM address generation unit performs a bit reverse From 0 to R
A fast Fourier transform apparatus wherein the generated address is converted for each symbol by incrementing for each symbol so as to circulate sequentially up to max times. 5. The fast Fourier transform apparatus according to claim 4, wherein the FFT processing unit performs the FFT processing by preferentially using a radix-4 butterfly operation, and the maximum number of bit reverses Rmax is one symbol. The fast Fourier transform apparatus is 1 when the number of samples is 4 ^m (m is a positive integer), and 2 ^m when the number of samples is 4 ^m · 2. 6. The fast Fourier transform device according to claim 4, wherein the RAM address generation unit includes a variable bit reverse unit that repeats a bit reverse process a specified number of times, and each of the variable bit reverse units performs one time. And a plurality of bit reverse circuits connected in series. Of the plurality of bit reverse circuits, the number corresponding to the designated number of bit reverses performs the bit reverse, and the remaining A fast Fourier transform apparatus characterized in that data is passed through. 7. The fast Fourier transform apparatus according to claim 6, wherein the variable bit reverse section performs a bit reverse in accordance with a plurality of sample numbers, and is effective for input data and output data. A fast Fourier transform apparatus comprising a bit shift means for bit-shifting data bit-reversed by the plurality of bit-reverse circuits so that the positions of the bits match. 8. The fast Fourier transform apparatus according to claim 7, wherein said variable bit reverse unit is provided with a bit exchange means for exchanging bits in a stage preceding any one of said plurality of bit reverse circuits. Features a fast Fourier transform device. 9. The fast Fourier transform apparatus according to claim 1, wherein the FFT processing unit includes a butterfly operation unit that performs an FFT process using a butterfly operation on the input data stored in the RAM. The arithmetic unit can execute a plurality of types of FFT processing that are substantially the same using different butterfly arithmetic operations, and store the output data of one symbol and the output data of the one symbol in the RAM next to the output data of the one symbol. In the input data of another symbol to be processed, data having a common index indicating the order in the symbol is stored in the RAM.
Wherein the type of FFT processing to be executed is changed for each symbol so as to be stored at the same address. 10. The fast Fourier transform device according to claim 9, wherein the butterfly operation unit performs symbolic FFT processing using a butterfly operation using a frequency thinning method and FFT processing using a butterfly operation using a time thinning method. A fast Fourier transform apparatus that performs the processing alternately every time. 11. A fast Fourier transform apparatus for performing fast Fourier transform, wherein first and second RAMs for storing input data for each symbol which is a set of data to be subjected to fast Fourier transform.
And fast Fourier transform processing (F) using butterfly operation on the input data stored in the first or second RAM.
And an FFT processing unit that performs an FT process. The first and second RAMs each include an FF for input data of one symbol stored in the RAM.
The data obtained as a result of the FFT processing by the T processing unit is stored as output data of the one symbol, and the fast Fourier transform apparatus includes the first and second RAs.
M is used to perform the FFT processing of the even-numbered symbols, and the other is used to perform the FF processing of the odd-numbered symbols.
The FFT processing unit performs a T process, wherein the output data of the i-th (i is a positive integer) symbol and the input data of the (i + 2) -th symbol have a common index indicating the order in the symbol. A fast Fourier transform apparatus for performing an FFT process so that data is stored at the same address in the first or second RAM. 12. The fast Fourier transform apparatus according to claim 11, wherein during the data output period of the i-th (i is a positive integer) symbol, the data input of the (i + 2) -th symbol and the (i + 1) -th symbol are performed. A fast Fourier transform device for performing a butterfly operation on a symbol. 13. The fast Fourier transform apparatus according to claim 11, wherein the FFT processing unit is a RAM address generation unit that generates an address for accessing the first and second RAMs; A butterfly operation unit for performing a butterfly operation based on the data stored in the RAM, and input data of the fast Fourier transform device or operation result data of the butterfly operation unit, which are input to the first or second RAM. A first data selection unit for selectively outputting, and a second data selection unit for receiving the output data of the first or second RAM as input, and selectively outputting the output data of the fast Fourier transform device or to the butterfly operation unit. And a control unit that controls the RAM address generation unit and the first and second data selection units. Parts are, i (i is a positive integer) in the input data of th output data and the (i + 2) -th symbol of the symbol, is data common index indicating the order in symbol, the first or second RA
A fast Fourier transform apparatus wherein the generated address is converted for each symbol so that the generated address is stored at the same address of M. 14. The fast Fourier transform apparatus according to claim 13, wherein the RAM address generation unit is configured to input a reference of an address for storing input data and output data of one symbol in the first or second RAM. An input / output address generating unit for generating a temporary address for output; and a butterfly for generating a temporary address for butterfly operation which is a reference of an address for storing intermediate data at the time of butterfly operation of one symbol in the first or second RAM. An address generation unit, converting the input / output temporary address generated by the input / output address generation unit into an input / output real address, and converting the butterfly operation temporary address generated by the butterfly address generation unit into a butterfly operation real address. Of the real address for input / output and the real address for butterfly operation. While outputs towards the said first RAM, the fast Fourier transform apparatus characterized by and a RAM address conversion unit for outputting the other to the second RAM. 15. The fast Fourier transform apparatus according to claim 14, wherein the RAM address conversion unit outputs a bit reverse process to the temporary input / output address generated by the input / output address generation unit from the control unit. A first variable bit reverse section that generates an input / output real address by performing the number of times indicated by the input / output bit reverse signal, and a butterfly operation temporary address generated by the butterfly address generation section. Performing a bit reverse process the number of times indicated by the butterfly operation bit reverse signal output from the control unit to generate a butterfly operation real address; and the first variable bit. A real address for input / output generated by the reverse unit and the second The real address for butterfly operation generated by the bit reverse unit is input, and one is set as the address of the first RAM and the other is set as the address of the second RAM according to the RAM selection signal output from the control unit. A fast Fourier transform device comprising: an address selection unit for selectively outputting. 16. The fast Fourier transform apparatus according to claim 15, wherein a number obtained by subtracting 1 from the number of times of returning to the original address when the bit reverse processing is repeatedly performed is defined as a maximum bit reverse number Rmax (Rmax is a positive integer). Assuming that the data input period for one symbol is a symbol period, the control unit sets the input / output bit reverse signal and the butterfly operation bit reverse signal every two symbol periods to indicate the number of repetitions of the bit reverse process. A fast Fourier transform apparatus characterized by updating each time from 0 to Rmax times in order. 17. The fast Fourier transform apparatus according to claim 14, wherein the RAM address conversion unit includes: a temporary input / output address generated by the input / output address generation unit; and a butterfly operation generated by the butterfly address generation unit. The temporary address is input, and according to the RAM selection signal output from the control unit,
An address selection unit for selecting and outputting one of the temporary addresses of the first RAM and the other as a temporary address of the second RAM; and a temporary address of the first RAM selectively output by the address selection unit. By performing the bit reverse process the number of times specified by the first RAM bit reverse signal output from the control unit, the first R
A first variable bit reverse section for generating an address of AM; and a second RAM output from the control section for performing bit reverse processing on the temporary address of the second RAM selected and output by the address selection section. By performing the number of times specified by the bit reverse signal for
A fast variable Fourier transform unit comprising: a second variable bit reverse section for generating an AM address. 18. The fast Fourier transform apparatus according to claim 17, wherein a number obtained by subtracting 1 from the number of times of returning to the original address when the bit reverse processing is repeatedly performed is defined as a maximum bit reverse number Rmax (Rmax is a positive integer). Assuming that the data input period for one symbol is one symbol period, the control unit indicates the bit reverse signal for the first RAM and the bit reverse signal for the second RAM every two symbol periods. A fast Fourier transform apparatus, wherein the number of processes is updated from 0 to Rmax in order. 19. The fast Fourier transform apparatus according to claim 16, wherein the FFT processing unit performs the FFT processing by preferentially using a radix-4 butterfly operation, and the maximum number of bit reverses Rmax is: A fast Fourier transform apparatus characterized in that the number is 1 when the number of samples, which is the number of data of one symbol, is 4 ^m (m is a positive integer), and is 2 ^m when the number of samples is 4 ^m · 2. 20. The fast Fourier transform apparatus according to claim 11, wherein the FFT processing unit is a RAM address generation unit that generates an address for accessing the first and second RAMs, and the first or second FFT processing unit. A butterfly operation unit for performing a butterfly operation based on the data stored in the RAM; and input data of the fast Fourier transform device or operation result data of the butterfly operation unit, and the first R
A first data selection unit for selectively outputting to the AM or the second RAM; and inputting the output data of the first or second RAM as input and selecting as output data of the fast Fourier transform apparatus or to the butterfly operation unit. A second data selection unit for outputting, a RAM address generation unit, and a control unit for controlling the first and second data selection units, wherein the butterfly operation unit uses different butterfly operations and is substantially Can be executed, and the index indicating the order in the symbol is common to the output data of the i-th (i is a positive integer) symbol and the input data of the (i + 2) -th symbol. The type of FFT processing to be executed is changed for each symbol so that the data to be stored is stored at the same address in the first or second RAM. Fast Fourier transform and wherein the at. 21. The fast Fourier transform apparatus according to claim 20, wherein the butterfly operation unit uses a butterfly operation by a frequency thinning method for input data of a symbol stored in the first or second RAM. A frequency decimation unit that performs an FFT process; and a time decimation unit that performs an FFT process on the input data of the symbols stored in the first or second RAM using a butterfly operation by a time decimation method. A fast Fourier transform apparatus. 22. A fast Fourier transform method for performing a fast Fourier transform using a RAM, wherein a first step of storing data to be transformed for one symbol, which is a set of data to be subjected to the fast Fourier transform, in the RAM. A second step of performing a fast Fourier transform process (FFT process) using a butterfly operation on the data to be transformed stored in the RAM in the first step, and storing process result data in the RAM; And a third step of reading the processing result data stored in the RAM in the second step from the RAM, and repeating the third step. The second step includes an N-th (N is a positive integer) time In the repetition the RAM
In the processing result data stored in the RAM and the data to be converted stored in the RAM in the (N + 1) -th repetition, data having a common index indicating the order in the symbol is stored at the same address in the RAM. A fast Fourier transform method, wherein an address for accessing a RAM is converted each time it is repeated. 23. The fast Fourier transform method according to claim 22, wherein the second step uses a bit reverse process of grouping bits of an address based on a radix of a butterfly operation and changing the order of the bits in a group unit. A fast Fourier transform method, wherein an address for accessing the RAM is converted each time it is repeated. 24. The fast Fourier transform method according to claim 23, wherein in the second step, an address for accessing the RAM is generated by repeatedly performing a bit reverse process on a reference address a predetermined number of times. The maximum number of bit reverse times Rmax (Rmax is a positive integer) is defined as the number obtained by subtracting 1 from the number of times of returning to the original address when the bit reverse process is repeatedly performed. The address for accessing the RAM is converted into the number of repetitions by incrementing the number of repetitions of the bit reverse process for a given address from 0 to Rmax in each repetition. Fast Fourier transform method. 25. The fast Fourier transform method according to claim 24, wherein the second step performs FFT processing using a radix-4 butterfly operation with priority, and the maximum number of bit reverses Rmax is 1 A fast Fourier transform method wherein the number of samples, which is the number of symbol data, is 1 when the number of samples is 4 ^m (m is a positive integer) and 2 ^m when the number of samples is 4 ^m · 2. 26. A fast Fourier transform method for performing a fast Fourier transform using a RAM, wherein a first step of storing data to be transformed for one symbol, which is a set of data to be subjected to the fast Fourier transform, in the RAM. A second step of performing a fast Fourier transform process (FFT process) using a butterfly operation on the data to be transformed stored in the RAM in the first step, and storing process result data in the RAM; And a third step of reading the processing result data stored in the RAM in the second step from the RAM. The second step uses a different butterfly operation and is substantially equivalent. Can be executed, and in the Nth (N is a positive integer) iteration, the RFT In the processing result data stored in M and the data to be converted stored in the RAM in the (N + 1) -th repetition, data having a common index indicating the order in the symbol is stored at the same address in the RAM. FF to execute
A fast Fourier transform method, wherein the type of T processing is changed each time it is repeated. 27. The fast Fourier transform method according to claim 26, wherein the second step includes performing an FFT process using a butterfly operation by a frequency thinning method and an FFT process using a butterfly operation by a time thinning method. A fast Fourier transform method wherein the method is performed alternately at each repetition. 28. A variable bit reverse circuit for repeating a bit reverse process for a butterfly operation a specified number of times, comprising a plurality of serially connected bit reverse circuits each performing a single bit reverse process. A variable bit reverse circuit comprising: a plurality of bit reverse circuits, the number of which corresponds to a designated number of bit reverses, performs a bit reverse, and the remaining ones pass data. 29. The variable bit reverse circuit according to claim 28, wherein said variable bit reverse circuit performs bit reverse in accordance with a plurality of sample numbers, and is effective for input data and output data. A variable bit reverse circuit comprising bit shift means for bit shifting data bit-reversed by the plurality of bit reverse circuits so that the positions of the bits match. 30. The variable bit reverse circuit according to claim 29, wherein a bit exchange means for exchanging bits is provided in a stage preceding any one of the plurality of bit reverse circuits. . 31. An inverse fast Fourier transform apparatus for performing an inverse fast Fourier transform, comprising: a RAM for storing input data for each symbol which is a group of data to be subjected to the inverse fast Fourier transform; and an input stored in the RAM. Inverse fast Fourier transform processing (IFFT processing) using butterfly operation on data
And an IFFT processing unit that performs an IFFT process on the input data of one symbol stored in the RAM by the IFFT processing unit.
The data obtained as a result of the processing is stored as the output data of the one symbol. The IFFT processing unit stores the output data of the one symbol and the one stored in the RAM next to the one symbol. An inverse fast Fourier transform apparatus characterized in that IFFT processing is performed so that data having a common index indicating the order in a symbol in the input data of the symbol is stored at the same address in the RAM. 32. The inverse fast Fourier transform apparatus according to claim 31, wherein the IFFT processing unit includes a RAM address generation unit that generates an address for accessing the RAM,
The RAM address is accessed according to the address generated by the M address generation unit. The RAM address generation unit outputs one symbol output data and the one symbol output data,
In the input data of other symbols stored in M, the generated address is converted for each symbol so that data having a common index indicating the order in the symbol is stored at the same address in the RAM. An inverse fast Fourier transform apparatus. 33. The inverse fast Fourier transform apparatus according to claim 31, wherein the IFFT processing unit includes a butterfly operation unit that performs an IFFT process using a butterfly operation on the input data stored in the RAM. The butterfly operation unit can execute a plurality of types of IFFT processing using different butterfly operations and being substantially equivalent, and stores the output data of one symbol and the output data of the one symbol in the RAM next to the output data of the one symbol. In the input data of another symbol, the type of IFFT processing to be executed is changed for each symbol so that data having a common index indicating the order in the symbol is stored at the same address in the RAM. Inverse fast Fourier transform device. 34. An inverse fast Fourier transform method for performing an inverse fast Fourier transform using a RAM, wherein the data to be transformed for one symbol, which is a group of data to be subjected to the inverse fast Fourier transform, is stored in the RAM. 1
A second step of performing an inverse fast Fourier transform process using a butterfly operation on the data to be converted stored in the RAM in the first step, and storing the processing result data in the RAM; And a third step of reading the processing result data stored in the RAM in the second step from the RAM. The second step is an N-th (N is a positive integer) repetition. In the processing result data stored in the RAM and the data to be converted stored in the RAM in the (N + 1) -th iteration, data having a common index indicating the order in the symbol is stored at the same address in the RAM. Thus, the address for accessing the RAM is converted each time it is repeated. An inverse fast Fourier transform method. 35. An inverse fast Fourier transform method for performing an inverse fast Fourier transform using a RAM, the method comprising storing, in the RAM, data to be converted for one symbol, which is a group of data to be subjected to the inverse fast Fourier transform. 1
And performing an inverse fast Fourier transform (IFFT) process using a butterfly operation on the data to be converted stored in the RAM in the first step, and storing the process result data in the RAM. And the third step of reading out the processing result data stored in the RAM in the second step from the RAM in the second step. The second step uses a different butterfly operation and substantially Can perform a plurality of types of IFFT processing that are substantially equivalent to each other, and the processing result data stored in the RAM in the Nth (N is a positive integer) iteration and (N + 1)
In the data to be converted stored in the RAM in the third repetition, the type of IFFT processing to be executed is changed for each repetition so that data having a common index indicating the order in the symbol is stored at the same address in the RAM. An inverse fast Fourier transform method characterized by changing. 36. An OFDM receiver for demodulating a received OFDM signal into received data, comprising: a digital demodulator for demodulating the OFDM signal into a baseband signal; and a baseband signal demodulated by the digital demodulator. A fast Fourier transform unit that performs fast Fourier transform and decodes complex data of a carrier wave, and generates received data based on the complex data of the carrier wave; wherein the fast Fourier transform unit is An OFDM receiving apparatus comprising the fast Fourier transform apparatus according to (1). 37. An OFDM transmission apparatus for modulating transmission data into an OFDM signal, comprising: an inverse fast Fourier transform unit for performing an inverse fast Fourier transform on complex data of a carrier generated from the transmission data; and an inverse fast Fourier transform unit. And a digital modulation unit that performs frequency conversion on an output of the conversion unit to generate an OFDM signal. The inverse fast Fourier transform unit includes the inverse fast Fourier transform device according to claim 31. An OFDM transmission device characterized by the above-mentioned.