KR100484418B1 - Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and ofdm receiver and transmitter - Google Patents

Abstract

In the high-speed Fourier transform apparatus, the present invention is designed to realize a low cost by reducing a required storage capacity. The present invention provides a RAM address for an even-numbered symbol stored in the RAM 101 and an odd-numbered symbol stored in the RAM 101. In accordance with the RAM address generated by the generation unit 105, the butterfly calculating unit 103 performs fast Fourier transform. The RAM address conversion unit 131 converts the input / output temporary address DAD into the input / output real address RDAD by performing bit reverse processing for the number of times indicated by the input / output bit reverse signal DBR. The butterfly operation guard address BAD is converted into the butterfly operation RADAD by performing bit reverse processing for the number of times indicated by the butterfly operation bit reverse signal BBR. Accordingly, in the output data of the i (i is an integer) symbol and the input data of the (i + 2) th symbol, data having a common index indicating the order in the symbols is the RAM 101 or RAM 102. Since the data can be stored in the same address, the overlap between the symbol input and the symbol output can be realized.

Description

FAST FOURIER TRANSFORMING APPARATUS AND METHOD, VARIABLE BIT REVERSE CIRCUIT, INVERSE FAST FOURIER TRANSFORMING APPARATUS AND METHOD, AND OFDM RECEIVER AND TRANSMITTER}

The present invention relates to a fast Fourier transform apparatus and method for performing a Fast Fourier Transform (FFT).

Recently, digitalization of television and radio broadcasting has been progressed with the advancement of digital communication technology and semiconductor integrated technology. In digital broadcasting using terrestrial waves, orthogonal frequency division multiplex (hereinafter, referred to as OFDM) is adopted as a modulation / demodulation scheme in many cases. OFDM is a method of efficiently transmitting some information within a limited frequency band, and has a feature for terrestrial broadcasting that is resistant to multipath interference. However, in OFDM, a large-scale fast Fourier transform of thousands of samples is required, and the cost reduction of the fast Fourier transform device is an important problem for practical use.

As an example of a conventional fast Fourier transform device, there is one described in A. Delaruelle et al. "A Channel Demodulator IC for Digital Audio Broadcasting" (IEEE Custom Integrated Circuit Conference, May 1994). It has two random access memories (RAMs) and uses one as an input buffer RAM for storing input data and two as fast Fourier transform RAMs for storing intermediate data during output and output data. If the data of the number of samples is 1 symbol, successive plural symbol processing processes the current symbol using two fast Fourier transform RAMs, and stores the input data of the next symbol in the input buffer RAM. do.

Further, as another example of a conventional fast Fourier transform device, there is one described in "A Fast Single Chip Implementation of 8192 Complex Points FFT" (IEEE Custom Integrated Circuit Conference, May 1994) by E. Bidet. Is a storage device having a predetermined number of pipeline registers between operators, and each operator operates by pipeline operation, which is equivalent to using two RAMs in terms of storage capacity. Since the output data can be sequentially output from the processed data, there is a problem in that the order of the input data and the output data is different.In order to reduce the processing after the fast Fourier transform, the order of the input data and the output data is used. Since it is desirable to add the same data RAM, It performs the force data string replaced. As a result, the memory capacity is equivalent to the fast Fourier transform unit by using the three RAM.

The fast Fourier transform device requires a storage device for storing input data for one symbol, intermediate data during operation, and output data. In addition, since the fast Fourier transform device used for modulation and demodulation needs to process a plurality of consecutive symbols, a memory device for storing input data of the next symbol is also required in parallel with the processing for the current symbol. Since these memories occupy most of the fast Fourier transform apparatus, the cost reduction of the fast Fourier transform apparatus can be realized by reducing the required storage capacity.

The two examples shown as conventional high speed Fourier transformers are equivalent in terms of storage capacity. However, in the case of realizing with an ASIC or the like, since the former, which can use a RAM library as a storage device, is advantageous in reducing the price, the former configuration is often used in the ASIC or the like.

However, in the configuration using the same RAM as the former, a RAM having a storage capacity capable of storing one symbol of data is required as one for the input buffer RAM, two for the fast Fourier transform RAM, and three accordingly. There has been a problem that the circuit size of the fast Fourier transform device increases. This problem becomes more pronounced as the number of samples per symbol increases.

Therefore, in the present invention, if the input data having the next symbol can be written into the fast Fourier transform RAM after reading the output data stored in the fast Fourier transform RAM, the function of the input buffer RAM can be provided to the fast Fourier transform RAM. It is newly conceived that the RAM for input buffer can be omitted.

If the input buffer RAM is omitted, the fast Fourier transform is performed as follows. First, the input data is stored in the fast Fourier transform RAM, the butterfly operation is performed while the intermediate data is stored in the fast Fourier transform RAM, and finally, the data stored in the fast Fourier transform RAM is read out to be output data.

In this case, however, a new problem arises. Focusing on the input / output data stored in the fast Fourier transform RAM, input data and output data having a common index indicating the order in the symbols are not stored in the same address of the fast Fourier transform RAM from the characteristics of the fast Fourier transform algorithm. Therefore, in the conventional configuration, since the input data of the next symbol is written in the order of the address from which the output data stored in the RAM is read, the order of the input data and the output data is different. In order to make the order of the input data and the output data the same, the data can be replaced after storing the input data or the output data in RAM. In this case, however, a data string replacement RAM having a storage capacity capable of storing one symbol of data can be used. It is necessary to add, and as a result, the memory capacity cannot be reduced.

In view of the above problems, an object of the present invention is to realize a low price by reducing a required storage capacity in a fast Fourier transform.

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, in this invention, the address which accesses RAM so that the output data of one symbol and the index which shows the order among symbols in the next symbol input data is common can be stored to the same address of RAM It will convert every time. In other words, an operation equivalent to data string replacement is realized by address translation. In addition, address conversion is performed by changing the number of bit reverses for a reference address for each symbol by using bit reverse processing for address conversion.

In addition, the present invention is to change the fast Fourier transform processing for each symbol so that the common data indices of the order of the symbols in the output data of one symbol and the input data of the next symbol can be stored at the same address in RAM. . For example, a butterfly operation by a decimation in time method and a butterfly operation by a decimation in frequency method are alternately performed for each symbol. The time selection method and the frequency selection method are equivalent to the fast Fourier transform, but the relationship between the order of input data and the order of output data is an object. This is used to alternate the time selection method and the frequency selection method, thereby making data string replacement unnecessary.

With this structure, the free area of the RAM after reading the output data can be used as an input buffer for storing input data of the next symbol, and the input buffer RAM can be omitted. The RAM reads the stored output data of one symbol and then writes the input data of the next symbol at the same address. In this way, the two RAMs can be configured by processing the even-numbered symbols among the plurality of consecutive symbols using the first RAM and simultaneously the odd-numbered symbols using the second RAM.

Specifically, the solution of the invention of claim 1 is a fast Fourier transform (FFT) device for fast Fourier transform (FFT) to store input data for each symbol that is a set of data for fast Fourier transform (Random Access Memory) And an FFT processing unit for performing fast Fourier transform processing (FFT processing) using a butterfly operation on the input data stored in the RAM, wherein the RAM includes the FFT for the input data of one symbol stored in the RAM. The data obtained as a result of the FFT processing by the processing unit is stored as output data of the one symbol, and the FFT processing unit is the output data of one symbol and the other symbol stored in the RAM after the output data of this symbol. In the input data, data in which the indices indicating the order in the symbols are common is the same as that of the RAM. It performs FFT processing to be stored in the address.

According to the invention of claim 1, by the FFT processing of the FFT processing unit, data having a common index indicating the order of symbols in the output data of one symbol and the input data of the next symbol can be stored at the same address in the RAM. For this reason, the free area of RAM after reading the output data can be used as an input buffer for storing the input data of the next symbol, and the input buffer RAM can be omitted without adding the data string replacement RAM. As a result, the storage capacity required for the fast Fourier transform can be reduced.

In the invention of claim 2, the FFT processing unit in the fast Fourier transforming apparatus of claim 1 includes a RAM address generator for generating an address for accessing the RAM, and the RAM is generated in accordance with the address generated by the RAM address generator. The RAM address generation unit is to access the data of one symbol and the input data of another symbol stored in the RAM next to the output data of one symbol. The generated address is converted for each symbol so as to be stored at the same address of the RAM.

According to the invention of claim 2, the RAM address generation unit converts the address for accessing the RAM for each symbol so that, in the output data of one symbol and the input data of the next symbol, data having a common index indicating the order in the symbols is stored in the RAM. It can be stored at the same address. In other words, an operation equivalent to data string replacement can be realized by address conversion.

In the invention of claim 3, the RAM address generation unit in the fast Fourier transforming apparatus of claim 2 groups bits of addresses based on the radix of the butterfly operation, and reverses the bit order in the group unit. By using the process, the address to be generated is converted for each symbol.

In the invention of claim 4, the RAM address generation unit in the fast Fourier transforming apparatus of claim 3 generates an address by repeatedly performing a bit reverse process a predetermined number of times with respect to a reference address, and repeats the bit reverse process. When the number of times of subtracting 1 from the number of times of returning to the original address is set to the maximum number of bit reverse times Rmax (Rmax is a positive integer), the RAM address generation unit resets the number of repetitions of bit reverse processing to the reference address as 0. The address generated by incrementing each symbol is sequentially converted from symbol to symbol so as to traverse from time to Rmax times.

In the invention of claim 5, in the fast Fourier transforming apparatus of claim 4, the FFT processing unit performs FFT processing using a butterfly operation of radix 4 first, and the maximum bit reverse number Rmax is one symbol of data. It is assumed that the sample number is 1 when 4 ^m (m is a positive integer) and m × 2 when the sample number is 4 ^m · 2.

In the invention of claim 6, the RAM address generation unit in the fast Fourier transforming apparatus of claim 4 includes a variable bit reverse unit for repeating bit reverse processing a specified number of times, and each of the variable bit reverse units performs one bit reverse process. And a plurality of bit reverse circuits connected in series, and a number of bits corresponding to a specified number of bit reverses among the plurality of bit reverse circuits performs bit reverse, and the remaining ones pass data.

In the seventh aspect of the present invention, the variable bit reverse portion of the fast Fourier transform apparatus of claim 6 performs bit reverse in correspondence to a plurality of samples, and the plurality of bits are adapted so that the positions of valid bits in input data and output data match. And bit shift means for bit shifting the bit reversed data by the bit reverse circuit.

In the invention of claim 8, the variable bit reverse portion in the fast Fourier transforming apparatus of claim 7 is provided with bit exchange means for exchanging bits at either front end of the plurality of bit reverse circuits.

In the invention of claim 9, the FFT processing unit in the fast Fourier transforming apparatus of claim 1 includes a butterfly calculating unit that performs an FFT process using a butterfly operation on the input data stored in the RAM, and the butterfly calculating unit A plurality of substantially equivalent FFT processes can be executed using different butterfly operations, and in the output data of one symbol and the input data of another symbol stored in the RAM after the output data of this symbol, It is assumed that the type of FFT processing to be executed is changed for each symbol so that data having a common index indicating the order in the data is stored at the same address of the RAM.

According to the invention of claim 9, by changing the type of FFT processing performed by the butterfly calculating unit for each symbol, data having a common index indicating the order in the symbols in the output data of one symbol and the input data of the next symbol is stored. The data can be stored at the same address.

In the invention of claim 10, the butterfly calculating unit of the fast Fourier transforming apparatus of claim 9 alternates the FFT processing using the butterfly operation by the frequency selection method and the FFT processing using the butterfly operation by the time selection method for each symbol. To do.

In addition, the solving means devised by the invention of claim 11 is a fast Fourier transform device for performing fast Fourier transform, and includes first and second RAMs for storing input data for each symbol which is a set of data for fast Fourier transform, and the first or second RAM. An FFT processing unit for performing fast Fourier transform processing (FFT processing) using a butterfly operation on the input data stored in the second RAM, wherein the first and second RAMs each include one symbol input data stored in the RAM. To store the data obtained as a result of the FFT processing by the FFT processing unit as the output data of the one symbol, and the fast Fourier transform device performs the FFT processing of the even symbol using one of the first and second RAMs. On the other hand, the FFT processing of odd numbered symbols is performed using the other side, and the FFT processing section is i (i is a positive integer). In the output data of the first symbol and the input data of the i + 2th symbol, FFT processing is performed so that data having a common index indicating the order in the symbols is stored at the same address of the first or second RAM.

According to the invention of claim 11, in the output data of the i-th symbol and the input data of the i + 2th symbol by FFT processing of the FFT processing unit, data having a common index indicating the order in the symbols is the first or second. It can be stored at the same address of RAM. Therefore, the free area of the first or second RAM after reading the output data can be used as an input buffer for storing the input data of the next symbol, and the RAM for the input buffer can be omitted without adding a data string replacement RAM. Can be. Therefore, the configuration of two RAMs is possible by performing the processing of even-numbered symbols using the first RAM and the processing of odd-numbered symbols using the second RAM, among the plurality of consecutive symbols. The storage capacity required for the Fourier transform can be reduced.

According to the twelfth aspect of the present invention, in the fast Fourier transforming apparatus of the eleventh aspect, the i + 2th symbol data is input during the data output period of the ith symbol, and the butterfly operation of the i + 1th symbol is performed. .

In the invention of claim 13, the FFT processing section of the fast Fourier transforming apparatus of claim 11 includes a RAM address generation section for generating an address for accessing the first and second RAMs, and data stored in the first or second RAM. A first to selectively output to the first or second RAM by inputting a butterfly operation unit performing a butterfly operation and input data of the fast Fourier transform device or calculation result data of the butterfly operation unit based on A second data selector for inputting a data selector, output data of the first or second RAM as output data of the fast Fourier transform device, or selectively outputting the output to the butterfly computing unit, and generating the RAM address And a controller for controlling the first and second data selection units, wherein the RAM address generation unit includes i (i In the output data of the first symbol and the input data of the i + 2th symbol, an address which is generated such that data having a common index indicating the order in the symbols is stored at the same address of the first or second RAM. To convert from symbol to symbol.

In the invention of claim 14, the RAM address generation unit in the fast Fourier transforming apparatus of claim 13 generates an input / output guard dress which is a reference for an address for storing a symbol input data and an output data in the first or second RAM. An I / O address generation unit, a butterfly address generation unit for generating a butterfly operation guard address as a reference for an address for storing intermediate data during a butterfly operation in the first or second RAM, and the I / O address Converts the input / output guard dress generated by the generation unit into the input / output thread address, and simultaneously converts the butterfly calculation guard address generated by the butterfly address generation unit into the butterfly operation thread; One of the dress and butterfly calculation dresses And a RAM address conversion section for outputting to the first RAM and outputting the other to the second RAM.

In the invention of claim 15, the RAM address conversion section of the fast Fourier transforming apparatus of claim 14 performs bit reverse processing on the input / output bit reverse signal outputted from the control section with respect to the input / output guard signals generated by the input / output address generation section. The control unit outputs bit reverse processing to the first variable bit reverse unit that generates the input / output shielded address by the number of times indicated by the " ", and the butterfly operation generated by the butterfly address generator. A second variable bit reverse unit for generating a butterfly operation seal address by performing the number of times indicated by the specified butterfly operation bit reverse signal, an input / output seal address generated by the first variable bit reverse unit, and the Generated by the second variable bit reverse portion An address selector for inputting a butterfly operation address and selecting and outputting one of the addresses as the address of the first RAM and the other as the address of the second RAM according to the RAM selection signal output from the controller; It is.

According to the sixteenth aspect of the present invention, in the fast Fourier transforming apparatus of the fifteenth aspect, the maximum bit reverse number Rmax (Rmax is a positive integer) is obtained by subtracting one from the number of times of returning to the original address when the bit reverse processing is repeatedly performed. If the data input period for one symbol is a symbol period, the control unit repeats the number of iterations of the bit reverse processing that instructs the input / output bit reverse signal and the butterfly operation bit reverse signal every two symbol periods. Are updated to traverse from Rmax times in turn.

In the invention of claim 17, in the fast Fourier transforming apparatus of claim 16, the FFT processing unit performs FFT processing by preferentially using a butterfly operation of radix 4, and the maximum bit reverse number Rmax is equal to one symbol. It is assumed that the number of samples, which is the data number, is 1 when 4 ^m (m is a positive integer) and m × 2 when the number of samples is 4 ^m · 2.

Further, in the invention of claim 18, the RAM address conversion unit in the fast Fourier transforming device of claim 14 is an input / output guard address generated by the input / output address generator and a butterfly operation value generated by the butterfly address generator. An address selection section for inputting an address, selecting one of the address as the guard address of the first RAM and outputting the other as the guard address of the second RAM in accordance with a RAM selection signal output from the controller; Generating an address of the first RAM by performing bit reverse processing for the number of instructions indicated by the first RAM bit reverse signal outputted from the controller, with respect to the guard address of the first RAM selectively outputted by the controller; A first variable bit reverse unit and the second output selectively selected by the address selector; And a second variable bit reverse part for generating an address of the second RAM by performing bit reverse processing for the number of instructions indicated by the second RAM bit reverse signal outputted from the control part.

In the invention of claim 19, in the fast Fourier transforming apparatus of claim 18, when the bit reverse processing is repeatedly performed, the maximum bit reverse number Rax (Rmax is defined as the number obtained by subtracting 1 from the number of times to return to the original address). (Integer) and the data input period for one symbol is one symbol period, the controller controls the bit reverse processing for instructing the first RAM bit reverse signal and the second RAM bit reverse signal every two symbol periods. Each update is made so that the number of times is circulated in order from zero to Rmax.

In the invention of claim 20, in the fast Fourier transforming apparatus of claim 19, the FFT processing unit performs FFT processing by preferentially using a butterfly operation of radix 4, and the maximum bit reverse number Rmax is one symbol. It is assumed that the number of samples as the data number is 4 ^m (m is a positive integer) and m × 2 when the number of samples is 4 ^m · 2.

In the invention of claim 21, the FFT processing unit in the fast Fourier transforming apparatus of claim 11 generates a RAM address generating unit for generating an address for accessing the first and second RAMs, and data stored in the first or second RAMs. A butterfly operation unit for performing a butterfly operation on the basis of the?, And inputting the input data of the fast Fourier transform device or the calculation result data of the butterfly operation unit as inputs, and selectively outputting to the first RAM or the second RAM. A second data selector for inputting the first data selector, the output data of the first or second RAM into output data of the fast Fourier transform device, or selectively outputting the output to the butterfly computing unit, and the RAM address And a control unit for controlling a generation unit and the first and second data selection units, wherein the butterfly operation unit By using different butterfly operations, a plurality of substantially equivalent FFT processes can be executed, and in the output data of the i symbol and the input data of the i + 2 symbol, indices indicating the order among the symbols are common. The type of FFT processing to be executed is changed for each symbol so that data is stored at the same address of the first or second RAM.

In the invention of claim 22, the butterfly calculating unit in the fast Fourier transforming apparatus of claim 21 performs FFT processing using butterfly calculation by a frequency selection method on input data of a symbol stored in the first or second RAM. And a frequency selection operation unit which performs an FFT process using a butterfly operation by the time selection method for the input data of the symbol stored in the first or second RAM.

In addition, in the fast Fourier transform method in which fast Fourier transform is performed by using RAM, the solution means for storing the data for conversion for one symbol, which is a set of data for fast Fourier transform, is stored in RAM. A second step of performing fast Fourier transform processing (FFT processing) using a butterfly operation on the conversion target data stored in the RAM in the first step, and storing the processing result data in the RAM; In the second step, the third step of reading out the processing result data stored in the RAM from the RAM is repeated. The second step is processing result data stored in the RAM in the N (N is a positive integer) iterations. And data in which the object to be converted is stored in the RAM in the N + th iterations, in which the indices indicating the order in symbols are common. The address for accessing the RAM is changed each time so as to be stored at the same address in the RAM.

According to the invention of claim 23, by converting the address for accessing the RAM every time it is repeated, the data having the same index indicating the order in the symbols in the output data of one symbol and the input data of the next symbol is identical to that of the RAM. It can be stored at the address. In other words, an operation equivalent to data string replacement is realized by address translation. For this reason, the free area of RAM after reading the output data can be used as an input buffer for storing input data of the next symbol, and the input buffer RAM can be omitted without adding a data string replacement RAM. As a result, the storage capacity required for the fast Fourier transform can be reduced.

In the invention of claim 24, the second step in the fast Fourier transforming method of claim 23 uses bit reverse processing to group bits of addresses based on the radix of the butterfly operation, and to change the order of the bits in groups. The address is accessed every time the RAM is accessed.

Further, in the invention of claim 25, the second step in the fast Fourier transform method of claim 24 is to generate a bit reverse process by repeating a predetermined number of times for an address that is a reference to the address for accessing the RAM. When the number of subtracted 1 from the number of times of returning to the original address when the reverse processing is repeatedly performed is set as the maximum bit reverse number Rmax (Rmax is a positive integer), the second step is to execute the bit reverse processing for the reference address. By increasing the number of repetitions from time to time in order from 0 to Rmax, the address for accessing the RAM is changed every repetition.

According to a twenty-sixth aspect of the present invention, in the fast Fourier transform method of the twenty-fifth aspect, the second step is to perform FFT processing using preferential butterfly operations of radix 4, and the maximum bit reverse number Rmax is one symbol data. It is assumed that the sample number is 1 when 4 ^m (m is a positive integer) and m × 2 when the sample number is 4 ^m · 2.

In addition, a solution for pursuing the invention of claim 27 is a fast Fourier transform method for performing fast Fourier transform using a RAM, comprising: storing in one RAM a conversion target data for one symbol which is a set of data for fast Fourier transform; A first step and a second step of performing fast Fourier transform processing (FFT processing) using a butterfly operation on the data to be converted stored in the RAM in the first step, and storing the processing result data in the RAM; In the second step, the third step of reading the processing result data stored in the RAM from the RAM is repeated, and the second step executes a plurality of substantially equivalent FFT processes while using different butterfly operations. Processing result data stored in the RAM in the Nth iteration (N is a positive integer) and stored in the RAM in the N + 1 iteration According to the converted data, so that the index indicating the order of the symbols common data is stored in the same address of the RAM, iteration change the type of FFT processing to be executed.

According to the invention of claim 27, the type of FFT processing to be executed is changed at each iteration, so that in the output data of one symbol and the input data of the next symbol, data having a common index indicating the order in the symbols is the same address in RAM. It can be stored in. For this reason, the free area of RAM after reading the output data can be used as an input buffer for storing the input data of the next symbol, and the input buffer RAM can be omitted without adding a data string replacement RAM. As a result, the storage capacity required for the fast Fourier transform can be reduced.

In the invention of claim 28, the second step in the fast Fourier transform method of claim 27 alternates between FFT processing using the butterfly operation by the frequency selection method and FFT processing using the butterfly operation by the time selection method. To do.

In the variable bit reverse circuit which performs the bit reversal processing for a butterfly operation repeatedly by the specified number of times, the several solution connected in series which performs one bit reverse processing, respectively in the invention. The reverse circuit includes a reverse circuit, and among the plurality of bit reverse circuits, a number corresponding to a specified number of bit reverses performs bit reverse, and the rest passes data.

According to the thirty-ninth aspect of the present invention, the variable bit reverse circuit of claim 29 performs bit reverse corresponding to a plurality of samples, and further includes a plurality of bit reverse circuits so as to match positions of valid bits in input data and output data. And bit shift means for bit shifting the bit reversed data.

Further, in the thirty-first aspect of the present invention, in the variable bit reverse circuit of the thirtieth aspect, it is assumed that bit exchange means for exchanging bits is provided before any one of the plurality of bit reverse circuits.

In addition, a solution for pursuing the invention of claim 32 is to apply the invention of claim 1 to an inverse fast Fourier transform device for performing Fourier transform, and to convert the input data into an inverse fast Fourier transform for inverse fast Fourier transform. A RAM to store for each symbol that is a set of data to be performed, and an IFFT processing unit to perform inverse fast Fourier transform processing (IFFT processing) using a butterfly operation on the input data stored in the RAM, wherein the RAM is one stored in the RAM. Storing the data obtained as a result of the IFFT processing by the IFFT processing unit for the input data of the symbol of as the output data of the one symbol, wherein the IFFT processing unit stores one symbol output data and this symbol after the one symbol; In the input data of other symbols to be stored, indices indicating the order in the symbols are common IFFT processing is performed so that the in-data is stored at the same address of the RAM.

In the invention of claim 33, the inverse fast Fourier transform device of claim 32, wherein the IFFT processing unit includes a RAM address generation unit for generating an address for accessing the RAM, and in accordance with the address generated by the RAM address generation unit. The RAM address generation unit is for accessing the RAM, and in the output data of one symbol and input data of another symbol stored in the RAM after the output data of this symbol, indices indicating the order among the symbols are common. It is assumed that the generated address is converted for each symbol so that data is stored at the same address of the RAM.

In the invention of claim 34, the inverse fast Fourier transform device of claim 32, wherein the IFFT processing unit includes a butterfly operation unit that performs an IFFT process using a butterfly operation on the input data stored in the RAM. The computing unit may execute a plurality of substantially equivalent IFFT processes while using different butterfly operations, and output data of one symbol and input data of another symbol stored in the RAM after the output data of this symbol. The type of IFFT processing to be executed is changed for each symbol so that data having a common index indicating the order in the symbols is stored at the same address of the RAM.

In addition, a solution for pursuing the invention of claim 35 applies the invention of claim 23 to an inverse fast Fourier transform, and in the inverse fast Fourier transform method in which an inverse fast Fourier transform is performed using a RAM, data for performing inverse fast Fourier transform A first step of storing data to be converted for one symbol, which is a set of data, in RAM; and performing an inverse fast Fourier transform process using a butterfly operation on the data to be converted stored in the RAM in the first step; The second step of storing the result data in the RAM, and the third step of reading the processing result data stored in the RAM from the RAM in the second step is repeated, the second step is N (N is defined The processing result data stored in the RAM in the first iteration and the data to be converted in the RAM in the N + 1 iteration. On, so is the index indicating the order of the symbols common data is stored in the same address of the RAM, to iteration converts the address for accessing the RAM.

In addition, a solution for pursuing the invention of claim 36 applies the invention of claim 27 to an inverse fast Fourier transform, and in the inverse fast Fourier transform method in which an inverse fast Fourier transform is performed using a RAM, data for inverse fast Fourier transform is performed. A first step of storing data to be converted for one symbol, which is a set in RAM, and an inverse fast Fourier transform process (IFFT process) using a butterfly operation on the data to be converted stored in the RAM in the first step; And repeating the second step of storing the processing result data in the RAM and the third step of reading the processing result data stored in the RAM from the RAM in the second step, wherein the second step is mutually Multiple different types of IFFT processing can be performed while using different butterfly operations, with N (N being a positive integer) In the processing result data stored in the RAM and the conversion target data stored in the RAM in the N + th iteration, data having a common index indicating the order in symbols is stored in the same address of the RAM. The type is changed at each iteration.

Further, the invention of claim 37 is an OFDM receiver for demodulating a received orthogonal frequency division multiplex (OFDM) signal into received data, comprising: a digital demodulator for demodulating an OFDM signal into a baseband signal, and a demodulated by the digital demodulator; A fast Fourier transform unit for performing fast Fourier transform on the received baseband signal, and decoding complex data of the carrier, and generating received data based on the complex data of the carrier, wherein the fast Fourier transform unit It consists of the fast Fourier converter described.

Further, in the invention of claim 38, in the OFDM transmitter which modulates transmission data into an OFDM signal, an inverse fast Fourier transform unit for performing inverse fast Fourier transform on complex data of a carrier generated from the transmission data, and the inverse fast Fourier transform; And a digital modulator that performs frequency conversion on the negative output and generates an OFDM signal, and the inverse fast Fourier transform unit comprises the inverse fast Fourier transform device according to claim 32.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

(Example)

(First embodiment)

Hereinafter, a fast Fourier transform apparatus according to a first embodiment of the present invention will be described with reference to the drawings.

1 is a block diagram showing the configuration of a fast Fourier transform apparatus according to a first embodiment of the present invention. In FIG. 1, 101 and 102 are first and second RAMs (i.e., RAM # 0 and RAM # 1 in FIG. 1) for storing input / output data and intermediate data during a butterfly operation, and 103 are butters for performing a butterfly operation. Ply calculation unit 104 is a rotor generator for generating a rotor for use in butterfly operation 105 is a RAM address generator for generating an address for accessing the first and second RAM (101, 102), 106 is a RAM address The control unit controls the generation unit 105 and the like.

As an element of the RAM address generator 105, 111 is an input / output address generator for generating an input / output guard address (DAD) which is a reference for a RAM address during data input / output, and 112 is a reference for a RAM address during a butterfly operation. The butterfly address generator for generating a butterfly operation guard address (BAD), 113 is an I / O bit reverse signal (DBR) with respect to the input / output guard address (DAD) generated by the input / output address generator (111). A first variable bit reverse part for generating the input / output shield address RDAD by performing bit reverse processing (described in detail later) by the number of times indicated by the < RTI ID = 0.0 >), < / RTI > Butter by performing bit reverse processing on the butterfly operation garde (BAD) as many times as indicated by the butterfly operation bit reverse signal (BBR). A second variable bit reverse unit for generating a fly operation seal address RBAD, and 115 is an input / output seal address RDAD and the second variable bit reverse unit 114 output from the first variable bit reverse unit 113; The address selection unit outputs the output butterfly arithmetic address RBAD as an input, selects one side as an address of the first RAM 101 and selects and outputs the other as an address of the second RAM 102. The RAM address conversion unit 131 is configured by the first and second variable bit reverse units 113 and 114 and the address selector 115.

In addition, 121 inputs the input data of the fast Fourier transform device and the calculation result data of the butterfly calculating unit 103 as input, one as input data of the first RAM 101, and the other as the second RAM 102. The first data selector 122 that selects and outputs the input data as the input data of < RTI ID = 0.0 >) < / RTI > Is a second data selector for selectively outputting the data as the input data of the butterfly operator 103.

The FFT processing unit is constituted by the butterfly calculating unit 103, the rotor generating unit 104, the RAM address generating unit 105, the control unit 106, and the first and second data selection units 121 and 122.

The operation of the fast Fourier transform device according to the present embodiment configured as described above will be described below. In the following description, the data of the sample number for Fourier transform is referred to as one symbol.

2 is a timing diagram showing processing timing in the fast Fourier transform apparatus according to the present embodiment. In this embodiment, as shown in Fig. 2, as the processing of the i-th (i is an integer) symbol, after the symbol input, a butterfly operation is performed in the (i + 1) th symbol input period, and (i + 2 In the second symbol input period, the symbol output after the Fourier transform is performed (the hatched portion in Fig. 2). In other words, in the present embodiment, when one symbol input period is one symbol period, the symbol input, the butterfly operation of the preceding symbol, and the two preceding symbol outputs are overlapped in one symbol period. In other words, in the i-th symbol input period, the butterfly operation of the (i-1) th symbol and the (i-2) th symbol output are performed in parallel.

In the present embodiment, the above operation is realized by appropriately using the two RAMs 101 and 102.

3 is a timing chart showing RAM switching timing in the fast Fourier transform device according to the present embodiment. Fig. 3 shows RAM switching timing when fast Fourier transform of the sample number N (N is a positive integer), and x (0) to x (N-1) are input data (data before conversion) for each symbol. ), X (0) to X (N-1) are output data (data after conversion) in each symbol. Note that the FFT process i (i is an integer) indicates a fast Fourier transform process of the i-th symbol.

In this embodiment, one of the two RAMs 101 and 102 (RAM # 0, RAM # 1) is used for fast Fourier transform of even symbols, and the other is fast Fourier transform of odd symbols. Do it. As shown in Fig. 3, in the FFT process (i), the input data x (0) to x (N-1) is stored in the first RAM 101 in the i-th symbol input period (symbol input (i)). ), the butterfly operation is performed while storing intermediate data in the first RAM 101 in the (i + 1) th symbol input period (butterfly operation (i)), and in the (i + 2) th symbol input period. Data stored in the first RAM 101 is read out as output data X (0) to X (N-1) (symbol output i). Similarly, FFT processing (i-2) and FFT processing (i + 2) are executed using the first RAM 101, while FFT processing (i-1) and FFT processing (i + 1) are second It is executed using the RAM 102.

In addition, the symbol input i and the symbol output i-2 are performed overlapping within one symbol period using the same RAM. As a result, the two RAMs 101 and 102 are alternately used for each symbol period for symbol input / output or butterfly calculation. The two RAMs 101 and 102 are replaced by the data selection units 121 and 122.

By overlapping the symbol input and the symbol output, one symbol period can be covered as an operation period of a butterfly operation requiring much RAM access and operation. This realizes a reduction in the operating speed required for the first and second RAMs 101 and 102 and a reduction in the circuit scale of the butterfly calculating unit 103.

4 is a signal flow graph showing a radix 4x2 time selection method as an example of a fast Fourier transform algorithm. 5 is a diagram illustrating arithmetic elements in a signal flow graph. 4 is a signal flow graph when the number of samples N = 32, where x (0) to x (N-1) are input data before conversion, and X (O) to X (N-1) are output data after conversion; Wi is the coefficient of rotor multiplication. Radix 4x2 represents the operation which combined radix 4 butterfly operation and radix 2 butterfly operation.

As shown in Fig. 4, in the fast Fourier transform algorithm, a butterfly operation for several stages and a rotor multiplication between stages are performed on input data x (O) to x (N-1) to output data X (O). To generate X (N-1). In the radix 4x2 time selection method shown in FIG. 4, radix 4 butterfly calculation is performed in two stages (stage 0, stage 1) of the first half, and radix 2 butterfly calculation is performed in a final stage (stage 2).

As shown in Fig. 5, each operation is performed according to the following expression.

<Radix 4 butterfly operation>

X0 = x0 + x1 + x2 + x3

X1 = x0-jx1-x2 + jx3

X2 = x0-x1 + x2-x3

X3 = x0 + jx1-x2-jx3

<Radix 2 butterfly operation>

XO = x0 + x1

X1 = xO-x1

<Rotor odds>

Y = yW ⁱ

W = e ^{-j2π / N}

The fast Fourier transform algorithm has a feature that the order of input data x (0) to x (N-1) and output data X (0) to X (N-1) are different. In the radix 4x2 time selection method shown in FIG. 4, the output data X (j) is in ascending order from j to 0, 1, 2, 3, ..., whereas the input data x (j) is j from above. = 0, 8, 16, 24 Skip to value.

In order to overlap the symbol input and the symbol output, reading of the output data and writing of the input data need to be performed in parallel. For this purpose, the index indicating the order of symbols in the output data of one symbol and the input data of the next symbol is common. Data must be stored at the same address in RAM. Therefore, conventionally, in order to match the order in which the input data and the output data are stored in the RAM, the order of the input data x (j) in the fast Fourier transform algorithm shown in FIG. 4 is similar to that of the output data X (j). From above, data string replacement with j = 0, 1, 2, 3 ... was required.

On the other hand, in the present embodiment, the address accessing the RAM is converted for each symbol by bit reverse processing to realize processing equivalent to data string replacement, thereby making data string replacement unnecessary. Specifically, by changing the number of iterations of the bit reverse processing for the reference address from symbol to symbol (this is called "variable bit reverse"), the address for accessing the RAM is converted for each symbol.

6 and 7 are diagrams for showing the effect of variable bit reverse of an address in this embodiment, FIG. 6 is a diagram showing data transfer between RAMs without variable bit reverse of an address, and FIG. A diagram showing data transfer between RAMs with variable bit reverse. 6 and 7 show data transfer between RAMs when the number of samples N = 8, and only one of two RAMs included in the fast Fourier transform device. The one RAM stores input / output data of either the even or odd symbols and intermediate data in the butterfly operation of the input data of the symbol.

In the FFT process [i], which is a fast Fourier transform for the i-th symbol, the butterfly operation is performed while storing input data x (0) to x (7) as a symbol input in RAM, and storing intermediate data during operation in RAM. Then, the output data X (0) to X (7) stored in the RAM is read and symbolically output.

In this case, in the data transfer between the RAMs without the variable bit reverse of the address as shown in Fig. 6, the output data X (k) of the FFT process [i] and the input data x (k) of the FFT process [i + 2] are It is not necessarily stored at the same address of the RAM. Therefore, after reading the output data X (k) of the FFT process [i], data string replacement is required to store the input data x (k) of the FFT process [i + 2] at the same address.

On the other hand, in the inter-RAM data transfer with the variable bit reverse of the address according to the present embodiment as shown in Fig. 7, the FFT process [i is performed by changing the input / output address and the butterfly operation address for each FFT process by bit reverse. RAM address at which the output data X (k) is stored and RAM address at which the input data x (k) of the FFT process [i + 2] are stored can be the same address. Accordingly, after reading the output data X (k) of the FFT process [i], the input data x (k) of the FFT process [i + 2] can be stored at the same address, and the symbol input and the symbol output before two are output. The overlap of can be realized.

Changes in the address for input and output and the address for butterfly operations are controlled by the number of bit reverses. The bit reverse count is initialized to zero after the FFT process is increased to become the maximum bit reverse count Rmax (Rmax is a positive integer). The maximum bit reverse number Rmax is a number obtained by subtracting 1 from the number of times of returning to the original address when the bit reverse process is repeatedly performed, and is determined by the number of samples, the type of butterfly operation used for the FFT process, and the like. In the example shown in FIG. 7, the maximum bit reverse number Rmax is two times, and the bit reverse number is updated for each FFT process to traverse from zero to two.

8 is a diagram illustrating an outline of bit reverse. Bit reverse is a method for calculating the order of data required for fast Fourier transform from the order of inputting data. Specifically, as shown in Fig. 8, first, the binary bits representing the data input order are grouped in order from the LSB in correspondence with each stage in the butterfly operation. If the number of bits corresponding to the stage s is r (s), the following equation (1) is obtained.

(s) = log ₂ (base of stage (s))

(s = 0, 1, ..., M-1: M is the number of stages)

Next, the grouped bits are reversed by replacing the upper and lower parts while maintaining the bit positions in the group.

FIG. 9 is a diagram showing an example of bit reverse, and is a diagram showing bit reverse in the radix 4x2 time selection method in the case of the sample number N = 32 as shown in FIG. For sample number N = 32,

N = 32 = 2 ⁵

The binary number representing the data input order is from 5 bits. First, binary numbers are grouped sequentially from the LSB in correspondence with each stage in the butterfly operation. As shown in Fig. 4, the stage 0 and 1 perform the radix 4 butterfly operation, and the stage 2 perform the radix 2 butterfly operation,

r (0) = r (1) = log ₂ 4 = 2

r (2) = log ₂ 2 = 1

Therefore, binary numbers representing the data input order are grouped into 2 bits, 2 bits, and 1 bit from the LSB. After grouping, bit reverse is performed by swapping the top and bottom while maintaining the bit position in the group. As a result, as shown in Fig. 9, the bit string a4 a3 a2 a1 a0 before the bit reverse is converted into the bit string a1 a0 a3 a2 a4 by bit reverse.

In this embodiment, a variable bit reverse that repeats bit reverse as shown in Figs. 8 and 9 is adopted, and the RAM address in data input / output and butterfly operations is appropriately converted.

FIG. 10 is a diagram showing an example of address change caused by variable bit reverse, and is a diagram corresponding to data transfer between RAMs shown in FIG. Fig. 7 shows data transfer between RAMs in the radix 4x2 time selection method when the number of samples N = 8, so the number of bits in the address is

N = 8 = 2 ³

3 bits, and the 3 bits address is grouped into 2 bits, 1 bit in order from the LSB, and bit reversed. Therefore, from the guard address a2 a1 a0 before the bit reverse, as the address, a2 a1 aO (number of bit reverses = O), al a0 a2 (number of bit reverses = 1), a0 a2 a1 (number of bit reverses = 2) are bits. Generated by reverse. The numeric string to the right of each address bit indicates the order of addresses by each address bit in decimal.

FIG. 11 is a diagram showing a change in address due to variable bit reverse, and is a diagram corresponding to data transfer between RAMs in the radix 4x2 time selection method when the number of samples N = 32. FIG. In FIG. 11, since the number of samples N is 32 (= ²⁵ ), the number of bits in the address is 5, and in stage 0 and 1, the radix 4 butterfly operation is performed, and in stage 2, the radix 2 butterfly operation is performed. The address is bit reversed grouped into 2 bits, 2 bits, and 1 bit in order from the LSB. Therefore, from the address before a bit reverse a4 a3 a2 a1 a0, as a real address, a4 a3 a2 a1 a0 (number of bit reverses = O), a1 a0 a3 a2 a4 (number of bit reverses = 1), a2 a4 a0 a3 a1 ( Bit reverse number = 2), a3 a1 a4 a0 a2 (bit reverse number = 3) and a0 a2 a1 a4 a3 (bit reverse number = 4) are generated by bit reverse.

Fig. 12 is a diagram showing a change in address due to variable bit reverse, and corresponding to data transfer between RAMs in the radix 4x2 time selection method in the case where the number of samples N = 16. In FIG. 12, since the sample number N is 16 (= 2 ⁴ ), the number of bits in the address is 4, and in stages 0 and 1, the radix 4 butterfly operation is performed. Grouped into bits and beat reversed. Therefore, from the guard address a3 a2 a1 a0 before the bit reverse, as the address, a3 a2 a1 a0 (the number of bit reverses = 0) and a1 a0 a3 a2 (the number of bit reverses = 1) are generated by bit reverse.

As can be seen from Figs. 10 to 12, repetition of the bit reverse of the address always returns to the original address. Therefore, the number of required real addresses is finite, and for example, the actual address can be generated by increasing the number of repetitions of the bit reverse processing to the reference address in order from 0 to the maximum bit reverse number Rmax. Can be.

In addition, in the case of Fig. 10, the maximum bit reverse number Rmax is 2 since the bit reverse is returned to the original address. Similarly, in the case of Fig. 11, the maximum bit reverse number Rmax is four, and in the case of Fig. 12, the maximum bit reverse number Rmax is one. When the radix 4x2 time selection method is used with the radix 4 butterfly operation first, the relationship between the number of samples N and the maximum bit reverse number Rmax can be expressed by the following equation (2).

For N = 4 ^m (m is a positive integer): ax = 1

For N = 4 ^m2 (m is a positive integer): ax = log ₂ N-1 = 2m

A detailed configuration and operation of each part of the fast Fourier transform device according to the present embodiment shown in FIG. 1 will be described below, taking the case of sample number N = 32 as an example.

Fig. 13 is a signal flow graph in the case of sample number N = 32, and is a figure which shows the calculation procedure of a butterfly operation in a present Example. In Fig. 13, the numbers given to the parts corresponding to the butterfly operations are the procedures of the butterfly operations in this embodiment. In order to reduce the power consumption of the device, in order to reduce the coefficient change of the rotor operation, the butterfly operation is carried out 4s (s is the stage number: s = 0, 1,…) in order from the top, In stage 2, the butterfly operations are executed in order from the top.

Processing in the order of operations shown in FIG. 13 will be described for the configuration and operation of each part of the fast Fourier transform apparatus according to the present embodiment.

14 and 15 are timing diagrams showing signals for controlling the RAM address generator 105 generated and output by the controller 106. In FIG. 14, DCN is an input / output timing signal for controlling the operation timing of the input / output address generator 111, BCN, BST is a butterfly operation timing signal and a butterfly for controlling the operation timing of the butterfly address generator 112. Operation stage signal. When the number of samples is N, the input / output timing signal DCN is a signal of 1og ₂ (N) bits, and the value thereof is sequentially changed from 0 to (N-1) during one symbol period, and iterates every symbol period. In this case, since N = 32, the input / output timing signal DCN is a 5 (= 1og ₂ 32) bit signal. When the number of stages of the butterfly operation is M, the value of the butterfly operation stage signal BST is changed in sequence from 0 to (M-1) during one symbol period, and the butterfly operation timing signal BCN The value of the butterfly arithmetic stage signal BST changes from 0 to (N-1) in a constant period.

In FIG. 15, the DBR denotes an input / output bit reverse signal for controlling the first variable bit reverse unit 113, the BBR denotes a butterfly reverse signal for controlling a second variable bit reverse unit, and the RSL denotes an address selector 115. The RAM selection signal for controlling the selection operation. The butterfly operation bit reverse signal BBR is updated to traverse from zero to the maximum bit reverse number Rmax in order, and the input / output bit reverse signal DBR is one symbol period longer than the butterfly operation bit reverse signal BBR. Updated late to traverse from zero to Rmax. The RAM selection signal RSL is switched between the "H" level and the "L" level for each symbol period.

16 is a timing diagram showing the operation timing of the butterfly calculating unit 103. The butterfly calculating unit 103 performs three rotor multiplications and one radix four butterfly operation at the stage of the butterfly operation of radix 4, and two rotor multiplications and two at the stage of the butterfly operation of radix 2 Two radix butterfly operations are performed. Namely, four inputs and four outputs are calculated. Therefore, as shown in FIG. 16, the butterfly calculating unit 103 is adapted to input data D0 to D3 read from the first RAM 101 or the second RAM 102 through the second data selecting unit 122. The rotor multiplication and the butterfly operation of radix 4 or radix 2 are performed, and data XO to X3 are output. Input / output of data is performed for each update period of the butterfly operation timing signal BCN generated by the control unit 106, and output of the output data X0 to X3 with respect to the input timing of the input data D0 to D3. The timing is delayed by four cycles.

The input / output address generator 111 receives an input / output timing signal DCN generated by the controller 106 and generates an input / output guard address DAD. The input / output guard DAD is determined irrespective of the number of bit reverses, and the input address generator 111 outputs the input / output timing signal DCN, which is a 5-bit signal, as the input / output guard DAD.

The butterfly address generation unit 112 takes the butterfly operation timing signal BCN generated by the control unit 106 as an input, and generates the butterfly operation guard address BAD. The butterfly arithmetic guard address BAD is determined by the stage number and the radix of the butterfly arithmetic irrespective of the number of bit reverses, and the butterfly address generating unit 112 is a part of the timing arithmetic signal BCN for the arithmetic operation. All bits are used to generate the butterfly operation guard (BAD) according to the butterfly operation stage signal (BST).

The first variable bit reverse unit 113 receives an input / output garde DAD generated by the input / output address generator 111 and is generated by the control unit 106 with respect to the input / output garde DAD. The bit reverse processing of the number of times indicated by the input and output bit reverse signal DBR is performed, and the input and output seal address RDAD is generated. Similarly, the second variable bit reverse unit 114 takes the butterfly operation guard address BAD generated by the butterfly address generation unit 112 as an input, and with respect to the butterfly operation guard address BAD. The number of bit reverse processes indicated by the butterfly arithmetic bit reverse signal BBR generated by the control unit 106 is performed to generate a butterfly arithmetic thread RBAD.

FIG. 17 is a diagram showing an example of the configuration of the first and second variable bit reverse units 113 and 114.

Fig. 17A shows an example of the configuration of the selector type, and shows the result of performing the bit reverse once by the bit reverse unit 501 with an address without bit reverse to the input address DAD (BAD). Address, the address of the result of performing the bit reverse twice by the bit reverse part 502, and the address of the result of performing the bit reverse Rmax times by the Rmax bit reverse part 503, respectively, The selector 504 selects and outputs the real address RDAD (RBAD) according to the bit reverse signal DBR (BBR) among the addresses.

17B shows an example of a tabular configuration, in which each address of the bit reverse result of the guard address DAD (BAD) is stored in a table (ROM) 505 in advance, and the entered guard address ( The address connected to the bit reverse signal DBR (BBR) by the bit connection circuit 506 on the upper (or lower) side of the DAD (BAD) is referred to as a reference address, and the real address RDAD (RBAD) from the table 505 is used. ).

FIG. 18 is a diagram showing an input / output address generation operation by the input / output address generating unit 111 and the first variable bit reverse unit 113 in this embodiment, and the input / output timing signal DCN and the bit reverse signal for input / output A diagram showing correspondence between the DBR, the input / output guard dress DAD, and the input / output shield address RDAD. As shown in FIG. 18, the input / output guard address DAD always becomes the input / output timing signal DCN regardless of the value of the input / output bit reverse signal DBR. In addition, the input / output shield RDAD divides the group into two bits, two bits, and one bit from the LSB for the input / output guard address DAD, and repeats bit reversal as many times as the value of the input / output bit reverse signal DBR. It becomes.

FIG. 19 is a view showing the operation of the butterfly operation address generation by the butterfly address generation unit 112 and the second variable bit reverse unit 114 in the present embodiment, and the butterfly operation timing signal BCN. ) Shows the correspondence between the butterfly operation stage signal BST and the butterfly operation bit reverse signal BBR, the butterfly operation guard address BAD, and the butterfly operation shield address RBAD. As shown in FIG. 19, the butterfly operation guard dress BAD uses the butterfly operation timing signal BCN as a reference butterfly operation stage regardless of the value of the butterfly operation bit reverse signal BBR. It is determined according to the signal BST. In addition, the butterfly arithmetic address (RBAD) is divided into two bits, two bits, and one bit from the LSB with respect to the butterfly arithmetic guard address (BAD), thereby recovering the value of the butterfly arithmetic bit reverse signal (BBR). The beat reverse is repeated.

The address selector 115 inputs the input / output seal address RDAD output from the first bit reverse circuit 113 and the butterfly operation seal address RBAD output from the second bit reverse circuit 114 as inputs. In accordance with the RAM selection signal RSL input from the control unit 106, one is designated as the address of the first RAM 101, and the other is selected and output as the address of the second RAM 102.

20 is a diagram showing the configuration of the address selector 115. In Fig. 20, 601 to 603 are select circuits, and 611 to 614 are registers. The RAM to which the input / output shield address RDAD is output by the address selector 115 among the first and second RAMs 101 and 102 is read into the same address after reading the output data stored at the designated address RDAD. Write the data. On the other hand, the RAM for outputting the butterfly operation address RBAD to the address selector 115 also reads the data stored at the designated address RBAD as the input data of the butterfly operation unit 103, and then reads the same address. The output data of the butterfly calculating unit 103 is written.

However, as shown in FIG. 16, since the data output from the butterfly calculator 103 is delayed with respect to the data input, the address selector 115 displays the butterfly operation address RBAD as shown in FIG. 20. ) Are provided with registers 611 to 614 for holding the predetermined period of time. The registers 611 to 614 operate in synchronism with the update cycle of the butterfly operation timing signal BCN, and by four serial connection of such registers, the address selector 115 outputs the data of the butterfly operation unit 113. It is possible to hold the butterfly computational address (RBAD) for the last four cycles of this data input. The selection circuit 603 selects and outputs either the butterfly arithmetic address RBAD or the four-period butterfly arithmetic address RBAD according to the butterfly arithmetic address selection signal BADSL. The selection circuits 601 and 602 select one of the input and output shield addresses RDAD and the butterfly operation shield addresses RBAD output from the selection circuit 603 according to the RAM selection signal RSL. ), And the other is selectively outputted as the address of the second RAM 102.

21 and 22 are timing diagrams illustrating RAM access timing using a RAM address output from the address selector 115, that is, a RAM address generated by the RAM address generator 105. Fig. 21 is a diagram showing the access timing of the RAM in data input / output, and Fig. 22 is a diagram showing the access timing of the RAM during the butterfly operation. In Figs. 21 and 22, portions indicated by diagonal lines represent RAM accesses of the same address.

As shown in Fig. 21, in the data input / output, the update cycle of the timing signal DCN for input / output is divided in half so that the first half is read access cycle and the second half is RAM access. At this time, data reading and data writing in one update period of the input / output timing signal DCN are performed for the same address.

On the other hand, in the butterfly operation, as shown in Fig. 22, the update cycle of the butterfly operation timing signal BCN is divided in half to perform RAM access with the first half of the read cycle and the second half of the write cycle. At this time, data reading in one update period of the butterfly operation timing signal BCN and data writing in an update period four cycles later from the one update period are performed for the same address.

As described above, the present embodiment converts each symbol by changing the number of bit reverses for the reference address as the reference for accessing the RAM for each symbol. Accordingly, output data of one symbol and input data of the next symbol are changed. In this case, data having a common index indicating the order of symbols can be stored at the same address in RAM. That is, after reading output data of one symbol from the RAM, input data of the next symbol can be written at the same address, and an empty area of the RAM after reading the output data is used as an input buffer for storing input data of the next symbol. Since it can be used, the RAM for the input buffer becomes unnecessary. Therefore, the configuration of the two RAMs is performed by appropriately changing the RAM so that the even-numbered symbols are processed by the first RAM and the odd-numbered symbols are processed by the second RAM. This becomes possible.

In addition, the structure of the variable bit reverse parts 113 and 114 shown in FIG. 17 is a case where the number of samples is fixed. On the other hand, when a fast Fourier transform device is used for a communication device, the fast Fourier transform of several kinds of samples must be performed according to the communication standard. In order to correspond to the fast Fourier transform apparatus according to the present embodiment to a plurality of samples, the variable bit reverse units 113 and 114 must be configured to enable address generation for each sample number. In other words, a variable bit reverse circuit is required that can execute a plurality of variable bit reverses having different conversion patterns.

For example, a variable bit reverse circuit capable of generating an address for each sample number can be configured by providing the configuration as shown in FIG. 17A with respect to each sample number. In this case, however, the circuit scale becomes enormous, which in turn leads to an increase in the circuit scale of the RAM address generator 105, which is undesirable.

Therefore, in the present embodiment, a configuration of a variable bit reverse circuit that realizes a plurality of variable bit reverses having different conversion patterns in a small circuit.

FIG. 23 is a diagram showing another example of the configuration of the first and second variable bit reverse units 113 and 114, and shows a variable bit reverse circuit for realizing a plurality of variable bit reverses having different conversion patterns in a small circuit. It is a circuit diagram. Specifically, the variable bit reverse circuit shown in FIG. 23 is configured to be capable of performing variable bit reverse for the number of samples N = 4, 8, 16, and 32, respectively. In Fig. 23, 701 to 704 are bit reverse circuits BR, 711 are bit exchange circuits BC as bit exchange means, and 721 are barrel shifters BS as bit shift means.

FIG. 24 is a circuit diagram showing the configuration of each circuit constituting the variable bit reverse circuit shown in FIG. 23, in which (a) is a configuration of the bit reverse circuit BR, and (b) is a bit switching circuit ( BC) and (c) show the configuration of the barrel shifter BS, respectively.

As shown in FIG. 23, each bit reverse circuit 701 to 704 is controlled by each bit of the bit reverse control signal BRSEL. As shown in FIG. 24A, each of the bit reverse circuits 701 to 704 outputs the input data as it is when the corresponding bit of the bit reverse control signal BRSEL is "0", while outputting it as it is. When &quot; 1 &quot;, bit reverse is performed in the radix 4x2 time selection method in the case where the number of samples N = 32 as shown in FIG. The operation is switched by the selector 801 in accordance with the bit reverse control signal BRSEL.

In addition, the bit exchange circuit 711 is controlled by the bit exchange control signal BCSEL. As shown in (b) of FIG. 24, when the bit exchange control signal BCSEL is "0", the data is output through the input data as it is, while when "1", the bit of the input data is exchanged up and down. do. The operation is switched by the selector 802 in accordance with the bit exchange control signal BCSEL.

The barrel shifter 721 is controlled by the shift control signal BSSEL (2 bits), and the selector controlled by the lower bit of the shift control signal BSSEL as shown in Fig. 24C. 803 and the selector 804 switch-controlled by the high order bit are connected in series. The selector 803 outputs the input data as it is when the lower bit of the shift control signal BSSEL is "0", and shifts the input data one bit to the right when "1". The selector 804 outputs the input data as it is when the upper bit of the shift control signal BSSEL is "0", and shifts the input data two bits to the right when it is "1". By this operation, the data inputted to the barrel shifter 721 is shifted 1 bit to the right when the shift control signal BSSEL is "00", 1 bit to the "01", and 2 bit to the right when the "10". , When it is 11, 3 bits are shifted right and output.

FIG. 25 is a diagram showing the set values of the respective control signals of the variable bit reverse circuit shown in FIG. 23, in which (a) is the number of samples N = 32, (b) is the number of samples N = 16, and (c). Indicates the set value of each control signal in the case where the number of samples N = 8 and (d) indicates the number of samples N = 4.

The bit reverse control signal BRSEL changes in accordance with the number of bit reverses, and a value is set so that the bit reverses only as much as the number of bit reverses from the input side among the bit reverse circuits 701 to 704. For example, in the case of the number of samples N = 32, as shown in FIG. 25 (a), the bit reverse control signal BRSEL indicates that only the bit reverse circuit 701 performs bit reverse when the number of bit reverses is one. 0001 ”, and when the number of bit reverses is three, only the bit reverse circuits 701 to 703 are set to“ 0111 ”to perform bit reverse.

The bit exchange control signal BCSEL changes according to the number of bit reverses only when the number of samples N = 8, and is set to "1" only when the bit reverse circuit 701 performs bit reverse. In other words, the bit exchange circuit 711 performs bit exchange only when the number of bit reverses is 1 or 2 when the number of samples N = 8.

The shift control signal BSSEL is a value other than "O0" when the number of bit reverses is odd when the number of samples N = 32 is different. The value is also set according to the number of samples. When the number of samples N = 16, it becomes "01" as shown in FIG. 25 (b). When the number of samples N = 8, it becomes "10" as shown in FIG. 25 (c). When N = 4, it becomes “11” as shown in Fig. 25D. That is, the barrel shifter 721 shifts the data one bit right when the number of bits reverse is 1 when the number of samples N = l6, and shifts the data two bits by the right when the number of bits reverse is 1 when the number of samples is N = 8. If the number of samples is N = 4, the data is shifted right three bits when the number of bit reverses is one.

The operation of the variable bit reverse circuit shown in FIG. 23 will be described taking the case where the sample number N = 8 as an example. In this case, the variable bit reverse is as shown in Fig. 10 from the guard address a2 a1 a0 before the bit reverse as a2 al a0 (number of bit reverses = 0), a1 a0 a2 (bit reverse number = 1), a0 as a real address. a2 a1 (bit reverse count = 2) is generated.

FIG. 26 is a diagram showing the operation of the variable bit reverse circuit shown in FIG. 23 when the number of samples N = 8, where (a) is the number of bit reverses, and (b) is the number of bit reverses. Indicates the operation when is 2.

When the number of bit reverses is 1, as shown in Fig. 26A, bit exchange, bit reverse, and 2-bit shift are performed. That is, since the bit exchange control signal BCSEL becomes "1", the bit exchange is performed by the bit exchange circuit 711, and since the bit reverse control signal BRSEL becomes "0001", the bit reverse circuit 701. Only bit reverse is performed, and since the bit shift control signal BSSEL becomes &quot; 10 &quot;, the bit shift of 2 bits is performed by the barrel shifter 721. The lower 3 bits of the bit string generated by this operation become an effective address, and a1 a0 a2 is generated from the address a2 a1 a0 as a real address.

When the number of bit reverses is two, as shown in FIG. 26B, bit swapping and two bit reverses are performed. That is, since the bit exchange control signal BCSEL becomes "1", bit exchange is performed by the bit exchange circuit 711, and the bit reverse control signal BRSEL becomes "0011". Bit reverse is performed by 702). On the other hand, since the bit shift control signal BSSEL becomes "00", the bit shift by the barrel shifter 721 is not performed. The lower 3 bits of the bit string generated by this operation become effective addresses, and aO a2 a1 is generated from the address a2 a1 a0 as a real address.

In the case of the number of samples N = 8, when the bit reverse count is 1 or 2, if no bit exchange is performed, an incorrect real address is generated. Fig. 27 is a view showing the operation in the case of no bit swapping, when the bit reverse count is 1, as shown in (a), a1 a0 a3 is generated as the address, and when the bit reverse count is 2 (b As shown in Fig. 6), a0 a3 a1 is generated as a real address, and all of them malfunction.

A configuration method and a control method in the case of generally extending the variable bit reverse circuit according to the present embodiment will be described. In this description, the following variables are used.

N (i)... Corresponding samples

N (i) = 2 ⁱ

(i is a positive integer: Mmin≤i≤Mmax)

Rmax (i)... Maximum number of bit reverses in sample number N (i)

AD [0]-AD [Mmax-1]

… Variable bit reverse address

<Configuration Method>

Bit reverse circuit BR

The number of stages as long as the variable bit reverse of the sample number N (Mbr) is enabled is provided.

From here,

Mbr = Mmax (when Mmax is odd)

Mbr = Mmax + 1 (when Mmax is even)

Shall be. That is, Mbr is always odd. therefore,

Stage number of BR = Rmax (Mbr)

= Mbr-1

It becomes

Bit exchange circuit (BC)

((M-1) / 2) bit switching circuits cross two stages of the bit reverse circuit BR from the input side at bit positions of AD [m] and AD [m-1] (m is an odd number other than Mbr) from the input side Insert it.

Barrel Shifter (BS)

After the final stage of the bit reverse circuit BR, a barrel shifter BS with a maximum number of shifts (Mmax-Mmin) is provided.

Fig. 28 is a block diagram of a variable bit reverse circuit capable of responding to the number of samples N = 2 ⁱ (2 ≦ ⁱ ≦ 11) according to the present embodiment constructed by the above-described configuration method. ·

<Control Method>

Bit reverse circuit (BR)

The bit reverse circuit BR is operated by the bit reverse number of times from the input side.

Bit exchange circuit (BC)

In the case of the sample number N (m) (m is an odd number other than Mbr), when the bit reverse number is other than 0, the bit exchange circuit BC of the bit positions AD [m] and AD [m-1] is operated. Only the one on the input side of the bit reverse circuit BR is operated.

Barrel Shifter (BS)

In the case of the sample number N (n), when the number of bit reverses is odd, only the (Mmax-n) bits are right shifted.

(2nd Example)

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

Fig. 29 is a block diagram showing the construction of a fast Fourier transform apparatus according to a second embodiment of the present invention. In the fast Fourier transform apparatus according to the present embodiment, internal components and control signals of the fast Fourier transform apparatus and the RAM address generator according to the first embodiment shown in FIG. 1 are only different. Only the control unit 206 is shown. In the fast Fourier transform apparatus according to the present embodiment, in the configuration of FIG. 1, the FFT processing unit includes a RAM address generation unit 105 and a control unit 106, and a RAM address generation unit 205 and a control unit 206 shown in FIG. 29. Replaced with. The FFT processor is composed of a butterfly operator 103, a rotor generator 104, a RAM address generator 205, a controller 206, and first and second data selectors 121, 122.

The RAM address generator 205 according to the present embodiment shown in FIG. 29 is different from the RAM address generator 105 according to the first embodiment shown in FIG. 1 in that the first and second variable bit reverse units ( The address selector 215 is provided in front of the 113 and 114.

The input / output address generator 111 generates an input / output guard dress DAD by inputting the input / output timing signal DCN. On the other hand, the butterfly address generation unit 112 receives the butterfly operation timing signal BCN and the butterfly operation stage signal BST as inputs, and generates and outputs a butterfly operation guard address BAD. Their operation is the same as in the first embodiment.

The address selector 215 takes an input / output guard address DAD output from the input / output address generator 111 and a butterfly operation guard address BAD output from the butterfly address generator 112 as an input. According to the RAM selection signal RSL, one side is used as the guard of the first RAM 101, and the other side is selectively outputted as the guard of the second RAM 102.

The first variable bit reverse unit 113 is configured by the first RAM bit reverse signal RBR0 output from the control unit 206 with respect to the guard address of the first RAM 101 output from the address selector 215. The indicated number of bits are reversed and output as a real address of the first RAM 101. Meanwhile, the second variable bit reverse unit 114 outputs the second RAM bit reverse signal RBR1 output from the control unit 206 with respect to the guard address of the second RAM 102 output from the address selector 215. The number of bits reversed by the bit is reversed and output as a real address of the second RAM 102.

Therefore, also in the fast Fourier transform device according to the present embodiment, the RAM address is specified substantially in the same manner as the first embodiment.

FIG. 30 shows the bit reverse signal RBR0 for the first RAM and the bit reverse signal RBR1 for the second RAM and the first and second RAMs 101 and 102 (RAM # 0, RAM #) generated by the controller 206. FIG. Fig. 1 is a timing diagram showing the operation relationship of 1). As shown in the first embodiment, when the maximum number of bit reverses is Rmax, the second RAM bit reverse signal RBR1 is updated to traverse from 0 to Rmax, and the first RAM bit reverse signal RBR0 is updated to the second RAM bit. It is updated to circulate from 0 to Rmax one symbol period later from the reverse signal RBR1. In addition, the first and second RAMs 101 and 102 alternately repeat data input / output and butterfly operations.

With the above configuration, the same operation as in the first embodiment can be realized, and the same effects as in the first embodiment can be obtained.

(Third embodiment)

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

Fig. 31 is a block diagram showing the construction of a fast Fourier transform device showing the third embodiment of the present invention. Different from the fast Fourier transform device according to the first embodiment shown in FIG. 1, the RAM address generation unit 305 does not have a variable bit reverse unit, and the butterfly operation unit 303 is a butterfly based on a time selection method. In addition to the calculation, it also has the function of performing the butterfly calculation by the frequency selection method.

In this embodiment, the fast Fourier transform using the butterfly operation by the time selection method and the fast Fourier transform using the butterfly operation by the frequency selection method are alternately performed for each symbol. The time selection method and the frequency selection method are equivalent to the fast Fourier transform, but the order relationship between the input data and the output data is symmetrical. This embodiment uses this to alternate between the time selection method and the frequency selection method, thereby making data string replacement unnecessary.

In Fig. 31, reference numeral 303 denotes a butterfly calculation unit, which is supplied from a frequency selection operation unit 341 performing a butterfly operation by the frequency selection method, a time selection operation unit 342 and a controller 306 performing a butterfly operation by the time selection method. The selection circuit 343 selects and outputs either one of the calculation results of the frequency selection operation unit 341 and the time selection operation unit 342 according to the selected selection method switching signal TSL. 304 is a rotor generator for generating a rotor for use in a butterfly operation by a time selection method or a frequency selection method. 305 is a RAM address generation unit that generates an address for controlling the first and second RAMs 101 and 102. In Fig. 31, those having the same functions as those in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted here. The FFT processing section includes a butterfly calculating section 303, a rotor generating section 304, a RAM address generating section 305, a control section 306, and first and second data selection sections 121 and 122.

The fast Fourier transform apparatus according to the present embodiment configured as described above performs the fast Fourier transform of even-numbered symbols by using one of two RAMs 101 and 102 as in the first embodiment, and uses the other. To perform the odd fast Fourier transform.

In order to realize the overlap between the symbol input and the two preceding symbol outputs without replacing the data strings, the RAM address was updated for each symbol by variable bit reverse in the first and second embodiments. The butterfly calculation unit is controlled so as to alternate the butterfly operation by the butterfly operation and the frequency selection method for each symbol.

32 is a signal flow graph illustrating a time-selection method and a frequency-selection method of radix 2 as an example of a fast Fourier transform algorithm. In the figure, (a) shows the radix 2 time selection method, (b) shows the radix 2 frequency selection method, and are all signal flow graphs in the case of the sample number N = 8. As shown in (a) of FIG. 32, in the radix two-time selection method, when the index of the input data x (j) becomes j = 0, 4, 2, 6 from the top, the index of the output data X (j) is from the top. From j = 0, 1, 2, 3 ... On the other hand, in the frequency selection method as shown in FIG. 32 (b), j = 0, 0 from above, in accordance with the index of the input data x (j) in accordance with the output data in the time selection method shown in FIG. 32 (a). In the ascending order of 1, 2, 3, the index of the output data X (j) becomes j = 0, 4, 2, 6 ... from the top, and the time alignment shown in FIG. Matches the input data in the method. In other words, the order of the input data and the output data in the frequency selection method coincides with the order of the output data and the input data in the time selection method.

Fig. 33 is a diagram showing an example of data transfer between RAMs in the present embodiment, and shows data transfer between RAMs when the time selection method and the frequency selection method are alternately performed for each symbol. The example shown in FIG. 33 is for the case where the number of samples N = 8 is shown with respect to one of two RAMs 101 and 102. FIG.

In FIG. 33, the FFT process [i] performs the butterfly operation by the time selection method, and the FFT process [i + 2] performs the butterfly operation by the frequency selection method. As shown in FIG. 33, the output data X (J) of the butterfly operation (FFT process [i]) by the time selection method is performed by alternately performing the butterfly operation by the time selection method and the butterfly operation by the frequency selection method. The order of the input data x (j) of the butterfly operation (FFT process [i + 2]) by the frequency selection method coincides with the order of the butterfly operation (FFT process [i + 2]) by the frequency selection method. Since the order of output data X (j) of) and the order of input data x (J) of the butterfly operation (FFT process [i]) by the time alignment method are identical, the output data of each FFT process and the next FFT process The order of the input data is consistent. Therefore, the read address of the output data X (k) of each FFT process and the write address of the input data x (k) of the next FFT process become the same. As a result, since the input data x (k) of the next FFT process can be stored at the same address after reading the output data X (k) of the FFT process, the overlap between the symbol input and the previous two symbol outputs can be realized.

As described above, according to this embodiment, the butterfly operation by the time selection method and the butterfly operation by the frequency selection method are alternately performed for each symbol, so that the order of the symbols in the output data of one symbol and the input data of the next symbol is changed. The data having the common indices indicated can be stored at the same address in the RAM. That is, after reading output data of one symbol from the RAM, input data of the next symbol can be written at the same address, and an empty area of the RAM after reading the output data is used as an input buffer for storing input data of the next symbol. Since it can be used, the RAM for the input buffer becomes unnecessary. Therefore, the structure of the two RAMs is changed by appropriately changing the RAM so that the even number symbol processing among the plurality of consecutive symbols is performed using the first RAM and the odd number symbol processing is performed using the second RAM. It becomes possible.

(Fourth embodiment)

Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

34 is a diagram showing the configuration of a fast Fourier transform apparatus according to the fourth embodiment of the present invention. In Fig. 34, reference numeral 401 denotes RAM for storing input / output data and intermediate data during a butterfly operation, 402 denotes a CPU for calculating a butterfly operation and an address of the RAM 401, and 403, 404 denotes a RAM 401 and a CPU 402. Is a bus for connecting a network, 403 is an address bus, and 404 is a data bus.

In this embodiment, the storage area of the RAM 401 is divided into two storage areas 405 and 406, and a fast Fourier transform of even-numbered symbols is performed by using one of the two storage areas 405 and 406. To perform an odd-numbered fast Fourier transform using the other. The CPU 402 generates an address for storing input / output data and intermediate data at the time of butterfly operation in the two storage areas 405 and 406 of the RAM 401. The CPU 402 also performs a butterfly operation by inputting data read from the RAM 401, and outputs the result of the calculation to the RAM 401.

With the above configuration, the same operation as that of the fast Fourier transform device according to the first embodiment can be realized. In this embodiment, the RAM storage area is divided into first and second storage areas, and even-numbered and odd-numbered fast Fourier transforms of consecutive symbols are used by using the first and second memory areas, respectively. The memory capacity can be reduced.

In the first to third embodiments, two RAMs are provided for storing input / output data and intermediate data at the time of operation. However, as in the fourth embodiment, one RAM may be divided into two storage areas.

In addition, although the time selection method was used as the fast Fourier transform algorithm in the first and second embodiments, the frequency selection method may be used. In the case of using the frequency selection method, the operation by the butterfly operation unit may be changed and the group division of address bits in the bit reverse by the variable bit reverse unit may be changed.

In the first and second embodiments, although two variable bit reverse portions are provided in the RAM address generation portion, one variable bit reverse portion is provided, and the bit reverse processing of the input / output address and the butterfly operation address may be time-divided. do.

In the first to third embodiments, two RAMs are provided for storing input / output data and intermediate data during operation. However, the number of RAMs in the present invention is not limited to two, but one or three or more. It may be.

(Application to inverse fast Fourier transform)

The present invention can also be implemented in the inverse fast Fourier transform as in the fast Fourier transform shown in the respective embodiments.

The algorithm of inverse fast Fourier transform can be realized only by transforming some operations in the algorithm of fast Fourier transform. For example, the radix 4x2 time selection method as an example of an inverse fast Fourier transform algorithm is represented by a signal flow graph such as a fast Fourier transform algorithm as shown in FIG. However, part of the calculation expression of the calculation element is different from the fast Fourier transform algorithm.

FIG. 35 is a diagram illustrating arithmetic elements when the signal flow graph of FIG. 4 represents an inverse fast Fourier transform algorithm. In the inverse fast Fourier transform algorithm, as shown in Fig. 35, each operation is performed according to the following expression. In addition, it is underlined with each expression and other expression of arithmetic elements in the fast Fourier transform of FIG.

<Radix 4 butterfly operation>

X0 = x0 + x1 + x2 + x3

X1 = x0 + jx1-x2-jx3

X2 = x0-x1 + x2-x3

X3 = x0-jx1-x2 + jx3

<Radix 2 butterfly operation>

X0 = x0 + x1

X1 = xO-x1

<Rotor Odds>

Y = yW ⁱ

W = e ^{j · 2π / N}

Therefore, in the first and second embodiments, the operation of the butterfly calculating unit 103 and the rotor generating unit 104 is changed. In the third embodiment, the butterfly calculating unit 303 and the rotor generating unit 304 are changed. In the fourth embodiment, by changing the butterfly operation and the rotor multiplication by the CPU 402, the fast Fourier inverse transform according to the present invention can be performed. In this case, for example, in the first embodiment, the butterfly calculating unit 103, the rotor generating unit 104, the RAM address generating unit 105, the control unit 106, and the first and second data selecting units 121, 122) constitutes an IFFT processing unit that performs inverse fast Fourier transform processing using a butterfly operation.

(Application to OFDM receiver and transmitter)

In addition, the fast Fourier transform apparatus according to the present invention is used in, for example, an OFDM receiver. Fig. 36 is a block diagram showing the configuration of an OFDM receiver having a fast Fourier transform apparatus according to the present invention, in which the fast Fourier transform apparatus according to the present invention is used as the fast Fourier transform unit 12. . The digital demodulator 11 converts the input OFDM signal into a baseband signal by digital demodulation, and the fast Fourier transform unit 12 performs fast Fourier transform on the baseband signal output from the digital demodulator 11. . An OFDM signal is a modulated signal using a plurality of carriers orthogonal to each other, and complex data of each carrier is decoded by fast Fourier transform. That is, the output of the fast Fourier transform unit 12 corresponds to the complex data of each decoded carrier. The error correction deinterleaved demapping unit 13 decodes the received data by performing a predetermined error correction deinterleaving demapping process on the output of the fast Fourier transform unit 12. By applying the fast Fourier transform device according to the present invention as the fast Fourier transform unit 12, the storage capacity required for the fast Fourier transform unit 12 is reduced, thereby realizing low cost of the entire OFDM receiver. .

Similarly, the inverse fast Fourier transform apparatus according to the present invention is used in, for example, an OFDM transmitter. FIG. 37 is a block diagram showing the configuration of an OFDM transmitter having an inverse fast Fourier transform apparatus according to the present invention. In this OFDM transmitter, an inverse fast Fourier transform apparatus according to the present invention is an inverse fast Fourier transform unit 22. As shown in FIG. It is used as. The OFDM transmitter shown in FIG. 37 performs the reverse processing of the OFDM receiver shown in FIG. 36 to generate an OFDM signal. That is, the encoding interleaving mapping unit 21 performs predetermined error correction encoding interleaving mapping processing on the transmission data, and generates complex data of each carrier. The inverse fast Fourier transform section 22 performs inverse fast Fourier transform processing on the complex data of each carrier, and the digital modulator performs frequency conversion of the output of the inverse fast Fourier transform section 22 to generate an OFDM signal. By applying the inverse fast Fourier transform device according to the present invention as the inverse fast Fourier transform portion 22, the storage capacity required for the inverse fast Fourier transform portion 22 is reduced, thereby reducing the cost of the entire OFDM transmitter. It can be realized.

According to the present invention, RAM access is performed by changing the number of bit reverses of an address for each symbol, so that data having a common index indicating the order of symbols in the output data of one symbol and the input data of the next symbol is stored at the same address in the RAM. This makes it possible to realize the overlap between the symbol input and the symbol output without requiring data string replacement.

Further, according to the present invention, the butterfly operation by the time selection method and the butterfly operation by the frequency selection method are alternately performed for each symbol, so that the index indicating the order among symbols is common in the output data of one symbol and the input data of the next symbol. Since the in-data can be stored at the same address in the RAM, it is possible to realize the overlap between the symbol input and the symbol output without requiring data string replacement.

This eliminates the need for a conventionally required input buffer RAM and reduces the cost of the high speed Fourier converter by reducing the storage capacity. RAM occupies most of the fast Fourier converters, and the effect of lowering the price by reducing the storage capacity is large.

In addition, since the data string replacement becomes unnecessary, the fast Fourier transform device used for the modulation and demodulation with the storage capacity can be reduced, so that the processing after the fast Fourier transform can be reduced.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the present invention as set forth in the appended claims.

1 is a block diagram showing the configuration of a fast Fourier transform apparatus according to a first embodiment of the present invention.

2 is a timing diagram showing processing timing in the fast Fourier transform apparatus according to the first embodiment of the present invention.

FIG. 3 is a timing diagram showing RAM switching timing in the fast Fourier transform apparatus according to the first embodiment of the present invention. FIG.

4 is a signal flow graph showing a radix 4x2 time selection method as an example of a fast Fourier transform algorithm.

5 illustrates arithmetic elements in a signal flow;

FIG. 6 shows data transfer between RAMs in the absence of variable bit reverse of an address. FIG.

7 illustrates data transfer between RAMs when there is a variable bit reverse of an address.

8 shows an overview of beat reverse.

FIG. 9 is a diagram showing an example of bit reverse, showing bit reverse in the radix 4x2 time selection method when the number of samples N = 32. FIG.

FIG. 10 is a diagram showing an example of an address change caused by variable bit reverse, and corresponds to data transfer between RAMs shown in FIG.

FIG. 11 is a diagram showing a change in address due to variable bit reverse, and corresponding to data transfer between RAMs in the radix 4x2 time selection method when the number of samples N = 32. FIG.

FIG. 12 is a diagram showing a change in address due to variable bit reverse, and corresponding to data transfer between RAMs in the radix 4x2 time selection method when the number of samples N = 16. FIG.

Fig. 13 is a signal flow graph in the case where the number of samples N = 32 is a diagram showing the calculation procedure of the butterfly operation in the first embodiment of the present invention.

FIG. 14 is a timing diagram showing a signal for controlling the RAM address generator 105 generated and output by the controller 106 in the fast Fourier transform apparatus according to the first embodiment of the present invention shown in FIG.

FIG. 15 is a timing diagram showing a signal for controlling the RAM address generator 105 generated and output by the controller 106 in the fast Fourier transform apparatus according to the first embodiment of the present invention shown in FIG.

16 is a timing diagram showing the operation timing of the butterfly calculating unit 103 in the fast Fourier transform apparatus according to the first embodiment of the present invention shown in FIG.

FIG. 17 is a view showing an example of the configuration of the first and second variable bit reverse sections 113 and 114 in the fast Fourier transform apparatus according to the first embodiment of the present invention shown in FIG. Configuration example of the selector type, (b) is configuration example of the table type

FIG. 18 is a diagram showing an operation of generating input / output addresses by the input / output address generating unit 111 and the first variable bit reverse unit 113 in the fast Fourier transform apparatus according to the first embodiment of the present invention. Figure showing the correspondence between the timing signal DCN and the bit reverse signal DBR for input / output, the input / output guard address DAD, and the input / output shield address RDAD.

FIG. 19 is a diagram showing a butterfly operation address generation operation performed by the butterfly address generation unit 112 and the second variable bit reverse unit 114 in the fast Fourier transform apparatus according to the first embodiment of the present invention. , Butterfly operation timing signal (BCN), butterfly operation stage signal (BST) and butterfly operation bit reverse signal (BBR), butterfly operation guard (BAD) and butterfly operation address (RBAD) Figure showing the correspondence of

20 is a diagram showing the configuration of the address selector 115 in the fast Fourier transform apparatus according to the first embodiment of the present invention.

Fig. 21 is a diagram showing access timing of RAM in data input / output in the fast Fourier transform apparatus according to the first embodiment of the present invention.

Fig. 22 is a diagram showing the access timing of RAM in the butterfly operation in the fast Fourier transform device according to the first embodiment of the present invention.

FIG. 23 is a diagram showing another example of the configuration of the first and second variable bit reverse units 113 and 114, and is configured to be capable of executing variable bit reverse for the number of samples N = 4, 8, 16, and 32, respectively. Schematic diagram showing beat reverse circuit

FIG. 24 is a circuit diagram showing the configuration of each circuit constituting the variable bit reverse circuit shown in FIG. 23, (a) is a configuration of the bit reverse circuit BR, and (b) is a configuration of the bit exchange circuit BC. (C) is a figure which shows the structure of the barrel shifter BS, respectively.

FIG. 25 is a diagram showing the set values of the respective control signals of the variable bit reverse circuit shown in FIG. 23, (a) shows the number of samples N = 32, (b) shows the number of samples N = 16, and (c) shows the samples. The number N = 8 and (d) show the set values of the respective control signals in the case where the number of samples N = 4.

FIG. 26 is a view showing the operation of the variable bit reverse circuit shown in FIG. 23 when the number of samples N = 8, (a) when the bit reverse number is 1, (b) the bit reverse number is 2 days, and FIG. Drawing showing the operation when

FIG. 27 is a diagram showing the operation of the variable bit reverse circuit shown in FIG. 23 when the number of samples N = 8 when there is no bit exchange, and (a) is when the bit reverse number is 1, (b) A diagram showing the operation when the bit reverse count is 2

Fig. 28 is a block diagram of a variable bit reverse circuit capable of responding to the number of samples N = 2 ⁱ (2 ≦ N ≦ 11) according to the present embodiment.

29 is a block diagram showing the configuration of a fast Fourier transform device according to a second embodiment of the present invention.

30 shows a bit reverse signal RBR0 for a first RAM, a bit reverse signal RBR1 for a second RAM, and first and second RAMs 101 and 102 in the fast Fourier transform apparatus according to the second embodiment of the present invention. Timing diagram showing the operation relationship of (RAM # 0, RAM # 1)

Fig. 31 is a block diagram showing the construction of a fast Fourier transform device in accordance with a third embodiment of the present invention.

32 is a signal flow graph showing an example of a fast Fourier transform algorithm, (a) is a signal flow graph showing a radix 2 time selection method, and (b) a signal flow graph showing a radix 2 frequency selection method.

Fig. 33 is a diagram showing an example of data transfer between RAMs according to the third embodiment of the present invention, and shows data transfer between RAMs when the time selection method and the frequency selection method are alternately performed for each symbol.

34 is a diagram showing the configuration of a fast Fourier transform apparatus according to a fourth embodiment of the present invention.

35 illustrates arithmetic elements in a signal flow illustrating an inverse fast Fourier transform.

36 is a diagram showing the configuration of an OFDM receiver using a fast Fourier transform apparatus according to the present invention.

37 is a diagram showing the configuration of an OFDM transmitter using an inverse fast Fourier transform apparatus according to the present invention.

Explanation of symbols on the main parts of the drawings

101: first RAM 102: second RAM

103: butterfly operation unit 105: RAM address generation unit

106: control unit 111: I / O address generation unit

112: butterfly address generator 113: first variable bit reverse unit

114: second variable bit reverse unit 115: address selector

121: first data selector 122: second data selector

131: RAM address conversion unit 205: RAM address generation unit

206: control unit 215: address selection unit

231: RAM address conversion unit 303: Butterfly operation unit

305: RAM address generation unit 306: Control unit

341: frequency selection calculator 342: time selection calculator

DAD: I / O garth dress BAD: Butterfly computation garth dress

RDAD: I / O Seal Address RBAD: Butterfly Calculation Address

DBR: bit reverse signal for I / O

BBR: bit reverse signal for butterfly operation

RSL: RAM select signal RBR0: Bit reverse signal for first RAM

RBR1: bit reverse signal for the second RAM

701 to 704: bit reverse circuit 711: bit swap circuit (bit swap means)

721 barrel shifter (bit shift means)

11: digital demodulator 12: fast Fourier transform unit

22 Inverse fast Fourier transform unit 23 Digital modulation unit

Claims (38)

(Twice) A Fast Fourier Transform (FFT) Fast Fourier Transform (FFT), RAM (Random Access Memory) for storing input data for each symbol, which is a set of data for fast Fourier transform, A FFT processing unit for performing fast Fourier transform processing (FFT processing) using a butterfly operation on the input data stored in the RAM, The RAM stores data obtained as a result of FFT processing by the FFT processing unit for input data of one symbol stored in the RAM as output data of the one symbol, The FFT processing unit includes, in the output data of one symbol and the input data of another symbol stored in the RAM after the output data of one symbol, data having a common index indicating the order among symbols is the same address of the RAM. And a fast Fourier transform for performing FFT processing to be stored in the memory. The method of claim 1, The FFT processing unit includes a RAM address generation unit for generating an address for accessing the RAM, and accesses the RAM according to an address generated by the RAM address generation unit, The RAM address generation section includes input data of one symbol and input data of another symbol which is stored in the RAM next to the output data of one symbol, and the data having a common index indicating the order of the symbols is stored in the RAM. A fast Fourier transform apparatus, wherein a generated address is converted for each symbol so as to be stored at the same address. The method of claim 2, The RAM address generation unit groups the bits of the addresses based on the radix of the butterfly operation, and converts the generated addresses for each symbol by using bit reverse processing for changing the order of the bits in groups. High speed Fourier inverter. (correction) The method of claim 3, wherein The RAM address generation unit generates an address by repeatedly performing a bit reverse process a predetermined number of times with respect to a reference address, When the number of times of returning to the original address is subtracted from the number of times to return to the original address when the bit reverse processing is repeatedly performed, the maximum number of bit reverse times Rmax (Rmax is a positive integer), And the RAM address generation unit converts the generated address for each symbol by incrementing the number of repetitions of the bit reverse processing with respect to the reference address in turn, from 0 to Rmax times in order. (correction) The method of claim 4, wherein The FFT processing unit performs FFT processing using preferential butterfly operations of radix 4, The maximum bit reverse number Rmax is 1 when the number of samples, which is the number of data of 1 symbol, is 4 ^m (m is a positive integer), and m × 2 when the number of samples is 4 ^m · 2. (correction) The method of claim 4, wherein The RAM address generation section includes a variable bit reverse section for repeating bit reverse processing a specified number of times, The variable bit reverse unit has a plurality of bit reverse circuits connected in series, each of which performs one bit reverse process, and a number corresponding to a specified number of bit reverses among the plurality of bit reverse circuits performs bit reverse, High speed Fourier inverter characterized in that passing the data. (correction) The method of claim 6, The variable bit reverse unit performs bit reverse corresponding to a plurality of samples, and bit-bit shifts the data bit-reversed by the plurality of bit reverse circuits so that the positions of valid bits in input data and output data match. A fast Fourier transform device comprising a shift means. The method of claim 7, wherein And said variable bit reverse portion is provided with bit exchange means for exchanging bits in front of any one of said plurality of bit reverse circuits. (correction) The method of claim 1, The FFT processing unit includes a butterfly operation unit that performs an FFT process using a butterfly operation on the input data stored in the RAM, The butterfly operation unit may execute a plurality of types of FFT processes that are substantially equivalent while using different butterfly operations, and output the data of one symbol and the other symbols stored in the RAM after the output data of this symbol. A fast Fourier transform apparatus for changing the type of FFT processing to be executed for each symbol so that data having common indices in the order of symbols in the input data is stored at the same address in the RAM. (correction) The method of claim 9, The butterfly operation unit alternately performs FFT processing using a butterfly operation by a frequency in decimation method and a FFT process using a butterfly operation by a decimation in time method for each symbol. High speed Fourier inverter. (correction) A fast Fourier transform device for performing fast Fourier transform, First and second RAMs for storing input data for each symbol that is a set of data for fast Fourier transform; A FFT processing unit for performing fast Fourier transform processing (FFT processing) using a butterfly operation on the input data stored in the first or second RAM, The first and second RAMs respectively store data obtained as a result of FFT processing by the FFT processing unit for input data of one symbol stored in the RAM as output data of the one symbol, The fast Fourier transform device performs FFT processing of even symbols using one of the first and second RAMs, and performs FFT processing of odd symbols using the other. The FFT processing unit outputs data of the i symbol (i is a positive integer) and input data of the i + 2 th symbol, the data having a common index indicating the order of symbols in the first or second RAM. A fast Fourier transform apparatus for performing FFT processing to be stored at the same address. (correction) The method of claim 11, A fast Fourier transform device characterized by performing a butterfly operation on the i + 1th symbol in addition to inputting the data of the i + 2th symbol in the data output period of the ith symbol. (correction) The method of claim 11, The FFT processing unit, A RAM address generator for generating an address for accessing the first and second RAMs; A butterfly operation unit performing a butterfly operation based on the data stored in the first or second RAM; A first data selector configured to input input data of the fast Fourier transform device or calculation result data of the butterfly calculator, and output the selected data to the first or second RAM; A second data selector for inputting the output data of the first or second RAM as input data and outputting the output data of the fast Fourier transform apparatus or selectively outputting the output to the butterfly calculating unit; A control unit controlling the RAM address generation unit and the first and second data selection units; The RAM address generation unit includes first or second data in which the index indicating the order among symbols is common in the output data of the i (i is a positive integer) and the input data of the i + 2 th symbol. A high-speed Fourier transform device, characterized in that for converting an address generated so as to be stored at the same address in RAM for each symbol. The method of claim 13, The RAM address generator, An input / output address generation unit for generating an input / output guard dress as a reference for an address for storing a symbol input data and output data in the first or second RAM; A butterfly address generation unit for generating a butterfly operation guard dress as a reference for an address for storing intermediate data during symbol butterfly operation in the first or second RAM; Converts the input / output address generated by the input / output address generation unit into the input / output thread address and simultaneously converts the butterfly operation generation address generated by the butterfly address generation unit into the butterfly operation address; And a RAM address converting section for outputting one of an input / output seal address and a butterfly calculation address to the first RAM and the other to the second RAM. (correction) The method of claim 14, The RAM address conversion unit, A first variable bit reverse is generated for the input / output address generated by the input / output address generation unit by generating the input / output real address by performing bit reverse processing for the number of times indicated by the input / output bit reverse signal output from the control unit. Wealth, The butterfly arithmetic address is performed by performing a bit reverse process on the butterfly arithmetic garth generated by the butterfly address generator by the number of times indicated by the butterfly arithmetic bit reverse signal output from the controller. A second variable bit reverse unit to generate, One of the input and output seal addresses generated by the first variable bit reverse unit and the butterfly operation generated address generated by the second variable bit reverse unit is input, and one of the RAM selection signals output from the controller is input. And an address selector which selects and outputs an address as the address of the first RAM and selects and outputs the other as the address of the second RAM. (correction) The method of claim 15, When the bit reverse processing is repeatedly performed, the number of times of returning to the original address minus one is assumed to be the maximum bit reverse number Rmax (Rmax is a positive integer), and the data input period for one symbol is the symbol period. The control unit, And updating the input / output bit reverse signal and the butterfly operation bit reverse signal for every two symbol periods so that the repeated number of times of instructing bit reverse processing is circulated from 0 to Rmax in turn. (correction) The method of claim 16, The FFT processing unit performs FFT processing using preferential butterfly operations of radix 4, The maximum bit reverse number (Rmax) is 1 when the number of samples, which is the number of data in one symbol, is 4 ^m (m is a positive integer), and m × 2 when the number of samples is 4 ^m · 2. (correction) The method of claim 14, The RAM address conversion unit, The input / output garth generated by the input / output address generation unit and the butterfly operation garth generated by the butterfly address generation unit are input, and one side is set according to the RAM selection signal output from the control unit. An address selector that is a RAM address and selects and outputs the other as a guard address of the second RAM; The address of the first RAM is subjected to bit reverse processing by the number of times indicated by the bit reverse signal for the first RAM output from the control unit with respect to the guard address of the first RAM selectively output by the address selecting unit. A first variable bit reverse unit to generate, The address of the second RAM is subjected to bit reverse processing by the number of times indicated by the bit reverse signal for the second RAM outputted from the control unit, for the guard address of the second RAM selectively outputted by the address selecting unit. And a second variable bit reverse part to generate. (correction) The method of claim 18, When the bit reverse processing is repeated, the number of times to return to the original address minus one is set as the maximum bit reverse number Rax (Rmax is a positive integer), and the data input period for one symbol is set to one symbol period. if, The control unit updates the bit reverse signal for the first RAM and the bit reverse signal for the second RAM every two symbol periods so as to circulate the number of instructed bit reverse processes sequentially from 0 times to Rmax times. Fourier Inverter. (correction) The method of claim 19, The FFT processing unit performs FFT processing using preferential butterfly operations of radix 4, The maximum bit reverse number (Rmax) is 1 when the number of samples, which is the number of data of 1 symbol, is 4 ^m (m is a positive integer), and m × 2 when the number of samples is 4 ^m · 2. (correction) The method of claim 11, The FFT processing unit, A RAM address generator for generating an address for accessing the first and second RAMs; A butterfly operation unit performing a butterfly operation based on data stored in the first or second RAM, A first data selector for inputting the input data of the fast Fourier transform device or the calculation result data of the butterfly calculation unit as input and outputting the selected data to the first RAM or the second RAM; A second data selector for inputting the output data of the first or second RAM as output data of the fast Fourier transform device or for selectively outputting the output to the butterfly computing unit; A control unit controlling the RAM address generation unit and the first and second data selection units; The butterfly calculating unit can execute a plurality of substantially equivalent FFT processes while using different butterfly operations, and in order for the output data of the i-th symbol and the input data of the i + 2th symbol, the order of the symbols is determined. A fast Fourier transform apparatus, wherein the type of FFT processing to be executed is changed for each symbol so that data having a common index is stored at the same address of the first or second RAM. (correction) The method of claim 21, The butterfly calculation unit, A frequency selection operation unit which performs FFT processing using a butterfly operation by a frequency selection method on input data of a symbol stored in the first or second RAM; And a time selection operator for performing FFT processing using a butterfly operation by a time selection method on input data of a symbol stored in the first or second RAM. (Twice) A fast Fourier transform method that performs fast Fourier transform using RAM, A first step of storing, in RAM, data to be converted for one symbol, which is a set of data for fast Fourier transform, A second step of performing fast Fourier transform processing (FFT processing) using a butterfly operation on the conversion target data stored in the RAM in the first step, and storing the processing result data in the RAM; Repeating the third step of reading the processing result data stored in the RAM from the RAM in the second step, The second step, In the processing result data stored in the RAM in the N (N is a positive integer) iteration and the data to be converted in the RAM in the N + 1 iteration, data having a common index indicating the order in the symbols is the RAM. A fast Fourier transform method, characterized in that each time the address that accesses the RAM is repeated so as to be stored at the same address of the RAM. (correction) The method of claim 23, The second step is to group bits of addresses based on the radix of the butterfly operation, and to convert each time the address accessing the RAM is repeated, using bit reverse processing to change the order of the bits in groups. A high speed Fourier transform method. The method of claim 24, The second step is to generate by repeating the bit reverse process a predetermined number of times with respect to an address which is a reference to the address for accessing the RAM, When the number of times to return to the original address is subtracted from the number of times to return to the original address when the bit reverse processing is repeated, the maximum number of bit reverse times Rmax (Rmax is a positive integer), In the second step, the fast Fourier transform method converts the address accessing the RAM every iteration by increasing the number of iterations of the bit reverse processing with respect to the reference address sequentially from 0 to Rmax. . (correction) The method of claim 25, The second step is to perform FFT processing using preferential butterfly operation of radix 4, The maximum bit reverse number (Rmax) is 1 when the number of samples, which is the number of data of 1 symbol, is 4 ^m (m is a positive integer), and m × 2 when the number of samples is 4 ^m · 2. (Twice) A fast Fourier transform method that performs fast Fourier transform using RAM, A first step of storing, in RAM, conversion target data for one symbol, which is a set of data for fast Fourier transform, A second step of performing fast Fourier transform processing (FFT processing) using a butterfly operation on the data to be converted stored in the RAM in the first step, and storing the processing result data in the RAM; Repeating the third step of reading the processing result data stored in the RAM in the RAM in the second step, The second step, It is possible to execute a plurality of substantially equivalent FFT processes while using different butterfly operations, and process result data stored in the RAM in the N (it is a positive integer) iteration and the RAM in the N + 1 iteration. A fast Fourier transform method for storing stored conversion target data, wherein the type of FFT processing to be executed is changed at each iteration so that data having a common index indicating the order in the symbols is stored at the same address in the RAM. (correction) The method of claim 27, The second step is a fast Fourier transform method characterized by alternately performing the FFT processing using the butterfly operation by the frequency selection method and the FFT processing using the butterfly operation by the time selection method each time. (correction) A variable bit reverse circuit for performing a bit reverse process for a butterfly operation repeatedly a specified number of times, A plurality of bit reverse circuits connected in series, each of which performs one bit reverse processing; And a number corresponding to a specified number of bit reverses among the plurality of bit reverse circuits performs bit reverse, and the rest of the bit reverse circuit passes data. The method of claim 29, The variable bit reverse circuit performs bit reverse in correspondence with a plurality of samples. And bit shift means for bit shifting data bit-reversed by said plurality of bit reverse circuits so that valid bit positions in input data and output data coincide. The method of claim 30, And a bit exchange means for performing a bit exchange in front of any one of said plurality of bit reverse circuits. (correction) An inverse fast Fourier transform for inverse fast Fourier transform, RAM for storing input data for each symbol that is a set of data for inverse fast Fourier transform; An inverse fast Fourier transform process (IFFT process) using a butterfly operation on the input data stored in the RAM; The RAM stores data obtained as a result of IFFT processing by the IFFT processing unit for input data of one symbol stored in the RAM as output data of the one symbol, The IFFT processing unit performs IFFT processing so that, in the input data of one symbol output data and the other symbols stored in the RAM after the one symbol, data having a common index indicating the order of symbols is stored at the same address of the RAM. Inverse fast Fourier inverter characterized in that for performing. (correction) The method of claim 32, The IFFT processor includes a RAM address generator for generating an address for accessing the RAM, and accesses the RAM according to an address generated by the RAM address generator, The RAM address generation unit has the same data in the RAM as the data indicating the order among the symbols in the output data of one symbol and the input data of another symbol stored in the RAM after the output data of this symbol. An inverse fast Fourier transform device for converting a generated address for each symbol so as to be stored in a symbol. (correction) The method of claim 32, The IFFT processing unit includes a butterfly operation unit that performs IFFT processing using a butterfly operation on the input data stored in the RAM, The butterfly operation unit may execute a plurality of types of IFFT processes that are substantially equivalent while using different butterfly operations, and output the data of one symbol and the other symbols stored in the RAM after the output data of this symbol. An inverse fast Fourier transform apparatus for changing the type of IFFT processing to be performed for each symbol so that data having a common index indicating the order of symbols in the input data is stored at the same address in the RAM. (Twice) An inverse fast Fourier transform method that performs inverse fast Fourier transform using RAM, A first step of storing, in RAM, data to be converted for one symbol, which is a set of data for inverse fast Fourier transform, A second step of performing inverse fast Fourier transform processing using a butterfly operation on the data to be converted stored in the RAM in the first step, and storing the processing result data in the RAM; Repeating the third step of reading the processing result data stored in the RAM from the RAM in the second step, In the second step, the index indicating the order of symbols in the processing result data stored in the RAM in the N (N is a positive integer) iterations and the data to be converted in the RAM in the N + 1 iterations is repeated. An inverse fast Fourier transform method, wherein an address for accessing the RAM is converted at each iteration so that common data is stored at the same address of the RAM. (Twice) An inverse fast Fourier transform method that performs inverse fast Fourier transform using RAM, A first step of storing, in RAM, data to be converted for one symbol, which is a set of data for inverse fast Fourier transform, A second step of performing inverse fast Fourier transform processing (IFFT processing) using a butterfly operation on the data to be converted stored in the RAM in the first step, and storing the processing result data in the RAM; Repeating the third step of reading the processing result data stored in the RAM from the RAM in the second step, The second step is capable of executing a plurality of substantially equivalent IFFT processes while using different butterfly operations and repeating the processing result data stored in the RAM and the N + 1th iterations in N (N is a positive integer) iterations. In the high-speed Fourier transform, the type of IFFT processing to be executed is changed at each iteration so that the data to be converted in the target data stored in the RAM is stored at the same address in the RAM in the conversion target data stored in the RAM. Way. (correction) An OFDM receiver for demodulating received orthogonal frequency division multiplex (OFDM) signals into received data, A digital demodulation section for demodulating an OFDM signal into a baseband signal, and a fast Fourier transform section for performing fast Fourier transform on the base band signal demodulated by the digital demodulation section and decoding complex data of the carrier. To generate received data based on complex data, And the fast Fourier transform unit comprises the fast Fourier transform device according to claim 1. (correction) An OFDM transmitter for modulating transmission data into an OFDM signal, An inverse fast Fourier transform unit for performing inverse fast Fourier transform on the complex data of the carrier data generated from the transmission data, and a digital modulator for performing frequency conversion on the output of the inverse fast Fourier transform unit and generating an OFDM signal, And said inverse fast Fourier transform unit comprises an inverse fast Fourier transform device as set forth in claim 32.