JP4830526B2 - Plasma display device - Google Patents

Description

  The present invention relates to a plasma display device using a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. Then, ultraviolet light is generated by gas discharge in each discharge cell, and color display is performed by exciting and emitting phosphors of RGB colors with this ultraviolet light.

  A method for driving the panel is generally a subfield method, that is, a method in which one field period is divided into a plurality of subfields having an address period and a sustain period, and then gradation display is performed by a combination of subfields that emit light. Is. In the address period of each subfield, address discharge is selectively generated in the discharge cells to be displayed to form wall charges. In the sustain period, a sustain pulse Psu is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  FIG. 12 is a circuit diagram showing a configuration of a sustain pulse generating circuit of a scan electrode driving circuit or a sustain electrode driving circuit in a conventional plasma display device. As shown in FIG. 12, sustain pulse generation circuit 400 includes a recovery capacitor Cr, a recovery coil L, switches SW11, SW12, SW21, SW22, and diodes D1, D2.

  The switch SW11 is connected between the power supply terminal V4 and the node N11, and the switch SW12 is connected between the node N11 and the ground terminal. The voltage Vsus is applied to the power supply terminal V4. The node N11 is connected to, for example, 480 sustain electrodes, and FIG. 12 shows a panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes and the ground terminal.

  The recovery capacitor Cr is connected between the node N13 and the ground terminal. A switch SW21 and a diode D1 are connected in series between the node N13 and the node N12, and a diode D2 and a switch SW22 are connected in series between the node N12 and the node N13. The recovery coil L is connected between the node N12 and the node N11.

  FIG. 13 is a timing chart showing the operation of the scan electrode driving circuit or sustain pulse generating circuit 400 during the sustain period in the conventional plasma display device. FIG. 13 shows the voltage at the node N11 and the operations of the switches SW21, SW11, SW22, and SW12 in FIG.

  First, in the period Ta, the switch SW21 is turned on and the switch SW12 is turned off. At this time, the switches SW11 and SW22 are off. As a result, the voltage at the node N11 gradually rises due to LC resonance caused by the recovery coil L and the panel capacitance Cp. Next, in the period Tb, the switch SW21 is turned off and the switch SW11 is turned on. As a result, the voltage at the node N11 rapidly increases, and the voltage at the node N11 is fixed to Vsus in the period Tc.

  Next, in the period Td, the switch SW11 is turned off and the switch SW22 is turned on. As a result, the voltage at the node N11 gradually drops due to LC resonance caused by the recovery coil L and the panel capacitance Cp. Thereafter, in the period Te, the switch SW22 is turned off and the switch SW12 is turned on. As a result, the voltage at the node N11 drops rapidly and is fixed to the ground potential. By repeating the above operation in the sustain period, the periodic sustain pulse Psu is applied to the plurality of sustain electrodes.

As described above, the rising part and the falling part of the sustain pulse Psu are the LC resonance part of the periods Ta and Td due to the operation of the switch SW21 or the switch SW22 and the edge part of the periods Tb and Te due to the ON operation of the switch SW11 or the switch SW12. e1 and e2 (see, for example, Patent Document 1).
Japanese Patent No. 3369535

  The switches SW11, SW12, SW21, and SW22 are usually constituted by FETs (field effect transistors) that are switching elements. Each FET has a capacitance between the drain and the source as a parasitic capacitance, and is connected to each FET. This wiring has an inductance component. Therefore, when the switch SW11 or the like performs a switching operation, switching noise is generated, switching noise is applied to the plurality of sustain electrodes, and the plurality of sustain electrodes serve as antennas, and unnecessary electromagnetic waves are radiated. Since the frequency and intensity of the unnecessary electromagnetic wave depend on the design conditions such as the size of the panel to be driven and the wiring design of the drive circuit, the frequency and intensity vary depending on the model design of the plasma display device. Such high-frequency electromagnetic radiation needs to be suppressed because it may adversely affect other electronic devices. For this reason, conventionally, a capacitor is connected in parallel between the drain and source of each FET to absorb FET switching noise. And every time a new model is designed, the driver circuit has been redesigned. For this reason, it is difficult to share the drive circuit board or redesign in a short time even if the models are different.

  The plasma display device of the present invention has been made in view of these problems, can suppress the radiation of unnecessary electromagnetic waves, and can share a drive circuit board or be redesigned in a short time even if the models are different. A plasma display apparatus is provided.

  In order to solve the above problems, a plasma display apparatus of the present invention includes a sustain pulse generating circuit that outputs a sustain pulse for driving a panel, and the sustain pulse generating circuit includes a voltage clamp unit having switching means, and switching means. And a plurality of series resonant circuits formed by connecting capacitors and inductances in series, and the inductances are formed by wiring patterns of the drive circuit board, and the inductance values are different from each other. To do.

  With such a configuration, it is possible to provide a plasma display device that can suppress the radiation of unnecessary electromagnetic waves and can share the drive circuit board or can be redesigned in a short time even if the models are different.

  Further, the switching means of the sustain pulse generating circuit of the plasma display device of the present invention has a plurality of switching elements, and a series resonant circuit formed by connecting a capacitor and an inductance in series to each of the plurality of switching elements is connected in parallel. May be. With such a configuration, by connecting a plurality of switching elements in parallel to form a voltage clamp unit, even for panels that require a larger current capacity, radiation of unnecessary electromagnetic waves can be suppressed, and the models are different. However, it is possible to provide a plasma display device that can share a drive circuit board or can be redesigned in a short time.

  According to the present invention, it is possible to provide a plasma display device that can suppress unnecessary electromagnetic radiation and can share a drive circuit board or can be redesigned in a short time even if the models are different.

(Embodiment)
The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is an exploded perspective view showing a main part of a panel of a plasma display device according to an embodiment of the present invention. The panel 10 is configured such that a glass front substrate 21 and a rear substrate 31 are arranged to face each other and a discharge space is formed therebetween. On the front substrate 21, a plurality of scanning electrodes 22 and sustaining electrodes 23 constituting display electrodes are formed in parallel with each other. A dielectric layer 24 is formed so as to cover the scan electrodes 22 and the sustain electrodes 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 covered with an insulating layer 33 are provided on the back substrate 31, and a grid-like partition wall 34 is provided on the insulating layer 33. A phosphor layer 35 is provided on the surface of the insulator layer 33 and the side surfaces of the partition walls 34. The front substrate 21 and the rear substrate 31 are arranged to face each other so that the scan electrode 22 and the sustain electrode 23 and the data electrode 32 intersect each other, and in the discharge space formed therebetween, for example, neon And a mixed gas of xenon. Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of the panel of the plasma display device. N scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 23 in FIG. 1) are arranged in the row direction, and m data electrodes D1 to D1 are arranged in the column direction. Dm (data electrode 32 in FIG. 1) is arranged. A discharge cell is formed at a portion where one pair of scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn and one data electrode D1 to Dm intersect, and m × n discharge cells are formed in the discharge space. Yes.

  FIG. 3 is a circuit block diagram showing the configuration of the plasma display device. The plasma display device includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, and a power supply circuit (not shown).

  The image signal processing circuit 51 converts the image signal sig into image data for each subfield. The data electrode driving circuit 52 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 55 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V and supplies them to each circuit block. Scan electrode drive circuit 53 supplies drive voltage waveforms to scan electrodes SC1 to SCn based on timing signals, and sustain electrode drive circuit 54 supplies drive voltage waveforms to sustain electrodes SU1 to SUn based on timing signals. Here, scan electrode driving circuit 53 includes sustain pulse generating circuit 100 for generating a sustain pulse, which will be described later, and sustain electrode driving circuit 54 is similarly provided with sustain pulse generating circuit 200.

  Next, a driving voltage waveform for driving the panel and its operation will be described. In the embodiment of the present invention, one field is divided into a plurality of subfields, and each subfield has an initialization period, an address period, and a sustain period. FIG. 4 is a diagram showing a driving voltage waveform applied to each electrode of the panel of the plasma display device.

  In the initializing period of the first subfield, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 (V), and from the voltage Vi1 (V) that is lower than the discharge start voltage with respect to the scan electrodes SC1 to SCn. A ramp voltage that gradually increases toward the voltage Vi2 (V) exceeding the discharge start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are stored on scan electrodes SC1 to SCn, and positive walls on sustain electrodes SU1 to SUn and data electrodes D1 to Dm. The voltage is stored. Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode. Thereafter, sustain electrodes SU1 to SUn are maintained at positive voltage Vh (V), and a ramp voltage that gradually decreases from voltage Vi3 (V) to voltage Vi4 (V) is applied to scan electrodes SC1 to SCn. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened, and the wall voltage on data electrodes D1 to Dm is reduced. Is also adjusted to a value suitable for the write operation.

  In the subsequent address period, scan electrodes SC1 to SCn are temporarily held at Vr (V). Next, a negative scan pulse voltage Va (V) is applied to scan electrode SC1 in the first row, and data electrodes D1 to Dm of discharge cells to be displayed in the first row among data electrodes D1 to Dm are positive. An address pulse voltage Vd (V) is applied. At this time, the voltage at the intersection between the data electrodes D1 to Dm and the scan electrode SC1 is determined by the externally applied voltage (Vd−Va) (V) being the wall voltage on the data electrodes D1 to Dm and the wall voltage on the scan electrode SC1. It is added and exceeds the discharge start voltage. Then, an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1 of this discharge cell, and on sustain electrode SU1. A negative wall voltage is accumulated on the data electrodes D1 to Dm. In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm and the scan electrode SC1 to which the address pulse voltage Vd (V) is not applied does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, positive sustain pulse voltage Vs (V) is applied to scan electrodes SC1 to SCn as a first voltage, and ground potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn as a second voltage. Apply. In the i-th discharge cell in which the address discharge has occurred at this time, the voltage between the scan electrode SCi and the sustain electrode SUi is the sustain pulse voltage Vs (V), the wall voltage on the scan electrode SCi, and the sustain electrode SUi. The upper wall voltage is added and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. At this time, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained. Subsequently, 0 (V) that is the second voltage is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs (V) that is the first voltage is applied to sustain electrodes SU1 to SUn. Then, in the i-th discharge cell in which the sustain discharge has occurred, the voltage between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge is again performed between the sustain electrode SUi and the scan electrode SCi. Occurs, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, by applying sustain pulses of the number corresponding to the luminance weight alternately to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, the sustain discharge continues in the discharge cells that have caused the address discharge in the address period. Done. Thus, the maintenance operation in the maintenance period is completed.

  The operations in the initialization period, address period, and sustain period in the subsequent subfield are substantially the same as those in the first subfield, and thus description thereof is omitted.

  Next, details of sustain pulse generation circuits 100 and 200 will be described. FIG. 5 is a circuit diagram of the sustain pulse generating circuit 200 of the plasma display device. Sustain pulse generation circuit 100 has the same circuit configuration as sustain pulse generation circuit 200.

  5 is an IGBT (insulated gate bipolar transistor, hereinafter abbreviated as “transistor”) Q1 to Q4, n capacitors C11 to C1n, n capacitors having excellent conduction characteristics as switching elements. C21-C2n, n inductances L11-L1n, n inductances L21-L2n, recovery capacitor Cr, recovery coil L, and diodes D1, D2.

  The transistor Q1 has one end connected to the power supply terminal V1, the other end connected to the node N1, and the gate to which the control signal S1 is input. The transistor Q1 has a collector-emitter capacitance CP1 as a parasitic capacitance. Between the collector-emitter of the transistor Q1, a first series resonance circuit including a capacitor C11 and an inductance L11 connected in series, and a series connection are provided. N LC resonance circuits are connected in parallel up to the n-th series resonance circuit composed of the capacitor C1n and the inductance L1n connected to. A voltage Vsus is applied to the power supply terminal V1.

  The transistor Q2 has one end connected to the node N1, the other end connected to the ground terminal, and a gate to which the control signal S2 is input. The transistor Q2 has a collector-emitter capacitance CP2 as a parasitic capacitance. Between the collector-emitter of the transistor Q2, a first series resonance circuit including a capacitor C21 and an inductance L21 connected in series, and a series connection are provided. N LC resonance circuits are connected in parallel up to the n-th series resonance circuit composed of the capacitor C2n and the inductance L2n connected to.

  The node N1 is connected to, for example, 480 sustain electrodes 23. In FIG. 5, a panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes 23 and the ground terminal is shown.

  The recovery capacitor Cr is connected between the node N3 and the ground terminal. Transistor Q3 and diode D1 are connected in series between nodes N3 and N2. Diode D2 and transistor Q4 are connected in series between nodes N2 and N3. The control signal S3 is input to the gate of the transistor Q3, and the control signal S4 is input to the gate of the transistor Q4. The recovery coil L is connected between the node N2 and the node N1.

  In the present embodiment, the transistors Q1 and Q2 correspond to switching means. The capacitor C11 and the inductance L11 are connected in series to form one series resonance circuit, and the capacitor C1n and the inductance L1n are connected in series to form another series resonance circuit. These series resonance circuits are switching means. The transistor Q1 is connected in parallel. Further, the capacitor C21 and the inductance L21 are connected in series to constitute one series resonance circuit, and the capacitor C2n and the inductance L2n are connected in series to constitute another series resonance circuit. These series resonance circuits are switching means. It is connected in parallel with a certain transistor Q2. The voltage clamp unit includes a power supply terminal V1, a ground terminal, and switching means.

  Next, the operation in the sustain period of sustain pulse generating circuit 200 configured as described above will be described. FIG. 6 is a timing chart showing the operation in the sustain period of the sustain pulse generating circuit of the plasma display device, and will be described by dividing it into periods Ta to Td.

(Ta period)
First, the control signal S2 goes low and the transistor Q2 turns off, and the control signal S3 goes high and the transistor Q3 turns on. At this time, the control signal S1 is at a low level and the transistor Q1 is turned off, and the control signal S4 is at a low level and the transistor Q4 is turned off. Therefore, the recovery capacitor Cr is connected to the recovery coil L via the transistor Q3 and the diode D1, and the voltage at the node N1 rises due to LC resonance caused by the recovery coil L and the panel capacitance Cp. At this time, the charge of the recovery capacitor Cr is discharged to the panel capacitor Cp through the transistor Q3, the diode D1, and the recovery coil L.

(Tb period)
Next, the control signal S1 goes high and the transistor Q1 turns on, and the control signal S3 goes low and the transistor Q3 turns off. Therefore, the node N1 is connected to the power supply terminal V1, the voltage of the node N1 rises rapidly, switching noise is generated, and then fixed to the voltage Vsus.

  At this time, the transistor Q1 is on, but the transistor Q2 is off. Until the transistor Q1 is turned on and is in a steady state, the switching noise is absorbed in n self-resonant frequency bands by the LC resonance circuit composed of the series connection of C11 and L11 to C1n and L1n connected in parallel to the transistor Q1. Is done. In addition, switching noise is absorbed in n self-resonant frequency bands by the LC resonance circuit composed of series connection of C21 and L21 to C2n and L2n connected in parallel to the transistor Q2 which is turned off.

(Tc period)
Next, the control signal S1 goes low and the transistor Q1 turns off, and the control signal S4 goes high and the transistor Q4 turns on. Therefore, the recovery capacitor Cr is connected to the recovery coil L via the diode D2 and the transistor Q4, and the voltage at the node N1 drops due to LC resonance caused by the recovery coil L and the panel capacitance Cp. At this time, the charge stored in the panel capacitor Cp is stored in the recovery capacitor Cr via the recovery coil L, the diode D2, and the transistor Q4, and the charge is recovered.

(Td period)
Next, the control signal S2 goes high and the transistor Q2 turns on, and the control signal S4 goes low and the transistor Q4 turns off. Therefore, the node N1 is connected to the ground terminal, the voltage of the node N1 drops rapidly, switching noise is generated, and then fixed to the ground potential.

  At this time, the transistor Q2 is on, but the transistor Q1 is off. Until the transistor Q2 is turned on and is in a steady state, the switching noise is absorbed in n self-resonant frequency bands by the LC resonance circuit composed of the series connection of C21 and L21 to C2n and L2n connected in parallel to the transistor Q2. Is done. In addition, switching noise is absorbed in n self-resonant frequency bands by an LC resonance circuit formed of a series connection of C11 and L11 to C1n and L1n connected in parallel to the transistor Q1 that is turned off.

  In this embodiment, the capacitors C11 to C1n and C21 to C2n use multilayer ceramic chip capacitors, and the inductances L11 to L1n and L21 to L2n are formed by the inductance component of the wiring pattern of the drive circuit board.

  FIG. 7 is a diagram showing an example of the wiring pattern of the driving circuit board around the transistor Q2 of the sustain pulse generating circuit 200 of the plasma display device. FIG. 8 is a circuit diagram corresponding to the wiring pattern of FIG. The transistor Q2 includes three transistors Q21, Q22, and Q23 in order to secure a current capacity for driving the panel capacity Cp. That is, the three transistors Q21, Q22, and Q23 correspond to a plurality of switching elements, and the capacitor C21 and the inductance L21 are connected in series to form a first series resonance circuit, and the capacitor C22 and the inductance L22 are in series. Are connected to each other to form a second series resonance circuit, and a capacitor C23 and an inductance L23 are connected in series to form a third series resonance circuit. Each series resonance circuit is connected to each switching element in parallel. ing. The collectors of the transistors Q21, Q22, and Q23 are each connected to the node N1, and the emitters are grounded. A control signal S2 is input to the gates of the transistors Q21, Q22, and Q23 via resistors.

  Similarly, the transistor Q1 of the sustain pulse generating circuit 200 shown in FIG. 5 includes three transistors Q11, Q12, and Q13 in order to secure a current capacity for driving the panel capacitor Cp. That is, the three transistors Q11, Q12, and Q13 correspond to a plurality of switching elements, and the capacitor C11 and the inductance L11 are connected in series to form a first series resonance circuit, and the capacitor C12 and the inductance L12 are in series. Are connected to each other to form a second series resonance circuit, and a capacitor C13 and an inductance L13 are connected in series to form a third series resonance circuit. Each series resonance circuit is connected in parallel to each switching element. ing. The collectors of the transistors Q11, Q12, and Q13 are each connected to the power supply terminal V1, and the emitters are connected to the node N1. A control signal S1 is input to the gates of the transistors Q11, Q12, and Q13 via resistors.

  In the wiring pattern of FIG. 7, transistors Q21, Q22, and Q23 indicate positions where the transistor Q2 is disposed. C indicates a collector, G indicates a gate, and E indicates an emitter terminal position. In the wiring pattern on the front surface of the drive circuit board, the collectors C of the transistors Q21, Q22, and Q23 are not connected to each other, but are connected to the node N1 on the back surface (or lower substrate surface) of the drive circuit board ( Not shown).

  The wiring pattern that forms the inductance L21 is a wiring pattern from one end of the capacitor C21 to the collector C. Similarly, the inductances L22 and L23 are formed by a wiring pattern from one end of the capacitors C22 and C23 to the collector C of each transistor.

  In FIG. 7, the wiring pattern forming the inductance L21 is a wiring pattern from one end of the capacitor C21 to the collector C of the transistor Q21, and is designed to be thick and long. In addition, the wiring patterns of the inductances L22 and L23 are also designed to be different, and the inductances L21, L22 and L23 are designed to have different inductance values. In this manner, by designing the inductance values to be different from each other, different series resonance frequencies can be set even if the same multilayer ceramic chip capacitor is used.

  In FIG. 7, the inductance value is changed by changing the thickness and length of the wiring pattern. However, it is also possible to change the inductance value by inserting a slit in the wiring. In FIG. 7, the inductance value is designed using one layer of wiring on the drive circuit board. However, the inductance value can be designed using a plurality of layers.

  Next, a procedure for suppressing unnecessary radiation using the wiring pattern and the capacitor configured as described above will be described. FIG. 9 is a flowchart showing a procedure for designing a series resonant circuit of the sustain pulse generating circuit 200 of the plasma display device. Usually, there are some frequencies where particularly strong radiation is generated in unnecessary radiation, and therefore, the series resonance frequency is designed in order of the frequency of strong radiation with respect to those frequencies. This procedure will be described assuming that there are n series resonant circuits.

  First, in step 1, k is defined as a number representing the number of times the flowchart is looped. Since there are n series resonant circuits, k is an integer up to n. As its initial value, k = 0 is set (S1).

  Next, k is incremented by 1 with k + 1 (S2).

  In step 3, unnecessary radiation is measured, the strongest radiation is selected at this time, and its frequency is determined as the k-th resonance frequency (S3).

  Next, a capacitor value C to be used is calculated from the k-th resonance frequency fk and the inductance value L of (n−k + 1) wiring patterns not used at this time. At this time, the calculated value of C can be obtained using the relational expression (2 × 3.14 × fk = 1 / √ (C × L)) of the series resonance circuit (S4).

  Next, a capacitor candidate to be used is determined from the capacitor value C calculated in step 4, and is sequentially mounted on the drive circuit board, and the resonance circuit which is the kth combination of the capacitor and the wiring pattern that can absorb the most unwanted radiation. A constant is determined (S5).

  In step 6, the kth capacitor is mounted on the wiring pattern combined in step 5, and unnecessary radiation is measured (S6).

  Then, when the unnecessary radiation is below the target value, the design is completed. Otherwise, it is determined whether k is equal to n.

  As a result, if they are not equal, the process returns to step 2, and k is incremented by one and the same procedure is repeated. When k is equal to n, it is difficult to sufficiently suppress with n resonance circuits. Therefore, the number of resonance circuits is increased or redesign is performed to change the inductance value L according to each wiring pattern. . And it returns to the beginning and reexamines (S7).

  In this way, it is possible to provide a plasma display device that can suppress unnecessary electromagnetic radiation and can share a drive circuit board or can be redesigned in a short period of time even if the models are different.

  FIG. 10 is a diagram showing an improvement example of the frequency characteristics of unnecessary radiation of the plasma display device. In the example shown here, there is unnecessary radiation having a peak around f1 of 35 MHz, f2 around 45 MHz, and f3 around 200 to 300 MHz, and the LC resonance frequency band of the frequency reduction means in order to effectively absorb these unnecessary radiation. Is designed to correspond to each.

  In FIG. 10, the frequency characteristic of the frequency reducing means that absorbs unnecessary radiation is indicated by relative gain, the frequency characteristic before improvement of unnecessary radiation is indicated by a dotted line, and the frequency characteristic after improvement is indicated by a solid line.

  Next, a specific example of the LC resonance circuit in the frequency band of f1, f2, and f3 is shown. Here, multilayer ceramic chip capacitors are used as the capacitors C21, C22, and C23. FIG. 11A shows an internal equivalent circuit of one monolithic ceramic chip capacitor C21. As shown in FIG. 11A, the internal equivalent circuit of the multilayer ceramic chip capacitor is an LCR series circuit.

  FIG. 11B is an equivalent circuit of an LC resonance circuit connected in parallel to the transistor Q21. As shown in FIG. 11B, the inductance L21 of the wiring pattern is connected in series to the LCR series circuit of the multilayer ceramic chip capacitor.

  The thickness of the copper foil of the wiring pattern of the driving circuit board used in this embodiment is 12.7 microns (0.5 mil), and the thickness of the interlayer insulating layer of the driving circuit board is 0.508 mm (20 mil).

  The resonance frequency f1 is 35 MHz, the capacitance value C1 of the capacitor C21 is 5600 pF, the internal resistance r1 is 15 milliohms, and the internal inductance L1 is 1 nH. An inductance L21 due to the wiring pattern is 2.7 nH, and the wiring pattern has a width W1 of 1.7 mm and a length L1 of 15.3 mm.

  The resonance frequency f2 is 45 MHz, the capacitance value C2 of the capacitor C22 is 3300 pF, the internal resistance r2 is 15 milliohms, and the internal inductance L2 is 1 nH. The inductance L22 due to the wiring pattern is 2.8 nH, and the wiring pattern has a width W2 of 1.3 mm and a length L2 of 13.2 mm.

  The resonance frequency f3 is 300 MHz, the capacitance value C3 of the capacitor C23 is 68 pF, the internal resistance r3 is 15 milliohms, and the internal inductance L3 is 1 nH. The inductance L23 due to the wiring pattern is 2.4 nH, and the wiring pattern has a width W3 of 1.0 mm and a length L3 of 10.3 mm.

  Thus, unnecessary radiation can be suppressed by combining the wiring pattern and the capacitor so that the resonant frequency band of the LC corresponds to a frequency band having a high radiation level of unnecessary radiation.

  In the example shown here, a circuit diagram in which all the transistors Q21, Q22, and Q23 are connected is shown, but one may be provided depending on the driving capability of the transistors. Even when there is one transistor, n LC resonance circuits are connected.

  When capacitors having the same capacitance value are used in two LC resonance circuits, anti-resonance may occur between the two resonance frequencies even if their inductances are different, which may worsen unnecessary radiation. is there. For this reason, it is desirable to use capacitors having different capacitance values in different LC resonance circuits so that anti-resonance does not occur.

  When the characteristics of the panel are changed, or when the frequency band of unwanted radiation to be absorbed fluctuates due to changes in the specifications of the set or wiring of the drive circuit board, the drive circuit board has been redesigned each time. According to the combination of the inductances L21 to L23 and the capacitor according to the wiring pattern of the drive circuit board according to the invention, it is possible to immediately adapt to the fluctuating unnecessary radiation frequency band.

  The plasma display device using the driving circuit in which the LC resonance circuit in which the capacitor and the inductance are connected in series to the switching element according to the present invention is connected in parallel to the switching element effectively absorbs the frequency band in which the radiation level of the switching noise generated in the driving circuit is high. This makes it possible to suppress unnecessary electromagnetic waves from the panel electrode, and is useful for a display device using a drive circuit that drives various capacitive loads.

The disassembled perspective view which shows the principal part of the panel of the plasma display apparatus in embodiment of this invention. Electrode arrangement of the plasma display panel Circuit block diagram showing the configuration of the plasma display device The figure which shows the drive voltage waveform applied to each electrode of the panel of the plasma display apparatus Circuit diagram of sustain pulse generation circuit of the plasma display device Timing diagram showing the operation of the sustain pulse generating circuit of the plasma display device during the sustain period The figure which shows an example of the wiring pattern of the drive circuit board around the transistor of the sustain pulse generation circuit of the plasma display device Circuit diagram corresponding to the wiring pattern of FIG. A flowchart showing a procedure for designing a series resonance circuit of a sustain pulse generation circuit of the plasma display device The figure which shows the improvement example of the frequency characteristic of the unnecessary radiation of the same plasma display device (A) is a diagram showing an internal equivalent circuit of a multilayer ceramic capacitor, (b) is an equivalent circuit diagram of an LC resonance circuit connected in parallel to a transistor The circuit diagram which shows the structure of the sustain pulse generation circuit of the scan electrode drive circuit or the sustain electrode drive circuit in the conventional plasma display apparatus Timing diagram showing operation of sustain period of scan electrode driving circuit or sustain pulse generating circuit in conventional plasma display device

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Dielectric layer 25 Protection layer 31 Back substrate 32 Data electrode 33 Insulator layer 34 Partition 35 Phosphor layer 51 Image signal processing circuit 52 Data electrode drive circuit 53 Scan electrode drive circuit 54 Sustain electrode drive circuit 55 Timing generation circuit 100, 200 Sustain pulse generation circuit C11-C1n, C21-C2n Capacitor Cp Panel capacitance Cp1, Cp2 Parasitic capacitance Cr Recovery capacitor D1, D2 Diode L Recovery coil L1-L3 Internal inductance L11-L1n, L21 to L2n Inductance Q1 to Q4 Transistor (switching element)
S1-S4 control signal

Claims (2)

A sustain pulse generating circuit for outputting a sustain pulse for driving the plasma display panel;
The sustain pulse generating circuit includes a voltage clamping unit having switching means, and a plurality of series resonance circuits connected in parallel to the switching means and having a capacitor and an inductance connected in series, and the inductance is a drive circuit A plasma display device characterized by being formed with a wiring pattern of a substrate and having different inductance values. The switching means of the sustain pulse generating circuit has a plurality of switching elements, and a series resonant circuit formed by connecting a capacitor and an inductance in series to each of the plurality of switching elements is connected in parallel. Item 2. The plasma display device according to Item 1.

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