JP4825357B2 - Simulation method, program for causing computer to execute the method, and recording medium recording the program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for simulating instruction operation of a microprocessor having a VLIW (Very Long Instruction Word) type architecture, and a program for causing a computer to execute the method.
[0002]
A microprocessor having a VLIW type architecture (hereinafter referred to as a VLIW processor) includes a plurality of instructions included in one VLIW instruction (hereinafter referred to as a VLIW instruction in order to distinguish individual instructions included in a VLIW instruction from a VLIW instruction). Execute) in parallel. That is, for example, as shown in FIG. 10, when the VLIW instruction 1 is composed of four basic instructions 11, 12, 13, and 14, the four basic instructions 11 and 12 in the same VLIW instruction 1 are used. , 13, 14 are processed simultaneously by the VLIW processor.
[0003]
In the same VLIW instruction, there are a basic instruction for writing data to the same resource (for convenience, the basic instruction I1) and a basic instruction for reading data from the same resource (for convenience, the basic instruction I2). May be included. In this case, the data read by the basic instruction I2 is data before being written by the basic instruction I1. Therefore, when simulating the instruction operation of the VLIW processor, care must be taken in handling such data. Care should also be taken when an exception occurs while simulating the instruction operation of the VLIW processor.
[0004]
[Prior art]
Conventionally, when a normal processor instruction operation is simulated using a computer such as a workstation, the instructions are sequentially operated one by one. Here, a normal processor is a microprocessor that does not employ a VLIW architecture. FIG. 11 is a flowchart of a program that causes a computer to execute a method for simulating an instruction operation of a normal processor. FIG. 12 is a schematic diagram illustrating a structure of data developed in the computer when the simulation is executed.
[0005]
When simulating a normal processor instruction operation, as shown in FIG. 11, the instruction is read (step S111), decoded (step S112), and the instruction type is determined (step S113). The corresponding instruction operation is performed (steps S114-1 to S114-4), the presence or absence of an exception is determined (steps S115-1 to S115-4), and if no exception occurs (steps S115-1 to S115-4: In No), the result is written (steps S116-1 to S116-4), and the process proceeds to the operation of the next instruction to perform the same processing.
[0006]
On the other hand, if an exception has occurred (steps S115-1 to S115-4: Yes), an exception operation is performed (steps S117-1 to S117-4), and the operation proceeds to the next instruction operation. In this way, a series of operations such as an instruction read operation, an operation operation, and an operation result write operation are sequentially performed for each instruction. The same applies to a processor configured to perform parallel processing by hardware, such as a superscalar processor.
[0007]
At this time, in the computer executing the simulation program, areas of the register value storage table 21 and the memory value storage table 22 are secured as shown in FIG. That is, the register value and the memory value necessary for the calculation are read from the register value storage table 21 or the memory value storage table 22, respectively. Then, the register value and the memory value obtained as a result of the calculation are written in the register value storage table 21 or the memory value storage table 22 in the result writing step, respectively. An area of the program counter value storage table 23 that holds the value of the program counter (PC) is also secured.
[0008]
[Problems to be solved by the invention]
Although the above-described simulation method is a method for a normal processor, since a simulation method for a VLIW processor has not been established at this stage, it is necessary to perform a simulation of the VLIW processor using a simulation method for a normal processor. is there. However, in that case, there are the following three problems.
[0009]
The first problem is the operation when there are a basic instruction for reading data and a basic instruction for writing data in the same resource in the same VLIW instruction. In such a case, in the actual processing by the VLIW processor, the data read by the data read command is the data before being written by the data write command. In contrast, in the method of sequentially executing basic instructions in the same VLIW instruction, the data may already be rewritten by a write instruction in the same VLIW instruction before the data is read.
[0010]
The second problem is the operation when an exception occurs in a basic instruction during execution of the VLIW instruction. In actual processing by the VLIW processor, writing of the execution result of a basic instruction in which no exception has occurred in the VLIW instruction may be prohibited. On the other hand, in the sequential execution method of the basic instruction, even if an exception is detected during execution of a certain basic instruction, the execution of another basic instruction in the same VLIW instruction has already ended, and as a result May have been written.
[0011]
The third problem is when writing the execution results of two or more basic instructions in the same resource. In such a case, in the processing by the actual VLIW processor, writing of execution results is suppressed, or when writing execution results of multiple instructions to the same resource is permitted, multiple data are stored. Merge to create a single write. On the other hand, in the sequential execution method of the basic instruction, the operation result of the previously executed instruction is overwritten by the operation result of the instruction executed later, so that only the subsequent result remains.
[0012]
Therefore, in order to simulate a VLIW processor using a normal processor simulation method, that is, a method of sequentially executing instructions one by one, it is necessary to solve the above-described problems.
[0013]
The present invention has been made in view of the above problems, and is a simulation method capable of simulating a VLIW processor using a simulation method that sequentially executes instructions one by one, and the method is a computer. An object of the present invention is to provide a program to be executed and a recording medium on which the program is recorded.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the present invention reads VLIW instructions one by one as shown in FIG. 1 and performs arithmetic operations on all basic instructions included in the VLIW instruction to be executed. Is temporarily stored in a temporary storage location 32 that is different from the resource data storage location 31 that is the original storage location, and after the calculation results of all the basic instructions are stored in the temporary storage location 32, the temporary storage location 32 is stored. A series of operations of reading all calculation results from and writing them to the resource data storage location 31 is performed for each VLIW instruction.
[0015]
If an exception occurs during the operation of a basic instruction in a VLIW instruction, the operation results of all the basic instructions in the VLIW instruction are discarded from the temporary storage location 32 and written to the resource data storage location 31. The configuration may be prohibited.
[0016]
If it is necessary to merge the operation results of two or more basic instructions included in the same VLIW instruction and store them in the resource data storage location 31, they are stored separately in the temporary storage location 32 as shown in FIG. The corresponding calculation results may be read out and merged before being written into the resource data storage location 31.
[0017]
According to the present invention, the operation results of all basic instructions included in the VLIW instruction to be executed are stored in the temporary storage location 32, and after storing all the operation results, the operation results are stored in the temporary storage location 32. Since the data read command is written in the resource data storage location 31, even if there are a basic command for reading data and a basic command for writing data to the same resource in the same VLIW command, The data before being written in is read out. In addition, the operation results of two or more basic instructions in the same VLIW instruction are merged and written to the same resource. Furthermore, when an exception occurs during the operation of a certain basic instruction, it is prevented that the operation result of another basic instruction in the VLIW instruction including that basic instruction is written.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a simulation method according to an embodiment of the present invention, a program for causing the computer to execute the method, and a recording medium on which the program is recorded will be described in detail with reference to the drawings.
[0019]
(Embodiment 1)
FIG. 3 is a flowchart of a program that causes a computer to execute the simulation method according to the first embodiment of the present invention. FIG. 4 is a schematic diagram showing the main part of the data structure developed in the computer when the simulation is executed.
[0020]
When simulation of a VLIW processor is started using a computer such as a workstation, first, all basic instructions included in one VLIW instruction to be simulated, that is, all basic instructions that are simultaneously processed in parallel, are stored in memory values. Read from the table 42 or the like (step S31). The read instruction information is stored in the execution instruction information storage table 44. When all the basic instructions included in one VLIW instruction are read (step S32: Yes), information on all the basic instructions included in one VLIW instruction to be simulated is stored in the execution instruction information storage table 44. It will be.
[0021]
Subsequently, information on one basic instruction is read from the execution instruction information storage table 44, and the basic instruction is decoded (step S33). Then, the instruction type is determined (step S34), and instruction operations such as arithmetic processing, read processing, write processing, or branch processing are performed corresponding to the determination result (steps S35-1 to S35-4). At this time, the resource value used for execution of the instruction is read from the register value storage table 41 in the case of a value held in the register, and from the memory value storage table 42 in the case of a value stored in the memory. The register value storage table 41 and the memory value storage table 42 correspond to the resource data storage location 31 shown in FIG.
[0022]
During the execution of the instruction, the value of the program counter is held by the program counter value storage table 43. When the instruction being executed is a branch instruction, the branch destination address is stored in the write program counter value table 47. When branching to a specified address as a result of execution of the branch instruction, the value stored in the write program counter value table 47 is held in the program counter value storage table 43.
[0023]
When saving the result after execution of the basic instruction, the result is not written directly to the register value saving table 41 or the memory value saving table 42, but in the case of a value to be written to the register, it is written to the writing register data table 45 or to the memory. If it is a value, it is once written (registered) in the write memory data table 46 (steps S36-1 to S36-4). The write register data table 45 and the write memory data table 46 correspond to the temporary storage location 32 shown in FIG. In this way, a series of operations of reading the basic instruction information from the execution instruction information storage table 44, decoding and executing the instruction, and temporarily writing the result into the write register data table 45 or the write memory data table 46 is performed in the same VLIW. This is done for all basic instructions contained in the instruction.
[0024]
When the execution results for all the basic instructions are written into the write register data table 45 or the write memory data table 46 (step S37: Yes), the result writing process is performed (step S38). In the result writing process, the data held in the write register data table 45 is written into the register value storage table 41, and the data held in the write memory data table 46 is written into the memory value storage table. The above operation is performed for all VLIW instructions.
[0025]
FIG. 5 is a flowchart illustrating an example of the result writing process. When the result writing process is started, it is first determined whether or not there is an instruction that has not been written (step S51), and if not (step S51: none), the result writing process is terminated. If there is an unprocessed instruction to be written (step S51: present), an unprocessed instruction is extracted from the execution instruction information storage table 44 (step S52), and written (registered) data indicating the storage location of the execution result of the instruction. Is taken out (step S53).
[0026]
If there is data to be written to the register value storage table 41 or the memory value storage table 42 (step S54: present), the write register data table 45 or the write memory data table 46 is based on the pointer 48 to the write data. The data is extracted from the data, and is written in the corresponding one of the register value storage table 41 and the memory value storage table 42 (step S55). Then, the process returns to step S52. If there is no data to be written in the register value storage table 41 or the memory value storage table 42 in step S54 (step S54: None), the process returns to step S51, and the subsequent processing is repeated until the result writing processing is completed.
[0027]
Here, an example in which merging is performed in the result writing process will be described. For example, the instruction mnemonic is represented by “Seti # 0x1000, Rd”, and the instruction operation is an instruction “write 0x1000 to the upper bits of the register number represented by Rd” and the instruction mnemonic is “Setlo # 8888, Rd”. When the instruction “write 8888 to the lower bits of the register number represented by Rd” is included in the same VLIW instruction, the instruction operation is merged. In this case, “0x1000” and “8888” temporarily stored in the write register data table 45 are read, and a value “0x10008888” obtained by merging them is written to Rd of the register value storage table 41.
[0028]
The simulation method described above can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, floppy disk, CD-ROM, MO, or DVD, and is executed by being read from the recording medium by the computer. The program can be distributed via the recording medium and a network such as the Internet.
[0029]
Next, a hardware configuration of a computer that executes the above-described simulation method will be described. FIG. 6 is a block diagram showing the hardware configuration. The computer includes, for example, a CPU 101, a ROM 102, a RAM 103, an HDD (hard disk drive) 104, an FDD (floppy disk drive) 106, a display 108, a communication interface (I / F) 109, a keyboard 111, and a mouse. Etc. (including various pointing devices) 112, a scanner 113, a printer 114, and a CD-ROM drive (including a DVD drive) 116 are connected to each other via a bus 100.
[0030]
The CPU 101 controls the entire apparatus and executes a VLIW instruction instead of the VLIW processor. The ROM 102 stores a boot program and the like. The RAM 103 is used as a work area for the CPU 101. In the RAM 103, the above-described register value storage table 41, memory value storage table 42, program counter value storage table 43, execution instruction information storage table 44, write register data table 45, write memory data table 46, and write program counter value table 47 Is expanded.
[0031]
The HDD (hard disk drive) 104 controls writing and reading of data to and from the HD (hard disk) 105 according to the control of the CPU 101. An FDD (floppy disk drive) 106 controls writing and reading of data with respect to an FD (floppy disk) 107 which is a detachable recording medium according to the control of the CPU 101.
[0032]
The display 108 displays a window (browser) regarding data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. A communication interface (I / F) 109 is connected to the network 150 via a wired or wireless communication line 110 and serves as an interface between the network 150 and the inside. The keyboard 111 includes a plurality of keys for inputting characters, numerical values, various instructions, and the like. The mouse 112 or the like is used to move a cursor, select a range, move a window, change its size, select an icon, move, and the like.
[0033]
The scanner 113 is a device for optically reading an image. The printer 114 prints the contents displayed in the window. The CD-ROM drive 116 controls reading of data from a CD-ROM (including DVD) 115 which is a detachable recording medium.
[0034]
According to the first embodiment described above, the operation results of all the basic instructions included in the VLIW instruction to be executed are stored in the write register data table 45 or the write memory data table 46 which is the temporary storage location 32, and all the After storing the operation results, the operation results are read from the write register data table 45 or the write memory data table 46 and stored in the register value storage table 41 or the memory value storage table 42 which is the original resource data storage location 31. Since data is written, even if there are a basic command for reading data from the same resource and a basic command for writing data in the same VLIW command, the data read command can read data before being written by the data write command. .
[0035]
In addition, the operation results of two or more basic instructions in the same VLIW instruction can be merged and written to the same resource. Therefore, the simulation of the VLIW processor can be correctly performed using a simulation method that sequentially executes instructions one by one.
[0036]
(Embodiment 2)
The simulation method according to the second embodiment is such that exception processing is performed when an exception occurs in the method of the first embodiment. FIG. 7 is a flowchart of a program that causes a computer to execute the simulation method according to the second embodiment of the present invention, and FIG. 8 is a schematic diagram showing the main part of the structure of data developed in the computer when the simulation is executed. is there.
[0037]
In the simulation method according to the second embodiment, the processing (steps S71 to S77) until the execution results are temporarily stored in the write register data table 45 or the write memory data table 46 for all the basic instructions in one VLIW instruction is executed. This is the same as steps S31 to S37 described in relation to FIG. 3 of the first embodiment. Therefore, in the description of steps S71 to S77, it is assumed that S31 to S37 are replaced with S71 to S77 in the description in the first embodiment, and redundant description is omitted.
[0038]
However, if an exception occurs during execution of a certain basic instruction in steps S75-1 to S75-4 in which the instruction operation is performed for each basic instruction, the write register data table 45 or the write memory data table is related to the basic instruction. “1” is written to the exception occurrence flag 49 without writing data to 46. The area of the exception occurrence flag 49 is secured in the RAM 103 together with areas of various tables indicated by reference numerals 41 to 47. As for the basic instruction for which no exception has occurred during execution, the execution result is temporarily written in the write register data table 45 or the write memory data table 46 as in the first embodiment (steps S76-1 to S76-4).
[0039]
When the execution results for all the basic instructions are written into the write register data table 45 or the write memory data table 46 (step S77: Yes), the exception occurrence flag 49 is checked (step S78). As a result of checking, if the value of the exception occurrence flag 49 is “0” (step S78: No), it means that no exception has occurred, so the result writing process is performed as in the first embodiment (step In step S79, the process proceeds to the next VLIW instruction simulation. The contents of the result writing process are as described with reference to FIG.
[0040]
As a result of checking the exception occurrence flag 49, if the value of the exception occurrence flag 49 is “1” (step S78: Yes), it means that an exception has occurred in any of the basic instructions in the VLIW instruction. Therefore, in this case, exception processing is performed without performing the result writing process in step S79 (step S80), and the process proceeds to the next VLIW instruction simulation.
[0041]
FIG. 9 is a flowchart illustrating an example of exception processing. When exception processing is started, the type of exception that has occurred is first examined (step S91). Then, the checked result is written as exception information in the register value storage table 41 (steps S92-1 to S92-4). Subsequently, the type of the exception that has occurred is checked (step S93). If the exception that has occurred is an exact exception (step S94: an exception that does not execute an instruction other than the exception generation instruction in the VLIW instruction) In this case, the data held in the write register data table 45 and the write memory data table 46, which are temporary storage locations 32 of the execution results, are discarded (step S95).
[0042]
That is, the VLIW instruction in which an exception has occurred is not executed. On the other hand, as a result of examining the type of the exception that occurred in step S93, if the exception that has occurred is an inexact exception (step S94: an exception of a type that completes execution of an instruction other than the exception occurrence instruction in the VLIW instruction) ), A result writing process is performed for the execution result of the basic instruction in which no exception has occurred (step S96). The contents of the result writing process are as described with reference to FIG.
[0043]
Here, an exact exception is an exception that guarantees that all instructions are completed for the instruction before the instruction in which the exception occurred, and that all instructions after the instruction in which the exception occurred are not executed. That is. In the case of the VLIW instruction, the VLIW instruction including the instruction in which the exception has occurred is not executed. On the other hand, an inexact exception is an exception that can be executed before an exception is detected even in an instruction after the instruction in which the exception occurred.
[0044]
For example, if an exception occurs in an instruction that takes a long time to detect an exception, and the execution time of the subsequent instruction is shorter than that, the execution of the subsequent instruction is terminated before the exception is detected. The execution result may have been written, and in such a case, an inexact exception occurs. However, even if an exception is inaccurate, if the execution time of an instruction in which no exception has occurred is too long, the execution result may not be written.
[0045]
Note that the simulation method of the second embodiment can be realized by executing a program prepared in advance by a computer, and the program is recorded on a computer-readable recording medium and read from the recording medium by the computer. This is the same as in the first embodiment in that the program is executed and the program can be distributed via the network.
[0046]
According to the second embodiment described above, as in the first embodiment, even when there are a basic instruction for reading data and a basic instruction for writing data to the same resource in the same VLIW instruction, In addition to being able to read data prior to being written by a data write instruction, merging the results of two or more basic instructions in the same VLIW instruction, and writing them to the same resource, it also handles correctly when an exception occurs can do. Therefore, the simulation of the VLIW processor can be correctly performed using a simulation method that sequentially executes instructions one by one.
[0047]
In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible.
[0048]
【The invention's effect】
According to the present invention, the operation results of all basic instructions included in the VLIW instruction to be executed are stored in the temporary storage location, and after storing all the operation results, the operation results are read from the temporary storage location. Since it is issued and written in the original storage location, it is possible to eliminate a problem that occurs when a VLIW processor is simulated using a simulation method that sequentially executes the above-described instructions one by one. Can be simulated correctly.
[Brief description of the drawings]
FIG. 1 is a principle diagram schematically showing a data structure and a data flow when a simulation method according to the present invention is executed.
FIG. 2 is a principle diagram schematically showing a data structure and a data flow when data is merged as a result of executing a simulation method according to the present invention.
FIG. 3 is a flowchart of a program that causes a computer to execute the simulation method according to the first embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a main part of a data structure developed in a computer when the computer executes the simulation method according to the first embodiment of the present invention;
FIG. 5 is a flowchart showing an example of a result writing process in the simulation method shown in FIG. 3;
FIG. 6 is a block diagram showing a hardware configuration of a computer used for executing a simulation method according to the present invention.
FIG. 7 is a flowchart of a program that causes a computer to execute the simulation method according to the second embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a main part of a data structure developed in a computer when the computer executes the simulation method according to the second embodiment of the present invention;
FIG. 9 is a flowchart showing an example of exception processing in the simulation method shown in FIG. 7;
FIG. 10 is a conceptual diagram illustrating an example of a configuration of a VLIW instruction.
FIG. 11 is a flowchart of a program that causes a computer to execute a method of simulating an instruction operation of a normal processor.
FIG. 12 is a schematic diagram showing a data structure when executing a method for simulating an instruction operation of a normal processor;
[Explanation of symbols]
31 Resource data storage location
32 Temporary storage location
41 Register value storage table
42 Memory value storage table
45 Write register data table
46 Write memory data table

Claims (4)

In simulating the instruction operation of a processor that executes a plurality of instructions in a VLIW instruction including a data read instruction and a data write instruction for the same resource in parallel,
Reading the VLIW instruction from a memory location;
Decoding each instruction included in the read VLIW instruction;
Performing a calculation operation corresponding to each decoded instruction and storing the calculation result in a first storage location;
If no exception has occurred during the arithmetic operation for any instruction in the VLIW instruction, the storage of the decoded operation result of each instruction to the first storage location is completed, and then the first storage is performed. Writing the operation result of each instruction stored in a location to a resource data storage location which is a second storage location;
Prohibiting writing operation results for all instructions of the VLIW instruction including the instruction to the second storage location when an exception occurs during an operation for an instruction in the VLIW instruction;
The exception is a first type exception that causes an instruction other than the instruction that generated the exception in the VLIW instruction to be unexecuted, or an instruction other than the instruction that generated the exception in the VLIW instruction has been executed. Determining whether it is a second type of exception,
If the exception is the first type of exception, discarding data held in the first storage location;
When the exception is the second type exception, a step of writing an operation result of an instruction other than the instruction that generated the exception among the VLIW instructions from the first storage location to the second storage location. When,
The simulation method characterized by including.   When the data write destinations of a plurality of instructions included in the VLIW instruction are different fields of the same resource, the corresponding calculation results are read from the first storage location, merged and written to the second storage location The simulation method according to claim 1, wherein: A program for causing a computer to execute the simulation method according to claim 1 or 2 . A computer-readable recording medium on which the program according to claim 3 is recorded.

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