JP2003228492A - Computer simulation program, verification method for model of processor, and computer simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a computer simulation program capable of detecting readout from an uninitialized area. <P>SOLUTION: When executing a program with a model of a processor on a computer simulation, the computer simulation program assigns a flag for a memory element indicating whether or not writing has been already executed for each memory element in the memory area accessed by the model of the processor. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer simulation program, and more particularly to a computer simulation program for executing a computer processor simulation at an instruction level.

2. Description of the Related Art Generally, a program operating on a computer has a text area (text section), a data area (data section), a BSS area (BSS section), a stack area, and a heap area. The text area is an area for holding an instruction string and has an initial value when the program is executed. The data area is an area for holding data whose initial value is fixed, and has an initial value when the program is executed. The BSS area is an area that holds data for which an initial value has not been set and originally does not have an initial value, but is generally initialized to zero by the OS or an initialization routine. The stack area is an area that holds a frame for calling a procedure and a stack variable, and does not have an initial value when the program is executed. The heap area is an area used as a dynamic memory area and has no initial value when the program is executed. Dynamic acquisition and release of the memory area is done by a dedicated A such as malloc function and free function.
It is realized via a PI (Application Program Interface).

When a read / write operation is performed on these areas at the time of program execution, even if a read operation is performed on an area having an initial value before a write operation, the operation of the program is not stable. Absent. However, if the read operation is performed before the write operation for the area having no initial value, the operation of the program may become unstable. Therefore, in order to realize a program that operates normally (a program that does not become unstable in operation), an illegal read operation from an uninitialized area must not be performed.

Here, a program including an illegal read operation from an uninitialized area is referred to as an "incorrect program".
A program that does not include an illegal read operation from an uninitialized area is called a “correct program”.

Generally, a read / write operation to a memory area executed by a computer includes an instruction fetch, a data load by a load instruction, a data store by a store instruction, an instruction prefetch, a read of a cache block from a memory to an instruction cache, Reading cache blocks from memory to data cache, writing cache blocks from data cache to memory, and so on. Here, regarding operations other than instruction prefetch and reading of a cache block from the memory to the instruction cache, the operation of the program does not become unstable if it is a “correct program”. However, regarding the instruction prefetch and the read operation of the cache block from the memory to the instruction cache, it is possible that the prefetch target area is not initialized even if it is a “correct program”. In this case, the operation of the program does not become unstable, but a slight performance deterioration can be considered.

When designing a processor, the design information (model) of the processor is often described in a hardware description language. At this time, as work to confirm the certainty of the design of the processor model,
On a simulator that can handle hardware description language,
The logic verification work is often executed by executing the logic verification program according to the processor model.

Here, considering the case where the logic verification program is an “incorrect program”, an uncorrected uninitialized area is read, and therefore the model may not perform the expected operation. Even if the logic verification program is a “correct program”, if the prefetch target area is not initialized, the uninitialized area expressed as indefinite is read, and the model operates as expected. May not.

As described above, when the logic verification program reads the uninitialized area, the model does not operate as expected. Therefore, if such a logic verification program is used,
Unable to perform valid verification work on the design of the processor model. Therefore, when a logic verification program for reading the uninitialized area is created, it is desirable to detect that the uninitialized area is read and correct the logic verification program.

In view of the above, it is an object of the present invention to provide a computer simulation program capable of detecting reading of an uninitialized area.

A computer simulation program according to the present invention, when executing a program by a model of a processor on a computer simulation, for each memory element of a memory area accessed by the model of the processor, It is characterized by allocating a flag indicating whether or not writing to the memory element has already been performed.

In the above computer simulation program, a flag indicating whether or not the contents of the memory element have already been written is provided for each memory element. Therefore,
By checking this flag when executing the memory read operation, it becomes possible to detect when the read operation from the uninitialized area occurs.

The processor model verification method according to the present invention creates a logic verification program, and writes to the memory element for each memory element of the memory area accessed by the processor model on the computer simulation. By executing the logic verification program with an instruction level simulator that assigns a flag indicating whether or not the read operation is performed, it is determined whether or not the read operation from the uninitialized area is performed, and the uninitialized When the read operation from the area is detected, each step of modifying the logic verification program is included.

In the above processor model verification method, a flag indicating whether or not the content of the memory element has already been written is provided for each memory element, and this flag is checked when the logic verification program is executed by the computer simulator. By doing so, "read operation from uninitialized area"
It is possible to detect the occurrence of. As a result, the logic verification program can be appropriately modified to execute an appropriate logic verification work.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a flow chart of an instruction level computer simulator according to the present invention.

The instruction level simulator according to the present invention is
In step ST1, instruction fetch is performed and the instruction to be executed is stored in the instruction register. Next, in step ST2, instruction decoding is performed to interpret the instruction to be executed. Finally, in step ST3, instruction execution is performed.

FIG. 2 is a flow chart of instruction fetch.

In the instruction fetch stage, first, step ST
At 1, the instruction address to be fetched is calculated. Next, in step ST2, an instruction is read from the memory area corresponding to the calculated address. Finally in step ST3,
The read instruction is stored in the instruction register.

FIG. 3 is a flow chart of instruction execution.

In the instruction execution stage, first, step ST1
Then, the type of the instruction is determined.

When the instruction to be executed is the load instruction, the effective address is calculated based on the read result of the register in step ST2. In step ST3, the memory area corresponding to the calculated effective address is read. In step ST4, the read content is written in the register as load data.

When the instruction to be executed is the store instruction, the effective address is calculated based on the read result of the register in step ST5. In step ST6, the store data is read from the register. In step ST7,
Write the store data to the memory area corresponding to the effective address.

If the instruction to be executed is an arithmetic instruction,
In step ST8, the register is read. Step ST
At 9, the calculation is performed based on the read result. Step ST
At 10, the calculation result is written in the register.

If the instruction to be executed is a branch instruction,
In step ST11, the register is read. Step S
At T12, the branch address is calculated based on the read result. In step ST13, the calculated result is written in the program counter (register).

In the instruction level simulator according to the present invention, the memory read operation in step ST2 of the instruction fetch stage of FIG. 2 and step ST3 of the instruction execution stage of FIG. 3 and the memory of step ST7 of the instruction execution stage in FIG. In the write operation, processing is performed to enable detection of uninitialized area read.

FIG. 4 is a flow chart showing a first embodiment of the memory write operation according to the present invention. FIG. 5 is a flow chart showing a first embodiment of the memory read operation according to the present invention.

First, as a preparatory step, when the instruction simulator of the instruction simulator is started, the flags corresponding to the respective elements of the memory are initialized to 0. FIG. 6 is a diagram showing a data structure corresponding to the first embodiment. As shown in FIG. 6, the memory area 10 includes a memory element 10a which is an area for storing a memory value and a flag area 10b corresponding to the memory element 10a.
, Are assigned as a single collection of a plurality of groups. Each of the flag areas 10b is initialized to 0 when the instruction simulator is activated. Hereinafter, the flag in the flag area 10b will be referred to as flag A.

When a memory write operation for writing to the memory element 10a at the specified address is executed during execution of the program in the instruction level simulator, first, FIG.
In step ST1 of, the memory element 10a to be written is
It is determined whether or not the flag A corresponding to is 0. If the flag A is 0, the flag A is changed to 1 in step ST2, and the process proceeds to step ST3. If the flag A is not 0, the process directly proceeds to step ST3. Step ST3
Then, the write data is written in the memory element 10a at the specified address.

When a memory read operation for reading the memory element 10a at the specified address is executed during execution of the program in the instruction level simulator, first, FIG.
In step ST1 of, the memory element 10a to be read
It is determined whether or not the flag A corresponding to is 0. If the flag A is 0, the read operation for the uninitialized area is detected in step ST2, and the process proceeds to step ST3. If flag A is not 0, then step ST3
Proceed to. In step ST3, data is read from the memory element 10a at the designated address.

As described above, in the first embodiment of the memory write operation and the memory read operation of the present invention, when managing a plurality of memory elements as a storage space, whether the contents of the memory elements have already been written or not. Providing a flag indicating whether or not each memory element makes it possible to detect a read operation from an uninitialized area.

FIG. 7 is a flow chart showing a second embodiment of the memory write operation according to the present invention. FIG. 8 is a flow chart showing a second embodiment of the memory read operation according to the present invention.

FIG. 9 is a diagram showing a data structure corresponding to the second embodiment. As shown in FIG. 9, the memory area 1
2 is a plurality of memory allocation areas 13 that are discretely allocated
In each memory allocation area 13, a memory element 13a, which is an area for storing a memory value, and a flag area 13b corresponding thereto are allocated as a single group. After that, the flag of the flag area 13b is set to the flag A.
Call.

FIG. 10 is a diagram showing a data structure for managing the discrete memory area of FIG. As shown in FIG. 10, a memory allocation management table 14 is provided, the head address of each memory allocation area 13 is a table entry 14a, and the pointer to the memory allocation area 13 corresponding to each head address is a further table entry 14b. . In this way, by managing the storage area by the memory allocation management table 14, while executing the computer simulation,
The memory allocation area 13 can be increased as needed at any time.

When a memory write operation for writing to the memory element 13a at the specified address is executed during execution of the program in the instruction level simulator, first, FIG.
In step ST1 of, the memory element 13a to be written
It is determined whether or not the memory allocation area 13 including is already allocated and secured. If so, it is determined in step ST2 whether or not the flag A corresponding to the memory element 13a to be written is 0. Flag A is 0
If so, the flag A is changed to 1 in step ST3, and the process proceeds to step ST6. If flag A is not 0,
Then, the process proceeds to step ST6. If it is determined in step ST1 that the memory allocation area 13 is not secured, the memory allocation area 13 is allocated in step ST4 and all the flags A in the allocated memory allocation area 13 are initialized to 0. To do. Thereafter, in step ST5, the flag A corresponding to the memory element 13a to be written is changed to 1. In step ST6, write data is written in the memory element 13a at the specified address.

When a memory read operation for reading the memory element 13a at the specified address is executed during execution of the program in the instruction level simulator, first, FIG.
In step ST1 of, the memory element 13a to be read
It is determined whether or not the memory allocation area 13 including is already allocated and secured. If so, it is determined in step ST2 whether the flag A corresponding to the memory element 13a to be read is 0. Flag A is 0
If so, the read operation for the uninitialized area is detected in step ST3, and the process proceeds to step ST6. flag
If A is not 0, the process directly proceeds to step ST6. If it is determined in step ST1 that the memory allocation area 13 is not secured, the memory allocation area 13 is allocated in step ST4 and all the flags A in the allocated memory allocation area 13 are initialized to 0. To do. Then, in step ST5, the read operation for the uninitialized area is detected. In step ST6, data is read from the memory element 13a at the designated address.

As described above, in the second embodiment of the memory writing operation and the memory reading operation of the present invention, a plurality of memory allocation areas are discretely allocated and managed as a plurality of memory allocation areas. In case,
By providing a flag indicating whether or not the content of the memory element has already been written to each memory element, it becomes possible to detect the read operation from the uninitialized area.

FIG. 11 is a flow chart showing a third embodiment of the memory write operation according to the present invention. 12
3 is a flowchart showing a third embodiment of the memory read operation according to the present invention.

FIG. 13 is a diagram showing a data structure corresponding to the third embodiment. The data structure shown in FIG. 13 is the same as the data structure for managing the discrete memory area shown in FIG. 9 except that the flag area 13c is provided for each memory allocation area 13. Hereinafter, the flag in the flag area 13c is referred to as flag B.

When a memory write operation for writing to the memory element 13a at a specified address is executed at the time of executing a program in the instruction level simulator, first, as shown in FIG.
In step ST1 of 1, the memory element 13 to be written
It is determined whether the memory allocation area 13 including a is already allocated and secured. If so, it is determined in step ST2 whether or not the flag A corresponding to the memory element 13a to be written is 0. If the flag A is 0, the flag A is changed to 1 in step ST3, and the process proceeds to step ST6. If flag A is not 0,
Go to step ST9. If it is determined in step ST1 that the memory allocation area 13 is not secured,
In step ST4, the memory allocation area 13 is allocated,
Set all flags A in the allocated memory allocation area 13 to 0
Initialize to. After that, in step ST5, the flag A corresponding to the memory element 13a to be written is changed to 1,
Go to step ST6.

In step ST6, it is determined whether or not the flag B of the memory allocation area 13 including the memory element 13a to be written is 0. If the flag B is 0, the process proceeds to step ST7. If the flag B is not 0, the process proceeds to step ST9.

At step ST7, all flags A in the memory allocation area 13 including the memory element 13a to be written are included.
Is determined to be 1. If all the flags A are 1, the corresponding flags B are changed to 1 in step ST8, and then the process proceeds to step ST9. If at least one flag A is not 1, the process directly proceeds to step ST9.

In step ST9, write data is written in the memory element 13a at the specified address.

When a memory read operation for reading the memory element 13a at the specified address is executed during execution of the program in the instruction level simulator, first, as shown in FIG.
In step ST1 of 2, the memory element 13 to be read
It is determined whether the memory allocation area 13 including a is already allocated and secured. If secured, the flag B of the memory allocation area 13 is set to 0 in step ST2.
Or not. If flag B is 0,
Go to step ST3. If the flag B is not 0, the process proceeds to step ST7.

In step ST3, it is determined whether or not the flag A corresponding to the memory element 13a to be read is 0. If the flag A is 0, the read operation for the uninitialized area is detected in step ST4, and step S
Proceed to T7. If the flag A is not 0, the process directly proceeds to step ST7.

In step ST1, memory allocation area 13
If it is determined that is not secured, step S
At T5, the memory allocation area 13 is allocated, and all the flags A in the allocated memory allocation area 13 are initialized to 0 and the corresponding flags B are initialized to 0. Then, in step ST6, the read operation for the uninitialized area is detected.

At step ST7, data is read from the memory element 13a at the designated address. With that, the process ends.

As described above, in the third embodiment of the memory writing operation and the memory reading operation of the present invention, a plurality of memory allocation areas are discretely allocated and managed as a plurality of memory allocation areas. In case,
A flag indicating whether or not the content of the memory element has already been written is provided for each memory element, and a flag indicating whether or not all the memory elements have already been written is provided for each memory allocation area. As a result, when all the memory elements in the memory allocation area have already been written, it becomes possible to detect the read operation from the uninitialized area without checking the flags of each memory element one by one. .

FIG. 14 is a flow chart showing a fourth embodiment of the memory write operation according to the present invention. Figure 15
9 is a flowchart showing a fourth embodiment of the memory read operation according to the present invention.

FIG. 16 is a diagram showing a data structure corresponding to the fourth embodiment. The data structure shown in FIG. 16 is the same as the data structure for managing the discrete memory area shown in FIG. 13 except that the count area 13d is provided for each memory allocation area 13. The count area 13d is a memory element 13a that is an uninitialized area.
A count number C that is incremented by one each time a write operation is executed is stored in the.

The flowchart of the fourth embodiment of the memory write operation shown in FIG. 14 is different from the flowchart of the third embodiment of the memory write operation shown in FIG.
The difference is that step ST7 is changed to steps ST7A and ST7B.

When the flag B is determined to be 0 in step ST6, the count number C is incremented by 1 in step ST7A. Then, in step ST7B, it is determined whether the count number C is equal to the number of memory elements in the memory allocation area 13. If both are equal, all flags A are 1, so the corresponding flag B is changed to 1 in step ST8. If they are not the same, at least one flag A is not 1, so the process proceeds to step ST9.

Since the flow chart of the fourth embodiment of the memory read operation shown in FIG. 15 is the same as the flow chart of the third embodiment of the memory read operation shown in FIG. 12, its explanation is omitted.

As described above, in the fourth embodiment of the memory write operation and the memory read operation of the present invention, a plurality of memory allocation areas are discretely allocated and managed as a plurality of memory allocation areas. In case,
A flag indicating whether or not the content of the memory element has already been written is provided for each memory element, and a flag indicating whether or not all the memory elements have already been written for each memory allocation area and the already written memory. And a counter for indicating the number of elements. As a result, it is possible to easily determine whether or not all the memory elements in the memory allocation area have already been written by checking the counter without checking the flags of each memory element one by one. Therefore, it becomes possible to efficiently detect the read operation from the uninitialized area.

FIG. 17 is a flow chart of verification work using the computer simulator according to the present invention.

In step ST1, a logic verification program is created. In step ST2, the logic verification program is executed by the instruction level simulator. That is, by executing the instruction level simulator shown in FIG. 1, the logic verification program created in step ST1 is executed on the simulator. At this time, for the data writing and data reading operations, any one of the first to fourth embodiments described above is used.

In step ST3, it is determined whether the logic verification program has ended normally and no access to the uninitialized area has been detected. In the above-described first to fourth embodiments, when the read operation from the uninitialized area is detected, the fact that the “read operation from the uninitialized area” is executed is displayed together with the information such as the read address in the error log, for example. To record. By checking this error log, it is possible to check whether or not there is a "read operation from the uninitialized area". The information indicating that the "read operation from the uninitialized area" has occurred may be sequentially displayed on the display of the computer simulator every time it occurs.

If the determination in step ST3 is NO, there is a problem with the logic verification program, so the logic verification program is corrected in step ST4, and the processes in and after step ST2 are repeated. If the determination in step ST3 is YES, there is no problem with the logic verification program, so the verification work using the logic verification program is executed in step ST5.

With the above, the processing is completed.

As described above, in the present invention, when the logic verification program is executed by the computer simulator, it is possible to detect that the "read operation from the uninitialized area" has occurred, and therefore the logic verification program is appropriately used. It can be modified to perform the appropriate logic verification work.

FIG. 18 is a diagram showing the configuration of an apparatus for executing computer simulation according to the present invention.

As shown in FIG. 18, the apparatus for executing the computer simulation according to the present invention is realized by a computer such as a personal computer or an engineering workstation. The device of FIG. 18 includes a computer 510, a display device 520 connected to the computer 510, a communication device 523, and an input device. The input device is, for example, the keyboard 52.
1 and mouse 522. The computer 510 is C
PU 511, RAM 512, ROM 513, secondary storage device 514 such as a hard disk, removable medium storage device 51
5 and an interface 516.

The keyboard 521 and the mouse 522 provide an interface with the user, and various commands for operating the computer 510 and user responses to requested data are input. The display device 520 displays the results processed by the computer 510, and displays various data to allow the user to interact when operating the computer 510. The communication device 523 is for communicating with a remote place, and is composed of, for example, a modem or a network interface.

The computer simulation method according to the present invention is provided as a computer program executable by the computer 510. This computer program is stored in a storage medium M that can be mounted in the removable medium storage device 515, and the storage medium M to the removable medium storage device 51 is stored in the storage medium M.
5, and is loaded into the RAM 512 or the secondary storage device 514. Alternatively, this computer program is stored in a storage medium (not shown) in a remote place, and is loaded from the storage medium into the RAM 512 or the secondary storage device 514 via the communication device 523 and the interface 516.

Keyboard 521 and / or mouse 522
When a user gives a program execution instruction via
The U 511 loads the program from the storage medium M, the remote storage medium, or the secondary storage device 514 into the RAM 512. The CPU 511 uses the free storage space of the RAM 512 as a work area, executes the program loaded in the RAM 512, and advances the processing while appropriately interacting with the user. The ROM 513 is the computer 510.
A control program for controlling the basic operation of is stored.

By executing the above computer program, the instruction level computer simulation method is executed as described in each of the above embodiments. Further, this computer simulation environment is a computer simulator.

Although the present invention has been described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.

In the computer simulation program according to the present invention, a flag indicating whether or not the content of the memory element has already been written is provided for each memory element. Therefore, by checking this flag when executing the memory read operation, it becomes possible to detect when the read operation from the uninitialized area occurs.

Further, in the method of verifying the model of the processor according to the present invention, a flag indicating whether or not the content of the memory element has already been written is provided for each memory element, and this flag is set when the logic verification program is executed by the computer simulator. By checking, it is possible to detect that the "read operation from the uninitialized area" has occurred. This allows you to modify the logic verification program as appropriate,
Appropriate logic verification work can be performed.

[Brief description of drawings]

FIG. 1 is a flowchart of an instruction level computer simulator according to the present invention.

FIG. 2 is a flowchart of instruction fetch.

FIG. 3 is a flowchart of instruction execution.

FIG. 4 is a flowchart showing a first embodiment of a memory write operation according to the present invention.

FIG. 5 is a flowchart showing a first embodiment of a memory read operation according to the present invention.

FIG. 6 is a diagram showing a data structure corresponding to the first example.

FIG. 7 is a flowchart showing a second embodiment of a memory write operation according to the present invention.

FIG. 8 is a flowchart showing a second embodiment of the memory read operation according to the present invention.

FIG. 9 is a diagram showing a data structure corresponding to the second embodiment.

10 is a diagram showing a data structure for managing the discrete memory area of FIG.

FIG. 11 is a flowchart showing a third embodiment of a memory write operation according to the present invention.

FIG. 12 is a flowchart showing a third embodiment of the memory read operation according to the present invention.

FIG. 13 is a diagram showing a data structure corresponding to the third example.

FIG. 14 is a flow chart showing a fourth embodiment of a memory write operation according to the present invention.

FIG. 15 is a flowchart showing a fourth embodiment of the memory read operation according to the present invention.

FIG. 16 is a diagram showing a data structure corresponding to the fourth example.

FIG. 17 is a flowchart of verification work using the computer simulator according to the present invention.

FIG. 18 is a diagram showing a configuration of an apparatus for executing computer simulation according to the present invention.

[Explanation of symbols]

510 computer 511 CPU 512 RAM 513 ROM 514 secondary storage device 515 Removable medium storage device 516 interface 520 display device 521 keyboard 522 mouse 523 Communication device

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Claims (10)

[Claims] 1. When executing a program by a model of a processor on a computer simulation, whether or not writing to the memory element has already been performed for each of the memory elements of the memory area accessed by the model of the processor. A computer simulation program characterized by allocating a flag indicating that. 2. The computer simulation program according to claim 1, wherein the memory area is managed as a single continuous allocation space, and the single continuous allocation space includes a plurality of the memory elements. 3. The memory area is managed by discretely allocating a plurality of single continuous allocation spaces, and the single continuous allocation space includes a plurality of the memory elements. The computer simulation program according to claim 1. 4. A flag is assigned to each of the single contiguous allocation spaces to indicate whether a write has already been performed to all of the corresponding memory elements. The computer simulation program described. 5. A count number is assigned to each of the single contiguous allocation spaces, the count number indicating the number of memory elements of the corresponding memory elements that have already been written. 4. The computer simulation program described in 4. 6. A read operation from an uninitialized area occurs when a read operation is performed on a memory element at a specified address and the flag corresponding to the memory element at the specified address indicates unwritten. The computer simulation program according to claim 1, wherein the computer simulation program detects that the above has been done. 7. A fetch step of fetching an instruction of the program, a decode step of decoding the instruction, and an instruction execution step of executing the decoded instruction,
7. The computer simulation program according to claim 6, wherein the read operation is executed in the fetch step and the instruction execution step. 8. The computer simulation program according to claim 6, wherein the fact that a read operation from the uninitialized area has occurred is recorded as an error log. 9. A logic verification program is created, and a flag indicating whether or not writing to the memory element has already been performed is assigned to each memory element of the memory area accessed by the model of the processor on the computer simulation. When the read operation from the uninitialized area is detected by executing the logic verification program with the instruction level simulator and checking the flag to determine whether or not the read operation from the uninitialized area is executed. A method of verifying a model of a processor by an instruction level simulator including each step of modifying the logic verification program. 10. When executing a program by a model of a processor on a computer simulation, whether or not writing to the memory element has already been performed for each of the memory elements of the memory area accessed by the model of the processor. A computer simulation method comprising the step of assigning a flag indicating that.