JP2015162191A - Software testing apparatus and software testing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide means for ensuring the accuracy of data copying processing in software quality evaluation.SOLUTION: A system simulator 10 comprises: an instruction set simulator 100 executing software and simulating the software; a memory model 200 simulating operation performed by a memory accessed by the software simulated by the instruction set simulator 100; and a copy omission detector 200 monitoring an access to the memory model 200 from the software, recording a monitoring result of the monitored access, and detecting whether a pre-defined error occurs to data copying processing on the basis of the recorded access monitoring result, the data copying processing being processing performed by the software for reading data on a copy source memory serving as a copy source and writing the data to a copy destination memory serving as a copy destination.

Description

  The present invention relates to a software test program for testing software quality.

  In an embedded software test (hereinafter, software is referred to as S / W), S / W quality evaluation is generally performed by using test coverage such as code coverage. For example, in Patent Document 1, in a maintenance support device for an embedded system in which a computer system composed of a plurality of modules is installed, a test of a cluster is performed, and a test coverage indicating a test coverage rate as an evaluation index for the result is obtained. Display techniques have been proposed. Patent Document 2 proposes a consistency check method that can clearly distinguish between match and mismatch between codes using new code coverage. Patent Document 3 proposes a technique for evaluating a test scenario by calculating device API call coverage.

JP2012-073692A JP 2009-163636 A JP 2012-103745 A

  In conventional S / W quality evaluation using code coverage, there is a problem that data copy omissions occurring under various conditions cannot be detected. Since Patent Documents 1 to 3 use code coverage, even if data copy processing is not properly implemented, it is erroneously determined that there is no problem in quality. This is because code coverage is an index indicating the coverage rate of the logical paths that can be passed in the source code, and does not determine whether each instruction is correct or incorrect.

  An object of the present invention is to guarantee the accuracy of data copy processing in S / W quality evaluation.

The software testing apparatus of the present invention
A software simulation unit that executes software to simulate the software;
A memory simulator for simulating the operation of a memory accessed by the software simulated by the software simulator;
The access to the memory simulation unit by the software is monitored, and the monitored access monitoring result is recorded. Based on the recorded access monitoring result, the data of the copy source memory that is a process of the software and serves as a copy source is recorded. The data copy process, which is a process of reading and writing to a copy destination memory as a copy destination, includes an error detection unit that detects whether or not a predefined error has occurred.

  According to the present invention, it is possible to guarantee the accuracy of the data copy process in the S / W quality evaluation.

FIG. 3 is a diagram of the first embodiment and is a configuration diagram of a system simulator 10. FIG. 5 is a flowchart of a copy leakage detection procedure when the system simulator 10 is used in the diagram of the first embodiment. FIG. 3 is a diagram of the first embodiment, and is a configuration diagram of a copy leakage detection unit 200. 3 is a detailed flowchart showing the contents of copy omission detection S11 in FIG. FIG. 3 is a diagram of the first embodiment and shows a memory map 400; FIG. 4 is a diagram of the first embodiment, showing a copy leak detection result 500; FIG. 3 is a diagram illustrating a copy leakage error list according to the first embodiment. 5 is a detailed flowchart showing the contents of table initialization S110 in FIG. 5 is a detailed flowchart showing the contents of memory access monitoring S111 in FIG. The detailed flowchart which shows the content of S1112 of FIG. The detailed flowchart which shows the content of S1114 of FIG. The detailed flowchart which shows the content of S1116 of FIG. 5 is a detailed flowchart showing details of error detection S114 in FIG. FIG. 3 is a configuration diagram of a system simulator 20 of a second embodiment. FIG. 9 is a flowchart of a copy leakage detection procedure when the system simulator 20 is used in the diagram of the second embodiment. FIG. 4 is a diagram of the second embodiment, and illustrates an example of a hardware configuration of system simulators 10 and 20.

Embodiment 1 FIG.
[Configuration of System Simulator 10]
FIG. 1 is a configuration diagram of a system simulator 10 (software test apparatus). The configuration of the system simulator 10 will be described with reference to FIG. The system simulator 10 includes an instruction set simulator (Instruction Set Simulator) 100, a copy omission detection unit 200 (error detection unit), and a memory model 300 (memory simulation unit). The operation of the system simulator 10 will be described later with reference to FIG.

(Instruction Set Simulator 100)
The instruction set simulator 100 (software simulation unit) has a function of reading S / W and test patterns and simulating (simulating) instruction processing, memory access, and program counter operations.

(Copy leakage detection unit 200)
The copy leak detection unit 200 monitors the access to the memory model 300 by S / W, records the monitored access monitoring result in a memory map record 211 described later, and is simulated based on the memory map record 211. It is detected whether or not a predefined error has occurred in the data copy processing by / W. The data copy process is a process based on S / W, and is a process of reading data from a source memory as a copy source and writing it into a destination memory as a copy destination. Specifically, the copy omission detection unit 200 performs copying based on the execution instruction address output from the instruction set simulator 100, the R / W (read / write) request to the memory model, the address, data, and the memory map 400. Perform leak detection. The detection result is output as a copy leak detection result 500. The internal configuration and operation of the copy leakage detection unit 200 will be described later with reference to FIGS.

(Memory model 300)
The memory model 300 has a function of simulating the operation of a memory mounted on the system. The system simulator 10 assumes two types: a source memory that is a data copy source and a destination memory that is a data copy destination. The two types of memories may be the same memory, or are configured using two independent memories. As long as the memory operation can be simulated correctly, the memory model mounting method for application to the system simulator 10 is not particularly limited.

(Memory map 400)
The memory map 400 is a file that defines a source memory R / W trigger setting, a source memory address, and a destination memory address pair.
FIG. 5 shows an image of the memory map 400.

(Copy leak detection result 500)
The copy leakage detection result 500 is an output of detailed information regarding copy leakage detected by the copy leakage detection unit 200.
FIG. 6 shows an output image of the copy leak detection result.
FIG. 7 shows a list of detectable errors.

[Overall Operation Flowchart of System Simulator 10]
FIG. 2 is a flowchart showing a copy leakage detection procedure when the system simulator 10 is used. The operation of the system simulator 10 will be described with reference to FIG.
(1) In S10, the instruction set simulator 100 executes S / W simulation.
(2) In S11, copy leakage is detected. A detailed flow for detecting copy leakage will be described with reference to FIGS. 4, 8, 9, 10, 11, 12, and 13. Details of S11 in FIG. 2 are shown in FIG. 4 will be further described in detail with reference to FIGS. 8, 9, and 13 (described later). Details of S110, S111, and S114 of FIG. 4 are FIGS. 8, 9, and 13, respectively. Details of S1112, S1114, and S1116 in FIG. 9 are shown in FIGS. 10 to 12 (described later).
(3) In S12, it is determined whether or not copy leakage is 0 (whether there is no copy leakage). If S12 is true (no copy omission), the test is terminated. If S12 is false (there is a copy omission), the process branches to S13.
(4) In S13, for example, the person in charge evaluates the copy leakage detection result 500 and identifies the cause of the copy leakage.
(5) In S14, for example, the person in charge corrects the copy omission cause location. After correction, S10 is executed again.
(6) The above process is executed until it is determined in S12 that copy leakage is zero.

[Configuration of Copy Leakage Detection Unit 200]
FIG. 3 is a configuration diagram of the copy leak detection unit 200. The internal configuration of the copy leak detection unit 200 will be described with reference to FIG. The copy omission detection unit 200 includes a memory map table 210, a table initialization unit 220, a memory access monitoring unit 230, and an error detection unit 240.

(Memory map table 210)
The memory map table 210 holds memory map records 211 (memory map information) for the number of combinations of the source memory address and the destination memory address. A combination of the source memory address and the destination memory address is defined in the memory map 400. The memory map record 211 is registered so that it can be searched using the source memory address or the destination memory address as a key.
The memory map table 210 is stored in the magnetic disk device 960 (an example of the memory map information storage unit) or the RAM 952 (an example of the memory map information storage unit) in the third embodiment showing the hardware configuration of the system simulator 10.

(Memory map record 211)
The memory map record 211 includes a source memory R / W trigger setting 212, a source memory push flag 213 (first flag), a source memory POP flag 214 (second flag), a source memory address 215, a destination memory address 216, and execution. It consists of an instruction address 217 and memory data 218.
In the source memory R / W trigger setting 212, the source memory address 215, and the destination memory address 216, the values of the memory map 400 are described as described later (table initialization process). The source memory PUSH flag 213, the source memory POP flag 214, the execution instruction address 217, the memory data 218, and the like are recorded according to the memory access monitoring result as described later (S11142, S11163).

(1) The source memory R / W trigger setting 212 indicates whether data is registered at the read or write timing of the source memory.
(2) The source memory PUSH flag 213 indicates whether or not the source memory data is registered in the table.
(3) The Source memory POP flag 214 indicates whether or not the source memory data has been deleted from the table.
(4) The source memory address 215 represents an address of the source memory.
(5) Destination memory address 216 represents the address of the destination memory.
(6) The execution instruction address 217 represents the address of the instruction that accessed the source memory.
(7) The memory data 218 represents data written to the source memory or data read from the source memory.

(Table initialization unit 220)
The table initialization unit 220 initializes the memory map table 210 so that the memory access monitoring unit 230 can search the memory map table 210 using the source memory address or the destination memory address as a key. Initialization is executed at the start of the S / W simulation. The table initialization unit 220 sets the source memory address and the destination memory address described in the memory map 400 as one set, and sets values in the source memory address 215 and the destination memory address 216 of one record. Further, the table initialization unit 220 sets the source memory R / W trigger setting described in the memory map 400 to the source memory R / W trigger setting 212. The table initialization unit 220 sets the source memory PUSH flag 213, the source memory POP flag 214, the execution instruction address 217, and the memory data 218 to zero. After completing the data setting, the table initialization unit 220 registers the memory map record 211 in the memory map table 210. A flowchart of the operation of the table initialization unit 220 will be described later with reference to FIG.

(Memory access monitoring unit 230)
The memory access monitoring unit 230 searches the memory map table 210 with the occurrence of a memory R / W request as a trigger. The memory map table 210 is searched using the memory address as a key, and if there is a hit record, data registration / deletion is performed. If a copy leak occurs during the simulation, the memory access monitoring unit 230 notifies the error detection unit 240 and causes the copy leak detection result 500 to output the detection result. The operation of the memory access monitoring unit 230 will be described later with reference to FIGS. 9, 10, 11, and 12.

(Error detection unit 240)
The error detection unit 240 operates at the timing of error notification from the memory access monitoring unit 230 or the end of simulation. The error detection unit 240 detects the cause of copy leakage based on the state of each memory map record 211 and outputs the detection result to the copy leakage detection result 500. The operation of the error detection unit 240 will be described later with reference to FIG.

[Detailed Operation of Copy Leakage Detection S11]
FIG. 4 is a detailed flowchart of copy leakage detection S11. The detailed operation of the copy omission detection S11 will be described with reference to FIG.
(1) In S110, the table initialization unit 220 initializes the table. Details of the operation of the table initialization unit 220 will be described later with reference to FIG.
(2) In S111, the memory access monitoring unit 230 monitors the memory access of the software, and if there is access, searches and updates the memory map table 210. Details of the operation of the memory access monitoring unit 230 will be described later with reference to FIGS. 9, 10, 11, and 12.
(3) In S112, the memory access monitoring unit 230 determines whether an error has occurred, and branches depending on whether an error has occurred in S111. If S112 is true (an error has occurred), the process proceeds to S114. If S112 is false (no error has occurred), the process proceeds to S113.
(4) In S113, the process branches depending on whether the simulation is completed. If S113 is true (simulation end), the process proceeds to S114. When S113 is false (simulation has not ended), the process returns to S111.
(5) In S114, when an error occurs in the memory access monitoring (S111) by the memory access monitoring unit 230, the error detection unit 240 outputs detailed information to the copy omission detection result 500. Further, after the simulation is completed, the error detection unit 240 checks the flag of each memory map record 211 in the memory map table 210 to check whether an error has occurred. Details of this will be described later with reference to FIG.

[Detailed Operation of Table Initialization S110]
FIG. 8 is a detailed flowchart of table initialization (S110) executed by the table initialization unit 220. The operation of the table initialization S110 by the table initialization unit 220 will be described with reference to the drawing. The operation subject in FIG. 8 is the table initialization unit 220.
(1) In S1100, the table initialization unit 220 reads memory map data from the memory map 400.
(2) In S1101, the table initialization unit 220 generates a memory map record 211, and clears all settings (212), flags (213, 214), addresses (215-217), and data (218) to 0. To do.
(3) In S1102, the table initialization unit 220 adds, to each item (212, 215, 216) of the memory map record 211 generated in S11001, the Source memory R / W trigger setting, Source memory address, and Destination read in S1100. Set the memory address.
(4) In S1103, the table initialization unit 220 registers the memory map record 211 generated in S1101 in the memory map table 210.
(5) In S1104, the process branches depending on whether all data in the memory map 400 has been read.
If S1104 is true (reading complete), the process ends. If S1104 is false (reading is incomplete), the process returns to S1100.

[Detailed Operation of Memory Access Monitoring S111]
FIG. 9 is a detailed flowchart of the memory access monitoring S111 performed by the memory access monitoring unit 230. The operating subject is the memory access monitoring unit 230. A detailed operation of the memory access monitoring S111 performed by the memory access monitoring unit 230 will be described with reference to FIG. The determination of S1111, S1113, S1115, etc. in FIG. 9 can be made by the memory access monitoring unit 230 referring to the input data such as the memory R / W request, memory address, etc. of FIG.
(1) In S1110, it is determined whether there is a memory access. The error detection unit 240 can determine whether or not a memory R / W request or the like is input in FIG. If S1110 is true (with memory access), the process branches to S1111. If S1110 is false (no memory access), the process ends.
(2) In S1111, the memory access monitoring unit 230 determines whether to read from the destination memory. If S1111 is true (reading from the Destination memory), the process branches to S1112. If S1111 is false (not reading from the Destination memory), the process branches to S1113.
(3) In S1112, the memory access monitoring unit 230 performs processing at the time of reading the destination memory. Details will be described later with reference to FIG.
(4) In S1113, the memory access monitoring unit 230 determines whether or not to write to the source memory. If S1113 is true (write to the source memory), the process branches to S1114. If S1113 is false (not writing to the source memory), the process branches to S1115.
(5) In S1114, the memory access monitoring unit 230 performs processing at the time of writing to the source memory. Detailed operation will be described later with reference to FIG.
(6) In S1115, the memory access monitoring unit 230 determines whether to write to the destination memory. If S1115 is true (write to the Destination memory), the process branches to S1116. If S1115 is false (not writing to the Destination memory), the process ends.
(7) In S1116, the memory access monitoring unit 230 performs processing at the time of writing to the destination memory. Details will be described later with reference to FIG.

[Details of Processing S1112 when Reading Destination Memory]
FIG. 10 is a detailed flowchart of the processing S1112 in reading the Destination memory. The operation subject is the memory access monitoring unit 230. With reference to FIG. 10, the detailed content of processing S1112 at the time of reading the Destination memory by the memory access monitoring unit 230 will be described.
(1) In S11120, the memory access monitoring unit 230 searches the memory map table 210 for a memory map record that hits the input memory address. If S11120 is true (the corresponding record exists), the process branches to S11121. If S11120 is false (the corresponding record does not exist), the process ends.
(2) In S11121, the memory access monitoring unit 230 branches the process depending on whether the Source memory PUSH flag 213 is invalid. If S11121 is true (Source memory PUSH flag 213 is invalid), the process ends. If S11121 is false (Source memory PUSH flag 213 is valid), the process branches to S11122. Note that the Source memory PUSH flag 213 is enabled in S11142 of FIG.
(3) In S11122, a read timing error is generated. The read timing error indicates that the destination memory is erroneously read before copying the data to the source memory to the destination memory by an interrupt or asynchronous read from the outside. That is, S11121 is false in S11121 (the Source memory PUSH flag 213 is valid) indicates that the data in the source memory is registered in the memory map table 210 (the process of S1113 in FIG. 12 has not been performed). 10 to 13, when an error occurs (S1112, S11143, S11164, S11167, S11168, S11169, S11143), the memory access monitoring unit 230 transmits an error detection request to the error detection unit 240 (FIG. 2). FIG. 3) shows “S1112, S11143, S11164, S11167, S11168, S11169, and S11143” as “errors defined in advance” in order to detect them as errors.

[Details of processing S1114 when writing to the source memory]
Details of the processing S1114 at the time of writing to the source memory will be described with reference to FIG. FIG. 11 is a detailed flowchart of the processing S1114 at the time of writing to the source memory. 11 is the memory access monitoring unit 230.
(1) In S11140, the memory access monitoring unit 230 searches the memory map table 210 for a record that hits the input memory address. If S11140 is true (the corresponding record exists), the process branches to S11141. If S11140 is false (the record does not exist), the process ends.
(2) In S11141, the memory access monitoring unit 230 branches depending on whether the Source memory PUSH flag 213 is invalid. If S11141 is true (Source memory PUSH flag 213 is invalid), the process branches to S11142. If S11141 is false (Source memory PUSH flag 213 is valid), the process branches to S11143.
(3) In S11142, the memory access monitoring unit 230 registers the input source memory data and the input execution instruction address, and validates the source memory PUSH flag 213.
(4) In S11143, the memory access monitoring unit 230 outputs a copy leakage error. The copy omission error indicates that writing to the source memory was performed before valid data in the source memory was copied to the destination memory.

[Details of Processing S1116 when Writing to Destination Memory]
FIG. 12 is a detailed flowchart of the processing S1116 at the time of writing to the destination memory. The operation subject is the memory access monitoring unit 230. With reference to FIG. 12, the operation of processing S1116 at the time of writing to the destination memory will be described.
(1) In S11160, the memory access monitoring unit 230 searches for a record that hits the memory address input to the memory map table 210. If S11160 is true (the corresponding record exists), the process branches to S11161. If S11160 is false (the record does not exist), the process ends.
(2) In S11161, the memory access monitoring unit 230 branches the process depending on whether the Source memory PUSH flag 213 is valid. If S11161 is true (Source memory PUSH flag 213 is valid), the process branches to S11162. If S11161 is false (Source memory PUSH flag 213 is invalid), the process branches to S11165.
(3) In S11162, the memory access monitoring unit 230 branches depending on whether the Destination memory data of the memory map record matches the input Source memory data. If S11162 is true (Destination memory data and Source memory data 218 match), the process branches to S11163. If S11162 is false (Destination memory data and Source memory data 218 do not match), the process branches to S11164.
(4) In S11163, the memory access monitoring unit 230 invalidates the Source memory PUSH flag 213 and validates the Source memory POP flag 214. An error does not occur in S11163, but this is because the memory map record 211 exists, the Source memory data PUSH flag is valid (the data is already stored in the Source memory), and the Destination memory data (the left side of FIG. 3 is input). This is because the source memory data (the value of the destination memory address 216 of the memory map record 211) is the same.
(5) In S11164, the memory access monitoring unit 230 outputs a Destination memory data error. The Destination memory data error indicates that data different from the copy source Source memory data has been written in the Destination memory.
(6) In S11165, the memory access monitoring unit 230 branches the process depending on whether the Source memory POP flag 214 is valid. If S11165 is true (the Source memory POP flag 214 is valid), the process branches to S11166. If S11165 is false (Source memory POP flag 214 is invalid), the process branches to S11169.
(7) In S11166, the memory access monitoring unit 230 branches the process depending on whether the Destination memory data and the Source memory data 218 match. If S11166 is true (Destination memory data and Source memory data 218 match), the process branches to S11167. If S11166 is false (Destination memory data and Source memory data 218 do not match), the process branches to S11168.
(8) In S11167, the memory access monitoring unit 230 outputs a Destination memory multiple write error. The Destination memory multiple write error indicates that writing to the Destination memory has been performed again to the Destination memory address that has already been copied.
(9) In S11168, the memory access monitoring unit 230 outputs a copy order error. The copy order error indicates that data has been written to the destination memory before data is stored in the source memory.
(10) In S11169, the memory access monitoring unit 230 outputs a copy order error. The copy order error indicates that data has been written to the destination memory before data is stored in the source memory.

[Details of error detection S114]
FIG. 13 is a detailed flowchart of error detection S114 performed by the error detection unit 240. The operation subject in FIG. 13 is the error detection unit 240. The operation of error detection S114 will be described with reference to FIG.
(1) In S1140, the error detection unit 240 branches depending on whether an error has occurred in the memory access monitoring. As described above (FIGS. 3 and 4), when the memory access monitoring unit 230 detects an error, the memory access monitoring unit 230 transmits an error detection request to the error detection unit 240 as an error output. If S1140 is true, the process branches to S1141. If S1140 is false, the process branches to S1142.
(2) In S1141, the error detection unit 240 outputs details of the error in the copy leakage detection result 500.
(3) In S1142, the error detection unit 240 acquires the memory map record 211 from the memory map table 210 (FIG. 2).
(4) In S1143, the error detection unit 240 determines whether or not the source memory PUSH flag 213 is valid. If S1143 is true, the process branches to S1144. If S1143 is false, the process proceeds to S1145.
(5) In S1144, the error detection unit 240 outputs a copy non-execution error. A copy non-execution error indicates that a normal copy was not performed due to a copy description omission, an address specification error in the copy description, or the like.
(6) In S1145, the error detection unit 240 outputs details of the error to the copy leakage detection result 500.
(7) In S1146, the process branches depending on whether all the records included in the memory map table 210 have been checked. If S1146 is true, the process ends. If S1146 is false, the process returns to S1142.

  As described above, since the system simulator 10 includes the copy leak detection unit 200, it is possible to detect copy leaks that occur at various factors and timings. Further, according to the system simulator 10, it is possible to detect data copy omissions that occur under various conditions, and it is possible to provide means for assuring the accuracy of data copy processing in S / W quality evaluation.

Embodiment 2. FIG.
The system simulator 20 according to the second embodiment will be described with reference to FIGS. 14 and 15. The system simulator 10 according to the first embodiment includes a copy leakage detection unit 200, but the system simulator 20 according to the second embodiment includes a code coverage measurement unit 600 in addition to the copy leakage detection unit 200. In the following description, only parts different from the first embodiment will be described.

  FIG. 14 is a configuration diagram of the system simulator 20. The overall configuration of the system simulator 20 will be described with reference to FIG. The system simulator 20 further includes a code coverage measurement unit 600 with respect to the system simulator 10. The instruction set simulator 100, the copy omission detection unit 200, the memory model 300, the memory map 400, the copy omission detection result 500, and the like are the same as those in the first embodiment.

(Code coverage measurement unit 600)
The code coverage measurement unit 600 has a function of measuring the instruction coverage rate based on the execution instruction address output from the instruction set simulator 100. The measurement result by the code coverage measurement unit 600 is output to the code coverage measurement result 700. As long as the code coverage can be measured correctly, the implementation method of the code coverage measurement unit 600 for application to the present system is not particularly limited. The code coverage measurement result 700 is an output of detailed information regarding the code coverage measured by the code coverage measurement unit 600.

  FIG. 15 is a flowchart showing the overall operation of the system simulator 20. The operation of the system simulator 20 will be described with reference to FIG. It consists of two phases: code coverage measurement and copy leak detection.

<Phase 1>
(1) In S20, the instruction set simulator 100 executes S / W simulation.
(2) In S21, the code coverage measurement unit 600 measures code coverage.
(3) In S22, the code coverage measurement unit 600 determines whether the code coverage is 100% (an example of a threshold). When S22 is true (the coverage is 100%), the process proceeds to S25. The code coverage of 100% is an example, and it may be 90% or more or 80% or more. The code coverage value as the threshold may be set freely. If S22 is false (the coverage is not 100%), the process branches to S23.
(3) In S23, for example, the person in charge evaluates the code coverage measurement result 700. In S24, for example, the person in charge corrects the corresponding part. After correction, S20 is executed again. The above process is executed in S22 until it is determined that the coverage is 100%. If the coverage is determined to be 100%, the process proceeds to phase 2.

<Phase 2>
Phase 2 is the same as FIG. 2 of the first embodiment.
(1) In S25, the instruction set simulator 100 executes S / W simulation.
(2) In S26, copy leakage is detected.
(3) In S27, it is determined whether copy leakage is 0 (whether there is no copy leakage). If S27 is true (no copy omission), the process ends. If S27 is false (there is a copy omission), the process branches to S28.
(4) In S28, for example, the person in charge evaluates the copy omission detection result 500 and specifies the copy omission cause location.
(5) In S29, for example, the person in charge corrects the copy omission cause location. After the correction, S25 is executed again.
(6) The above process is executed until it is determined in S27 that copy leakage is zero.

Since the system simulator 20 according to the second embodiment includes the copy leakage detection unit and the code coverage measurement unit, the following two phases can be verified and S / W quality can be guaranteed.
<Phase 1>
The test pattern is corrected until the code coverage measurement result is 100%. In this phase, the validity of the test pattern can be guaranteed.
<Phase 2>
Until the copy omission becomes 0, the cause of the copy omission in the source code is corrected. In this phase, the accuracy of copy processing can be guaranteed.

Embodiment 3 FIG.
FIG. 16 is a diagram illustrating an example of a hardware configuration of the system simulators 10 and 20. The fourth embodiment will be described with reference to FIG. In the fourth embodiment, a hardware configuration of system simulators 10 and 20 which are computers will be described. Since the hardware configurations of the system simulators 10 and 20 are the same, the system simulator 10 will be described.

  In FIG. 16 showing hardware resources, a system simulator 10 that is a computer includes a CPU 950 (Central Processing Unit) that executes a program. The CPU 950 is connected to a ROM (Read Only Memory) 951, a RAM (Random Access Memory) 952, a display device 953, a keyboard 954, a mouse 955, a communication board 956, a CDD 957, and a magnetic disk device 960 via a bus 958. Control hardware devices. Instead of the magnetic disk device 960, a storage device such as an optical disk device or a flash memory may be used.

  The RAM 952 is an example of a volatile memory. Recording media such as the ROM 951, the CDD 957, and the magnetic disk device 960 are examples of nonvolatile memories. These are examples of a storage device or a storage unit, a storage unit, and a buffer. The communication board 956, the keyboard 954, and the like are examples of an input unit and an input device. The communication board 956, the display device 953, and the like are examples of an output unit and an output device. The communication board 956 is connected to the network.

  The magnetic disk device 960 stores an operating system 961 (OS), a program group 962, and a file group 963. The programs in the program group 962 are executed by the CPU 950 and the operating system 961.

  The program group 962 stores a program for executing the function described as “˜unit” in the description of the above embodiment. The program is read and executed by the CPU 950.

  In the description of the above embodiment, the file group 963 includes “determination result”, “calculation result”, “extraction result”, “generation result”, and “processing result”. The described information, data, signal values, variable values, parameters, and the like are stored as items of “˜file” and “˜database”. The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory. In addition, information, data, signal values, variable values, and parameters stored in a recording medium such as a disk or memory are read out to the main memory or cache memory by the CPU 950 via a read / write circuit, and extracted, searched, referenced, and compared. Used for CPU operations such as calculation, calculation, processing, output, printing, display, etc. Information, data, signal values, variable values, and parameters are temporarily stored in the main memory, cache memory, and buffer memory during CPU operations such as extraction, search, reference, comparison, operation, calculation, processing, output, printing, and display. Memorized.

  In the description of the embodiment described above, data and signal values are stored in the memory of the RAM 952, the compact disk of the CDD 957, the magnetic disk of the magnetic disk device 960, other optical disks, mini disks, DVDs (Digital Versatile Disk), and the like. Recorded on a recording medium. Data and signals are transmitted online via a bus 958, signal lines, cables, or other transmission media.

  In the above description of the embodiment, what has been described as “to part”, “instruction set simulator” and “memory model” may be “to means”, and “to step”, It may be “˜procedure” or “˜processing”. That is, what has been described as “˜unit” may be implemented by software alone, a combination of software and hardware, or a combination of firmware. Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD. The program is read by the CPU 950 and executed by the CPU 950. That is, the program causes the computer to function as the “˜unit” described above. Alternatively, the computer executes the procedure and method of “to part” described above.

  In the above embodiment, the system simulator 10 has been described, but it is obvious from the above description that this operation can also be grasped as a program. Moreover, it is clear from the above description that the operation of each “˜unit” of the system simulator 10 can be grasped as a method.

  10, 20 System simulator, 100 Instruction set simulator, 200 Copy omission detection unit, 210 Memory map table, 211 Memory map record, 212 Source memory R / W trigger setting, 213 Source memory PUSH flag, 214 Source memory POP flag, 215 Source Memory address, 216 Destination memory address, 217 Execution instruction address, 218 Memory data, 220 Table initialization unit, 230 Memory access monitoring unit, 240 Error detection unit, 300 Memory model, 400 Memory map, 500 Copy leak detection result, 600 code Coverage measurement unit, 700 code coverage measurement result.

Claims (7)

A software simulation unit that executes software to simulate the software;
A memory simulator for simulating the operation of a memory accessed by the software simulated by the software simulator;
The access to the memory simulation unit by the software is monitored, and the monitored access monitoring result is recorded. Based on the recorded access monitoring result, the data of the copy source memory that is a process of the software and serves as a copy source is recorded. A software test apparatus comprising: an error detection unit configured to detect whether or not a predefined error has occurred in data copy processing, which is processing for reading and writing to a copy destination memory. The software testing device is:
A memory map information storage unit in which memory map information including a set of an address of the copy source memory and an address of the copy destination memory is stored in advance in the data copy process;
The error detection unit
The software test apparatus according to claim 1, wherein the access monitoring result is recorded in the memory map information, and the error is detected based on the memory map information in which the access monitoring result is recorded. The memory map information stored in the memory map information storage unit is:
Including a first flag indicating which of the two states, valid and invalid,
The error detection unit
Monitoring whether or not an instruction to write data to the copy source memory is transmitted to the memory simulation unit by the software, and enabling the first flag based on detection of an instruction to write data to the copy source memory; The software test apparatus according to claim 2, wherein the error is detected based on a state of the first flag. The memory map information stored in the memory map information storage unit is:
Including a second flag indicating which of the two states, valid and invalid,
The error detection unit
The software monitors whether or not an instruction to write data to the copy destination memory is transmitted to the memory simulation unit, and validates the state of the second flag based on detection of an instruction to write data to the copy destination memory. The software test apparatus according to claim 3, wherein the error is detected based on states of the first flag and the second flag. The software test apparatus further includes:
The code coverage measurement part which measures the code coverage which shows an instruction coverage based on the execution instruction address output from the software simulation part which simulates the said software is provided in any one of Claims 1-4 characterized by the above-mentioned. The software testing device described. The error detection unit
When the code coverage measurement result by the code coverage measurement unit exceeds a preset threshold, it is detected whether the predefined error has occurred based on the access monitoring result. The software test apparatus according to claim 5. On the computer,
A process of executing software to simulate the software;
A process for simulating the operation of a memory accessed by the software to be simulated;
Monitors the memory access process by the software to be simulated, records the monitored access monitoring result, and reads the data of the copy source memory that is the process of the software and is the copy source based on the recorded access monitoring result A software test program for executing a process of detecting whether or not a predefined error has occurred in a data copy process that is a process of writing to a copy destination memory as a copy destination.

Images