JP4818241B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a memory cell array suitable for high density and high integration.

  A flash memory is well known as a nonvolatile semiconductor memory device that can electrically rewrite data and is suitable for high density and large capacity. In general, in a flash memory, a plurality of memory cells having a MOS transistor structure having a stacked gate in which a charge storage layer and a control gate are stacked are connected in an array. A word line signal is input to the control gates of these memory cells, and a bit line signal is input to the source or drain of the memory cells.

  FIG. 8A is a plan view showing the configuration of the memory cell array in the NOR type flash memory. FIG. 8B is a sectional view taken along line 8B-8B of the memory cell array shown in FIG.

  As shown in FIG. 8B, a charge storage layer 103 is formed on the p-type silicon semiconductor substrate 101 via a tunnel gate insulating film 102. A control gate 105 is formed on the charge storage layer 103 via an inter-gate insulating film 104. The memory cell has a stacked gate in which a charge storage layer 103 and a control gate 105 are stacked. This laminated gate is processed vertically in a self-aligning manner so that the side ends are aligned.

  One memory cell includes a source 106A and a drain 106B formed by an n-type diffusion layer. The source 106A and the drain 106B are formed on both sides of the stacked gate. One of the source 106A and the drain 106B is connected to the bit line 108 through the bit line contact 107, and the other is connected to the common source line 110 through the common source line contact 109.

  The common source line 110 and the source 106A are connected to each other through a contact, a structure directly connected by a buried metal line, and the source of the memory cell for each bit line using a diffusion layer. Such structures are widely used. Here, a case where connection is made to the common source line 110 via the contact 109 is shown.

  The bit line contact 107 has a so-called self-aligned contact structure in which the side edge is adjacent to the stacked gate, and a part of the contact 107 protrudes over the stacked gate at the connection portion with the bit line 108. Yes. The reason for this structure is to reduce the size of the memory cell array by eliminating the dimensional margin between the bit line contact 107 and the stacked gate. In order to obtain a self-aligned contact shape, the laminated gate is covered with a cap material 111, for example, a silicon nitride film, and the cap material 111 on the control gate 105 is formed thick. This prevents a short circuit between the control gate 105 and the conductive material embedded in the contact hole, for example, low resistance polysilicon or metal material. Reference numeral 112 denotes an interlayer insulating film made of a BPSG film or the like.

  The common source line contact 109 does not have a self-aligned contact structure, and has a margin between the stacked gate and the contact 109. This is because in the NOR type memory, a potential difference of about 10 V is generated between the control gate and the source during the erase operation, and it is difficult to make a self-aligned contact in order to maintain the breakdown voltage at this time.

  FIG. 9A is a plan view showing a configuration of a memory cell array in the NAND flash memory. FIG. 9B is a cross-sectional view taken along the line 9B-9B of the memory cell array shown in FIG.

  A plurality of memory cells share the source and drain and are connected in series to form a NAND string. Select transistors are arranged at both ends of the NAND string. Of the selection transistors arranged at both ends, the drain or source of one selection transistor is connected to the bit line 208 via the bit line contact 207, and the drain or source of the other selection transistor is connected to the common source line contact 209. To the common source line 210.

  FIG. 9B is a cross-sectional view taken along line 9B-9B of the memory cell array shown in FIG.

  The memory cell and the select transistor each have a stacked gate in which a charge storage layer 203 and a control gate 205 are stacked as in the NOR type memory cell. The charge storage layer 203 or the charge storage layer 203 of the selection transistor and the control gate 205 are connected to the gate signal line at a location different from the region shown in the drawing.

  The bit line contact 207 has a so-called self-aligned contact structure in which a side end portion thereof is adjacent to the stacked gate, and a part of the contact 207 extends over the stacked gate at a connection portion with the bit line 208. ing. This is because the size of the memory cell array is reduced by eliminating the dimension margin between the bit line contact 207 and the stacked gate. In order to obtain a self-aligned contact shape, the laminated gate is covered with a cap material 211, for example, a silicon nitride film, and the cap material 211 on the control gate 205 is formed thick. This prevents a short circuit between the control gate 205 and a conductive material embedded in the contact hole, such as low-resistance polysilicon or metal material.

  In the NAND type, similar to the bit line contact 207, the common source line contact 209 has a self-aligned contact structure. This is because in the NAND memory, only a potential difference of the power supply voltage (about 3 V) is generated between the common source line 210 and the control gate 205 of the selection transistor adjacent to the source line, and self-aligned contact is performed. This is because no problem occurs.

  The purpose of the self-aligned contact structure is to reduce the cell array length in the direction of the bit line 208 by eliminating a margin between the contact and the gate, and is very effective regardless of the NAND type or the NOR type. Further, it is considered that the effectiveness of the self-aligned contact structure is further enhanced as the gate length is reduced as the design rule is reduced. This is because the alignment variation during lithography is difficult to scale at the same rate as the reduction of the gate length, and the distance between the contact and the gate is not reduced to the same extent as the gate length.

  Here, the formation of the bit line contact 207 and the common source line contact 209 is normally performed as follows. First, the stacked gate is filled with an interlayer insulating film 213, for example, a silicon dioxide film with a BPSG film or the like having improved melt properties by mixing impurities such as boron and phosphorus, and planarization is performed by CMP or the like.

  Thereafter, contact holes are opened by dry etching. In this contact hole opening, if the etching selection ratio between the cap material 211 covering the control gate 205 and the interlayer insulating film 213 is not high, the cap material 211 on the control gate 205 is thinned or completely removed. The control gate 205 is exposed. In this case, when the contact material is embedded, a defect that the control gate 205 and the contact material are short-circuited occurs. For this reason, as the cap material 211, a silicon nitride-based film capable of obtaining a relatively high selection ratio with respect to the silicon dioxide-based interlayer insulating film 213 is widely used.

  However, when the silicon nitride film is formed so as to cover the gate of the transistor, a laminated insulating film structure composed mainly of a silicon dioxide film and a silicon nitride film is formed on the diffusion layer beside the gate. Therefore, hot electrons generated in the channel during the pentode operation of the transistor are captured at the interface of the laminated insulating film (interface between the gate insulating film and the silicon nitride film) to form an electron trap. When this electron trap occurs, it is generally known that the on-current of the transistor is modulated, the threshold voltage fluctuates, and the surface junction withstand voltage deteriorates.

  The flash memory has a memory cell array and a peripheral circuit. The peripheral circuit is formed outside the memory cell array region and is a circuit for generating and driving a control gate signal and a bit line signal. In this flash memory, in order to reduce the processing steps and to make the processing process common, peripheral transistors constituting the peripheral circuit often have a gate structure similar to that of the memory cell. For this reason, the peripheral transistor also has a shape in which the gate is covered with the cap material, and there is a high possibility of causing the above-described characteristic deterioration as in the case of the memory cell and the select transistor.

  In order to solve this problem, a structure in which a silicon dioxide film is sandwiched between a silicon nitride film and a gate has been proposed (see, for example, Patent Document 1). The object is to suppress the capture of hot electrons by increasing the distance between the diffusion layer and the silicon nitride film by sandwiching a silicon dioxide film between the thin gate insulating film and the silicon nitride film on the diffusion layer.

  However, it is very difficult to match the structure in which the silicon dioxide film is sandwiched between the silicon nitride film and the gate with the above-described self-aligned contact structure because of the following problems.

  10A, 10B, 11A, and 11B form a self-aligned contact in a structure in which a silicon dioxide-based film is sandwiched between a silicon nitride film and a stacked gate. It is sectional drawing of the process in the case.

  After forming the stacked gate, a silicon dioxide film 214 and a silicon nitride film 215 are sequentially deposited, for example, about 200 mm and 400 mm, respectively. Further, after the interlayer insulating film 213 is embedded and the interlayer insulating film 213 is melted by thermal annealing, the interlayer insulating film 213 is planarized by, for example, CMP as shown in FIG.

  Subsequently, a resist film 216 is applied on the structure shown in FIG. Thereafter, as shown in FIG. 10B, a resist film 216 corresponding to the contact portion is opened by lithography.

  Next, as shown in FIG. 11A, the interlayer insulating film 213 is etched by dry etching using the resist film 216 as a mask. At this time, the silicon nitride film 215 and the silicon nitride film of the cap material 211 are etched in accordance with the etching selection ratio between the interlayer insulating film 213 and the silicon nitride film. In general, etching concentrates at the gate end portion, and the film loss tends to increase. Therefore, the silicon dioxide film 214 is partially exposed, and in the worst case, the silicon dioxide film 214 may be etched back.

  Thereafter, an interface cleaning process such as an HF process is performed on the structure shown in FIG. 11A, and then a contact material 217, for example, a metal such as low-resistance polysilicon or tungsten (W) is embedded. ), The contact material 217 is planarized to complete the formation of the contact.

  In the manufacturing method described above, there is a high possibility that the contact material 217 (embedded electrode material) enters the portion where the silicon dioxide film 214 in the contact hole is etched back and recedes, and short-circuits with the control gate 205. Therefore, in the prior art, it is difficult to use a structure in which the silicon dioxide film 214 is sandwiched between the silicon nitride film 215 and the stacked gate for improving reliability in common with the self-aligned contact structure.

  Another problem when the self-aligned contact structure is used for the bit line contact and the common source line contact is a film residue on the side surface of the step portion of the element isolation insulating film.

  FIG. 12 is a cross-sectional view of the memory cell array shown in FIG. 11B cut along the line 12-12 in FIG. 9A.

  As shown in FIG. 12, on the semiconductor region sandwiched between the element isolation insulating films 217, the bit line contact 207 and the semiconductor region are electrically connected. On the side surfaces on both sides of the element isolation insulating film 217, the silicon dioxide film 214 and the silicon nitride film 215 covering the stacked gate remain in a spacer shape. This significantly reduces the contact area between the bit line contact 207 and the semiconductor region. This reduction in the contact area causes an effective reduction in the cell current. Therefore, the silicon nitride film 215 on the semiconductor region must be completely removed when the contact hole is opened.

  However, on the other hand, the silicon nitride film on the control gate 205 needs to be left for self-alignment contact. Due to this trade-off, the processing margin is significantly reduced.

  The problem becomes more prominent particularly when the element isolation insulating film is formed higher than the semiconductor region. When element isolation is performed using a self-aligned STI method (for example, see Patent Document 2), since the element isolation insulating film is formed higher than the semiconductor substrate, the influence is larger than the LOCOS element isolation structure. . The self-aligned STI method is a kind of shallow trench groove element isolation (STI) method, in which a trench groove is formed after depositing a charge storage layer.

  In addition, when low resistance polysilicon is used as a contact material embedded in the bit line contact, a barrier metal material such as Ti or TiN is not used as a buffer film, and the contact even when the impurity concentration of the diffusion layer is relatively low. There is a feature that an ohmic contact can be obtained without causing abnormal resistance or increased junction leakage.

  For this reason, although the contact resistance is higher than that of the metal buried contact, the contact using the same buried material as the bit line contact is connected to the peripheral circuit for the purpose of reducing the element by reducing the margin of the contact and the semiconductor region. It may be used in peripheral transistors that constitute. For example, a case where it is used for contact with a diffusion layer of a high voltage transistor is reported (for example, see Patent Document 3).

  In this case, it is necessary to open the contact hole of the high breakdown voltage transistor simultaneously with the contact hole opening of the bit line contact. However, the gate insulating film of the high voltage transistor is much thicker than the memory cell. For example, the thickness of the gate insulating film of the memory cell is about 100 mm, whereas the thickness of the gate insulating film of the high voltage transistor is 150 to 200 mm for the NOR flash memory and 300 to 400 mm for the NAND flash memory. It is. Therefore, in order to completely open the contact hole on the diffusion layer of the high breakdown voltage transistor, it is necessary to further etch the gate insulating film by about 150 to 400 mm after removing the silicon nitride film on the diffusion layer by etching.

  However, if the additional etching is performed, the cap material on the control gate is reduced in the bit line contact, and the element isolation insulating film partially applied to the contact portion is recessed due to the etching. That is, when the self-aligned contact structure is used for forming the bit line contact, there is a problem that it is very difficult to form the contact of the peripheral transistor in the same process as the bit line contact.

As described above, when the bit line contact has a self-aligned contact structure, there is a problem that the conventionally proposed technique cannot be used.
Japanese Patent Application No. 11-328149 Japanese Patent Application No. 6-071567 Japanese Patent Application No. 11-273466

  The present invention can reduce a residue of an insulating film covering a stacked gate remaining in a spacer shape on both side surfaces of an element isolation insulating film, and can increase a contact area between a contact and a semiconductor region An object is to provide a storage device.

According to one embodiment, a nonvolatile semiconductor memory device includes an element isolation region made of an element isolation insulating material embedded in a plurality of trench grooves formed in a semiconductor substrate, and a plurality of electrically isolated regions by the element isolation region. A first semiconductor region of a first conductivity type; second and third semiconductor regions of a second conductivity type formed in the first semiconductor region and spaced apart from each other; the second semiconductor region and the third semiconductor region; A stacked gate including a charge storage layer, a control gate, and a cap insulating film on the control gate, and the second and third semiconductors. An interlayer insulating film formed on the region; a bit line formed on the interlayer insulating film for inputting / outputting a signal; a source line formed on the interlayer insulating film for inputting / outputting a signal; Embedded in interlayer insulation film And bit line contacts for electrically connecting the said bit line and said second semiconductor region, embedded in the interlayer insulating film, a source line contact for electrically connecting the source line and said third semiconductor region A non-volatile semiconductor memory device including a peripheral circuit including a peripheral transistor for controlling signals of the bit line, the source line, and the control gate , wherein the charge storage layer is aligned with the trench groove. is disposed, the device isolation region is formed to a position higher than the semiconductor substrate surface, and the position of the element isolation region under the control gate is rather higher than the position of the element isolation region between the control gate, the peripheral The transistor has a gate electrode, a source diffusion layer, and a drain diffusion layer, and a contact material connected to any of the source diffusion layer and the drain diffusion layer is the above-described via. A gate insulating film adjacent to the contact material connected to one of the source diffusion layer and the drain diffusion layer is below the gate electrode. It is characterized by being thinner than the thickness of the gate insulating film .

  According to the present invention, the insulating film covering the stacked gate can reduce the residue remaining in a spacer shape on both side surfaces of the element isolation insulating film, and can increase the contact area between the contact and the semiconductor region. It is possible to provide a conductive semiconductor memory device.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
First, a NOR type nonvolatile semiconductor memory device will be described as a first embodiment of the present invention.

  FIG. 1A is a plan view showing a configuration of a memory cell array in the NOR type nonvolatile semiconductor memory device according to the first embodiment. FIG. 1B is a cross-sectional view taken along line 1B-1B of the memory cell array.

  A trench groove for element isolation is formed in the p-type silicon semiconductor substrate 11 or the p-type well. An insulating material for element isolation, for example, silicon dioxide material is embedded in the trench. A thin tunnel insulating film 12 through which a tunnel current can flow is formed on the entire surface of the channel region on the substrate thus separated.

  A charge storage layer 13 is formed on the tunnel insulating film 12. The charge storage layer 13 is formed so that the side end thereof is aligned with the element isolation region. A part of the charge storage layer 13 extends to the element isolation region, and the charge storage layer 13 is cut on the element isolation region to be separated for each memory cell. A control gate 15 is formed on the charge storage layer 13 via an inter-gate insulating film 14.

  On the control gate 15, for example, a silicon nitride film is formed as the gate cap film 16. The gate cap film 16 and the control gate 15 are vertically processed in a self-aligned manner so that the side edges are aligned with the charge storage layer 13, and the stacked gate structure is formed by the charge storage layer 13, the control gate 15 and the gate cap film 16. Is formed. The semiconductor substrate 11 on both sides of the stacked gate is formed with a source 17A and a drain 17B doped with impurities of the opposite conductivity type to the p-type semiconductor substrate (or p-type well) 11 in the channel portion. These source 17A and drain 17B are made of an n-type diffusion layer.

  A bit line contact 18 connected to the drain 17B is formed on the drain 17B. A common source line contact 19 connected to the source 17A is formed on the source 17A. The bit line contact 18 and the common source line contact 19 are made of a low resistance polysilicon, which is a conductive material, and a metal material. The upper portions of the contacts 18 and 19 are flattened, the bit line contact 18 is connected to the bit line 20 made of a metal electrode, and the common source line contact 19 is connected to the common source line 21.

  The stacked gate of the memory cell is covered with a gate barrier film 22 made of a silicon dioxide film. Further, the gate barrier film 22 is covered with a contact barrier film 23 made of a silicon nitride film. Here, the side surface of the stacked gate adjacent to the bit line contact 18 has a structure in which the gate barrier film 22 is partially removed and this side surface is directly covered with the contact barrier film 23. In other words, the gate barrier film 22 is formed on the side surface of the stacked gate adjacent to the common source line contact 19, and the contact barrier film 23 is further formed on the gate barrier film 22. On the other hand, the gate barrier film 22 is not formed on the side surface of the stacked gate adjacent to the bit line contact 18, and the contact barrier film 23 is directly formed on this side surface. Further, as shown in FIG. 1B, an interlayer insulating film 24, for example, a BPSG film or the like is formed on the semiconductor substrate 11.

  The common source line contact 19 is disposed at a predetermined distance from the contact barrier film 23 formed on the side surface of the stacked gate. The bit line contacts 18 are arranged without a distance so as to be in contact with the contact barrier film 23 formed on the side surface of the stacked gate. Further, the bit line contact 18 is formed so as to partially protrude from the contact barrier film 23 formed on the upper surfaces of the stacked gates on both sides. The bit line contact 18 is formed on the semiconductor substrate 11 so as to be buried between contact barrier films (silicon nitride films) 23 on adjacent stacked gates. The structure of the bit line contact 18 is a self-aligned contact structure in which a contact material is embedded in a contact hole formed by self-alignment processing using the contact barrier film 23 and the gate cap film 16 as a mask. Actually, the bit line contact 18 has a shape embedded in a contact hole between stacked gates in which a part of the gate cap film 16 and the contact barrier film 23 is etched.

  In the NOR type memory cell shown in this embodiment, on the bit line contact 18 side, the space between the bit line contact 18 and the stacked gate is eliminated as much as possible (self-aligned contact structure), thereby reducing the size of the memory cell array. ing. On the other hand, on the side of the common source line contact 19, the self-aligned contact structure is not used, and further, on the side surface of the stacked gate adjacent to the common source line contact 19 and the surface of the gate insulating film 12 in order to suppress the fluctuation of the electrical characteristics of the memory cell. A gate barrier film 22 of silicon dioxide film is formed.

  If the common source line contact 19 side is not provided with a self-aligned contact structure, a high voltage of 10 V or higher is applied between the source diffusion layer and the control gate during the erase operation, making it difficult to achieve a self-aligned contact structure. Because it is.

  On the common source line contact 19 side, the surface of the gate insulating film 12 is covered with the gate barrier film 22 because hot carriers (mainly holes) generated when a high voltage is applied between the source diffusion layer and the semiconductor substrate during the erase operation. This is because that is suppressed by being injected into the gate insulating film 12 and trapped between the gate insulating film 12 and the contact barrier film 23.

  In the above embodiment, the gate barrier film 22 needs to have a thickness of about 100 to 200 mm to prevent hot carriers from being tunnel-injected. The film thickness of the contact barrier film 23 needs to be, for example, about 200 to 400 mm in consideration of the etching selection ratio when forming the contact hole by self-alignment.

Further, although a silicon dioxide film is used as the gate barrier film 22, other oxide insulating films may be used. Other oxide insulating film, for example, (such as _Al 2 _{O 3)} aluminum oxide film, a metal oxide film such as tantalum oxide film (such as _Ta 3 _{O 5).} Further, although the silicon nitride film is used as the contact barrier film 23, other nitride insulating films may be used.

  According to the NOR type nonvolatile semiconductor memory device of the first embodiment having such a structure, the stacked gate adjacent to the bit line contact 18 is formed when the contact hole of the bit line contact having the self-aligned contact structure is formed. Since the gate barrier film (silicon dioxide film) 22 is not formed on the side surface, the contact material enters the vacant region where the gate barrier film 22 is etched, and the contact material and the control gate are short-circuited. Absent.

  Furthermore, since the gate barrier film (silicon dioxide film) 22 is formed between the gate insulating film 12 and the contact barrier film 23 adjacent to the source diffusion layer 17A, the gate insulating film 12, the contact barrier film 23, During which the hot carriers can be prevented from being captured.

[Second Embodiment]
Next, a NAND type nonvolatile semiconductor memory device will be described as a second embodiment of the present invention.

  FIG. 2A is a plan view showing the configuration of the memory cell array in the NAND-type nonvolatile semiconductor memory device according to the second embodiment. FIG. 2B is a sectional view taken along line 2B-2B of the memory cell array.

  A trench groove for element isolation is formed in the p-type silicon semiconductor substrate 31 or the p-type well. An insulating material for element isolation, for example, silicon dioxide material is embedded in the trench. A thin tunnel insulating film 32 through which a tunnel current can flow is formed on the entire surface of the channel region on the substrate thus isolated.

  On the tunnel insulating film 32, a charge storage layer 33 is formed. The charge storage layer 33 is formed so that the side end thereof is aligned with the element isolation region. The charge storage layer 33 partially extends to the element isolation region, and is cut on the element isolation region to be separated for each memory cell. A control gate 35 is formed on the charge storage layer 33 via an inter-gate insulating film 34.

  On the control gate 35, for example, a silicon nitride film is formed as the gate cap film 36. The gate cap film 36 and the control gate 35 are vertically processed in a self-aligned manner so that the side edges thereof are aligned with the charge storage layer 33, and a stacked gate structure is formed by the charge storage layer 33, the control gate 35 and the gate cap film 36. Is formed. On the semiconductor substrate 31 on both sides of the stacked gate, an n-type diffusion layer 37 doped with an impurity having a polarity opposite to that of the p-type semiconductor substrate (or p-type well) 31 in the channel portion is formed. These n-type diffusion layers 37 serve as a source or a drain.

  The plurality of stacked gates are arranged in series so as to share the n-type diffusion layer. A bit line contact 38 and a common source line contact 39 are formed on the n-type diffusion layer 37 at the end of these stacked gates connected in series. The stacked gate adjacent to the contacts 38 and 39 operates as a selection transistor. In the selection transistor, a signal is directly applied to the charge storage layer 33 after the charge storage layer 33 and the control gate 35 are short-circuited. A plurality of stacked gates sandwiched between select transistors operate as memory cells.

  The bit line contact 38 and the common source line contact 39 are made of a low resistance polysilicon which is a conductive material and a metal material. The upper portions of these contacts 38 and 39 are flattened, the bit line contact 38 is connected to a bit line 40 made of a metal electrode, and the common source line contact 39 is connected to a common source line 41, respectively.

  The stacked gate of the memory cell and the stacked gate of the select transistor are covered with a gate barrier film 42 made of a silicon dioxide film. Further, the gate barrier film 42 is covered with a contact barrier film 43 made of a silicon nitride film. Here, in the stacked gate of the selection transistor adjacent to the bit line contact 38, the gate barrier film 42 is partially removed on the side surface adjacent to the bit line contact 38, and this side surface is directly formed by the contact barrier film 43. It has a covered structure. Further, in the stacked gate of the selection transistor adjacent to the common source line contact 39, the gate barrier film 42 is partially removed from the side surface adjacent to the common source line contact 39, and this side surface directly contacts the contact barrier film 43. The structure is covered with. In other words, the gate barrier film 42 is formed on the side surface of the select transistor on the side close to the memory cell, and the contact barrier film 43 is formed on the gate barrier film 42. However, the gate barrier film 42 is not formed on the side surface close to the bit line contact 38 or the common source line contact 39 of the stacked gate of the selection transistor, and the contact barrier film 43 is directly formed on this side surface. Has been. On the semiconductor substrate 31, as shown in FIG. 2B, an interlayer insulating film 44, for example, a BPSG film is formed.

  The bit line contact 38 is arranged without a distance so as to be in contact with the contact barrier film 43 formed on the side surface of the select transistor. Further, the bit line contact 38 is formed to partially protrude on the stacked gates on both sides. The bit line contact 38 is formed on the semiconductor substrate 31 so as to be buried between contact barrier films (silicon nitride films) 43 on the stacked gates of adjacent select transistors. The structure of the bit line contact 38 is a self-aligned contact structure in which a contact material is embedded in a contact hole formed by self-alignment processing using the contact barrier film 43 and the gate cap film 36 as a mask. As shown in FIG. 2B, the bit line contact 38 has a shape embedded in a contact hole between stacked gates in which a part of the gate cap film 36 and the contact barrier film 43 is etched.

  Similarly, the common source line contact 39 is arranged without a distance so as to be in contact with the contact barrier film 43 formed on the side surface of the stack gate of the selection transistor. Further, the common source line contact 39 is formed to partially extend on the stacked gates on both sides. The common source line contact 39 is formed on the semiconductor substrate 31 so as to be buried between contact barrier films (silicon nitride films) 43 on the stacked gates of adjacent selection transistors. The common source line contact 39 has a self-aligned contact structure in which a contact material is embedded in a contact hole formed by self-alignment processing using the contact barrier film 43 and the gate cap film 36 as a mask. As shown in FIG. 2B, the common source line contact 39 has a shape in which a part of the gate cap film 36 and the contact barrier film 43 is embedded in a contact hole between stacked gates.

  In the NAND type memory cell shown in this embodiment, the stacked gate of the memory cell is covered with a gate barrier film 42 of a silicon dioxide film, and the gate barrier film 42 is further covered with a contact barrier film 43 of a silicon nitride film. . On the other hand, the stacked gate of the selection transistor has a structure in which the side surface adjacent to the contact 38 or 39 is not covered with the gate barrier film 42 but directly covered with the contact barrier film 43.

  The reason why the gate barrier film 42 is formed on the surface of the gate insulating film 32 between the stacked gates by covering the stacked gate of the memory cell with the gate barrier film 42 of the silicon dioxide film is the case of the NOR type memory cell of the first embodiment. Similarly to the above, hot carriers (mainly holes) are injected into the gate insulating film 32 and are prevented from being trapped between the gate insulating film 32 and the contact barrier film 43.

  In the embodiment, the film thickness of the gate barrier film 42 needs to be about 100 to 200 mm in order to prevent hot carriers from being tunnel-injected. The film thickness of the contact barrier film 43 needs to be about 200 to 400 mm, for example, in consideration of the etching selection ratio when the contact hole is formed by self-alignment.

Further, although the silicon dioxide film is used as the gate barrier film 42, other oxide insulating films may be used. Other oxide insulating film, for example, (such as _Al 2 _{O 3)} aluminum oxide film, a metal oxide film such as tantalum oxide film (such as _Ta 3 _{O 5).} Further, although the silicon nitride film is used as the contact barrier film 43, other nitride insulating films may be used.

  According to the NAND-type nonvolatile semiconductor memory device of the second embodiment having such a structure, when the contact hole of the bit line contact 38 (or common source line contact 39) having the self-aligned contact structure is formed, Since the gate barrier film (silicon dioxide film) 42 is not formed on the side surface of the stacked gate adjacent to the line contact (or the common source line contact), the contact material is formed in the area where the gate barrier film 42 is etched. The contact material and the control gate are not short-circuited.

  Further, a gate barrier film (silicon dioxide film) 42 is formed between the gate insulating film 32 on both sides of the stacked gate of the memory cell (on the n-type diffusion layer 37 serving as a source or drain) and the contact barrier film 43. Therefore, the capture of hot carriers between the gate insulating film 32 and the contact barrier film 43 can be suppressed. As a result, it is possible to prevent fluctuations in the electrical characteristics of the memory cell due to the influence of hot carrier trapping.

  Next, a method for manufacturing the NAND memory cell will be described.

  3 (a), 3 (b), 4 (a), and 4 (b) are cross-sectional views of main steps showing a method for manufacturing the NAND type memory cell.

  As shown in FIG. 3A, a gate cap film 36 made of a silicon nitride film is formed on the stacked structure having the charge storage layer 33 and the control gate 35. A stacked gate is formed by vertical processing in a self-aligning manner so that the side ends of the charge storage layer 33, the control gate 35, and the gate cap film 36 are aligned.

  After the stacked gate is formed, a silicon dioxide film is deposited as the gate barrier film 42. Thereafter, the gate barrier film 42 on the stacked gate side surface of the select transistor adjacent to the bit line contact 38 or the common source line contact 39 is peeled off by lithography and etching.

  Subsequently, as shown in FIG. 3B, a silicon nitride film to be a contact barrier film 43 when the contact hole is opened is deposited. Further, an interlayer insulating film (for example, a BPSG film) 44 is formed on the contact barrier film 43. After the interlayer insulating film 44 is melted by thermal annealing, the interlayer insulating film 44 is planarized by, for example, CMP.

  Next, as shown in FIG. 4A, contact holes are opened by lithography and dry etching. At this time, a part of the gate cap film (silicon nitride film) 36 is also etched corresponding to the etching selection ratio between the interlayer insulating film (BPSG film) 44 and the contact barrier film (silicon nitride film) 43.

  Subsequently, as shown in FIG. 4B, after performing interface cleaning processing such as HF processing, a contact material, for example, a metal such as low-resistance polysilicon or tungsten (W) is embedded and planarized to form a bit line contact. 38 and a common source line contact 39 are formed.

  In such a NAND memory cell manufacturing method, the gate barrier film 42 on the side face of the selection transistor stacked gate in contact with the bit line contact 38 or the common source line contact 39 is peeled off in advance, so that the gate barrier is opened when the contact hole is opened. The film 42 is exposed and the gate barrier film 42 is locally etched back. Thereafter, when the contact material is buried, the contact material and the control gate 35 are prevented from being short-circuited.

[Third Embodiment]
Next, a NAND type nonvolatile semiconductor memory device will be described as a third embodiment of the present invention. In the second embodiment, all of the gate barrier film 42 covering the stacked gate side surface of the select transistor adjacent to the contact 38 or 39 is peeled off. However, in this third embodiment, the dry etching conditions are optimized. Thus, only the gate barrier film 42 covering the side surface of the gate cap film 36 is removed.

  FIG. 5 is a cross-sectional view of a memory cell array in the NAND-type nonvolatile semiconductor memory device according to the third embodiment.

  As shown in FIG. 5, the gate barrier film 42A covering the side surface of the stacked gate adjacent to the contact 38 or 39 covers the entire side surface of the charge storage layer 33 and the side surface of the inter-gate insulating film 34 and only a part of the side surface of the control gate 35. Covering. Other structures are the same as those in the second embodiment.

  In order to form the structure as shown in FIG. 5, when the contact hole is opened, the dry etching conditions are optimized, and the gate barrier film covering the side surface of the stacked gate is retracted to the side surface of the control gate 35.

  Also in the third embodiment having such a structure, a gate barrier film (silicon dioxide film) 42A is formed on the side surface of the gate cap film 36 adjacent to the bit line contact 38 (or the common source line contact 39). Therefore, the gate barrier film 42A is not exposed when the contact hole is formed. Therefore, when the contact hole is formed, the gate barrier film 42A is not exposed, and the contact material does not enter the vacant region where the gate barrier film 42A is etched and the contact material and the control gate are not short-circuited.

  Further, a gate barrier film (silicon dioxide film) 42A is provided between the gate insulating film 32 on both sides of the stacked gates of the selection transistor and the memory cell (on the n-type diffusion layer 37 forming the source or drain) and the contact barrier film 43. Therefore, the trapping of hot carriers between the gate insulating film 32 and the contact barrier film 43 can be suppressed. As a result, it is possible to prevent fluctuations in the electrical characteristics of the memory cell due to the influence of hot carrier trapping.

Note that although a silicon dioxide film is used as the gate barrier film 42A, other oxide insulating films may be used. Other oxide insulating film, for example, (such as _Al 2 _{O 3)} aluminum oxide film, a metal oxide film such as tantalum oxide film (such as _Ta 3 _{O 5).}

[Fourth Embodiment]
Next, a NAND type nonvolatile semiconductor memory device will be described as a fourth embodiment of the present invention. In the third embodiment, only the gate barrier film 42 covering the side surface of the gate cap film 36 of the selection transistor adjacent to the contact 38 or 39 is removed, but in the fourth embodiment, the selection transistor and The gate barrier film 42 covering the side surfaces of the gate cap film 36 of both memory cells is removed.

  FIG. 6 is a cross-sectional view of a memory cell array in the NAND-type nonvolatile semiconductor memory device according to the fourth embodiment.

  As shown in FIG. 6, the gate barrier film 42A covering the side surface of the stacked gate adjacent to the contact 38 or 39 covers the entire side surface of the charge storage layer 33 and the side surface of the inter-gate insulating film 34 and only a part of the side surface of the control gate 35. Covering. Further, the gate barrier film 42A that covers the side surface of the stacked gate of the memory cell also covers the entire side surface of the charge storage layer 33 and the side surface of the inter-gate insulating film 34 and only a part of the side surface of the control gate 35. Other structures are the same as those in the second embodiment.

  In order to form the structure as shown in FIG. 6, when the contact hole is opened, the dry etching conditions are optimized without using lithography, and the stacked gate of the memory cell is formed in the same manner as the side face of the gate cap film 36 of the select transistor. The gate barrier film that covers the side surface of the gate cap film 36 may be etched at the same time and may be retracted to the side surface of the control gate 35.

  Also in the fourth embodiment having such a structure, a gate barrier film (silicon dioxide film) 42A is formed on the side surface of the gate cap film 36 adjacent to the bit line contact 38 (or the common source line contact 39). Therefore, the gate barrier film 42A is not exposed when the contact hole is formed. Therefore, when the contact hole is formed, the gate barrier film 42A is not exposed, and the contact material does not enter the region that is etched and opened, and the contact material and the control gate 35 are not short-circuited.

  Further, a gate barrier film (silicon dioxide film) 42A is provided between the gate insulating film 32 on both sides of the stacked gates of the selection transistor and the memory cell (on the n-type diffusion layer 37 forming the source or drain) and the contact barrier film 43. Therefore, the trapping of hot carriers between the gate insulating film 32 and the contact barrier film 43 can be suppressed. As a result, it is possible to prevent fluctuations in the electrical characteristics of the memory cell due to the influence of hot carrier trapping.

Note that although a silicon dioxide film is used as the gate barrier film 42A, other oxide insulating films may be used. Other oxide insulating film, for example, (such as _Al 2 _{O 3)} aluminum oxide film, a metal oxide film such as tantalum oxide film (such as _Ta 3 _{O 5).}

[Fifth Embodiment]
Next, a NAND type nonvolatile semiconductor memory device will be described as a fifth embodiment of the invention. In the fifth embodiment, common reference numerals are assigned to parts common to the second embodiment.

  FIG. 7A is a cross-sectional view taken along the word line of the memory cell array in the NAND-type nonvolatile semiconductor memory device according to the fifth embodiment. FIG. 7B is a cross-sectional view in the word line direction of the bit line contact portion of the memory cell array. FIG. 7C is a cross-sectional view of a peripheral transistor constituting a peripheral circuit of the NAND nonvolatile semiconductor memory device. This peripheral transistor is, for example, a high breakdown voltage transistor whose gate insulating film is much thicker than the memory cell.

  A self-aligned STI structure in which the side end portion of the charge storage layer is aligned with a trench groove forming an element isolation region is effective as an element isolation structure in a slash memory. However, as shown in FIG. 12, since the element isolation region is formed higher than the semiconductor substrate, in the region between adjacent control gates, the gate barrier film 214 and the contact barrier film 215 are element-isolated in a spacer shape. There was a problem of remaining on the side surface of the region 217.

  In this embodiment, as shown in FIG. 7B, the film thickness of the element isolation insulating film 51 between adjacent control gates is made smaller than the film thickness of the element isolation insulating film 52 below the control gate 35. The residue of the gate barrier film 42 and the contact barrier film 43 is eliminated. As a result, in the bit line contact formation portion, the exposed area of the semiconductor substrate can be increased and the contact resistance can be reduced.

  Further, among the peripheral transistors constituting the peripheral circuit, the film thickness of the gate insulating film of the high voltage transistor is generally much larger than that of the memory cell. For this reason, when forming the contact hole, it is necessary to remove the thick gate insulating film of the peripheral transistor after etching the contact barrier film 43 and the gate barrier film 42, and simultaneously with the bit line contact having the self-aligned contact structure, It has been difficult to form transistor contacts.

  On the other hand, in this embodiment, as shown in FIG. 7C, the gate insulating film 54 on the diffusion layer where the contact 53 of the high voltage transistor is formed in advance is thinned. As a result, the contact hole for the high voltage transistor can be formed simultaneously with the formation of the contact hole for the bit line contact.

  Actually, a method of forming this structure will be described below.

  First, the stacked gate including the gate cap film is vertically processed, and then the element isolation insulating film and the gate insulating film between the gates are etched using the gate cap film as a mask. At this time, it is important to perform etching with a high selectivity on the silicon nitride film which is the gate cap film and the silicon substrate. The etching amount must be such that the gate insulating film of the high voltage transistor can be removed. Furthermore, the height of the element isolation insulating film needs to be higher than the upper part of the trench groove, that is, the semiconductor substrate surface, and lower than the upper part of the charge storage layer. By this etching, the film thickness of the element isolation insulating film between the gates becomes thinner than the film thickness of the element isolation insulating film under the gate.

  When the gate barrier film 42 and the contact barrier film 43 are formed after the surface treatment of the gate side surface by thermal oxidation or the like, since the film thickness of the element isolation insulating film is reduced in advance, the side surface of the element isolation insulating film 51 The exposure height is reduced, and the occurrence of a spacer-like residue when the contact hole is opened can be suppressed.

  The present invention is not limited to the above-described embodiment, and the thickness of the gate insulating film, the electrode material, and the like can be appropriately selected.

  Preferred embodiments of the invention are described below.

  1. The conductive material constituting the charge storage layer is, for example, a polycrystalline silicon material or an amorphous silicon material having high electrical conductivity due to impurity doping.

  2. The charge storage layer is formed on a thermal oxide film of, for example, about 100 mm formed on the semiconductor substrate.

  3. The control gate is, for example, a single layer of a silicon material such as a polycrystalline silicon material or an amorphous silicon material having high electrical conductivity due to impurity doping, a refractory metal material such as tungsten (W), or a silicide such as tungsten silicide (WSi). A low-resistance metal material such as a salicide formed by depositing a metal such as titanium (Ti) on the silicon material and chemically reacting with silicon by thermal annealing, or aluminum (Al) It is.

  4). The control gate is formed on a silicon dioxide film having a thickness of, for example, about 100 to 200 mm or a laminated film of silicon dioxide and silicon nitride film formed on the charge storage layer.

  5. The element isolation insulating film is, for example, a silicon dioxide material excellent in high aspect embedding characteristics, or PSG or BPSG containing impurities such as phosphorus (P) or boron (B), or a laminated structure of the above materials.

  The present invention relates to a side surface of a stacked gate in which at least a bit line contact is adjacent among a memory cell and a select transistor covered with a first insulating film (eg, silicon dioxide film) and a second insulating film (eg, silicon nitride film). The first insulating film is removed from the gate electrode, and the element isolation insulating film between the control gates is made thinner than the element isolation insulating film under the control gate to make the side wall height of the element isolation insulating film in the bit line contact portion And lowering the thickness of the gate insulating film in the contact portion connected to the source diffusion layer or drain diffusion layer of the high voltage transistor than the thickness of the gate insulating film under the gate electrode of the transistor As a result, the processing margin when the bit line contact has a self-aligned contact structure can be increased, and high density and high reliability can be achieved. Nonvolatile semiconductor memory device can be realized.

Although the silicon dioxide film is used as the first insulating film, other oxide insulating films may be used. Other oxide insulating film, for example, (such as _Al 2 _{O 3)} aluminum oxide film, a metal oxide film such as tantalum oxide film (such as _Ta 3 _{O 5).} Further, although the silicon nitride film is used as the second insulating film, other nitride-based insulating films may be used.

(A) is a top view which shows the structure of the memory cell array in the NOR type non-volatile semiconductor memory device of 1st Embodiment, (b) is sectional drawing along the 1B-1B line | wire of the said memory cell array. (A) is a top view which shows the structure of the memory cell array in the NAND type non-volatile semiconductor memory device of 2nd Embodiment, (b) is sectional drawing along the 2B-2B line | wire of the said memory cell array. It is sectional drawing of the main 1st processes which show the manufacturing method of the NAND type memory cell of the said 2nd Embodiment. It is sectional drawing of the 2nd main process which shows the manufacturing method of the NAND type memory cell of the said 2nd Embodiment. It is sectional drawing of the memory cell array in the NAND type non-volatile semiconductor memory device of 3rd Embodiment. It is sectional drawing of the memory cell array in the NAND-type non-volatile semiconductor memory device of 4th Embodiment. It is sectional drawing of the memory cell array in the NAND type nonvolatile semiconductor memory device of 5th Embodiment. (A) is a top view which shows the structure of the memory cell array in the conventional NOR type flash memory, (b) is sectional drawing along the 8B-8B line | wire of the said memory cell array. (A) is a top view which shows the structure of the memory cell array in the conventional NAND type flash memory, (b) is sectional drawing along the 9B-9B line | wire of the said memory cell array. It is sectional drawing of the 1st process in the case of forming a self-aligned contact in the structure which sandwiches a silicon dioxide film between a silicon nitride film and a lamination gate. It is sectional drawing of the 2nd process in the case of forming a self-alignment contact in the structure which pinches | interposes a silicon dioxide film between a silicon nitride film and a laminated gate. FIG. 12 is a cross-sectional view of the memory cell array shown in FIG. 11B taken along line 12-12 in FIG. 9A.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... p-type silicon semiconductor substrate (or p-type well), 12 ... Tunnel insulating film, 13 ... Charge storage layer, 14 ... Inter-gate insulating film, 15 ... Control gate, 16 ... Gate cap film, 17A ... Source, 17B ... Drain, 18 ... bit line contact, 19 ... common source line contact, 20 ... bit line, 21 ... common source line, 22 ... gate barrier film, 23 ... contact barrier film, 24 ... interlayer insulating film, 31 ... p-type silicon semiconductor Substrate (or p-type well), 32 ... tunnel insulating film, 33 ... charge storage layer, 34 ... inter-gate insulating film, 35 ... control gate, 36 ... gate cap film, 37 ... n-type diffusion layer, 38 ... bit line contact 39 ... Common source line contact, 40 ... Bit line, 41 ... Common source line, 42 ... Gate barrier film, 43 ... Contact barrier film, 44 Interlayer insulating film

Claims (3)

An element isolation region made of an element isolation insulating material embedded in a plurality of trench grooves formed in a semiconductor substrate;
A plurality of first-conductivity-type first semiconductor regions electrically isolated by the element isolation region;
Second and third semiconductor regions of the second conductivity type formed in the first semiconductor region and spaced apart from each other;
A charge storage layer, a control gate, and a cap insulating film on the control gate are formed on the first semiconductor region between the second semiconductor region and the third semiconductor region via a gate insulating film. Stacked gates;
An interlayer insulating film formed on the second and third semiconductor regions;
A bit line formed on the interlayer insulating film for inputting and outputting signals;
A source line formed on the interlayer insulating film for inputting and outputting signals;
A bit line contact embedded in the interlayer insulating film and electrically connecting the second semiconductor region and the bit line;
A source line contact embedded in the interlayer insulating film and electrically connecting the third semiconductor region and the source line ;
A peripheral circuit including a peripheral transistor for controlling the signal of the bit line, the source line and the control gate;
A nonvolatile semiconductor memory device comprising:
The charge storage layer is arranged so that the trench groove and the side end face are aligned, the element isolation region is formed to a position higher than the surface of the semiconductor substrate, and the position of the element isolation region under the control gate is controlled high from the position of the element isolation region between the gate rather,
The peripheral transistor has a gate electrode, a source diffusion layer, and a drain diffusion layer, and a contact material connected to either the source diffusion layer or the drain diffusion layer is the same transistor as the contact material that forms the bit line contact or the source line contact Because
A nonvolatile semiconductor memory characterized in that a gate insulating film adjacent to a contact material connected to either the source diffusion layer or the drain diffusion layer is thinner than a gate insulating film under the gate electrode. apparatus.   The nonvolatile semiconductor memory device according to claim 1, wherein a position of an element isolation region between the control gates is higher than a semiconductor substrate surface and lower than an upper surface of the charge storage layer. The peripheral transistor is a high breakdown voltage transistor that drives a high voltage for writing and erasing applied to the memory cell during a charge transfer operation of the memory cell having the stacked gate, and a film thickness of a gate insulating film under the gate electrode the nonvolatile semiconductor memory device according to claim 1 or 2, wherein the greater thickness than the gate insulating film under the charge accumulation layer of the memory cell.

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