JP5657612B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a trench portion in a semiconductor substrate between bit lines and between word lines and a manufacturing method thereof.

  In recent years, nonvolatile memories, which are semiconductor devices capable of rewriting data, have been widely used. In the technical field of such a nonvolatile memory, technical development for the purpose of miniaturization of memory cells is being promoted in order to increase the storage capacity. Non-volatile memories include flash memories having a structure such as a MONOS (Metal Oxide Nitride Oxide Silicon) type or a SONOS (Silicon Oxide Nitride Oxide Silicon) type in which charges are accumulated in an ONO (Oxide / Nitride / Oxide) film. Further, among them, there is a flash memory in which a bit line is embedded in a semiconductor substrate and serves as a source region and a drain region for the purpose of miniaturization of a memory cell.

  The prior art (prior art 1) will be described with reference to FIGS. FIG. 1 is a top view of a flash memory according to Prior Art 1. FIG. 2 is a cross-sectional view thereof, FIG. 2 (a) is a cross-sectional view taken along line AA of FIG. 1, and FIG. 2 (b) is a cross-sectional view taken along line BB of FIG. Referring to FIG. 1, bit line 14 extends in the vertical direction of FIG. 1, and word line 15 extends in the width direction of the bit line.

  Referring to FIG. 2, a bit line 14 serving as a source region and a drain region is embedded in a semiconductor substrate 10. An ONO film 12 is formed on the semiconductor substrate 10. A word line 15 that also serves as a gate electrode is formed on the ONO film 12.

  The semiconductor substrate 10 under the word line 15 (gate electrode) between the bit lines 14 (between the source region and the drain region) serves as a channel. By accumulating charges in the ONO film 12 on the channel, it functions as a nonvolatile memory.

  Patent Documents 1 and 2 disclose a technique in which a thermal silicon oxide film is formed on a bit line in a semiconductor device in which a trench portion is provided in the semiconductor substrate 10 between the bit lines 14 and between the word lines 15. Has been. When the word line is formed, a trench recess is provided in the semiconductor substrate using the thermally oxidized silicon film on the bit line as a mask.

  In Patent Document 1, the gate electrode structure on the channel is one layer of word lines (conventional technique 2). On the other hand, in Patent Document 2, the gate electrode structure on the channel is a floating gate, a silicon oxide film, and a control gate (word line) (prior art 3).

JP 2004-111874 A JP 05-198778 A

  FIG. 3 is a diagram for explaining a problem in the prior art 1. 3A is a top view of the flash memory according to the related art 1, and FIG. 3B is a cross-sectional view taken along the line BB. Referring to FIG. 3A, in the prior art 1, in the charge writing to the ONO film 12, a high voltage is applied between the bit lines 14, and high energy is generated in the channel 50 under the word line 15 (gate electrode). The trapped charge is trapped in the trap layer in the ONO film 12.

However, the current in the semiconductor substrate 10 below the word line 15 also flows on both sides of the channel 50 below the word line 15 as indicated by the broken line arrow in FIG. In FIG. 3B, the channel expands on both sides of the channel 50 below the word line 15 (reference numeral 52). For this reason, as shown in FIG. 3A, charges are trapped not only in the ONO film 12 below the word line 15 (reference numeral 54) but also in the ONO film 12 on both sides of the word line 15. (Reference numeral 54a)
As described above, when charges are trapped in the ONO film 12 on both sides of the word line 15, the following problems occur. First, the charge cannot be erased during the erase operation. Furthermore, charges are trapped in the ONO film 12 below the adjacent word line 15. These also cause a problem that the memory cell malfunctions. For this reason, it is difficult to reduce the interval between the word lines 15 and make the memory cells finer.

  Therefore, it is conceivable to provide a trench portion in the semiconductor substrate 10 between the bit lines 14 and between the word lines 15 as in the conventional techniques 2 and 3. However, in the structure (LOCOS structure) in which the thermal silicon oxide film is provided on the bit line as in the conventional techniques 2 and 3, a bird beak is generated and it is difficult to miniaturize. Further, in the prior art 3, since the oxide film layer is provided between the control gate and the flow taking gate, the etching for forming the floating gate, the control gate and the trench portion becomes complicated. This is because the oxide film on the bit line is used as a mask in the etching for forming the trench portion.

  An object of the present invention is to provide a semiconductor device capable of miniaturizing a memory cell by performing element isolation between word lines and a manufacturing method thereof.

  The present invention is provided on a bit line formed in a semiconductor substrate, an insulating film line continuously provided on the bit line in a longitudinal direction of the bit line, and the semiconductor substrate between the bit lines. A gate electrode provided on and in contact with the gate electrode and extending in a width direction of the bit line, and a trench portion formed in the semiconductor substrate between the bit lines and between the word lines. , A semiconductor device comprising: According to the present invention, by providing the trench portion, no current flows through the semiconductor substrate on both sides of the word line. As a result, charges are not trapped in the ONO films on both sides of the word line. Therefore, it is possible to provide a semiconductor device in which a word line interval can be narrowed and a memory cell can be miniaturized.

  The present invention can be a semiconductor device in which the side surface in the width direction of the insulating film line is substantially perpendicular to the surface of the semiconductor substrate. According to the present invention, memory cells can be miniaturized without occurrence of bird's beaks.

  In the present invention, the insulating film line may be a semiconductor device including a silicon oxide film. According to the present invention, when the trench portion is formed in the semiconductor substrate, the etching selectivity with respect to the silicon semiconductor substrate can be increased.

  The present invention can be a semiconductor device including an insulating film layer provided on the trench portion. According to the present invention, elements can be reliably separated between channels.

  The present invention includes a barrier layer provided between the trench portion and the insulating film layer, the insulating film layer including a silicon nitride film, and the barrier layer including a silicon oxide film as a semiconductor device. it can. According to the present invention, it is possible to prevent the silicon nitride film from being peeled off due to stress. Further, it is possible to prevent hydrogen in the silicon nitride film from diffusing into the ONO film and deteriorating characteristics.

  The present invention can be a semiconductor device in which a channel cut region having a conductivity type opposite to the bit line is formed in the semiconductor substrate of the trench portion. According to the present invention, element isolation between channels can be more reliably performed.

  The present invention can be a semiconductor device including a side wall formed on a side surface of the trench portion. According to the present invention, since the distance between the channel cut region and the channel can be secured, it is possible to prevent the channel from becoming narrow due to the depletion layer from the P-type region.

  The present invention can be a semiconductor device including an ONO film provided between the semiconductor substrate and the gate electrode. According to the present invention, in a flash memory having an ONO film, trapping of charges in the ONO film on both sides of the word line can be suppressed.

  The present invention includes a step of forming a bit line in a semiconductor substrate, a step of forming an insulating film line continuously formed in the longitudinal direction of the bit line on the bit line, and the semiconductor between the bit lines. Forming a gate electrode on the substrate; forming a word line in contact with the gate electrode and extending in a width direction of the bit line; and between the bit lines and between the word lines Forming a trench portion in the semiconductor substrate, and the step of forming the trench portion includes a step of etching the semiconductor substrate using at least the insulating film line as a mask. . According to the present invention, by forming the trench portion, no current flows through the semiconductor substrate on both sides of the word line. As a result, charges are not trapped in the ONO films on both sides of the word line. Therefore, it is possible to provide a method for manufacturing a semiconductor device in which the word line interval can be narrowed and the memory cells can be miniaturized.

  In the present invention, the step of forming the bit line includes a step of implanting ions into the semiconductor substrate in the opening formed in the first metal layer that constitutes the gate electrode, and the insulating film line is formed. The step of forming includes: a step of depositing an insulating film line layer on the opening and the first metal layer; and a step of polishing the insulating film line layer to the first metal layer. It can be set as a manufacturing method. According to the present invention, the bit line and the insulating film line can be formed by self-alignment. Therefore, the insulating film line can be continuously formed in the longitudinal direction of the bit line. Also, by forming the insulating film line in the opening of the first metal layer, the side surface of the insulating film line can be made substantially perpendicular to the semiconductor substrate. Thereby, the memory cell can be miniaturized.

  According to the present invention, the step of forming the insulating film line may be a method for manufacturing a semiconductor device including a step of forming a silicon oxide film by a CVD method. According to the present invention, bird's beak does not occur, and the memory cell can be further miniaturized.

  The present invention can be a method for manufacturing a semiconductor device including a step of forming an insulating film layer on the trench portion. According to the present invention, it is possible to more reliably separate elements between channels.

  The present invention includes a step of forming a barrier layer including a silicon oxide film layer on the trench portion, and the step of forming the insulating film layer includes a step of forming a silicon nitride film layer on the barrier layer. It can be set as the manufacturing method of a semiconductor device. According to the present invention, it is possible to prevent the silicon nitride film from being peeled off due to stress. Further, it is possible to prevent hydrogen in the silicon nitride film from diffusing into the ONO film and deteriorating characteristics.

  The present invention can be a method for manufacturing a semiconductor device including a step of forming a contact hole connected to the bit line in the insulating film line between the insulating film layers. According to the present invention, when the contact hole is formed, the insulating film line can be selectively etched with respect to the insulating film layer. As a result, it is not necessary to secure an alignment margin when exposing the bit line and the contact hole, and the memory cell can be miniaturized.

  The present invention can be a semiconductor device manufacturing method including a step of forming a channel cut region having a conductivity type opposite to the bit line in the semiconductor substrate of the trench portion. According to the present invention, element isolation between channels can be more reliably performed.

  The present invention may be a method of manufacturing a semiconductor device, wherein the step of forming the channel cut region includes a step of performing ion implantation into the trench using the insulating film line and the word line as a mask. According to the present invention, the channel cut region can be formed in a self-aligned manner with the trench portion. Therefore, the manufacturing process can be reduced. Further, it is not necessary to consider misalignment during exposure, and the memory cell can be miniaturized.

  The present invention includes a step of forming a side wall on a side portion of the trench portion, and the step of forming the channel cut region includes ions formed in the trench portion using the insulating film line, the word line, and the side wall as a mask. It can be set as the manufacturing method of the semiconductor device including the process of implanting. According to the present invention, since the distance between the channel cut region and the channel can be secured, it is possible to prevent the channel from becoming narrow due to the depletion layer from the P-type region. Furthermore, the channel cut region can be formed in a self-aligned manner with the trench portion. Therefore, the manufacturing process can be reduced. Further, it is not necessary to consider misalignment during exposure, and the memory cell can be miniaturized.

  The present invention includes a method of manufacturing a semiconductor device, including a step of forming an ONO film on the semiconductor substrate, wherein the step of forming the gate electrode is a step of forming a gate electrode on the ONO film. it can. According to the present invention, in a flash memory having an ONO film, trapping of charges in the ONO film on both sides of the word line can be suppressed.

  According to the present invention, it is an object to provide a semiconductor device and a method for manufacturing the same capable of element isolation between word lines and miniaturization of memory cells.

FIG. 1 is a top view of a memory cell of a flash memory according to Prior Art 1. FIG. 2 is a cross-sectional view of a memory cell of a flash memory according to prior art 1, FIG. 2 (a) is a cross-sectional view taken along line AA in FIG. 1, and FIG. 2 (b) is a cross-sectional view taken along line BB in FIG. It is. 3A and 3B are diagrams for explaining the problems of the prior art. FIG. 3A is a top view of the memory cell of the flash memory, and FIG. 3B is a cross-sectional view taken along line BB in FIG. is there. FIG. 4 is a top view of the memory cell of the flash memory according to the first embodiment. 5 is a cross-sectional view of the memory cell of the flash memory according to the first embodiment. FIGS. 5A, 5B, and 5C are cross-sectional views taken along lines AA, BB, and C-, respectively, of FIG. It is C sectional drawing. 6 is a cross-sectional view of the memory cell of the flash memory according to the first embodiment, FIG. 6A is a cross-sectional view taken along the line DD in FIG. 4, and FIG. 6B is a cross-sectional view taken along the line EE in FIG. It is. FIG. 7 is a cross-sectional view (part 1) illustrating the method of manufacturing the flash memory according to the first embodiment. FIGS. 7A, 7B, and 7C are cross-sectional views taken along lines AA and BB in FIG. It is a figure equivalent to a section and a DD section. FIG. 8 is a cross-sectional view (No. 2) illustrating the method of manufacturing the flash memory according to the first embodiment. FIGS. 8A, 8B, and 8C are a cross-sectional view taken along the line AA in FIG. It is a figure equivalent to a section and a DD section. FIG. 9 is a cross-sectional view (No. 3) illustrating the method of manufacturing the flash memory according to the first embodiment. FIGS. 9A, 9B, and 9C are cross-sectional views taken along line AA and BB in FIG. It is a figure equivalent to a section and a DD section. FIG. 10 is a cross-sectional view (part 4) illustrating the manufacturing method of the flash memory according to the first embodiment. FIGS. 10 (a), 10 (b), and 10 (c) are cross-sectional views taken along lines AA and BB in FIG. It is a figure equivalent to a section and a DD section. FIG. 11 is a cross-sectional view (No. 5) showing the method of manufacturing the flash memory according to the first embodiment. FIGS. 11 (a), 11 (b), and 11 (c) are cross sections taken along line AA and BB in FIG. It is a figure equivalent to a section and a DD section. FIG. 12 is a cross-sectional view (No. 6) showing the method of manufacturing the flash memory according to the first embodiment, and FIGS. 11A, 11B, and 11C are views corresponding to the CC cross section of FIG. is there. FIG. 13 is a cross-sectional view (No. 1) illustrating the method for manufacturing the flash memory according to the second embodiment, and FIGS. 13A and 13B correspond to the AA cross section and the DD cross section of FIG. 4, respectively. FIG. FIG. 14 is a cross-sectional view (No. 2) illustrating the method for manufacturing the flash memory according to the second embodiment. FIGS. 14A and 14B correspond to the AA cross section and the DD cross section of FIG. FIG. FIG. 15 is a cross-sectional view (No. 3) showing the method of manufacturing the flash memory according to the second embodiment, and FIGS. 15A and 15B correspond to the AA cross section and the DD cross section of FIG. 4, respectively. FIG. FIG. 16 is a cross-sectional view (No. 1) showing the flash memory manufacturing method according to the third embodiment, and FIGS. 16A and 16B correspond to the AA cross section and the DD cross section of FIG. 4, respectively. FIG. FIG. 17 is a cross-sectional view (No. 2) illustrating the method of manufacturing the flash memory according to the third embodiment. FIGS. 17A and 17B correspond to the AA cross section and the DD cross section of FIG. FIG. FIG. 18 is a cross-sectional view (No. 1) showing the method for manufacturing the flash memory according to the fourth embodiment, and FIGS. 18A and 18B correspond to the AA cross section and the DD cross section of FIG. 4, respectively. FIG. FIG. 19 is a sectional view (No. 2) showing the manufacturing method of the flash memory according to the fourth embodiment, and FIGS. 19A and 19B correspond to the AA section and the DD section of FIG. 4, respectively. FIG.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 4 is a top view (a protective film, a wiring layer, and an interlayer insulating film are not shown) of the flash memory according to the first embodiment. 5A is a cross-sectional view taken along line AA in FIG. 4, FIG. 5B is a cross-sectional view taken along line BB in FIG. 4, and FIG. 5C is a cross-sectional view taken along line CC in FIG. . 6A is a DD cross-sectional view of FIG. 4, and FIG. 6B is an EE cross-sectional view of FIG. Referring to FIG. 4, a bit line 14 embedded and formed in a P-type silicon semiconductor substrate 10 (or a P-type region formed in the semiconductor substrate) and continuously formed in the longitudinal direction of the bit line 14 thereon. The formed insulating film line 18 extends in the vertical direction of FIG. Further, although not shown in FIG. 4, the wiring layer 36 extends on the bit line 14 in the longitudinal direction of the bit line 14.

  A word line 20 extends in the width direction of the bit line. Each time a plurality of word lines 20 are crossed, a contact hole is formed. The contact hole is filled with a plug metal 34 to connect the bit line 14 and the wiring layer 36. This is because the resistance of the bit line 14 is high because it is formed of a diffusion layer. For this reason, the write / erase characteristics of the memory cell deteriorate. Therefore, in order to prevent this deterioration, the bit line 14 is connected to the low-resistance wiring layer 36 every time a plurality of word lines 20 are exceeded.

  A cross section between the word lines 20 in the longitudinal direction of the word lines 20 will be described with reference to FIG. A trench portion 22 is formed in the semiconductor substrate 10 between the bit lines 14, and a silicon nitride film is provided as an insulating film layer 24 on the trench portion 22. Bit lines 14 are embedded in the semiconductor substrate 10. A silicon oxide film is provided thereon as an insulating film line 18. An interlayer insulating film 30 is provided on the insulating film line 18 and the insulating film layer 24. A wiring layer 36 is provided on the bit line 14 on the interlayer insulating film 30. A protective film 38 is provided on them.

  A cross section of the word line 20 in the longitudinal direction of the word line 20 will be described with reference to FIG. The trench 22 is not provided in the semiconductor substrate 10 between the bit lines 14, and a channel is formed in the semiconductor substrate 10. An ONO film 12 is provided on the semiconductor substrate 10 between the bit lines 14. A gate electrode 16 is provided between the insulating film lines 18 on the ONO film 12. The bit line 14 formed in the semiconductor substrate 10 functions as a source region and a drain region. An insulating film line 18 is provided on the bit line 14. A word line 20 is provided in contact with the insulating film line 18 and the gate electrode 16. Thereby, the gate electrode 16 and the word line 20 are connected. An interlayer insulating film 30 is provided on the word line 20, and the top is the same as in FIG.

  With reference to FIG. 5C, a cross section that crosses the contact hole 32 in the longitudinal direction of the word line 20 will be described. The space between the bit lines 14 is the same as that shown in FIG. A contact hole is formed on the bit line 14 and a plug metal 34 is embedded. A wiring layer 36 is provided on the plug metal 34, and the bit line 14 and the wiring layer 36 are connected by a contact hole.

  A cross section between the bit lines 14 in the longitudinal direction of the bit lines 14 will be described with reference to FIG. Between the word lines 20, a trench portion 22 is formed in the semiconductor substrate 10, and an insulating film layer 24 is formed on the trench portion 22. Under the word line 20, the trench portion 22 is not formed, and a channel is formed in the semiconductor substrate 10. An ONO film 12 is provided on the semiconductor substrate 10, a gate electrode 16 is provided on the ONO film 12, and a word line 18 is provided on the gate electrode 16. An interlayer insulating film 30 is provided on the word line 16 and the insulating film layer 24, and a protective film 38 is provided on the interlayer insulating film 30.

  With reference to FIG. 6B, a cross section of the bit line 14 in the longitudinal direction of the bit line 14 will be described. Bit lines 14 are embedded in the semiconductor substrate 10. An insulating film line 18 is continuously formed on the bit line 14. A word line 20 is provided on the insulating film line 18. An interlayer insulating film 30 is provided on the word line 20 and the insulating film line 18. A wiring layer 36 is provided on the interlayer insulating film 30, and a protective film 38 is provided on the wiring layer 36. The bit line 14 and the wiring layer 36 are connected by a contact hole 32 formed in the insulating film line 18 and the interlayer insulating film 30 every time a plurality of word lines 20 are exceeded. A plug metal 34 is embedded in the contact hole 32.

  The flash memory according to the first embodiment includes a trench portion 22 formed in the semiconductor substrate 10 between the bit lines 14 and between the word lines 20. As a result, unlike the prior art 1, no current flows in the semiconductor substrate 10 on both sides of the word line 20 and no charge is trapped in the ONO film 12 on both sides of the word line 20. Therefore, the interval between the word lines 20 can be narrowed, and the memory cell can be miniaturized.

  When the word line is a single layer as in prior art 2, it is difficult to make the insulating film line 18 into a substantially vertical shape. This is because the burying property of the word line 20 between the insulating film lines 18 is deteriorated. Therefore, as in the first embodiment, the gate electrode 16 is provided between the insulating film lines 18, and the word line 20 is provided so as to overlap therewith. Thereby, the subject of the prior art 2 can be solved. The gate electrode 16 and the word line 20 are provided in contact with each other. As a result, as described later in the description of the manufacturing method, when the trench portion 22 is formed, it is not necessary to perform complicated etching as in the prior art 3.

  When the insulating film line is formed of a thermal oxide film as in the prior arts 2 and 3, the side surface of the insulating film line 18 becomes an inclined surface, the channel width becomes narrow due to bird's beak, and it is difficult to miniaturize the memory cell. Therefore, as in the first embodiment, it is preferable that the side surface in the width direction of the insulating film line 18 is substantially perpendicular to the surface of the semiconductor substrate 10. The term “substantially perpendicular” means that the thermal oxide silicon film having the LOCOS structure is formed perpendicularly to the film. As a result, the memory cell can be miniaturized without occurrence of bird's beak.

  The insulating film line 18 only needs to be insulative, but the insulating film line 18 preferably includes a silicon oxide film as in the first embodiment. Thereby, when the trench part 22 is formed, the etching selectivity with respect to the silicon semiconductor substrate 10 can be increased.

  Further, it is preferable to provide the insulating film layer 24 on the trench portion 22 as in the first embodiment. As a result, the channels can be reliably insulated from each other. Further, by using the insulating film line 18 as the silicon oxide film and the insulating film layer 22 as the silicon nitride film as in the first embodiment, the silicon oxide film can be selectively etched with respect to the silicon nitride film. As a result, it is not necessary to secure an alignment margin when exposing the bit line 14 and the contact hole, and the memory cell can be miniaturized.

  Further, an ONO film 12 is provided between the semiconductor substrate 10 and the gate electrode 16. As described above, in the flash memory having the ONO film 12, it is possible to suppress trapping of charges in the ONO film 12 on both sides of the word line 20.

  Next, a method for manufacturing the flash memory according to the first embodiment will be described with reference to FIGS. 7 to 11 are cross-sectional views corresponding to the AA cross section of FIG. 4 and FIGS. 7B to 11B are cross-sectional views corresponding to the BB cross section of FIG. FIG. 7C is a cross-sectional view corresponding to the cross section DD in FIG. 12 is a cross-sectional view corresponding to the CC cross section of FIG.

  Referring to FIG. 7, a tunnel oxide film (silicon oxide film) is formed as a ONO film 12 on a P-type silicon semiconductor substrate 10 (or a P-type region in the semiconductor substrate) by a thermal oxidation method, and a trap layer (silicon nitride film). A top oxide film (silicon oxide film) is formed by a CVD method. On the ONO film 12, a polycrystalline silicon film is formed as a first metal layer 16a that is to constitute the gate electrode 16. A photoresist 44 having an opening in a region where the bit line 14 is to be formed is formed on the first metal layer 16a. Using the photoresist 44 as a mask, the first metal layer 16a and the ONO film 12 are etched to form an opening 48. Thereby, as shown in FIGS. 7A and 7B, an opening 48 is formed in a region where the bit line 14 and the insulating film line 18 are to be formed. As shown in FIG. 7C, a first metal layer 16a is continuously provided between the bit lines 14 where the bit lines 14 are formed. The side surface of the opening 48 is formed substantially perpendicular to the surface of the semiconductor substrate 10. The film thickness of the first metal layer 16a is 100 nm, the width of the opening 48 (that is, the bit line width) is 70 nm, and the distance between the bit lines is 160 nm.

  Referring to FIG. 8, arsenic ions, for example, are implanted into semiconductor substrate 10 using photoresist 44 as a mask, and photoresist 44 is removed. Thereafter, an N-type bit line 14 is formed in the semiconductor substrate 10 by heat treatment. A silicon oxide film layer having a thickness of about 180 nm is deposited on the opening 48 and the first metal layer 16a so as to fill the opening 48 by a high-density plasma CVD apparatus. By using a high-density plasma type CVD apparatus, the silicon oxide film 18 can be reliably embedded in the opening 48 having a large aspect ratio of 2.7. The CMP method is used to polish the silicon oxide film layer up to the first metal layer 16a. As a result, the insulating film line 18 embedded in the opening 48 is formed on the bit line 14. At this time, the thickness of the first metal layer 16a is about 90 nm.

  Thus, the bit line 14 and the insulating film line 18 can be formed by self-alignment. Therefore, the insulating film line 18 can be continuously formed in the longitudinal direction of the bit line 14. Further, by forming the insulating film line 18 in the opening 48, the side surface of the insulating film line 18 can be made substantially perpendicular to the semiconductor substrate 10. Thereby, the memory cell can be miniaturized. Furthermore, by forming the insulating film line by the CVD method, no bird's beak is generated, and the memory cell can be further miniaturized.

  Referring to FIG. 9, a second metal layer 20a that should constitute word line 20 is formed on insulating film line 18 and first metal layer 16a using a polycrystalline silicon film. On the second metal layer 20a, a photoresist 46 having an opening other than a region where the word line 20 is formed is formed. The photoresist 46 is not formed in the region to be between the word lines 12 as shown in FIG. 9A, and the photoresist 46 is not formed in the region to be the word line 12 as shown in FIG. Is formed. The second metal layer 20a has a film thickness (that is, a word line film thickness) of 100 nm, a word line width of 75 nm, and a word line interval of 75 nm.

  Referring to FIG. 10, second metal layer 20a, first metal layer 16a and ONO film 12 are etched using photoresist 46 as a mask. Further, a trench portion 22 having a depth of 40 nm is formed in the semiconductor substrate 10 between the bit lines 14 and between the word lines 20. At this time, as shown in FIG. 10A, in the region between the word lines 20, the second metal layer 20a and the first metal layer 16a between the bit lines 14 are etched. Further, a trench portion 22 is formed in the semiconductor substrate 10 between the bit lines 14. An insulating film line 18 is provided on the bit line 14. The insulating film line 18 is composed of a silicon oxide film. Therefore, the insulating film line 18 can be left by selectively etching the second metal layer 20a and the first metal layer 16a made of a polycrystalline silicon film or the like with respect to the silicon oxide film. As a result, even when the trench portion 22 is formed in the semiconductor substrate 10, the bit line 14 can be prevented from being etched.

  As shown in FIG. 10B, the first metal layer 16 a and the second metal layer 20 a remain in the region where the word line 20 is formed, thereby forming the gate electrode 16 and the word line 20. Therefore, the gate electrode 16 is formed on the semiconductor substrate 10 between the bit lines 14, and the word line 20 that is in contact with the gate electrode 16 and extends in the width direction of the bit line 14 is formed. Further, a trench portion 22 is formed in the semiconductor substrate 10 between the bit lines 14 and between the word lines 20. The trench portion 22 is formed by etching the semiconductor substrate 10 using at least the insulating film line 18 as a mask.

  If there is a silicon oxide film between the first metal layer 16a and the second metal layer 20a as in the prior art 3, after the second metal film 20a is etched, it stops at this silicon oxide film, Etching takes time. Therefore, it was necessary to etch the silicon oxide film under different conditions and to etch the first metal layer 16a. In the first embodiment, the word line 20 on the gate electrode 16, that is, the second metal layer 20a on the first metal layer 16a is provided in contact with the ONO film 12 so that the etching can be continuously performed. The complicated etching is not necessary.

  As described above, the bit line 14 and the insulating film line 18 are formed by self-alignment through the opening 48 formed in the first metal layer 16a. Furthermore, a second metal layer 20a is formed thereon. Then, etching for forming the word line 20, the gate electrode 16 and the trench portion 22 is performed using the same mask. Thereby, the word line 20, the gate metal 16, and the trench part 22 can be formed by self-alignment. Therefore, the manufacturing process can be reduced. Furthermore, it is not necessary to consider misalignment during exposure, and the memory cell can be miniaturized.

  Referring to FIG. 11, a 100 nm-thickness silicon nitride film is formed as an insulating film layer 24 on the trench portion 22 so as to bury the trench portion 22 by a CVD method or a high-density plasma CVD apparatus. Then, the insulating film layer 24 is embedded by etching the entire surface or polishing using a CMP method. The insulating film layer 24 can more reliably isolate elements between the channels under the word lines 20.

  Next, a region where the contact hole 32 is formed will be described with reference to FIG. FIG. 12A shows the same manufacturing process as FIG. Before the contact hole is formed, the cross section has the same configuration as FIG. 11A corresponding to the AA cross section of FIG. Referring to FIG. 12B, a silicon oxide film such as BPSG (Boro-Phospho Silicated Glass) is formed as an interlayer insulating film 30 on the insulating film layer 24 and the insulating film line 18 by using the CVD method. Using the photoresist as a mask, the insulating film line 18 between the interlayer insulating film 30 and the insulating film layer 24 is etched to form a contact hole 32 connected to the bit line 14.

  The interlayer insulating film 30 and the insulating film line 18 are silicon oxide films, and the insulating film layer 24 is a silicon nitride film. Therefore, the silicon oxide film can be selectively etched with respect to the silicon nitride film. Thereby, even when the opening of the photoresist forming the contact hole 32 is deviated from the bit line 14, the contact hole 32 is not formed away from the bit line 14. If the contact hole 32 is formed away from the bit line 14, a junction current flows between the bit line 14 and the semiconductor substrate 10. In the first embodiment, this can be prevented. As a result, it is not necessary to secure an alignment margin when exposing the bit line 14 and the contact hole, and the memory cell can be miniaturized.

  Referring to FIG. 12C, a metal such as Ti / WN or Ti / TiN and W is embedded in the contact hole 32 to form a plug metal 34. Thereafter, the wiring layer 36 and the protective film 38 are formed, and the flash memory according to the first embodiment is completed.

  Example 2 is an example in which a barrier layer is provided on the bottom and sides of the insulating film layer 24. 13 to 15 are views showing a method for manufacturing a flash memory according to the second embodiment. Each figure (a) is a sectional view corresponding to the section AA in FIG. 4, and each figure (b) is a sectional view corresponding to the section DD in FIG. In FIG. 13, the manufacturing steps up to FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Referring to FIG. 14, a barrier layer 26 including a silicon oxide film layer is formed on the upper and side surfaces of trench portion 22 and the side surfaces of ONO film 12, insulating film line 18, gate electrode 16, and word line 20 by a CVD method. The film thickness of the barrier layer 26 is 30 nm. A silicon nitride film layer is formed as an insulating film layer 24 on the barrier layer 26 by a CVD method or a high-density plasma type CVD apparatus. After that, the insulating film layer 24 and the barrier layer 26 are embedded by etching the entire surface or polishing using a CMP method. Thereafter, the flash memory according to the second embodiment is completed by performing the same steps as those in FIG. 12 of the first embodiment.

  The flash memory according to the second embodiment can obtain the same effects as those of the first embodiment. In addition, the flash memory according to the second embodiment includes a barrier layer 26 (including) a silicon oxide film provided between the trench portion 22 and the insulating film layer 24 (including) a silicon nitride film. Yes. Thereby, peeling of the silicon nitride film due to stress can be prevented. Further, it is possible to prevent hydrogen in the silicon nitride film from diffusing into the ONO film 12 and deteriorating characteristics. The barrier layer 26 is preferably formed on at least the trench portion 22 for the purpose of preventing peeling, and is preferably formed on at least the side surface of the ONO film 12 for the purpose of barrier to the ONO film 12.

  The third embodiment is an example in which the channel cut region 40 is provided in the trench portion 22. 16 and 17 are diagrams illustrating a method for manufacturing a flash memory according to the third embodiment. Each figure (a) is a sectional view corresponding to the section AA in FIG. 4, and each figure (b) is a sectional view corresponding to the section DD in FIG. Referring to FIG. 16, first, the manufacturing steps up to FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Thereafter, boron, for example, is ion-implanted into the semiconductor substrate 10 of the trench portion 22 using the insulating film line 18 and the word line 20 as a mask to form a P-type (cut-type opposite to the bit line 14) channel cut region 40. For example, ion implantation is performed with an implantation energy of 65 keV and a dose of 1E13 cm−3.

  Referring to FIG. 17, a silicon nitride film is formed as an insulating film layer 24 on the trench portion 22 as in FIG. 11 of the first embodiment. Thereafter, the flash memory according to the third embodiment is completed by performing the same steps as those in FIG. 12 of the first embodiment.

  The flash memory according to the third embodiment can obtain the same effects as those of the first embodiment. In addition, since the flash memory according to the third embodiment has the P-type channel cut region 40 in the trench portion 22, element isolation between channels below the word line 20 can be more reliably performed. Further, since the channel cut region 40 is formed using the insulating film line 18 and the word line 20 as a mask, the channel cut region 40 can be formed in self-alignment with the trench portion 22. Therefore, the manufacturing process can be reduced. Further, it is not necessary to consider misalignment during exposure, and the memory cell can be miniaturized.

  The fourth embodiment is an example in which the side wall 28 is formed on the side surface of the trench portion 22 and the channel cut region 40 is provided. 18 and 19 are diagrams showing a method for manufacturing a flash memory according to the fourth embodiment. Each figure (a) is a sectional view corresponding to the section AA in FIG. 4, and each figure (b) is a sectional view corresponding to the section DD in FIG. Referring to FIG. 18, first, the manufacturing process up to FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Thereafter, the sidewall 28 is formed on the side surface of the trench portion 22 by using a sidewall method. The width of the side wall 28 is, for example, 15 nm. The side wall 28 is formed of, for example, a silicon oxide film or a silicon nitride film. For example, boron is ion-implanted into the semiconductor substrate 10 under the same conditions as in the third embodiment, using the insulating film line 18, the word line 20, and the sidewall 28 as a mask, and then heat-treated. Thereby, a P-type (opposite conductivity type to the bit line 14) channel cut region 40 is formed.

  Referring to FIG. 19, a silicon nitride film is formed as an insulating film layer 24 on the trench portion 22 as in FIG. 11 of the first embodiment. Thereafter, the flash memory according to the fourth embodiment is completed by performing the same steps as those of the first embodiment shown in FIG.

  The flash memory according to the fourth embodiment can obtain the same effects as those of the third embodiment. In addition, since the distance between the channel cut region 40 and the channel can be secured in the flash memory according to the fourth embodiment, it is possible to prevent the channel from becoming narrow due to the depletion layer from the P-type region. Further, since the channel cut region 40 is formed using the insulating film line 18, the word line 20 and the side wall 28 as a mask, the channel cut region 40 can be formed in self-alignment with the trench portion 22. Therefore, the manufacturing process can be reduced. Further, it is not necessary to consider misalignment during exposure, and the memory cell can be miniaturized.

  Note that the channel cut region 40 as in the third or fourth embodiment may be provided in the flash memory having the barrier layer 26 as in the second embodiment.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

Claims (2)

A bit line formed in a semiconductor substrate;
A first insulating film line provided continuously on the bit line in the longitudinal direction of the bit line;
A second insulating film provided between the first insulating film lines on the semiconductor substrate, the top surface of the second insulating film being provided on the bit line;
A gate electrode provided on the semiconductor substrate between the bit lines;
A word line provided in contact with the gate electrode and extending in a width direction of the bit line;
A third insulating film provided on the word line, the first insulating film line, and the second insulating film, and different from the second insulating film;
A trench part formed in the semiconductor substrate between the bit lines and between the word lines,
The side surface in the width direction of the first insulating film line is substantially perpendicular to the surface of the semiconductor substrate,
The semiconductor device, wherein the first insulating film line and the third insulating film are silicon oxide films, and the third insulating film is a silicon nitride film. Forming a bit line in the semiconductor substrate;
A first insulating film line formed continuously on the bit line in the longitudinal direction of the bit line, wherein a side surface in the width direction of the first insulating film line is approximately the surface of the semiconductor substrate. Forming the first insulating film line that is vertical;
A second insulating film located between the first insulating film lines on the semiconductor substrate, and a top surface of the second insulating film forms the second insulating film provided on the bit line. Forming a gate electrode on the semiconductor substrate between the step and the bit line;
Forming a word line provided in contact with the gate electrode and extending in a width direction of the bit line;
Forming a third insulating film different from the second insulating film on the word line, the first insulating film line, and the second insulating film;
Forming a trench portion in the semiconductor substrate between the bit lines and between the word lines,
The step of forming the trench portion includes a step of etching the semiconductor substrate using at least the first insulating film line as a mask,
The method of manufacturing a semiconductor device, wherein the first insulating film line and the third insulating film are silicon oxide films, and the third insulating film is a silicon nitride film.

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