JP2007150068A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a memory cell which can prevent any formation of an offset structure and prevent degradation of a short channel characteristic. <P>SOLUTION: A first laminated gate and a second laminated gate are formed in this order on a semiconductor substrate 11. The first laminated gate has a first tunnel oxide film 12, a first floating gate 5, a first integrate insulating film 13, and a first control gate 4 stacked in this order. The second laminated gate has a second tunnel oxide film 12, a second floating gate 5, a second integrate insulating film 13, and a second control gate 4 stacked in this order. Gate sidewall insulating films 16 are formed on the sidewall of the first laminated gate and on the sidewall of the second laminated gate. Further, an n<SP>+</SP>-type diffusion layer 2B is formed on the semiconductor substrate 11 between the first and second laminated gates. The surface of the n<SP>+</SP>-type diffusion layer 2B contacted with the gate sidewall insulating films 16 is formed to be higher than the surface of the n<SP>+</SP>-type diffusion layer 2B between the gate sidewall insulating films 16. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, for example, a non-volatile semiconductor memory device including NAND memory cells and a method for manufacturing the same.

  In recent years, NAND-type EEPROMs are widely used as electrically rewritable nonvolatile semiconductor memory devices. The NAND-type EEPROM includes a plurality of memory cells (hereinafter referred to as NAND cells) connected in series, and select gate transistors arranged at both ends of the NAND cell.

  FIG. 14 shows a partial cross-sectional structure of the NAND cell. Between the cell diffusion layer 103 formed in the p-type well region 102 on the semiconductor substrate 101, a tunnel insulating film 104, a floating gate 105, an inter-gate insulating film (interpoly insulating film) 106, a polysilicon film 107A, and a metal silicide A control gate 107 made of the film 107B and a gate mask material 108 are stacked, and a memory cell is constituted by these layers. Further, a thermal oxide film 109 is formed so as to cover the gate. A plurality of memory cells having such a structure are connected in series so that adjacent memory cells share a source or drain (see, for example, Patent Document 1).

  The NAND cell described above may have the following problems. As shown in FIG. 14, the semiconductor substrate (cell diffusion layer 103) in the vicinity of the end portion (gate edge) of the floating gate 105 is etched back (region indicated by 110 in FIG. 14), and in the vicinity of the floating gate end portion. The semiconductor substrate has caused substrate digging. For this reason, the memory cell transistor tends to have an offset structure, the cell current cannot be drawn, and the number of memory cells with poor short channel characteristics increases. Further, the tunnel oxide film 104 formed under the gate edge of the floating gate 105 is easily damaged, and an electron trap or the like enters the tunnel oxide film, so that the cell current is deteriorated or the data retention is lowered. The long-term reliability of the cell may deteriorate.

On the other hand, as another conventional technique, after gate processing, there is a method of opening a resist only between select gates, reducing the height of STI (Shallow Trench Isolation), and ensuring the contact area of the bit line contact and the source line contact. . However, in this method, since a step remains between the STI and the active element region in the memory cell, the polysilicon film deposited to form the gate beside the STI step between the gates of the memory cell remains and becomes defective. There are many cases. Moreover, since a photoetching process (PEP process) is added, it is disadvantageous in terms of manufacturing cost.
JP 2002-57230 A

  Therefore, an object of the present invention is to provide a semiconductor device including a memory cell that is unlikely to have an offset structure and can prevent deterioration of short channel characteristics, and a method for manufacturing the same. In addition, a semiconductor device including a memory cell that can hardly damage a gate insulating film near the gate end, can improve cell current degradation, and can improve data retention and long-term reliability, and a manufacturing method thereof. The purpose is to provide.

  In order to achieve the above object, a semiconductor device according to an embodiment of the present invention includes a first semiconductor region formed in a surface region of a semiconductor substrate, and a surface region of the semiconductor substrate spaced apart from the first semiconductor region. A second semiconductor region formed; a first tunnel insulating film formed on the semiconductor substrate between the first semiconductor region and the second semiconductor region; and a first tunnel insulating film formed on the first tunnel insulating film. A first floating gate; a first inter-gate insulating film formed on the first floating gate; a first control gate formed on the first inter-gate insulating film; and a side surface of the first floating gate And a first sidewall insulating film formed on a side surface of the first control gate, and a third semiconductor region formed in a surface region of the semiconductor substrate and separated from the first and second semiconductor regions. A second tunnel insulating film formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region, a second floating gate formed on the second tunnel insulating film, A second inter-gate insulating film formed on the second floating gate; a second control gate formed on the second inter-gate insulating film; a side surface of the second floating gate; and the second control gate. A second sidewall insulating film formed on a side surface, and the surface of the second semiconductor region that contacts the first and second sidewall insulating films is formed on the first sidewall insulating film and the second sidewall insulating film. It is characterized by being higher than the surface of the second semiconductor region between the film.

  In another embodiment of the present invention, a semiconductor device includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a first conductive film on the first insulating film, and the first conductive Forming a device isolation region on the semiconductor substrate on which the film is formed; forming a second insulating film on the first conductive film and the device isolation region; and second conductive on the second insulating film. Forming a film, processing the first insulating film, the first conductive film, the second insulating film, and the second conductive film to form a first tunnel insulating film, a first film on the semiconductor substrate; The first stacked gate, the second tunnel insulating film, the second floating gate, the second inter-gate insulating film, and the second control gate, which are stacked in the order of the floating gate, the first inter-gate insulating film, and the first control gate. And a second laminated gate laminated with Forming a source region or a drain region in the semiconductor substrate between the first stacked gate and the second stacked gate; on the first stacked gate; on the second stacked gate; Forming a third insulating film on the semiconductor substrate and processing the third insulating film by anisotropic etching to insulate side walls on the side surfaces of the first stacked gate and on the side surfaces of the second stacked gate Forming a film; and performing anisotropic etching in a self-aligned manner on the sidewall insulating film formed on the side surface of the first stacked gate and on the side surface of the second stacked gate, and the element isolation region And a step of lowering the height.

  According to the present invention, it is possible to provide a semiconductor device including a memory cell that is unlikely to have an offset structure and can prevent deterioration of short channel characteristics, and a manufacturing method thereof. In addition, a semiconductor device including a memory cell that can hardly damage a gate insulating film near the gate end, can improve cell current degradation, and can improve data retention and long-term reliability, and a manufacturing method thereof. Can provide.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common reference numerals are given to common portions throughout the drawings.

[First Embodiment]
First, a semiconductor device according to a first embodiment of the present invention will be described. Here, a nonvolatile semiconductor memory device provided with NAND memory cells is taken as an example of the semiconductor device.

  FIG. 1 is a layout diagram of the NAND type memory cell according to the first embodiment. A region surrounded by a dotted line indicates one memory cell block 1. The memory cell block 1 includes a NAND cell in which a plurality of memory cells are connected in series so that adjacent memory cells share a source or drain, and select gate transistors disposed at both ends of the NAND cell. Yes.

  An active element region 2 and an element isolation region 3 are formed on a semiconductor substrate, and a plurality of control gates 4 of memory cells are arranged in parallel on the active element region 2 and the element isolation region 3. A floating gate 5 is formed between the active element region 2 and the control gate 4. A drain side select gate transistor 6 is formed at one end of the memory cell block 1, and a source side select gate transistor 7 is formed at the other end of the memory cell block 1. Further, a bit line contact 8 and a source line contact 9 are formed between the drain side select gate transistors 6 and between the source side select gate transistors 7, respectively.

  Next, the cross-sectional structure of the NAND memory cell according to the first embodiment will be described with reference to a cross-sectional view taken along line AA in the NAND memory cell shown in FIG.

  FIG. 2 is a cross-sectional view showing the structure of the NAND type memory cell of the first embodiment.

  On the p-type semiconductor substrate 11, a p-type well region 2A as an active element region 2 is formed. In the surface region of the p-type well region 2A, a plurality of n + -type diffusion layers 2B constituting the source or drain are formed apart from each other. A tunnel oxide film 12 as a gate insulating film is formed between the n + -type diffusion layers 2B, and a floating gate 5 is formed on the tunnel oxide film 12. The floating gate 5 is made of, for example, a polysilicon film. An intergate insulating film 13 is formed on the floating gate 5, and a control gate 4 is formed on the intergate insulating film 13. The control gate 4 comprises a polysilicon film 4A formed on the intergate insulating film 13 and a metal silicide film 4B formed on the polysilicon film 4A. A gate mask material 14 made of a silicon nitride film or the like is formed on the control gate 4. A silicon oxide film 15 as a protective film is formed on the side surface of the floating gate 5, the side surface of the control gate 4, the side surface of the gate mask material 14, and the upper surface of the gate mask material 14. . Further, TEOS (Tetraethylorthosilicate) or the like is formed on the side surface of the floating gate 5, the side surface of the control gate 4, the side surface of the gate mask material 14, and the silicon oxide film 15 formed on the n + -type diffusion layer 2B. A gate sidewall insulating film 16 made of is formed.

  Here, n exists between the gate side wall insulating film 16 formed on the side surface of the gate of the memory cell and the gate side wall insulating film 16 formed on the side surface of the gate of the memory cell adjacent to the memory cell. The + type diffusion layer (semiconductor substrate) 2B is lower than the semiconductor substrate below the tunnel oxide film 12 and the gate sidewall insulating film 16, and the substrate is dug. However, the surface of the semiconductor substrate in the vicinity of the end of the floating gate 5 is not lower than the surface of the semiconductor substrate under the tunnel oxide film 12, and the substrate is not dug.

  In the NAND type memory cell having the structure shown in FIG. 2, since the substrate is not dug at the gate edge of the memory cell, the memory cell transistor is unlikely to have an offset structure, and the short channel characteristic in the memory cell transistor is deteriorated. Can also prevent. Further, since the substrate is not dug at the gate edge, the tunnel oxide film at the gate edge is not easily damaged, and the entry of electron traps or the like into the tunnel oxide film can be reduced. As a result, the deterioration of the cell current can be improved, the data retention can be improved, and the long-term reliability of the memory cell can be improved.

  Next, a method for manufacturing the NAND memory cell according to the first embodiment will be described. 3 to 10 are cross-sectional views of each process showing a method for manufacturing a NAND type memory cell, and show cross sections along the line AA in FIG.

  As shown in FIG. 3, ion implantation for forming a well region is performed on a p-type semiconductor substrate 11 to form a p-type well region 2 </ b> A on the p-type semiconductor substrate 11. Thereafter, ion implantation for channel formation is performed in the p-type well region 2A. Next, as shown in FIG. 4, a silicon oxide film to be the tunnel oxide film 12 is formed on the p-type well region 2A by thermal oxidation. Subsequently, a polysilicon film to be the floating gate 5 is formed on the tunnel oxide film 12 by the CVD method. Thereafter, although not shown, a step of forming STI as an element isolation region is performed.

  Next, as shown in FIG. 5, an inter-gate insulating film 13, a polysilicon film 4A and a metal silicide film 4B, and a gate mask material 14 are formed on the polysilicon film to be the floating gate 5. Form in order. Subsequently, a resist film is formed on the gate mask 14, and as shown in FIG. 6, the resist film is patterned to form a resist pattern 17 for gate processing. Thereafter, anisotropic etching such as RIE is performed to form the control gate 4 and floating gate 5 of the memory cell and the gate (not shown) of the select gate transistor, as shown in FIG.

  Next, in the prior art, in order to secure the contact area between the bit line contact 8 and the source line contact 9 and the diffusion layer formed between the select gate transistors as shown in FIG. It is desirable to reduce the height of the STI to the same level as the active element region 2 to eliminate the step between the STI and the active element region. Also, the step between the STI and the active element region is reduced in order to improve the short-circuit failure between the floating gates due to the polysilicon film deposited between the gates of the memory cells to form the gates and remaining on the side of the STI step. It is desirable to do. For this reason, conventionally, after the gate is processed, additional anisotropic etching is additionally performed. However, at this time, although the height of the STI is lowered, as shown in FIG. 14, the substrate digging occurred in the semiconductor substrate.

  Therefore, in the first embodiment, the following steps are performed without performing additional anisotropic etching. First, after the gate is processed, post-gate oxidation is performed as shown in FIG. That is, after forming the floating gate 5, the control gate 4, and the gate mask material 14, by thermal oxidation, on the side surface of the floating gate 5, on the side surface of the control gate 4, on the side surface of the gate mask material 14, and for the gate A silicon oxide film 15 is formed as a protective film on the upper surface of the mask material 14 and on the p-type well region 2A.

  Next, as shown in FIG. 8, an n + -type diffusion layer (cell diffusion layer) 2B constituting a source or drain is formed by ion implantation in the p-type well region 2A between the gates of the memory cells. At this time, unlike the prior art, the surface of the n + -type diffusion layer 2B between the gates is at the same height as the surface of the p-type well region 2A under the tunnel oxide film 12, and there is no substrate excavation. The impurity profile of layer 2B is as desired.

  Subsequently, as shown in FIG. 9, a TEOS film to be the gate sidewall insulating film 16 is formed on the silicon oxide film 15 by the CVD method. Then, anisotropic etching such as RIE is performed, and as shown in FIG. 10, on the side surface of the floating gate 5, on the side surface of the control gate 4, on the side surface of the gate mask material 14, and on the n + -type diffusion layer 2B. A gate sidewall insulating film 16 is formed on the silicon oxide film 15 formed thereon.

  Thereafter, in order to reduce the height of the STI and to remove the remainder of the polysilicon film deposited for forming the floating gate 5, as shown in FIG. Etching is performed. In other words, anisotropic etching is performed on the gate sidewall insulating film 16 in a self-aligned manner. At this time, although not shown, the STI height between the control gates 4 is lower than the STI height under the control gate 4. Through the above manufacturing process, the NAND type memory cell shown in FIG. 2 is manufactured.

  In the semiconductor device including the NAND type memory cell manufactured by using the manufacturing method described above, the semiconductor substrate (region indicated by 18 in FIG. 2) in the vicinity of the floating gate end (gate edge) causes the substrate to be dug. Not. For this reason, it is difficult for the memory cell to form an offset structure, and it is possible to prevent deterioration of short channel characteristics. Further, the tunnel oxide film existing in the vicinity of the gate edge becomes difficult to be damaged, and the entry of an electron trap or the like into the tunnel oxide film can be reduced. Thereby, deterioration of the cell current can be reduced, and further, it is possible to prevent the data retention from being lowered and the long-term reliability of the memory cell from being deteriorated.

  In the first embodiment, in order to improve the short channel characteristics at the same time as the ion implantation for forming the n + -type diffusion layer between the memory cells shown in FIG. 8, in order to adjust the threshold value of the memory cell. It may be necessary to perform ion implantation. In such a case, the fact that the substrate is not dug at the gate edge of the memory cell is further advantageous in reducing the offset structure generated in the memory cell transistor.

[Second Embodiment]
Next explained is a semiconductor device according to the second embodiment of the invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 11 is a cross-sectional view showing the structure of the NAND type memory cell of the second embodiment. This NAND type memory cell is formed by the following manufacturing method. In the first embodiment, as shown in FIG. 9, after a TEOS film to be the gate sidewall insulating film 16 is formed on the silicon oxide film 15, a resist film is opened only between the gates of the select gate transistors. Then, the height of STI is reduced to some extent by anisotropic etching such as RIE. This reduces the polysilicon film remaining on the STI side surface between the gates of the select gate transistors. Thereafter, the resist film is removed, and anisotropic etching such as RIE is further performed on the semiconductor substrate including the memory cell and the select gate transistor. The semiconductor device shown in FIG. 11 is manufactured by the above manufacturing method.

  In the NAND type memory cell having the structure shown in FIG. 11, the etching amount d1 of the n + type diffusion layer 2C between the gates of the select gate transistors is larger than the etching amount d2 of the n + type diffusion layer 2B between the gates of the memory cell. large. That is, the surface of the n + -type diffusion layer 2C is formed lower than the surface of the n + -type diffusion layer 2B. According to the semiconductor device of the second embodiment, the height of the STI existing between the gates of the selection gate transistors is reduced to some extent, and the polysilicon film remaining on the STI side surface can be reduced. The contact area between the contact and the n + -type diffusion layer 2C can be increased. Other configurations and effects are the same as those of the first embodiment.

[Third Embodiment]
Next explained is a semiconductor device according to the third embodiment of the invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  After forming the NAND type memory cell of the first embodiment, as shown in FIG. 12, the resist film 19 is opened only between the gates of the selection gate transistor to adjust the threshold value of the selection gate transistor. In some cases, additional ion implantation is performed to adjust the threshold value between the gates. In such a case, the gate sidewall insulating film 16 can be removed by wet etching or the like before ion implantation. Further, the fact that the substrate is not dug at the gate edge of the select gate transistor reduces the offset structure generated in the select gate transistor when it is necessary to additionally perform ion implantation for threshold adjustment in this way. This is even more advantageous. Other configurations and effects are the same as those of the first embodiment.

[Fourth Embodiment]
Next explained is a semiconductor device according to the fourth embodiment of the invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the first embodiment, as shown in FIG. 10, after performing anisotropic etching using the gate sidewall insulating film 16 as a spacer, an n-type diffusion layer is formed between the gates of the memory cells as shown in FIG. In addition, ion implantation is performed to form an n ++ type diffusion layer 2D. Thereby, the resistance of the n-type diffusion layer constituting the source or drain can be lowered while maintaining the short channel characteristics of the memory cell. Other configurations and effects are the same as those of the first embodiment.

  In addition, each of the above-described embodiments can be implemented not only independently but also in an appropriate combination. Furthermore, the above-described embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.

1 is a layout diagram of a NAND memory cell according to a first embodiment of the present invention. 1 is a cross-sectional view showing the structure of a NAND memory cell according to a first embodiment. FIG. 6A is a cross-sectional view of the first step showing the method for manufacturing the NAND memory cell according to the first embodiment. It is sectional drawing of the 2nd process which shows the manufacturing method of the NAND type memory cell of 1st Embodiment. It is sectional drawing of the 3rd process which shows the manufacturing method of the NAND type memory cell of 1st Embodiment. It is sectional drawing of the 4th process which shows the manufacturing method of the NAND type memory cell of 1st Embodiment. It is sectional drawing of the 5th process which shows the manufacturing method of the NAND type memory cell of 1st Embodiment. It is sectional drawing of the 6th process which shows the manufacturing method of the NAND type memory cell of 1st Embodiment. It is sectional drawing of the 7th process which shows the manufacturing method of the NAND type memory cell of 1st Embodiment. It is sectional drawing of the 8th process which shows the manufacturing method of the NAND type memory cell of 1st Embodiment. It is sectional drawing which shows the structure of the NAND type memory cell of 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the NAND type memory cell of 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the NAND type memory cell of 4th Embodiment of this invention. FIG. 6 is a partial cross-sectional view of a conventional NAND cell.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell block, 2 ... Active element area | region, 2A ... p-type well area | region, 2B ... n <+> type | mold diffused layer, 3 ... Element isolation area | region, 4 ... Control gate, 4A ... Polysilicon film, 4B ... Metal silicide film | membrane, DESCRIPTION OF SYMBOLS 5 ... Floating gate, 6 ... Drain side selection gate transistor, 7 ... Source side selection gate transistor, 8 ... Bit line contact, 9 ... Source line contact, 11 ... P-type semiconductor substrate, 12 ... Tunnel oxide film, 13 ... Between gates Insulating film, 14 ... Mask material for gate, 15 ... Silicon oxide film, 16 ... Gate side wall insulating film, 17 ... Resist pattern, 18 ... Region, 19 ... Resist film.

Claims (5)

A first semiconductor region formed in a surface region of the semiconductor substrate;
A second semiconductor region formed in a surface region of the semiconductor substrate and spaced apart from the first semiconductor region;
A first tunnel insulating film formed on the semiconductor substrate between the first semiconductor region and the second semiconductor region;
A first floating gate formed on the first tunnel insulating film;
A first inter-gate insulating film formed on the first floating gate;
A first control gate formed on the first inter-gate insulating film;
A first sidewall insulating film formed on a side surface of the first floating gate and a side surface of the first control gate;
A third semiconductor region formed on the surface region of the semiconductor substrate and spaced apart from the first and second semiconductor regions;
A second tunnel insulating film formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region;
A second floating gate formed on the second tunnel insulating film;
A second inter-gate insulating film formed on the second floating gate;
A second control gate formed on the second inter-gate insulating film;
A second sidewall insulating film formed on a side surface of the second floating gate and on a side surface of the second control gate;
The surface of the second semiconductor region in contact with the first and second sidewall insulating films is higher than the surface of the second semiconductor region between the first sidewall insulating film and the second sidewall insulating film. A featured semiconductor device. A fourth semiconductor region formed on the surface region of the semiconductor substrate and spaced apart from the first, second, and third semiconductor regions;
A first gate insulating film formed on the semiconductor substrate between the third semiconductor region and the fourth semiconductor region;
A third control gate formed on the first gate insulating film;
A third sidewall insulating film formed on a side surface of the third control gate;
A fifth semiconductor region formed on the surface region of the semiconductor substrate and spaced apart from the first, second, third, and fourth semiconductor regions;
A second gate insulating film formed on the semiconductor substrate between the fourth semiconductor region and the fifth semiconductor region;
A fourth control gate formed on the second gate insulating film;
A fourth sidewall insulating film formed on a side surface of the fourth control gate;
Further comprising
The surface of the fourth semiconductor region in contact with each of the third and fourth sidewall insulating films is higher than the surface of the fourth semiconductor region between the third sidewall insulating film and the fourth sidewall insulating film,
The surface of the fourth semiconductor region between the third sidewall insulating film and the fourth sidewall insulating film is the surface of the second semiconductor region between the first sidewall insulating film and the second sidewall insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is lower. A first protective film formed between a side surface of the first floating gate and a side surface of the first control gate, and the first sidewall insulating film;
A second protective film formed between a side surface of the second floating gate and a side surface of the second control gate, and the second sidewall insulating film;
The semiconductor device according to claim 1, further comprising:   In the first, second, and third semiconductor regions, semiconductor regions having an impurity concentration higher than that of the first, second, and third semiconductor regions are formed in a self-aligned manner with respect to the first and second sidewall insulating films. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. Forming a first insulating film on the semiconductor substrate;
Forming a first conductive film on the first insulating film;
Forming an element isolation region in the semiconductor substrate on which the first conductive film is formed;
Forming a second insulating film on the first conductive film and the element isolation region;
Forming a second conductive film on the second insulating film;
The first insulating film, the first conductive film, the second insulating film, and the second conductive film are processed to form a first tunnel insulating film, a first floating gate, and a first gate on the semiconductor substrate. A first stacked gate stacked in the order of the insulating film and the first control gate, a second stacked stack stacked in the order of the second tunnel insulating film, the second floating gate, the second inter-gate insulating film, and the second control gate. Forming a gate;
Forming a source region or a drain region in the semiconductor substrate between the first stacked gate and the second stacked gate;
Forming a third insulating film on the first stacked gate, on the second stacked gate, and on the semiconductor substrate;
Processing the third insulating film by anisotropic etching to form a sidewall insulating film on the side surface of the first stacked gate and on the side surface of the second stacked gate;
Performing a self-aligned anisotropic etching on the sidewall insulating film formed on the side surface of the first stacked gate and on the side surface of the second stacked gate to reduce the height of the element isolation region; ,
A method for manufacturing a semiconductor device, comprising:

Images