JP2005235891A - Non-volatile semiconductor memory apparatus and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory apparatus that is highly reliable, and wherein a diffused layer and a contact of a select transistor are electrically and appropriately connected and the surface of the diffused layer of a memory cell transistor are protected from etching; and to provide its manufacturing method. <P>SOLUTION: The method for manufacturing the non-volatile semiconductor memory apparatus includes a step to form an element isolation film in the element isolation area of a p-type silicon substrate 1; a step to cover a laminated gate provided with a floating gate electrode 6 and a control gate electrode 8, a selection gate electrode of the select transistor, n-type diffused layers 3, 4 and 10, a gate electrode of a high-voltage transistor, and an LDD layer of the high-voltage transistor and to form a mask material; a step to etch an element isolation insulating film by using the mask material as an etching mask; and step to inject n-type dopants to the upper part of the p-type silicon substrate 1 while the mask material is used as a mask. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  Among semiconductor memory devices, electrically rewritable nonvolatile semiconductor memory devices (EEPROM) require a voltage of about 10 to 20 V for writing and erasing. On the other hand, the interface and the logic unit are driven at 1 to 5 V, for example. In such a nonvolatile semiconductor memory device, a high voltage system circuit that handles a voltage of about 10 to 20 V and a low voltage system circuit that handles a voltage of about 1 to 5 V are mixed on the same semiconductor chip. This is because the high-voltage transistor and the low-voltage transistor cannot generally achieve the required performance in terms of withstand voltage and driving capability. The same applies to a semiconductor chip in which an EEPROM and a logic LSI are mixedly mounted.

  A method of manufacturing this conventional nonvolatile semiconductor memory device will be described with reference to FIGS. 11 to 14 are sectional views showing a conventional method for manufacturing a nonvolatile semiconductor memory device in the order of steps. In this example, a memory cell unit is formed in the memory cell formation region MCR, a low voltage transistor is formed in the low voltage transistor formation region LVR, and a high voltage transistor is formed in the high voltage transistor formation region HVR. Will be explained.

  First, a trench groove is formed in the element isolation region of the P-type silicon substrate 1, and an element isolation insulating film (not shown) is filled in the trench groove. Subsequently, in the element region on the P-type silicon substrate 101, a thin gate insulating film 102 is formed in the memory cell forming region MCR and the low voltage transistor forming region LVR, and a thick gate insulating film is formed in the high voltage transistor forming region HVR. A film 103 is formed.

  Next, in the memory cell formation region MCR, the floating gate electrode 104, the inter-gate insulating film 105, the control gate electrode 106, and the gate cap film 107 are sequentially stacked on the gate insulating film 102 to form a stacked gate. In the memory cell formation region MCR, the selection gate electrode 108, the inter-gate insulating film 109, the selection gate electrode 110, and the gate cap film 111 are sequentially stacked on the gate insulating film 102 to form the selection gate electrode of the selection transistor. . Further, in the low voltage transistor formation region LVR, gate electrodes 112 and 113 and a gate cap film 114 are sequentially stacked on the gate insulating film 102 to form a gate electrode of the low voltage transistor. Further, in the high voltage transistor formation region HVR, gate electrodes 115 and 116 and a gate cap film 117 are sequentially stacked on the gate insulating film 103 to form a gate electrode of the high voltage transistor.

  Next, as shown in FIG. 11, the element isolation insulating film and the gate insulating films 102 and 103 are etched using the gate cap films 107, 111, 114, and 117 as an etching mask.

  Next, as shown in FIG. 12, a gate barrier film 118 is formed on the side walls of the stacked gate and the exposed upper surface of the P-type silicon substrate 101. Then, ion implantation is performed using the stacked gate as a mask to form a low concentration N-type diffusion layer. By this step, N-type diffusion layers 119, 120, 121, 122 and LDD diffusion layers 123, 124, 125, 126 are formed on the P-type silicon substrate 101.

  Next, as shown in FIG. 13, a region in which a high-concentration N-type diffusion layer is formed in the peripheral transistor region (low-voltage transistor formation region LVR and high-voltage transistor formation region HVR), and N-type diffusion layer 121 A resist is patterned by photolithography so that the upper surface of the substrate is opened, and ion implantation is performed using the resist as a mask to form a high-concentration N-type diffusion layer. By this step, impurities are further implanted into the N-type diffusion layer 121, and N-type diffusion layers 127, 128, 129, and 130 are formed on the P-type silicon substrate 101 in the peripheral transistor region.

  Then, the contact barrier film 131 and the interlayer insulating film 132, the contact hole, and the bit line contact 133 and the bit line 134 are sequentially formed by a known method as shown in FIG. Thus, a conventional nonvolatile semiconductor memory device is completed.

  When the gate barrier film 118 and the contact barrier film 131 are deposited when the upper surface of the element isolation insulating film is higher than the upper surface of the N-type diffusion layer 121, the gate barrier is formed at the step portion between the element isolation insulating film and the N-type diffusion layer 121. Film 118 and contact barrier film 131 are deposited thick. Then, when the contact hole is formed by etching the interlayer insulating film 132, the gate barrier film 118 and the contact barrier film 131 deposited on the step portion between the element isolation insulating film and the N-type diffusion layer 121 are not sufficiently removed. The gate barrier film 118 and the contact barrier film 131 remain in a spacer shape on the side surfaces on both sides of the element isolation insulating film. Then, the contact area between the bit line contact 133 and the N-type diffusion layer 121 is remarkably reduced, resulting in an effective reduction in cell current.

However, in this conventional method for manufacturing a nonvolatile semiconductor memory device, the element isolation insulating film is etched in advance before the gate barrier film 118 and the contact barrier film 131 are formed. That is, the level difference between the element isolation insulating film and the N-type diffusion layer 121 is reduced, and the amounts of the gate barrier film 118 and the contact barrier film 131 remaining in the form of spacers on the side surfaces of the element isolation insulating film are reduced. For this reason, the conventional method for manufacturing a nonvolatile semiconductor memory device increases the contact area between the bit line contact 133 and the N-type diffusion layer 121, and electrically improves the bit line contact 133 and the N-type diffusion layer 121. A connection state can be obtained.
Japanese Patent Laying-Open No. 2002-57230 (page 14, FIG. 7)

  In the above conventional method for manufacturing a nonvolatile semiconductor memory device, the gate insulating films 102 and 103 are etched under such a condition that only the gate insulating films 102 and 103 are etched without etching the P-type silicon substrate 101. However, it is generally difficult to ensure a sufficient selection ratio at this time. For this reason, when the gate insulating films 102 and 103 are etched, the surface of the P-type silicon substrate 101 is also slightly etched. The etching of the surface of the P-type silicon substrate 101 is particularly remarkable in the memory cell formation region MCR and the low-voltage transistor formation region LVR where the gate insulating film is thin. This is because the etching amount of the gate insulating film is adjusted so as to remove the thick gate insulating film 103, and therefore, the memory cell formation region MCR provided with the gate insulating film 102 thinner than the gate insulating film 103 and the low gate insulating film 103. This is because, in the voltage transistor formation region LVR, the P-type silicon substrate 101 is etched accordingly.

  If the surface of the P-type silicon substrate 101 is etched in the memory cell formation region MCR, it becomes a source of crystal defects or heavy metal contamination is likely to occur. For this reason, the conventional nonvolatile semiconductor memory device manufacturing method cannot provide a highly reliable nonvolatile semiconductor memory device.

  The present invention has been made from the above background, and the reliability is such that the diffusion layer of the selection transistor and the contact are electrically well connected, and the surface of the diffusion layer of the memory cell transistor is protected from etching. An object of the present invention is to provide a high-volatile nonvolatile semiconductor memory device and a method for manufacturing the same.

  In order to achieve the above object, a non-volatile semiconductor memory device according to the present invention has a first conductivity type having first and second element regions and an element isolation region that separates the first and second element regions. In the first semiconductor region and the first element region, the first and second diffusion layers of the second conductivity type are provided on the upper portion of the semiconductor substrate so as to be spaced apart from each other. A memory cell unit having at least one memory cell transistor in which a stacked gate having a floating gate electrode and a control gate electrode is provided on the semiconductor substrate via a first insulating film between the diffusion layers; In the first element region, third and fourth diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and between the third diffusion layer and the fourth diffusion layer. In the semiconductor group A selection gate electrode provided on the first insulating film via the first insulating film, the third diffusion layer connected in series to the memory cell unit, and the fourth diffusion layer of the selection transistor; A contact provided in contact with the upper surface and a height of the upper surface of the region adjacent to the fourth diffusion layer provided in the element isolation region of the semiconductor substrate are higher than the height of the upper surface of the first insulating film. A lower element isolation insulating film, and in the second element region, fifth and sixth diffusion layers of the second conductivity type are provided on the semiconductor substrate and spaced apart from each other, and the fifth diffusion layer and Between the sixth diffusion layer, a gate electrode is provided on the semiconductor substrate via a second insulating film thicker than the first insulating film, and among the fifth and sixth diffusion layers, The region adjacent to the gate electrode Covering said second insulating film is characterized by comprising a peripheral transistor provided.

  A nonvolatile semiconductor memory device according to the present invention includes a first conductivity type semiconductor substrate having first and second element regions and an element isolation region that separates the first and second element regions, In the first element region, first and second diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and between the first diffusion layer and the second diffusion layer. A memory cell unit having at least one memory cell transistor in which a stacked gate having a floating gate electrode and a control gate electrode is provided on the semiconductor substrate via a first insulating film; and the first element region. The third conductivity type third and fourth diffusion layers are spaced apart from each other on the semiconductor substrate, and the semiconductor substrate is disposed between the third diffusion layer and the fourth diffusion layer. Said first insulation A selection transistor in which a selection gate electrode is provided, the third diffusion layer connected in series to the memory cell unit, and a contact provided in contact with the upper surface of the fourth diffusion layer of the selection transistor And an element isolation insulating film provided in the element isolation region of the semiconductor substrate, the height of the upper surface of the region adjacent to the fourth diffusion layer being lower than the height of the upper surface of the first insulating film; In the second element region, fifth and sixth diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and the fifth diffusion layer and the sixth diffusion layer In the meantime, a seventh conductivity type second diffusion layer having an impurity concentration lower than that of the fifth diffusion layer is provided in contact with the fifth diffusion layer, and the fifth diffusion layer and the sixth diffusion layer are provided. From the sixth diffusion layer between the layers An eighth diffusion layer of a second conductivity type having a low impurity concentration is provided in contact with the sixth diffusion layer, and the first insulation is provided between the seventh diffusion layer and the eighth diffusion layer. A peripheral transistor in which a gate electrode is provided on the semiconductor substrate through a second insulating film thicker than the film, and the second insulating film is provided to cover the seventh and eighth diffusion layers. It is characterized by doing.

  Furthermore, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a first conductive type semiconductor substrate having first and second element regions and an element isolation region that separates the first and second element regions. The step of forming an element isolation insulating film in the element isolation region, the step of forming a first insulating film on the semiconductor substrate in the first element region, and the step of forming the first element region in the second element region. Forming a second insulating film thicker than the first insulating film on the semiconductor substrate; forming a stacked gate having a floating gate electrode and a control gate electrode on the first insulating film; Forming a selection gate electrode on the first insulating film apart from the stacked gate; forming a gate electrode on the second insulating film; and in the first element region The top of the semiconductor substrate A step of forming first and second diffusion layers of a second conductivity type with the stacked gate interposed therebetween; and a second conductivity type with the selection gate electrode sandwiched between the first element region and the semiconductor substrate. Forming the third and fourth diffusion layers, and forming the fifth and sixth diffusion layers of the second conductivity type with the gate electrode sandwiched above the semiconductor substrate in the second element region The first insulating film on the fourth diffusion layer, the second insulating film on the region of the fifth and sixth diffusion layers separated from the gate electrode, and A step of etching the element isolation insulating film; and a step of implanting a second conductivity type impurity into the fourth diffusion layer and a region of the fifth and sixth diffusion layers separated from the gate electrode. It is characterized by comprising.

  According to the present invention, a highly reliable nonvolatile semiconductor memory device in which the diffusion layer of the selection transistor and the contact are electrically connected well and the surface of the diffusion layer of the memory cell transistor is protected from etching, and A manufacturing method thereof can be provided.

  Embodiments of a nonvolatile semiconductor memory device and a method for manufacturing the same according to the present invention will be described below with reference to FIGS. In this embodiment, a NAND type nonvolatile semiconductor memory device will be described as an example of the nonvolatile semiconductor memory device.

  First, the structure of the memory cell array of the nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIGS. FIG. 1 is a plan view showing the structure of the memory cell array of the nonvolatile semiconductor memory device according to this embodiment, and FIG. 2 is a cross-sectional view taken along line AA of the memory cell array shown in FIG. .

  An element isolation region is provided in the upper part of the P-type silicon substrate 1 so as to surround the element region 2, and a trench groove for element isolation is provided in the element isolation region. An element isolation insulating film such as a silicon dioxide film is embedded in the trench groove, and the element region 2 is thereby electrically isolated.

  In the element region 2 of the P-type silicon substrate 1, a plurality of memory cell transistors are connected in series sharing a source and a drain, and a memory cell unit is configured by the plurality of memory cell transistors. In each memory cell transistor, an N-type diffusion layer 3 (first diffusion layer) and an N-type diffusion layer 4 (second diffusion layer) are provided apart from each other on the P-type silicon substrate 1. Yes. These N-type diffusion layers 3 and 4 serve as the source or drain of the memory cell transistor. A floating gate electrode 6 is provided on the P-type silicon substrate 1 between the N-type diffusion layer 3 and the N-type diffusion layer 4 via a gate insulating film 5 (first insulating film). Further, a control gate electrode 8 is provided on the floating gate electrode 6 via an inter-gate insulating film 7, and a gate cap film 9 is provided on the control gate electrode 8. The control gate electrode 8 and the gate cap film 9 are vertically processed in a self-aligned manner so that the side edges thereof are aligned with the floating gate electrode 6, and the floating gate electrode 6, the control gate electrode 8, and the gate cap film 9 store the memory. A stacked gate of the cell transistor is formed. Thus, each memory cell transistor has a stacked gate, and this stacked gate operates as a memory cell.

  At both ends of the plurality of memory cell transistors connected in series, the selection transistor is connected in series while sharing the N-type diffusion layer 10 (third diffusion layer) at the outermost end of the memory cell transistor. In the selection transistor, an N-type diffusion layer 11 (fourth diffusion layer) is provided above the P-type silicon substrate 1 so as to be separated from the N-type diffusion layer 10. These N-type diffusion layers 10 and 11 serve as the source or drain of the selection transistor. A selection gate electrode 12 is provided on the P-type silicon substrate 1 via the gate insulating film 5 between the N-type diffusion layer 10 and the N-type diffusion layer 11. Further, a selection gate electrode 14 is provided on the selection gate electrode 12 via an inter-gate insulating film 13, and a gate cap film 15 is provided on the selection gate electrode 14. The selection gate electrode 14 and the gate cap film 15 are vertically processed in a self-aligned manner so that the side edges thereof are aligned with the selection gate electrode 12, and the selection transistor is selected by the selection gate electrodes 12, 14 and the gate cap film 15. A gate electrode is formed. The selection gate electrode 14 is short-circuited to the selection gate electrode 12 so that a signal is directly applied from the selection gate electrode 14 to the selection gate electrode 12. The stacked gate of the memory cell transistor and the select gate electrode of the select transistor are covered with a gate barrier film 16 and a contact barrier film 17 (third insulating film) which are insulating films.

  An upper surface of the N type diffusion layer 11 of the selection transistor is opened to provide an interlayer insulating film 18, and a bit line contact 19 and a source line contact 20 are in contact with the upper surface of the N type diffusion layer 11 in the opening of the interlayer insulating film 18. Is provided. The bit line contact 19 and the source line contact 20 are electrically separated from the selection gate electrode of the selection transistor by the gate barrier film 16 and the contact barrier film 17. The bit line contact 19 is connected to the bit line 21 and the source line contact 20 is connected to a source line (not shown). The bit line contact 18 is adjacent to the stack gate of the select transistor via the gate barrier film 16 and the contact barrier film 17 on its side surface, and protrudes above the stack gate of the select transistor at the connection portion with the bit line 21. ing. That is, the bit line contact 19 is formed in a self-aligned manner with respect to the selection transistor. Similarly to the bit line contact 19, the source line contact 20 is also formed in a self-aligned manner with respect to the selection transistor. As described above, since the nonvolatile semiconductor memory device according to this example employs the self-aligned contact structure, the memory cell array length in the bit line 21 direction can be reduced.

  FIG. 3 shows a cross-sectional view along the line BB of the memory cell array shown in FIG. In the element isolation region, a trench groove for element isolation is provided above the P-type silicon substrate 1, and a silicon oxide film 22 as an element isolation insulating film is embedded in the trench groove. An interlayer insulating film 18 is provided on the P-type silicon substrate 1. A contact hole reaching the upper surface of the N-type diffusion layer 11 is provided in the interlayer insulating film 18, and a bit line contact 19 is provided in contact with the upper surface of the N-type diffusion layer 11 inside the contact hole.

  In the nonvolatile semiconductor memory device according to this example, the upper surface of the silicon oxide film 22 is lower than the upper surface of the gate insulating film 5, and the level difference between the N-type diffusion layer 11 and the silicon oxide film 22 is low. It has become. For this reason, the amount of the gate barrier film 16 and the contact barrier film 17 remaining in a spacer shape on the side surface of the silicon oxide film 22 is reduced, and as a result, the contact area between the bit line contact 19 and the N-type diffusion layer 11 is increased. Thus, an electrically good connection state between the N-type diffusion layer 11 and the bit line contact 19 is obtained.

  Next, the structure of the transistors constituting the peripheral circuit of the nonvolatile semiconductor memory device according to this example is described with reference to FIG. The peripheral circuit of the memory cell array shown in FIGS. 1 to 3 is generally composed of MOS transistors. The peripheral circuit is roughly composed of two types of transistors, a high voltage transistor and a low voltage transistor. 4A shows the structure of a low voltage transistor, and FIG. 4B shows the structure of a high voltage transistor.

  The low voltage transistor includes N-type diffusion layers 23 and 24, LDD diffusion layers 25 and 26, a gate insulating film 5 and gate electrodes 27 and 28, and a gate cap film 29. An N-type diffusion layer 23 and an N-type diffusion layer 24 are provided apart from each other on the P-type silicon substrate 1. These N-type diffusion layers serve as the source or drain of the low voltage transistor. An LDD diffusion layer 25 is provided in contact with the N-type diffusion layer 23 between the N-type diffusion layer 23 and the N-type diffusion layer 24 above the P-type silicon substrate 1, and the LDD diffusion layer 26 is provided with the N-type diffusion layer. It is provided in contact with the layer 24. These LDD diffusion layers 25 and 26 are N-type having a lower impurity concentration than the N-type diffusion layers 23 and 24. Gate electrodes 27 and 28 are provided on the P-type silicon substrate 1 via the gate insulating film 5 between the LDD diffusion layer 25 and the LDD diffusion layer 26, and a gate cap film 29 is formed on the gate electrode 28. Is provided. The gate electrode 27 and the gate electrode 28 are in contact with each other, and the gate electrodes 27 and 28 form the gate electrode of the low voltage transistor.

  The high voltage transistor includes an N type diffusion layer 30 (fifth diffusion layer), an N type diffusion layer 31 (sixth diffusion layer), an LDD diffusion layer 32 (seventh diffusion layer), and an LDD diffusion layer 33 (first element). 8 diffusion layers), a gate insulating film 34 (second insulating film), gate electrodes 35 and 36, and a gate cap film 37. An N-type diffusion layer 30 and an N-type diffusion layer 31 are provided apart from each other on the P-type silicon substrate 1. These N-type diffusion layers serve as the source or drain of the high voltage transistor. Further, an LDD diffusion layer 32 is provided in contact with the N-type diffusion layer 30 between the N-type diffusion layer 30 and the N-type diffusion layer 31 above the P-type silicon substrate 1, and the LDD diffusion layer 33 is provided with the N-type diffusion layer. It is provided in contact with the layer 31. These LDD diffusion layers 32 and 33 are N-type having a lower impurity concentration than the N-type diffusion layers 30 and 31. In addition, gate electrodes 35 and 36 are provided on the P-type silicon substrate 1 via the gate insulating film 34 between the LDD diffusion layer 32 and the LDD diffusion layer 33, and a gate cap film 37 is provided on the gate electrode 36. Is provided. The gate electrode 35 and the gate electrode 36 are in contact with each other, and the gate electrodes 35 and 36 form the gate electrode of the high voltage transistor.

  Note that the gate insulating film 34 of the high-voltage transistor is formed thicker than the gate insulating film 5 of the low-voltage transistor so as not to be destroyed by the high voltage. The gate insulating film 34 is provided so as to cover the LDD diffusion layer 32, the LDD diffusion layer 33, and the space between the LDD diffusion layer 32 and the LDD diffusion layer 33. Further, the high-voltage transistor has a longer distance from the N-type diffusion layer to the gate electrode (distance provided with the LDD diffusion layer) than the low-voltage transistor.

  Next, a method for manufacturing the nonvolatile semiconductor memory device according to this example shown in FIGS. 1 to 4 will be described with reference to FIGS. 5 to 10 are cross-sectional views showing the method of manufacturing the nonvolatile semiconductor memory device according to this example in the order of steps. Here, the memory cell shown in FIG. 2 is formed in the memory cell formation region MCR, the low-voltage transistor shown in FIG. 4A is formed in the low-voltage transistor formation region LVR, and the high-voltage transistor A case where the high voltage transistor shown in FIG. 4B is formed in the formation region HVR will be described.

  First, a trench groove is formed in the element isolation region of the P-type silicon substrate 1, and a silicon oxide film 22 as an element isolation insulating film is filled in the trench groove. By this step, the memory cell formation region MCR (first element region), the low voltage transistor formation region LVR, and the high voltage transistor formation region HVR (second element region) are electrically isolated. Then, as shown in FIG. 5, a thin gate insulating film 5 is formed in the memory cell forming region MCR and the low voltage transistor forming region LVR, and a thick gate insulating film 34 is formed in the high voltage transistor forming region HVR. Form.

  Next, as shown in FIG. 6, a polysilicon film 38 to be the floating gate electrode 6, the selection gate electrode 12, and the gate electrodes 27 and 35 is formed. Then, after an ONO film 39 (a film in which an oxide film, a nitride film, and an oxide film are sequentially stacked) to be an intergate insulating film 13 is formed on the polysilicon film 38, a peripheral transistor region (low voltage transistor formation region) The ONO film 39 formed in the LVR and the high voltage transistor formation region HVR) is removed. For example, a resist is patterned by opening the peripheral transistor region by photolithography, and the ONO film 39 exposed in the peripheral transistor region is etched using the resist as an etching mask. Subsequently, a polysilicon film 40 to be the control gate electrode 8, the selection gate electrode 14, and the gate electrodes 28 and 36 is formed. Further, a gate mask material 41 which becomes an etching mask at the time of laminated gate processing is formed on the polysilicon film 40.

  Next, a resist is patterned by photolithography so as to cover the region where the stacked gate is to be formed, and using this resist as an etching mask, for example, by anisotropic etching, the gate mask material 41, the polysilicon film 40, the ONO film 39, and The polysilicon film 38 is sequentially patterned. By this step, as shown in FIG. 7, in the memory cell formation region MCR, the stacked gate of the memory cell transistor is formed by the floating gate electrode 6, the control gate electrode 8, and the gate cap film 9, and the select gate electrodes 12, 14 and A selection gate electrode of the selection transistor is formed by the gate cap film 15. In the low voltage transistor formation region LVR, the gate electrodes of the low voltage transistor are formed by the gate electrodes 27 and 28. In the high voltage transistor formation region HVR, the gate electrodes of the high voltage transistor are formed by the gate electrodes 35 and 36. Is formed. In this step, the gate insulating films 5 and 34 may be slightly etched when the polysilicon film 38 is etched, but the P-type silicon substrate 1 is not exposed if there is an appropriate selection ratio. Subsequently, for example, post-gate oxidation at about 850 ° C. and about 5 nm is performed in an oxygen atmosphere to form the gate barrier film 16.

  Next, for example, ion implantation of N-type impurities such as phosphorus is performed using the stacked gate of the memory cell transistor, the selection gate electrode of the selection transistor, the gate electrode of the low voltage transistor, and the gate electrode of the high voltage transistor as a mask. Thereby, an LDD diffusion layer is formed. As a result of this step, as shown in FIG. 8, in the memory cell formation region MCR, N-type diffusion layers 3 and 4 are formed on the P-type silicon substrate 1 with the stacked gates of the memory cell transistors interposed therebetween. N-type diffusion layers 10 and 11 are formed with the selection gate electrode interposed therebetween. In the low-voltage transistor formation region LVR, LDD diffusion layers 25 and 26 are formed on the P-type silicon substrate 1 with the gate electrode of the low-voltage transistor interposed therebetween. In the high-voltage transistor formation region HVR, LDD diffusion layers 32 and 33 are formed across the gate electrode of the voltage transistor.

  Next, as shown in FIG. 9, in the memory cell formation region MCR, gate insulation is performed so that the stacked gate of the memory cell transistor, the selection gate electrode of the selection transistor, and the N-type diffusion layers 3, 4, 10, and 11 are covered. A resist 42 (mask material) is patterned on the film 5 by photolithography. In the low voltage transistor formation region LVR, the gate electrode of the low voltage transistor and the region adjacent to the gate electrode of the low voltage transistor among the LDD diffusion layers 25 and 26 are covered on the gate insulating film 5. The resist 42 is patterned. Further, in the high-voltage transistor formation region HVR, the gate electrode of the high-voltage transistor and the region adjacent to the gate electrode of the high-voltage transistor among the LDD diffusion layers 32 and 33 are covered on the gate insulating film 34. The resist 42 is patterned.

  Next, as shown in FIG. 10, using the resist 42 as an etching mask, the gate insulating films 5 and 34 and the silicon oxide film 22 not covered with the resist 42 are etched by, for example, anisotropic etching. By this step, the upper surface of the silicon oxide film 22 becomes lower than the upper surface of the gate insulating film 5 below the stacked gate of the memory cell transistor or the selection gate electrode of the selection transistor. Subsequently, N-type impurities such as arsenic are ion-implanted into the upper portion of the P-type silicon substrate 1 not covered with the resist 42 using the resist 42 as a mask. By this step, impurities are further implanted into the N-type diffusion layer 11 in the memory cell formation region MCR. The reason why the impurity concentration of the N-type diffusion layer 11 is made high is to reduce the contact resistance with the bit line contact 19 or the source line contact 20 to be formed later. In addition, N-type diffusion layers 23 and 24 are formed in the low-voltage transistor formation region LVR, and N-type diffusion layers 30 and 31 are formed in the high-voltage transistor formation region HVR.

  Next, a contact barrier film 17 is formed covering the gate barrier film 16, and an interlayer insulating film 18 is further formed covering the contact barrier film 17. Subsequently, a contact hole reaching the upper surface of the N-type diffusion layer 11 is formed in the interlayer insulating film 18 and the contact hole is filled with a conductive material, so that the bit line is in contact with the upper surface of the N-type diffusion layer 11. A contact 19 and a source line contact 20 are formed. When forming the contact hole in the interlayer insulating film 18, the gate barrier film 16 and the contact barrier film 17 on the selection gate electrode of the selection transistor are used as etching masks in a self-aligned manner with respect to the selection gate electrode of the selection transistor. Contact holes are formed. Thereby, the nonvolatile semiconductor memory device according to this example shown in FIGS. 1 to 4 is completed.

  In the method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment described above, the memory cell unit including the memory cell transistor is covered with the resist 42 in the step of etching the silicon oxide film 22 using the resist 42 as an etching mask. . Therefore, in the method of manufacturing the nonvolatile semiconductor memory device according to this example, the substrate surface between the stacked gates of the memory cell transistors (the surface of the N-type diffusion layers 3 and 4 that are the source or drain of the memory cell transistor) is etched. Therefore, a highly reliable nonvolatile semiconductor memory device can be provided by preventing crystal defects and heavy metal contamination.

  In the method of manufacturing the nonvolatile semiconductor memory device according to this example, the resist 42 used as an etching mask in the step of etching the silicon oxide film 22 is used as a mask for ion implantation performed in the subsequent steps. That is, the mask used in the step of etching the silicon oxide film 22 and the step of ion implantation is shared. For this reason, the method for manufacturing the nonvolatile semiconductor memory device according to the present embodiment uses a mask such as photolithography as compared with the case where separate masks are used in the step of etching the silicon oxide film 22 and the step of ion implantation. The number of steps for forming the film is small, and the manufacturing cost can be reduced.

  Further, in the method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment, the silicon oxide film 22 that is the element isolation insulating film is etched to form the N-type diffusion layer 11 as in the conventional method of manufacturing the nonvolatile semiconductor memory device. By reducing the level difference between the upper surface and the upper surface of the silicon oxide film 22, the contact resistance between the bit line contact 19 and the source line contact 20 and the N-type diffusion layer 11 can be reduced.

  In the nonvolatile semiconductor memory device and the manufacturing method thereof according to the present embodiment, a NAND type nonvolatile semiconductor memory device is described as an example of the nonvolatile semiconductor memory device, but the nonvolatile semiconductor memory device is a NAND. It is not limited to a type nonvolatile semiconductor memory device. For example, even in a NOR type nonvolatile semiconductor memory device, the same effect as in the present embodiment can be obtained.

  In the nonvolatile semiconductor memory device and the manufacturing method thereof according to the present embodiment, a P-type silicon substrate is described as an example of the semiconductor substrate. However, the semiconductor substrate is not limited to the P-type silicon substrate.

  Furthermore, in the method for manufacturing the nonvolatile semiconductor memory device according to this example, post-gate oxidation is performed to form the gate barrier film 16, but this post-gate oxidation is not necessarily a necessary process. For example, heat treatment in a nitrogen atmosphere or the like instead of oxidation may be performed, and heat treatment may not be performed.

  Further, in the nonvolatile semiconductor memory device and the manufacturing method thereof according to this example, after the silicon oxide film 22 is etched using the resist 42 as an etching mask, ion implantation is performed using the resist 42 as a mask. The order is not limited to this. Even if the silicon oxide film 22 is etched using the resist 42 as an etching mask after ion implantation using the resist 42 as a mask, the same effect as in this embodiment can be obtained.

  Further, in the method of manufacturing the nonvolatile semiconductor memory device according to this embodiment, the stacked gate of the memory cell transistor, the selection gate electrode of the selection transistor, the gate electrode of the low voltage transistor, and the gate electrode of the high voltage transistor are provided. Although formed simultaneously, these gate electrodes are not necessarily formed simultaneously. For example, even when each gate electrode is formed separately, the same effect as in this embodiment can be obtained.

  Further, in the nonvolatile semiconductor memory device and the manufacturing method thereof according to this embodiment, the contact barrier film 17 (third insulating film) is formed so as to cover the stacked gate of the memory cell transistor and the select gate electrode of the select transistor. However, the contact barrier film 17 is not necessarily formed so as to cover the stacked gate of the memory cell transistor. In order to electrically isolate the bit line contact 19 and the source line contact 20 from the selection gate electrode of the selection transistor, at least the selection gate electrode of the selection transistor is adjacent to the N-type diffusion layer 11 (fourth diffusion layer). What is necessary is just to cover and form the part to perform.

  The present invention can be variously modified without departing from the scope of the invention in the implementation stage.

  As described above in detail, the characteristics of the nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention are summarized as follows.

  The nonvolatile semiconductor memory device according to the present invention includes a first conductivity type semiconductor substrate having first and second element regions and an element isolation region that separates the first and second element regions, and the first In the element region, first and second diffusion layers of the second conductivity type are provided on the semiconductor substrate and spaced apart from each other, and floating between the first diffusion layer and the second diffusion layer. In the first element region, a memory cell unit having at least one memory cell transistor in which a stacked gate having a gate electrode and a control gate electrode is provided on the semiconductor substrate via a first insulating film, and Third and fourth diffusion layers of the second conductivity type are provided on the semiconductor substrate so as to be spaced apart from each other, and the second conductivity type third and fourth diffusion layers are provided on the semiconductor substrate between the third diffusion layer and the fourth diffusion layer. 1 through insulation film A selection transistor having a selection gate electrode, the third diffusion layer connected in series to the memory cell unit, and a contact provided in contact with an upper surface of the fourth diffusion layer of the selection transistor; An element isolation insulating film provided in the element isolation region of the semiconductor substrate, the height of the upper surface of the region adjacent to the fourth diffusion layer being lower than the height of the upper surface of the first insulating film; In the second element region, fifth and sixth diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and between the fifth diffusion layer and the sixth diffusion layer. A gate electrode is provided on the semiconductor substrate via a second insulating film thicker than the first insulating film, and covers a region adjacent to the gate electrode in the fifth and sixth diffusion layers. The second insulating film is It is characterized by comprising a vignetting peripheral transistor.

  A nonvolatile semiconductor memory device according to the present invention includes a first conductivity type semiconductor substrate having first and second element regions and an element isolation region that separates the first and second element regions, In the first element region, first and second diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and between the first diffusion layer and the second diffusion layer. A memory cell unit having at least one memory cell transistor in which a stacked gate having a floating gate electrode and a control gate electrode is provided on the semiconductor substrate via a first insulating film; and the first element region. The third conductivity type third and fourth diffusion layers are spaced apart from each other on the semiconductor substrate, and the semiconductor substrate is disposed between the third diffusion layer and the fourth diffusion layer. Said first insulation A selection transistor in which a selection gate electrode is provided, the third diffusion layer connected in series to the memory cell unit, and a contact provided in contact with the upper surface of the fourth diffusion layer of the selection transistor And an element isolation insulating film provided in the element isolation region of the semiconductor substrate, the height of the upper surface of the region adjacent to the fourth diffusion layer being lower than the height of the upper surface of the first insulating film; In the second element region, fifth and sixth diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and the fifth diffusion layer and the sixth diffusion layer In the meantime, a seventh conductivity type second diffusion layer having an impurity concentration lower than that of the fifth diffusion layer is provided in contact with the fifth diffusion layer, and the fifth diffusion layer and the sixth diffusion layer are provided. From the sixth diffusion layer between the layers An eighth diffusion layer of a second conductivity type having a low impurity concentration is provided in contact with the sixth diffusion layer, and the first insulation is provided between the seventh diffusion layer and the eighth diffusion layer. A peripheral transistor in which a gate electrode is provided on the semiconductor substrate through a second insulating film thicker than the film, and the second insulating film is provided to cover the seventh and eighth diffusion layers. It is characterized by doing.

  Furthermore, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a first conductive type semiconductor substrate having first and second element regions and an element isolation region that separates the first and second element regions. The step of forming an element isolation insulating film in the element isolation region, the step of forming a first insulating film on the semiconductor substrate in the first element region, and the step of forming the first element region in the second element region. Forming a second insulating film thicker than the first insulating film on the semiconductor substrate; forming a stacked gate having a floating gate electrode and a control gate electrode on the first insulating film; Forming a selection gate electrode on the first insulating film apart from the stacked gate; forming a gate electrode on the second insulating film; and in the first element region The top of the semiconductor substrate A step of forming first and second diffusion layers of a second conductivity type with the stacked gate interposed therebetween; and a second conductivity type with the selection gate electrode sandwiched between the first element region and the semiconductor substrate. Forming the third and fourth diffusion layers, and forming the fifth and sixth diffusion layers of the second conductivity type with the gate electrode sandwiched above the semiconductor substrate in the second element region The first insulating film on the fourth diffusion layer, the second insulating film on the region of the fifth and sixth diffusion layers separated from the gate electrode, and A step of etching the element isolation insulating film; and a step of implanting a second conductivity type impurity into the fourth diffusion layer and a region of the fifth and sixth diffusion layers separated from the gate electrode. It is characterized by comprising.

  Furthermore, the manufacturing method of the nonvolatile semiconductor memory device according to the present invention includes the stacked gate, the first diffusion layer, the second diffusion layer, the third diffusion layer, the gate electrode, and the fifth. And a step of covering the region of the sixth diffusion layer adjacent to the gate electrode and forming a mask material on the first and second insulating films, the first insulating film, In the step of etching the second insulating film and the element isolation insulating film, the first insulating film, the second insulating film, and the element isolation insulating film are etched using the mask material as a mask, and the second insulating film and the element isolation insulating film are etched. In the step of implanting the conductivity type impurity, the second conductivity type impurity is implanted using the mask material as a mask.

  Further, the method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of etching the first insulating film, the second insulating film, and the element isolation insulating film, and implanting the second conductivity type impurity. A step of forming a third insulating film covering at least a portion of the select gate electrode adjacent to the fourth diffusion layer, covering the third insulating film, and Forming an interlayer insulating film on the semiconductor substrate; forming a contact hole reaching the upper surface of the fourth diffusion layer in the interlayer insulating film in a self-aligned manner with respect to the selection gate electrode; and the contact And a step of forming a contact in contact with the upper surface of the fourth diffusion layer by filling the inside of the hole with a conductive material.

1 is a plan view showing a structure of a memory cell of a nonvolatile semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view taken along a bit line showing the structure of a memory cell of a nonvolatile semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view taken along a word line showing the structure of a memory cell of a nonvolatile semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view showing a structure of a peripheral transistor of a nonvolatile semiconductor memory device according to an example of the present invention. Sectional drawing which shows the 1st process of the manufacturing method of the non-volatile semiconductor memory device based on the Example of this invention. Sectional drawing which shows the 2nd process of the manufacturing method of the non-volatile semiconductor memory device based on the Example of this invention. Sectional drawing which shows the 3rd process of the manufacturing method of the non-volatile semiconductor memory device based on the Example of this invention. Sectional drawing which shows the 4th process of the manufacturing method of the non-volatile semiconductor memory device based on the Example of this invention. Sectional drawing which shows the 5th process of the manufacturing method of the non-volatile semiconductor memory device based on the Example of this invention. Sectional drawing which shows the 6th process of the manufacturing method of the non-volatile semiconductor memory device based on the Example of this invention. Sectional drawing which shows the 1st process of the manufacturing method of the conventional non-volatile semiconductor memory device. Sectional drawing which shows the 2nd process of the manufacturing method of the conventional non-volatile semiconductor memory device. Sectional drawing which shows the 3rd process of the manufacturing method of the conventional non-volatile semiconductor memory device. Sectional drawing which shows the 4th process of the manufacturing method of the conventional non-volatile semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate 2 ... Element area | region 3, 4, 10, 11, 23, 24, 30, 31 ... N-type diffused layer 5, 34 ... Gate insulating film 6 ... Floating gate electrode 7, 13 ... Inter-gate insulating film 8 ... Control gate electrodes 9, 15, 29, 37 ... Gate cap films 12, 14 ... Selection gate electrode 16 ... Gate barrier film 17 ... Contact barrier film 18 ... Interlayer insulating film 19 ... Bit line contact 20 ... Source line contact 21 ... Bit line 22 ... Silicon oxide films 25, 26, 32, 33 ... LDD diffusion layers 27, 28, 35, 36 ... Gate electrodes 38, 40 ... Polysilicon film 39 ... ONO film 41 ... Gate mask material 42 ... Resist

Claims (5)

A first conductivity type semiconductor substrate having first and second element regions and an element isolation region for separating the first and second element regions;
In the first element region, first and second diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and between the first diffusion layer and the second diffusion layer. A memory cell unit having at least one memory cell transistor in which a stacked gate having a floating gate electrode and a control gate electrode is provided on the semiconductor substrate via a first insulating film;
In the first element region, third and fourth diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and between the third diffusion layer and the fourth diffusion layer. A selection transistor in which a selection gate electrode is provided on the semiconductor substrate via the first insulating film, and the third diffusion layer is connected in series to the memory cell unit;
A contact provided in contact with an upper surface of the fourth diffusion layer of the selection transistor;
An element isolation insulating film provided in the element isolation region of the semiconductor substrate, the height of the upper surface of the region adjacent to the fourth diffusion layer being lower than the height of the upper surface of the first insulating film;
In the second element region, fifth and sixth diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and the fifth diffusion layer and the sixth diffusion layer In the meantime, a gate electrode is provided on the semiconductor substrate via a second insulating film thicker than the first insulating film, and a region adjacent to the gate electrode in the fifth and sixth diffusion layers And a peripheral transistor provided with the second insulating film. A first conductivity type semiconductor substrate having first and second element regions and an element isolation region for separating the first and second element regions;
In the first element region, first and second diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and between the first diffusion layer and the second diffusion layer. A memory cell unit having at least one memory cell transistor in which a stacked gate having a floating gate electrode and a control gate electrode is provided on the semiconductor substrate via a first insulating film;
In the first element region, third and fourth diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and between the third diffusion layer and the fourth diffusion layer. A selection transistor in which a selection gate electrode is provided on the semiconductor substrate via the first insulating film, and the third diffusion layer is connected in series to the memory cell unit;
A contact provided in contact with an upper surface of the fourth diffusion layer of the selection transistor;
An element isolation insulating film provided in the element isolation region of the semiconductor substrate, the height of the upper surface of the region adjacent to the fourth diffusion layer being lower than the height of the upper surface of the first insulating film;
In the second element region, fifth and sixth diffusion layers of the second conductivity type are provided apart from each other above the semiconductor substrate, and the fifth diffusion layer and the sixth diffusion layer In the meantime, a seventh conductivity type second diffusion layer having an impurity concentration lower than that of the fifth diffusion layer is provided in contact with the fifth diffusion layer, and the fifth diffusion layer and the sixth diffusion layer are provided. An eighth diffusion layer of the second conductivity type having an impurity concentration lower than that of the sixth diffusion layer is provided in contact with the sixth diffusion layer, and the seventh diffusion layer and the A gate electrode is provided on the semiconductor substrate through a second insulating film thicker than the first insulating film between the eight diffusion layers and covers the seventh and eighth diffusion layers. And a peripheral transistor provided with a second insulating film. Location. Forming a device isolation insulating film in the device isolation region in a first conductivity type semiconductor substrate having first and second device regions and device isolation regions separating the first and second device regions; ,
Forming a first insulating film on the semiconductor substrate in the first element region;
Forming a second insulating film thicker than the first insulating film on the semiconductor substrate in the second element region;
Forming a stacked gate having a floating gate electrode and a control gate electrode on the first insulating film;
Forming a selection gate electrode on the first insulating film and spaced apart from the stacked gate;
Forming a gate electrode on the second insulating film;
Forming a second conductivity type first and second diffusion layer on the semiconductor substrate with the stacked gate interposed therebetween in the first element region;
Forming a second conductive type third and fourth diffusion layer on the semiconductor substrate with the selection gate electrode interposed therebetween in the first element region;
Forming, in the second element region, fifth and sixth diffusion layers of second conductivity type on the semiconductor substrate with the gate electrode interposed therebetween;
The first insulating film on the fourth diffusion layer, the second insulating film on a region of the fifth and sixth diffusion layers separated from the gate electrode, and the element isolation insulating film Etching the step,
And a step of injecting a second conductivity type impurity into a region of the fourth diffusion layer and the fifth and sixth diffusion layers separated from the gate electrode. For manufacturing a conductive semiconductor memory device. A region adjacent to the gate electrode in the stacked gate, the first diffusion layer, the second diffusion layer, the third diffusion layer, the gate electrode, and the fifth and sixth diffusion layers And further comprising a step of forming a mask material on the first and second insulating films,
In the step of etching the first insulating film, the second insulating film, and the element isolation insulating film, the first insulating film, the second insulating film, and the element isolation insulating are performed using the mask material as a mask. Etching the film,
4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein in the step of implanting the second conductivity type impurity, the second conductivity type impurity is implanted using the mask material as a mask. After the step of etching the first insulating film, the second insulating film, and the element isolation insulating film, and the step of implanting the impurity of the second conductivity type, at least the first of the selection gate electrodes Forming a third insulating film covering a portion adjacent to the diffusion layer of 4;
Covering the third insulating film and forming an interlayer insulating film on the semiconductor substrate;
Forming a contact hole reaching the upper surface of the fourth diffusion layer in the interlayer insulating film in a self-aligned manner with respect to the selection gate electrode;
5. The method according to claim 3, further comprising: forming a contact in contact with an upper surface of the fourth diffusion layer by filling the contact hole with a conductive material. A method for manufacturing a nonvolatile semiconductor memory device according to claim.

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