JP4811325B2 - III-V nitride semiconductor substrate and method for manufacturing the same - Google Patents

Description

  The present invention relates to a group III-V nitride semiconductor substrate having excellent surface properties by suppressing crystal defects, and a method for manufacturing the same, and in particular, an epitaxial layer in which uneven surface steps are suppressed to be small can be formed. The present invention relates to a group III-V nitride semiconductor substrate and a method for manufacturing the same.

  Conventionally, III-V group nitride semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), and gallium aluminum nitride (GaAlN) have a sufficiently large forbidden band, and the interband transition is also a direct transition type. Therefore, application to short wavelength light emitting elements such as semiconductor laser elements and light emitting diodes has been actively studied. In addition, application to electronic devices such as field effect transistors is also expected due to the fact that the saturation drift velocity of electrons is high and the use of two-dimensional carrier gas by heterojunction is possible.

  Group III-V nitride semiconductor layers constituting these elements are formed by vapor phase growth methods such as metal organic growth (MOVPE), molecular beam vapor phase epitaxy (MBE), and hydride vapor phase epitaxy (HVPE). And produced by epitaxial growth on the underlying substrate. However, there is no underlying substrate whose lattice constant matches that of the III-V nitride semiconductor layer. Therefore, it is difficult to obtain a high-quality growth layer, and many crystal defects were included in the obtained III-V group nitride semiconductor layer. Since the crystal defect becomes a factor that hinders improvement in device characteristics, studies for reducing the crystal defect in the group III-V nitride semiconductor layer have been actively conducted.

  As a method for obtaining a group III nitride crystal having relatively few crystal defects, a low temperature deposition buffer layer (buffer layer) is formed on a different substrate (sapphire substrate) such as sapphire as a base substrate, and the low temperature deposition buffer is formed. A method of forming an epitaxial growth layer (epi layer) on the layer is known. In the crystal growth method using this low-temperature deposition buffer layer, first, AlN or GaN is deposited on a sapphire substrate at around 500 ° C. to form an amorphous film or a continuous film partially containing polycrystal. Next, the sapphire substrate is heated to around 1000 ° C. to evaporate or crystallize part of the film to form crystal nuclei with a high density. Using this as a growth nucleus, a GaN film (GaN substrate) with relatively good crystallinity can be obtained.

  However, even if this method for forming the low temperature deposition buffer layer is used, the obtained GaN substrate has a problem that crystal defects such as threading dislocations and vacancies exist. The method of forming was still insufficient to obtain the currently desired high performance devices.

  In view of the above circumstances, a method of using a GaN substrate as a substrate for crystal growth and forming a semiconductor multilayer film constituting an element on the GaN substrate has been actively studied. Here, in this specification, the GaN substrate for crystal growth is referred to as a self-standing GaN substrate (GaN free-standing substrate). As a method for obtaining this GaN free-standing substrate, for example, ELO (Epitaxial Lateral Overgrowth) technology is known (see, for example, Non-Patent Document 1). This ELO method is a technique for obtaining a GaN layer with few dislocations by forming a mask having an opening on a base substrate and laterally growing from the opening of the mask.

  When this ELO method is used, for example, after forming a GaN layer on a sapphire substrate, the sapphire substrate can be removed by etching or the like to obtain a GaN free-standing substrate (see, for example, Patent Document 1).

  As a method that further develops the ELO method, for example, there is a FIELO (Facet-Initiated Epitaxial Lateral Overgrowth) method (see, for example, Non-Patent Document 2). This FIELO method is common to the ELO method in that selective growth is performed using a silicon oxide mask. However, the facet is formed in the mask opening portion during selective growth to change the propagation direction of dislocations and to change the upper surface of the epi layer. This is a technique for reducing threading dislocations leading to. By using this FIELO method, for example, if a thick GaN layer is grown on a sapphire substrate and then the sapphire substrate is removed, a high-quality GaN free-standing substrate with few crystal defects can be obtained.

  As another method for obtaining a low-dislocation GaN free-standing substrate, for example, there is a DEEP (Dislocation Elimination by the Epi-growth with Inverted-Pyramidal Pits) method (see, for example, Patent Document 2). In this DEEP method, a GaN layer is grown using a mask made of silicon nitride or the like patterned on a GaAs substrate, and a number of pits (holes) surrounded by facets are intentionally formed on the crystal surface. The dislocations are accumulated at the bottom of each of the other regions, thereby lowering the other regions.

  The ELO method, the FIELO method, and the DEEP method described above grow a crystal while exposing a facet surface at the crystal growth interface at the initial stage of crystal growth. Dislocations that propagate during crystal growth have the property of bending the direction of travel by the facet plane. By utilizing this, dislocation density on the substrate surface can be reduced by preventing dislocations from reaching the crystal surface. Further, when a crystal is grown while forming and maintaining pits surrounded by facet planes at the crystal growth interface, dislocations accumulate at a high density at the bottom of the pits. If dislocations accumulate at the bottom of the pit, dislocations that collide with each other disappear, or dislocation loops are formed to stop progressing to the substrate surface, effectively reducing the dislocation density on the substrate surface. Can be made.

  Since a GaN free-standing substrate is used as a semiconductor substrate by peeling or removing a thick epitaxially grown crystal on a heterogeneous substrate such as sapphire after growth, the vicinity of the heteroepitaxy interface at the initial stage of crystal growth must be dislocated. It is difficult to suppress the occurrence of For this reason, dislocations generated at a high density must be reduced during the growth of a thick film epicrystal serving as a substrate, and finally a low dislocation must be realized on the substrate surface. Therefore, by forming facets as in the above-described ELO method, FIELO method, and DEEP method, the dislocation propagation direction is changed to lower the crystal surface. Then, after the thick epitaxially grown crystal is grown, it is ground and flattened until there is no unevenness due to the facet surface remaining on the crystal surface. The back surface of the substrate is also processed flat until it reaches a predetermined thickness. On the crystal surface, a region grown on the (0001) C plane and a region grown on the facet are mixed. It has been found that the region grown on the facet plane is more doped with oxygen than the region grown on the C plane (see, for example, Patent Document 3).

  The crystal surface that has been ground until there are no irregularities due to the facet surface remaining on the crystal surface is rough and must be polished. The crystal surface is smoothed by performing three-stage polishing such as rough polishing, precision polishing, and chemical-mechanical polishing (CMP) on the crystal surface. Free abrasive grains such as silicon carbide, alumina, diamond, etc. are used as the physical polishing action, but by gradually reducing the grain size of the abrasive grains, the roughness of the crystal surface is lowered to form a mirror surface. be able to.

  On the other hand, CMP is a polishing method that covers a wide range of mechanisms over the entire “mechanical + chemical” polishing, such as a method that combines a chemical effect and a mechanical effect, a method that uses a chemomechanical effect, and a method that applies a mechanochemical effect. It is. However, the final polishing / finishing process by CMP has a problem that surface damage remains on the crystal surface (see, for example, Patent Document 4). When surface damage is present on the substrate surface, there is a problem in that the characteristics of electronic devices grown on the surface are deteriorated. As an example, for example, the output of the laser diode is reduced, or the life of the laser diode is deteriorated.

  In the technique described in Patent Document 4, the surface of the GaN free-standing substrate is shaved by a thickness of 0.01 to 10 μm by performing etching using an etching gas (for example, reactive ion etching, plasma etching, thermal etching), The surface damage on the surface of the GaN free-standing substrate is to be removed.

  In addition, every time three stages of polishing, rough polishing, precision polishing, and CMP, are performed, a step-like step is formed in a defect gathering region called a stripe core that is located immediately below the pit surrounded by the facet surface and has a high density of dislocations. Has occurred, and the level difference gradually increases (for example, see Patent Document 5). When epitaxial growth is performed on the surface of the GaN free-standing substrate where the step is generated, a step is also generated in the epi layer itself. If there is a step in the epi layer, a good element portion cannot be produced thereon.

In the technique described in Patent Document 5, CMP is performed using a weakly alkaline (NH ₄ OH) chemical. As a result, when the step between the C-plane grown region and the defect assembly region is reduced to 0.5 μm or less, the step of the epitaxial layer epitaxially grown thereon is also reduced.
JP-A-11-251253 JP 2003-165799 A JP 2002-373864 A Japanese Patent No. 3546023 JP 2004-335646 A Appl.Phys.Lett.71 (18) 1638 (1997) A.Usui, et al., Jpn. J. Appl. Phys. Vol.40 (2001) pp.L140-L143

  As a result of diligent research, the inventors of the present invention have found that in CMP, which is final polishing such as the technique described in Patent Document 5, the surface of the GaN free-standing substrate has a C-plane grown region during crystal growth. I learned that there was no step in the faceted area. However, when the surface damage of the GaN free-standing substrate generated by CMP is removed by etching (gas etching) using an etching gas after CMP is performed, GaN free-standing is performed as in the technique described in Patent Document 4 above. It has been found that even when the substrate surface is cut by a thickness of 0.01 to 10 μm, a step is generated between the region grown on the C plane and the region grown on the facet during crystal growth.

  A region grown at the C-plane during crystal growth and a region grown at the facet plane are greatly different in physical and chemical properties because the contained impurity concentrations are greatly different. Gas etching has a strong chemical action. For this reason, a difference occurs in the etching rate, and it is considered that a step is generated between the region grown on the C-plane and the region grown on the facet during crystal growth.

The inventors further analyzed the composition of the surface of the GaN free-standing substrate by SIMS (Secondary Ion Mass Spectroscopy) with respect to silicon (Si) contained in quartz, which is generally used as a material for a crystal growth reaction tube. However, the Si concentration in the region grown on the facet during crystal growth was 6 × 10 ¹⁸ cm ⁻³ , but the Si concentration in the region grown on the C plane during crystal growth was less than 1 × 10 ¹⁷ cm ^−3. I understood. This suggests that the chemical / physical properties differ between the C-plane grown region and the facet-grown region during crystal growth.

  In a GaN free-standing substrate, there is a step between the region grown on the C-plane and the region grown on the facet during crystal growth. Therefore, when an epitaxial layer is epitaxially grown on this GaN free-standing substrate, By taking over the step, a step also occurs in the epi layer. When an electronic device such as a semiconductor laser element is manufactured using such a GaN free-standing substrate, the interfacial interface is disturbed, or the cladding layer and the active layer do not function as designed, and the yield decreases.

  The present invention has been made to solve the above-described conventional problems, and it is possible to form an epitaxial layer that has excellent surface properties by suppressing crystal defects and that suppresses uneven surface steps to be small. It is an object of the present invention to provide a group III-V nitride semiconductor substrate and a method for manufacturing the same.

  In order to solve the above problems, the present inventors have conducted extensive studies on the final surface treatment of the semiconductor single crystal surface. For example, by controlling the etching conditions such as the etching rate and the etching amount, It is now possible to form a step between the region grown in step 1 and the region grown on the facet so as to satisfy a certain dimension or less, and it has been found that there is no practical problem as a substrate for crystal growth. The present invention has been reached.

That is, the present invention is composed of a GaN semiconductor single crystal, and the semiconductor single crystal is grown on a first region grown on the (0001) C plane during crystal growth and on a facet plane which is a crystal plane other than the (0001) C plane. The single crystal surface comprising the first region and the second region subjected to the etching process is controlled by controlling the etching rate and the etching amount so that the step with the second region satisfies 0.3 μm or less. In the group III-V nitride semiconductor substrate, the semiconductor substrate is provided.

Furthermore, the present invention is characterized in that after a GaN semiconductor single crystal is grown on a base substrate, an etching process is performed on the surface of the GaN semiconductor single crystal so that an etching rate and an etching amount satisfy the following relationship. There is a method for manufacturing a group III-V nitride semiconductor substrate.

  0 <(etching rate) × (etching amount) ≦ 2.00

  In the preferred group III-V nitride semiconductor substrate of the present invention, the etching process is performed so that the step difference between the region grown on the C plane and the region grown on the facet during the crystal growth satisfies 0.3 μm or less. In this case, it is preferable to set the etching rate and the etching amount in a relationship of 0 <(etching rate) × (etching amount) ≦ 2.00. In the case where the etching process is performed so that the level difference satisfies 0.05 μm or less, it is preferable to set the etching rate and the etching amount in a relationship of 0 <(etching rate) × (etching amount) ≦ 0.50. It is preferable to perform a surface treatment by etching using an inert gas.

  In a preferred group III-V nitride semiconductor substrate of the present invention, an epitaxial layer can be deposited on a group III-V nitride semiconductor single crystal by an epitaxial method. The epitaxial layer is preferably composed of a single crystal base material having the same crystal orientation as the group III-V nitride semiconductor single crystal.

  In the method for producing a group III-V nitride semiconductor substrate of the present invention, when the step difference between the region grown on the C-plane and the region grown on the facet during crystal growth is stabilized to 0.3 μm or less, the etching rate Etching is performed so that the etching amount satisfies the relationship of 0 <(etching rate) × (etching amount) ≦ 2.00, or the etching rate and the etching amount are 0 <(etching rate) × (etching). Any method of performing the etching treatment so as to satisfy the relationship of (quantity) ≦ 0.50 may be adopted. Prior to the etching treatment, it is preferable to perform chemical mechanical polishing on the entire surface of the semiconductor single crystal.

  As the etching amount and the etching rate, a scatter diagram can be obtained by plotting the multiplication value of the etching amount and the etching rate and the step of the region grown on the C plane and the facet surface during crystal growth on the X axis and the Y axis. The amount of etching and the etching rate can be obtained by creating and calculating an approximate curve of each point with respect to the scatter diagram by, for example, the least square method and obtaining the slope of the approximate curve.

  The present invention makes it possible to stabilize the step between the region grown on the C-plane and the region grown on the facet during crystal growth of the semiconductor single crystal within a range of 0.3 μm or less, and is deposited on the semiconductor single crystal. The step of the epitaxial layer can be stabilized within a range of 0.5 μm or less. Since the step of the epi layer can be suppressed to be small, the characteristics and uniformity of an electronic device such as a transistor or a diode can be improved, and the yield can be improved.

  Hereinafter, preferred embodiments of the present invention will be specifically described.

  The semiconductor single crystal substrate according to the embodiment of the present invention is not a base substrate on which a semiconductor multilayer film is formed. This semiconductor single crystal substrate is a substrate for semiconductor single crystal growth obtained by crystal growth on a different substrate such as sapphire as a base substrate by a conventional method. As a single crystal used for a semiconductor single crystal substrate, for example, a group III-V nitride single crystal having the same crystal orientation can be used. Examples of the group III-V nitride-based single crystal include an AlN single crystal, a GaN single crystal, and an AlGaN single crystal. By comprising the same group III-V nitride semiconductor single crystal having the same crystal orientation, the fluctuation range of the thickness of the semiconductor single crystal substrate can be prevented.

As a manufacturing method of the semiconductor single crystal substrate, it can be manufactured using the same manufacturing technique as the conventional manufacturing method such as ELO method, FIELO method, and DEEP method. Using these manufacturing techniques, for example, after forming a GaN layer on a sapphire substrate, the sapphire substrate can be removed by etching to obtain a GaN free-standing substrate. In this GaN free-standing substrate, the crystal surface is lowered in dislocation by changing the propagation direction of dislocations generated at high density by facets generated during the growth of the thick film epicrystal. On this crystal surface, a region grown on the (0001) C plane and a region grown on the facet plane are mixed. In the embodiment of the present invention, although not particularly limited, the surface of the crystal is flattened by surface treatment such as rough polishing, precision polishing, and chemical mechanical polishing (CMP) until there is no unevenness due to the facet surface of the crystal surface. Grind or polish. As CMP which is final polishing, it is preferable to use, for example, ammonium hydroxide (NH ₄ OH).

Reactive ion etching (RIE) treatment using an active gas such as Br-based gas or F-based gas is performed on the surface of the GaN free-standing substrate after performing CMP to remove surface damage left by CMP. be able to. After performing the RIE process on the GaN free-standing substrate, an epitaxial layer can be formed by epitaxial growth on the obtained GaN free-standing substrate by the epitaxial method. The epi layer is preferably made of, for example, a GaN-based single crystal base material and preferably has the same crystal orientation as the group III-V nitride semiconductor single crystal.

  The concentration of impurities contained in the region grown on the (0001) C plane during crystal growth and the region grown on the facet plane other than the C plane are different in physical and chemical properties. Therefore, when the surface damage caused by CMP is removed by performing RIE on the surface of the GaN free-standing substrate after CMP, uneven steps are generated between the C-plane growth region and the facet growth region. The level difference can be reduced by controlling etching conditions such as RIE etching rate and etching amount. As the etching process, any method other than RIE may be used. For example, thermal etching, plasma etching, or the like can be used.

  After performing CMP on the GaN free-standing substrate, the RIE process is performed by controlling the etching conditions such as the etching rate and the etching amount, so that the step between the region grown on the C plane and the region grown on the facet during crystal growth is The GaN free-standing substrate can be formed so as to be stabilized within the initial target range of 0.3 μm or less. When the variation is suppressed so that the step on the surface of the GaN free-standing substrate is 0.3 μm or less, the etching rate and the etching amount are 0 <[etching rate (μm / h)] × It is preferable to perform the etching process so as to satisfy the relationship of [etching amount (μm)] ≦ 2.00. By suppressing the step on the surface of the GaN free-standing substrate to 0.3 μm or less, an epi layer can be formed on the GaN free-standing substrate so that the step of the epi layer deposited on the GaN free-standing substrate is 0.5 μm or less. it can. The maximum allowable step difference of the epi layer is preferably about 0.5 μm.

  More preferably, the step on the GaN free-standing substrate surface is 0.05 μm or less. In this case, the step of the epi layer deposited on the GaN free-standing substrate can be formed to 0.1 μm or less. When the variation is suppressed so that the step on the surface of the GaN free-standing substrate is 0.05 μm or less, the etching rate and the etching amount are 0 <[etching rate (μm / h)] × It is preferable to perform the etching process so as to satisfy the relationship of [etching amount (μm)] ≦ 0.50.

  Etching is performed so that the etching rate and the etching amount satisfy the relationship of 0 <[etching rate (μm / h)] × [etching amount (μm)] ≦ 2.00, or the etching rate and the etching amount are , 0 <[etching rate (μm / h)] × [etching amount (μm)] ≦ 0.50 Therefore, the step of the epitaxial layer can be stabilized to be small, and the step of the epi layer can be suppressed to a small level. Thereby, the yield of electronic devices such as transistors and diodes can be improved, and the performance of the electronic devices can be improved.

  The etching amount and the etching rate that do not cause a problem in practice for performing the surface treatment of the group III-V nitride semiconductor substrate are, for example, an approximate curve between a multiplication value of the etching amount and the etching rate and a step on the surface of the GaN free-standing substrate. Can be determined based on As an example, a scatter diagram is created by plotting, for example, the multiplication value of the etching amount and the etching rate and the step on the surface of the GaN free-standing substrate on the X axis and the Y axis. For the scatter diagram, an approximate curve that passes through the approximate points of each point is calculated by the least square method, and the slope of the approximate curve is obtained. Thereby, the multiplication value of the etching amount and the etching rate, and the respective values of the etching amount and the etching rate can be set.

  Hereinafter, examples will be described in detail with reference to Tables 1 to 5 and FIGS. 1 to 4 as more specific embodiments of the present invention.

As a substrate for growing a group III-V nitride semiconductor single crystal, a GaN free-standing substrate grown by a conventional method was used. As the polishing of the GaN free-standing substrate, it was roughly polished with a grindstone (diamond) having fixed abrasive grains, and then precisely polished with a grindstone (diamond) having free abrasive grains and an average particle diameter of 1 μm. Thereafter, CMP was performed using a grindstone (diamond) having free abrasive grains and an average particle diameter of 0.1 μm and ammonium hydroxide (NH ₄ OH). After performing CMP, surface damage of the GaN free-standing substrate was removed by RIE using an etching gas containing chlorine gas. Then, the amount of a step (hereinafter referred to as a substrate step) between a region grown on the C-plane and a region grown on the facet during crystal growth was examined using a contact-type step meter (for example, manufactured by ULVAC).

  In general, in RIE, the etching rate increases as the pressure in the furnace is lowered, the input power is increased, and the gas supply amount is increased. In view of this, the in-furnace pressure, the input power, and the gas supply amount were set to specific values, and the substrate step amount of the GaN free-standing substrate when the etching rate was changed by changing the etching time of RIE was investigated.

  Table 1 below collectively shows the results of the RIE conditions when the etching rate is changed by changing the etching time of RIE in Example 1 and the substrate step amount after RIE.

  In Table 1, as the RIE conditions, the input power is increased by 25 W within a range of 25 to 300 W to 12 types, the furnace pressure is 10 Pa, the gas supply amount is 50 sccm, the etching amount is 1.2 μm, Furnace & substrate temperature was 25 ° C. Then, the RIE process was performed by variously changing the etching time within a range of 30 to 360 minutes, and the etching rate was changed by 0.2 μm / h within a range of 0.2 to 2.4 μm / h.

  As is apparent from Table 1, the etching rate can be changed by changing the input power and the etching time, but it can be seen that the substrate step of the GaN free-standing substrate increases with the change in the etching rate. The corresponding results are plotted on the graph of FIG.

  FIG. 1 is a graph showing an example of the substrate step amount and the etching rate of the GaN free-standing substrate according to Example 1 subjected to the RIE process as described above.

  As can be seen from the figure, when the etching rate is 1.0 μm / h or less, the step difference of the GaN free-standing substrate gradually increases. It can be understood that when the etching rate exceeds 1.0 μm / h, the step difference of the GaN free-standing substrate rapidly increases as the etching rate changes.

  From the above points, it becomes possible to reduce the substrate step of the GaN free-standing substrate by reducing the etching rate. It can be understood that the substrate step of the GaN free-standing substrate cannot be reduced unless the power, etching time and etching rate are set appropriately.

  Furthermore, a GaN free-standing substrate was produced by the same procedure as in Example 1. Then, while setting the furnace pressure, the input power, and the gas supply amount to certain values, and changing the etching amount by changing the etching time of RIE, the substrate step amount of the GaN free-standing substrate is changed to a contact type step. The total was investigated.

  Table 2 below collectively shows the RIE conditions when the etching amount is changed by changing the RIE etching time in Example 2 and the result of the substrate step amount after the RIE.

  As the RIE conditions shown in Table 2, the etching time is increased by 15 minutes within a range of 15 to 150 minutes and 10 types, the furnace pressure is 10 Pa, the input power is 150 W, the gas supply amount is 50 sccm, The etching rate was 1.2 μm / h, and the in-furnace & substrate temperature was 25 ° C. Then, the RIE process was performed by increasing the etching time by 15 minutes within the range of 15 to 150 minutes, and the etching amount was changed by 0.3 μm within the range of 0.3 to 3 μm.

  As can be seen from Table 2, the etching amount gradually increases as the etching time changes, and the substrate step of the GaN free-standing substrate increases as the etching amount changes. The corresponding results are plotted on the graph of FIG.

  FIG. 2 is a graph showing an example of the substrate step amount and the etching amount of the GaN free-standing substrate according to the second embodiment subjected to the RIE process as described above.

  As is apparent from the figure, when the etching amount is 0.9 μm or less, the step difference of the GaN free-standing substrate gradually increases. It can be seen that when the etching amount exceeds 0.9 μm, the step difference of the GaN free-standing substrate rapidly increases as the etching amount changes.

  From the above points, it is possible to reduce the substrate step of the GaN free-standing substrate by reducing the etching amount, but in any case, the surface of the GaN free-standing substrate is shaved by ensuring a constant etching rate. However, it can be understood that the substrate step of the GaN free-standing substrate cannot be reduced and stabilized unless the etching amount is set appropriately.

  Furthermore, a GaN free-standing substrate was produced by the same procedure as in Example 1. Based on the above investigation results, the amount of step difference of the GaN free-standing substrate when the etching time and etching rate of RIE are changed, and the amount of epi step difference of the GaN-based epi layer epitaxially grown on the GaN free-standing substrate are calculated. Each was investigated with a contact-type step gauge.

  Table 3 below summarizes the results of the RIE conditions when the RIE etching time and the etching rate in Example 3 were changed, the substrate step amount of the GaN free-standing substrate after RIE, and the epi step amount of the epi layer.

  The RIE conditions shown in Table 3 are 18 types of input power of 20 to 250 W, furnace pressure of 10 Pa, gas supply amount of 50 sccm, etching amount of 1.2 μm, furnace & substrate temperature of 25 ° C. It was. Then, the RIE treatment was performed by changing the etching time variously within the range of 36 to 360 minutes and changing the etching rate variously within the range of 0.2 to 2.0 μm / h.

  As can be seen from Table 3, when a substrate step occurs in the GaN free-standing substrate, an epi step also occurs in the epi layer, but in any case, the substrate step of the GaN free-standing substrate must be kept small. Thus, it can be seen that the epi level difference of the epi layer cannot be reduced. The corresponding results are plotted on the graph of FIG.

  FIG. 3 is a graph showing the relationship between the substrate step amount of the GaN free-standing substrate according to Example 3 subjected to the RIE process as described above and the epi step amount of the epi layer.

  As can be understood from the figure, when the substrate step of the GaN free-standing substrate is 0.3 μm, which is the initial target, the epi step of the epi layer reaches 0.5 μm. In order to obtain an epi layer whose epi level difference is 0.5 μm or less, it is sufficient that the substrate level difference of the GaN free-standing substrate is 0.3 μm or less. If the substrate step exceeds 0.3 μm, the epi step cannot be made 0.5 μm or less.

  From the above points, it can be seen that the epitaxial step can be suppressed to a value of 0.5 μm or less by setting the substrate step of the GaN free-standing substrate to 0.3 μm or less. It can be seen that by setting the substrate step of the GaN free-standing substrate to 0.05 μm or less, which is the most preferable value, the epi step can be suppressed to a value of 0.1 μm or less.

  Furthermore, a GaN free-standing substrate was produced by the same procedure as in Example 1. And based on the said investigation result, the board | substrate level | step difference amount of the GaN self-supporting board | substrate when changing the etching rate by changing the etching amount of RIE was investigated with the contact-type level | step difference meter.

  Tables 4 and 5 below show RIE conditions when the etching rate is changed by changing the RIE etching amount in Example 4, the substrate step amount of the GaN free-standing substrate after RIE, the etching amount, and the etching. Expresses the relationship between speeds together.

  As the RIE conditions shown in Tables 4 and 5, the input power is increased by 25 W in a range of 25 to 300 W to 12 types, the furnace pressure is 10 Pa, the gas supply amount is 50 sccm, the furnace & substrate temperature Was 25 ° C. Then, the etching time of RIE is set to four types of 30 minutes, 60 minutes, 90 minutes, and 120 minutes, and the etching amount within the range of 0.1 to 4.8 μm for each of these etching times is 0.1 μm and 0.8 μm, respectively. The amount of step difference of the GaN free-standing substrate when the etching rate was changed by changing each of 2 μm, 0.3 μm, and 0.4 μm was investigated using a contact step meter.

  As apparent from Tables 4 and 5, the RIE etching amount and the etching rate have a correlation, but even if each of the etching amount and the etching rate increases quantitatively, the substrate of the GaN free-standing substrate. It can be seen that the amount of the step varies greatly.

Based on the results of Tables 4 and 5, a scatter diagram was created by Arrhenius plotting the multiplication value of the etching amount and the etching rate and the substrate step amount of the GaN free-standing substrate on the X axis and the Y axis. For the scatter plot obtained by the Arrhenius plot, an approximate curve expression y = −0.0335x ⁶ + 0.4813x ⁵ −2.6457x ⁴ + 7.0741x ³ passing through the approximate point of each point by the least square method. −9.8806x ² + 9.3598x + 0.0845 was calculated. The slope of the approximate curve was obtained, and a highly accurate approximate curve with a certainty factor R-square value (R ² = 0.9939) close to 1 was created. From the slope of this approximate curve, a multiplication value of the etching amount and the etching rate at which the substrate step of the GaN free-standing substrate satisfies 0.3 μm or less can be set. By selecting a parameter such as a product of an etching amount and an etching rate, the occurrence of defective products can be reduced, and a high yield can be maintained. The result is shown in FIG.

  FIG. 4 shows a graph in which the multiplication value of the etching amount and the etching rate according to Example 4 subjected to the RIE treatment as described above and the substrate step amount of the GaN free-standing substrate are plotted, and the entire distribution obtained by the plotting is shown. It is a figure which shows an approximated curve.

  As can be understood from the figure, in order to obtain a GaN free-standing substrate having a substrate step of 0.3 μm or less, the relationship of [etching rate (μm / h)] × [etching amount (μm)] ≦ 2.00 It can be understood that it is necessary to control the etching amount and the etching rate as shown in FIG. If the RIE process is performed under these etching conditions, the substrate step of the GaN free-standing substrate can be reduced to 0.3 μm or less, which is the initial target, regardless of which of RIE input power and etching time. By making the substrate level difference 0.3 μm or less, as shown in FIG. 3, the epi level difference of the epi layer can be suppressed to 0.5 μm or less. Further, in order to obtain a GaN free-standing substrate having a substrate step of 0.05 μm or less, the etching amount and the etching amount so as to have a relationship of [etching rate (μm / h)] × [etching amount (μm)] ≦ 0.50 It can be understood that it is necessary to control the etching rate. When the substrate step is 0.05 μm, the step of the epi layer can be 0.1 μm as shown in FIG.

  In view of the above, by controlling the etching rate and the etching amount within the range of [etching rate (μm / h)] × [etching amount (μm)] ≦ 2.00, the substrate step of the GaN free-standing substrate can be practically used. It can be understood that an epi layer having an epi level difference of 0.5 μm or less can be obtained by stabilizing to 0.3 μm or less without causing any problem. Further, by controlling the etching rate and the etching amount within the range of [etching rate (μm / h)] × [etching amount (μm)] ≦ 0.50, the step difference of the GaN free-standing substrate is reduced to 0.05 μm or less. It becomes possible to stabilize, and an epi level | step difference can be suppressed to 0.1 micrometer or less. As a result, a GaN free-standing substrate that can reliably maintain the quality can be effectively obtained.

  As described above, by controlling the etching rate and the etching amount, the step difference of the GaN free-standing substrate can be stabilized to 0.3 μm or less, preferably 0.05 μm or less. As a result, the epi level difference can be reduced to 0.5 μm or less, preferably 0.1 μm or less. It can be understood that the product value is not deteriorated because the variation in the inclination angle and depth of the uneven step can be suppressed.

  In each of the above embodiments, surface damage due to CMP is removed by performing RIE treatment on the GaN free-standing substrate. However, as the etching treatment, surface treatment processing of the GaN free-standing substrate can be performed by plasma etching, for example. As plasma etching conditions, for example, the furnace temperature is 1000 ° C., the substrate temperature is 1000 ° C., the hydrogen gas flow rate is 5 L / min, the etching rate is 1.2 μm / h, and the etching amount is 1.2 μm. Since the etching rate and the etching amount are controlled within the range of [etching rate (μm / h)] × [etching amount (μm)] ≦ 2.00, the C plane growth region and the facet growth region The step can be suppressed to about 0.15 μm. Therefore, the present invention is not limited to the above embodiments and examples, and various design changes can be made without departing from the spirit of the invention.

  The group III-V nitride semiconductor substrate of the present invention can be effectively used for the production of semiconductor light emitting devices such as LEDs and semiconductor lasers, and semiconductor light receiving devices.

It is a graph which shows the relationship between the etching rate of RIE, and the level | step difference amount of the area | region which grew on the C surface and the facet plane at the time of crystal growth. It is a graph which shows the relationship between the etching amount of RIE, and the level | step difference amount of the area | region which grew on the C surface and the facet plane at the time of crystal growth. It is a graph which shows the relationship between the level | step difference amount of the area | region grown by the C-plane growth and the facet plane at the time of crystal growth, and the level | step difference amount of an epi layer. A graph plotting the product of the RIE etching amount and the etching rate, the step amount of the region grown on the C-face and the facet during the crystal growth, and an approximation showing the entire distribution obtained by the plot It is a figure which shows a curve.

Claims (10)

GaN semiconductor single crystal,
The GaN semiconductor single crystal has a step difference of 0.3 μm or less between a first region grown on the (0001) C plane and a second region grown on a facet plane which is a crystal plane other than the (0001) C plane during crystal growth. In order to satisfy the above, the etching rate and the etching amount are controlled to provide a single crystal surface comprising the first region and the second region subjected to the etching process. Group nitride semiconductor substrate.   2. The group III-V nitride semiconductor substrate according to claim 1, wherein the step is further 0.05 [mu] m or less. 3. The group III-V nitride semiconductor substrate according to claim 1, wherein the etching rate and the etching amount satisfy the following relationship.
0 <(etching rate) × (etching amount) ≦ 2.00 3. The group III-V nitride semiconductor substrate according to claim 2, wherein the etching rate and the etching amount further satisfy the following relationship.
0 <(etching rate) × (etching amount) ≦ 0.50 The group III-V nitride semiconductor substrate according to claim 1, wherein the etching treatment is etching using an active gas . An epitaxial layer is deposited on the semiconductor single crystal by an epitaxial method,
2. The group III-V nitride semiconductor substrate according to claim 1, wherein the epitaxial layer is formed of a single crystal base material having the same crystal orientation as the GaN semiconductor single crystal. A group III-V characterized in that after a GaN semiconductor single crystal is grown on a base substrate, an etching process is performed on the surface of the GaN semiconductor single crystal so that the etching rate and the etching amount satisfy the following relationship: A method for manufacturing a nitride semiconductor substrate.
0 <(etching rate) × (etching amount) ≦ 2.00 8. The method for producing a group III-V nitride semiconductor substrate according to claim 7, wherein the etching rate and the etching amount further satisfy the following relationship.
0 <(etching rate) × (etching amount) ≦ 0.50   The etching rate and the etching amount are determined by a step between a region grown on the (0001) C plane during crystal growth and a region grown on a facet plane that is a crystal plane other than the (0001) C plane, the etching amount, and the etching amount. 9. The method for producing a group III-V nitride semiconductor substrate according to claim 7 or 8, wherein an approximate curve with a multiplication value of an etching rate is calculated and obtained based on the approximate curve. 9. The method for producing a group III-V nitride semiconductor substrate according to claim 7, wherein chemical mechanical polishing is performed on the entire surface of the GaN semiconductor single crystal prior to the etching process.

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