JP4359770B2 - III-V nitride semiconductor substrate and production lot thereof - Google Patents
III-V nitride semiconductor substrate and production lot thereof Download PDFInfo
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 14
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 10
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- Crystals, And After-Treatments Of Crystals (AREA)
Description
本発明は、サーマルクリーニングによる表面荒れが抑えられたIII−Ｖ族窒化物系半導体基板及びその製造ロットに関する。 The present invention relates to a III-V nitride semiconductor substrate and its production lots surface roughening is suppressed by the thermal cleaning.
窒化ガリウム（GaN）、窒化インジウムガリウム（InGaN）、窒化ガリウムアルミニウム（GaAlN）等の窒化物系半導体材料は禁制帯幅が大きく、バンド間遷移が直接遷移型であるため、短波長発光素子への適用が検討されている。また電子の飽和ドリフト速度が大きいこと、ヘテロ接合による２次元キャリアガスの利用が可能なこと等から、電子素子への応用も期待されている。 Nitride-based semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), and gallium aluminum nitride (GaAlN) have a large forbidden band width and direct transition type between bands. Application is under consideration. In addition, application to electronic devices is also expected due to the high saturation drift velocity of electrons and the use of two-dimensional carrier gas by heterojunction.
窒化物系半導体は、バルク結晶成長が難しいことが問題であったが、最近ようやく実用に耐えるレベルのGaN自立基板が開発されてきている。現在、広く使用されているGaN成長用の下地基板はサファイアであり、単結晶サファイアからなる下地基板の上に有機金属気相成長法（MOVPE法）、分子線気相成長法（MBE法）、ハイドライド気相成長法（HVPE法）等の気相成長法で、GaNをヘテロエピタキシャル成長させ、その上に同じ炉内で連続して又は別の成長炉に移して窒化物系半導体エピタキシャル層を成長させ、デバイスを作製する方法が一般に用いられている。 A problem with nitride-based semiconductors is that bulk crystal growth is difficult, but recently, GaN free-standing substrates have finally been developed to withstand practical use. Currently, the widely used substrate for GaN growth is sapphire, and metal organic vapor phase epitaxy (MOVPE method), molecular beam vapor phase epitaxy (MBE method) on the base substrate made of single crystal sapphire, GaN is heteroepitaxially grown by vapor phase growth methods such as hydride vapor phase epitaxy (HVPE method), and nitride-based semiconductor epitaxial layers are grown on it continuously or in another growth furnace in the same furnace. A method of manufacturing a device is generally used.
サファイア下地基板はGaNと格子定数が異なるため、サファイア下地基板上に直接GaNを成長させる方法では単結晶膜を成長させることができない。このため、特開平4-297023号（特許文献１）は、サファイア下地基板上にSi等をヘテロ成長させる目的で考案された低温バッファ層の技術をGaNの成長に応用し、サファイア下地基板上に500℃程度の低温でAlNやGaNのバッファ層を成長させ、この低温バッファ層で格子の歪みを緩和させてからその上にGaNを成長させる方法を提案した。低温成長窒化物層を低温バッファ層として用いることにより、サファイア下地基板上にGaNの単結晶をエピタキシャル成長させることが可能になった。しかし、低温バッファ層は成長温度と成長膜厚の最適な範囲が狭いため、低温バッファ層を再現性よく形成するのが難しい。 Since the sapphire base substrate has a lattice constant different from that of GaN, a single crystal film cannot be grown by the method of growing GaN directly on the sapphire base substrate. For this reason, Japanese Patent Application Laid-Open No. H4-297023 (Patent Document 1) applies a technique of a low-temperature buffer layer devised for hetero-growth of Si or the like on a sapphire base substrate to the growth of GaN. A method was proposed in which a buffer layer of AlN or GaN was grown at a low temperature of about 500 ° C., and lattice strain was relaxed with this low-temperature buffer layer, and then GaN was grown thereon. By using a low-temperature grown nitride layer as a low-temperature buffer layer, it has become possible to epitaxially grow a GaN single crystal on a sapphire base substrate. However, since the low temperature buffer layer has a narrow optimum range of growth temperature and growth film thickness, it is difficult to form the low temperature buffer layer with good reproducibility.
そこで、サファイア下地基板上にデバイス構造の半導体多層膜を連続的にエピタキシャル成長させるのではなく、予め下地基板上にGaN層だけを成長させた基板を作製し、この基板上にエピタキシャル層を成長させてデバイスを形成する方法も用いられている。 Therefore, instead of continuously epitaxially growing the semiconductor multilayer film of the device structure on the sapphire base substrate, a substrate in which only the GaN layer was grown in advance on the base substrate was fabricated, and the epitaxial layer was grown on this substrate. A method of forming a device is also used.
しかしながら、サファイア下地基板上にGaN層を成長させたいわゆるGaNテンプレートでは、低温バッファ層の技術を用いても、下地基板と結晶格子のずれを解消するのは難しく、得られるGaN層は109〜1010個/cm2もの転位密度を有する。この欠陥は、GaN系デバイス、特にLDや紫外発光LEDを作製する上で障害となるため、GaNテンプレートは、もっぱらデバイス特性に転位の影響が出にくい可視LED用や電子デバイス用に用いられている。 However, in the so-called GaN template grown GaN layer on a sapphire base substrate, even using techniques cold buffer layer, it is difficult to eliminate the deviation of the underlying substrate and the crystal lattice, the resulting GaN layer 109 - 10 Dislocation density as high as 10 pieces / cm 2 . This defect is an obstacle to the fabrication of GaN-based devices, especially LDs and UV-emitting LEDs, so GaN templates are used exclusively for visible LEDs and electronic devices that are less susceptible to dislocations on device characteristics. .
転位密度の低いエピタキシャル層が要求されるLDや紫外LEDデバイスには、結晶成長用の基板としてGaN層のみからなる基板を用い、この上に素子部を構成する半導体多層膜を形成する手法が検討されている。このような結晶成長用のGaNのみからなる基板をGaN自立基板と呼ぶ。 For LD and UV LED devices that require an epitaxial layer with a low dislocation density, a substrate consisting of only a GaN layer is used as the substrate for crystal growth, and a method of forming a semiconductor multilayer film that forms the device on this is studied. Has been. Such a substrate made of only GaN for crystal growth is called a GaN free-standing substrate.
GaN自立基板は一般に、サファイア下地基板等の異種基板上に厚くエピタキシャル成長させた低転位密度のGaN層を下地基板から剥離することにより得られたものである。例えば、特開平10-256662号（特許文献２）は、サファイア下地基板上にGaN層を厚く成長させた後、サファイア下地基板を除去する方法を開示しており、特開平11-251253号（特許文献３）は、Appl. Phys. Lett., 1997年, 第71巻, 第18号, 2638頁に記載されているELO（Epitaxial Lateral Overgrowth）と呼ばれる転位低減化技術を用い、サファイア下地基板上にGaN層を形成した後、サファイア下地基板をエッチング等により除去することにより、GaN自立基板を得る方法を開示している。特開2003-178984号（特許文献４）は、Y. Oshima等, Jpn. J. Appl. Phys., 2003年, 第42巻, L1〜L3頁に記載されているVAS（Void-Assisted Separation）法を用い、サファイア等の下地基板上に、網目構造のTiN薄膜を介して低転位密度のGaN層を成長させ、下地基板とGaN層の界面のボイドによりGaN層を容易に剥離する方法を開示している。これらの方法で得られたGaN基板は、通常アズグロウンの状態では、その表面にピット、ヒロック等のモフォロジが現れており、そのままではデバイス用のエピタキシャル層を成長させることが難しい。このため、基板表面を研磨加工して、鏡面に仕上げてから使用するのが一般的である。 A GaN free-standing substrate is generally obtained by peeling off a GaN layer having a low dislocation density, which is thickly grown on a different substrate such as a sapphire base substrate, from the base substrate. For example, Japanese Patent Laid-Open No. 10-256662 (Patent Document 2) discloses a method of removing a sapphire base substrate after a GaN layer is grown thickly on the sapphire base substrate. Reference 3) uses a dislocation reduction technique called ELO (Epitaxial Lateral Overgrowth) described in Appl. Phys. Lett., 1997, Vol. 71, No. 18, p. 2638. A method for obtaining a GaN free-standing substrate by forming a GaN layer and then removing the sapphire base substrate by etching or the like is disclosed. JP 2003-178984 (Patent Document 4) describes VAS (Void-Assisted Separation) described in Y. Oshima et al., Jpn. J. Appl. Phys., 2003, Vol. 42, pages L1-L3. Discloses a method of growing a low dislocation density GaN layer on a base substrate such as sapphire via a networked TiN thin film and easily peeling the GaN layer with a void at the interface between the base substrate and the GaN layer. is doing. The GaN substrate obtained by these methods usually has a morphology such as pits and hillocks on its surface in an as-grown state, and it is difficult to grow an epitaxial layer for a device as it is. For this reason, the substrate surface is generally used after being polished to a mirror finish.
III族窒化物系半導体のデバイス構造を形成するためのエピタキシャル成長には、MOVPE法がしばしば用いられている。MOVPE法によりサファイア下地基板上にIII族窒化物系半導体をエピタキシャル成長させる場合、サファイア下地基板表面の汚れを除去するために、サファイア下地基板を水素ガス雰囲気中、1000℃以上で一定時間以上加熱する、いわゆるサーマルクリーニングが一般的に行われている。 The MOVPE method is often used for epitaxial growth to form a III-nitride semiconductor device structure. When the group III nitride semiconductor is epitaxially grown on the sapphire base substrate by the MOVPE method, the sapphire base substrate is heated in a hydrogen gas atmosphere at 1000 ° C. or higher for a predetermined time or longer in order to remove the contamination on the surface of the sapphire base substrate. So-called thermal cleaning is generally performed.
GaN基板（GaNテンプレートやGaN自立基板）上に、MOVPE法によりIII族窒化物系半導体単結晶をエピタキシャル成長させる場合も、GaN基板表面の汚れや、表面を鏡面加工する際に導入された残留歪を除去する目的で、サーマルクリーニングが行われている。例えば、特開2000-252217号（特許文献５）は、GaN単結晶基板の研磨表面の欠陥をなくすため、エピタキシャル成長前に水素ガス及びアンモニアガスを含む雰囲気中でGaN基板を加熱する方法を開示している。また特開2003-59835号（特許文献６）は、GaNテンプレートやGaN自立基板に1200℃以下の温度でサーマルクリーニングを行う方法を開示している。 Even when a group III nitride semiconductor single crystal is epitaxially grown on a GaN substrate (GaN template or GaN free-standing substrate) by the MOVPE method, dirt on the surface of the GaN substrate and residual strain introduced when the surface is mirror-polished. Thermal cleaning is performed for the purpose of removal. For example, Japanese Patent Laid-Open No. 2000-252217 (Patent Document 5) discloses a method of heating a GaN substrate in an atmosphere containing hydrogen gas and ammonia gas before epitaxial growth in order to eliminate defects on the polished surface of the GaN single crystal substrate. ing. Japanese Patent Laid-Open No. 2003-59835 (Patent Document 6) discloses a method of performing thermal cleaning on a GaN template or a GaN free-standing substrate at a temperature of 1200 ° C. or lower.
GaNテンプレートやGaN自立基板にサーマルクリーニングを行う場合、基板表面の汚れや歪層だけを除去し、表面のGaN結晶にダメージを与えないのが望ましい。しかしながら、サーマルクリーニング中に往々にして基板の表面荒れ（基板表面のGaN結晶が熱分解又は昇華して、基板表面の平坦性が損なわれる現象）が生じてしまうことがある。熱分解の場合、基板表面に金属Gaのドロップレットが生じることもある。熱分解又は昇華したGaNは基板上の別の箇所で再成長し、単結晶性を損なう場合もある。いずれにせよ、これらの結果として生じる基板の表面荒れは、その上に成長するエピタキシャル層との界面急峻性を乱し、またエピタキシャル層の結晶性や平坦性を乱して、作製するデバイスの特性や信頼性の低下をもたらす。 When performing thermal cleaning on a GaN template or GaN free-standing substrate, it is desirable to remove only the dirt and strained layer on the substrate surface and not damage the GaN crystal on the surface. However, surface roughness of the substrate often occurs during thermal cleaning (a phenomenon in which the flatness of the substrate surface is impaired due to thermal decomposition or sublimation of GaN crystals on the substrate surface). In the case of thermal decomposition, metallic Ga droplets may be generated on the substrate surface. Thermally decomposed or sublimated GaN may re-grow at other locations on the substrate, impairing single crystal properties. In any case, the resulting surface roughness of the substrate disturbs the sharpness of the interface with the epitaxial layer grown on it, and also disturbs the crystallinity and flatness of the epitaxial layer, resulting in the characteristics of the device to be fabricated. And decrease reliability.
GaN結晶の熱分解又は昇華は、温度だけでなく、熱処理中のガスの種類や圧力にも依存する。特許文献６の方法は、基板表面にダメージを与えずにサーマルクリーニングを行い、加熱による基板の表面荒れが生じる前に結晶成長を開始させるという技術的思想に基づく。しかし、この方法では、同一条件でサーマルクリーニングを行った場合でも、表面荒れの生じる基板と生じない基板が発生し、再現性という点で満足できるものではない。 Thermal decomposition or sublimation of GaN crystals depends not only on temperature but also on the type and pressure of gas during heat treatment. The method of Patent Document 6 is based on the technical idea that thermal cleaning is performed without damaging the substrate surface, and crystal growth is started before surface roughness of the substrate is caused by heating. However, this method is not satisfactory in terms of reproducibility, even when thermal cleaning is performed under the same conditions, a substrate with a rough surface and a substrate with no surface roughness are generated.
通常、GaAs等の半導体基板の製造ロットは、同一のバルク結晶から切り出されたウェハから構成されており、ロット内のウェハの特性にばらつきが出にくい。しかし、GaN基板の場合、前述のように１枚ずつ結晶を成長させるため、GaAs等の他の半導体基板に比べて、同一ロット内でもウェハの特性にばらつきが生じやすい。このため、GaN基板では同一ロットから選んだ複数のウェハに同一条件でサーマルクリーニングを行った場合でも、表面荒れの生じる基板と生じない基板が出てしまうというGaN基板に特有の問題が発生する。 Usually, a manufacturing lot of a semiconductor substrate such as GaAs is composed of wafers cut from the same bulk crystal, and the characteristics of the wafers in the lot do not easily vary. However, in the case of a GaN substrate, since the crystals are grown one by one as described above, the wafer characteristics tend to vary even within the same lot as compared to other semiconductor substrates such as GaAs. For this reason, even when thermal cleaning is performed on a plurality of wafers selected from the same lot under the same conditions, a problem peculiar to the GaN substrate that a substrate with a rough surface and a substrate with no surface appear appear.
従って本発明の目的は、優れた熱安定性を有するためにサーマルクリーニングによる表面荒れが生じにくいIII−Ｖ族窒化物系半導体基板及びその製造ロットを提供することである。
Accordingly, an object of the present invention is to provide a surface roughness hardly occurs group III-V nitride-based semiconductor substrate and a manufacturing lots by thermal cleaning in order to have excellent thermal stability.
上記目的に鑑み鋭意研究の結果、本発明者は、(a) III−Ｖ族窒化物系半導体基板のサーマルクリーニングによる表面荒れは、サーマルクリーニングの熱処理条件だけでなく、結晶の分解しやすさ等のIII−Ｖ族窒化物系半導体基板そのものの特性、特にIII−Ｖ族窒化物系半導体基板表面の転位密度と、不純物として結晶中に存在する水素原子の濃度の両方に依存すること、(b) 従って、転位密度と水素原子濃度の積をGaN結晶の熱分解のし易さの指標とし、それを所定のレベル以下に抑えることにより、熱的に安定なためにサーマルクリーニングによる表面荒れがほぼ完全に抑えられたIII−Ｖ族窒化物系半導体基板が得られることを発見し、本発明に想到した。 As a result of diligent research in view of the above object, the present inventor has found that (a) surface roughness due to thermal cleaning of a group III-V nitride-based semiconductor substrate is not only thermal treatment conditions for thermal cleaning but also ease of crystal decomposition. Of the III-V nitride semiconductor substrate itself, in particular, depending on both the dislocation density on the surface of the III-V nitride semiconductor substrate and the concentration of hydrogen atoms present in the crystal as impurities (b) Therefore, the product of the dislocation density and the hydrogen atom concentration is used as an index of the ease of thermal decomposition of the GaN crystal, and by suppressing it to a predetermined level or less, the surface roughness due to thermal cleaning is almost constant for thermal stability. The inventors have found that a completely suppressed group III-V nitride-based semiconductor substrate can be obtained, and have arrived at the present invention.
すなわち、本発明のIII−Ｖ族窒化物系半導体基板は、少なくとも表面近傍がIII−Ｖ族窒化物系半導体の単結晶からなり、表面近傍の前記単結晶中の水素原子濃度[H]（水素原子数/cm3）と前記単結晶の表面における転位密度[D]（個/cm2）との積（[H]×[D]）が１×1025以下であることを特徴とする。 That is, the group III-V nitride semiconductor substrate of the present invention is composed of a single crystal of a group III-V nitride semiconductor at least near the surface, and the hydrogen atom concentration [H] (hydrogen in the single crystal near the surface The product ([H] × [D]) of the number of atoms / cm 3 ) and the dislocation density [D] (number / cm 2 ) on the surface of the single crystal is 1 × 10 25 or less.
本発明のIII−Ｖ族窒化物系半導体基板は、III−Ｖ族窒化物系半導体の単結晶からなる自立基板であるのが好ましい。III−Ｖ族窒化物系半導体単結晶は六方晶系の窒化ガリウムであるのが好ましい。この場合、基板表面はC面のIII族面であるのが好ましい。基板表面はまた鏡面研磨されているのが好ましい。基板表面の算術平均粗さRa（JIS B 0601-1994）は10 nm以下であるのが好ましい。 The group III-V nitride semiconductor substrate of the present invention is preferably a free-standing substrate made of a single crystal of a group III-V nitride semiconductor. The III-V nitride semiconductor single crystal is preferably hexagonal gallium nitride. In this case, the substrate surface is preferably a C-group III surface. The substrate surface is also preferably mirror polished. The arithmetic average roughness Ra (JIS B 0601-1994) of the substrate surface is preferably 10 nm or less.
本発明のIII−Ｖ族窒化物系半導体基板の製造ロットは、複数のIII−Ｖ族窒化物系半導体基板から構成されるIII−Ｖ族窒化物系半導体基板の製造ロットであり、製造ロットを構成するすべての基板が、上記のIII−Ｖ族窒化物系半導体基板であることを特徴とする。 The production lot of the group III-V nitride semiconductor substrate of the present invention is a production lot of a group III-V nitride semiconductor substrate composed of a plurality of group III-V nitride semiconductor substrates. All the substrates which comprise are said III-V group nitride semiconductor substrates, It is characterized by the above-mentioned.
本発明のIII−Ｖ族窒化物系半導体デバイスは上記III−Ｖ族窒化物系半導体基板を用い、前記III−Ｖ族窒化物系半導体基板の上に、III−Ｖ族窒化物系半導体結晶からなるエピタキシャル層が形成されていることを特徴とする。 The group III-V nitride semiconductor device of the present invention uses the above group III-V nitride semiconductor substrate, and a group III-V nitride semiconductor crystal is formed on the group III-V nitride semiconductor substrate. An epitaxial layer is formed.
本発明のIII−Ｖ族窒化物系半導体デバイスの製造方法は、III−Ｖ族窒化物系半導体基板を水素ガスとアンモニアガスの混合ガス中で1200℃以下の温度で熱処理した後、前記III−Ｖ族窒化物系半導体基板上にIII−Ｖ族窒化物系半導体結晶をエピタキシャル成長させることを特徴とする。 In the method for producing a III-V nitride semiconductor device of the present invention, a III-V nitride semiconductor substrate is heat-treated at a temperature of 1200 ° C. or less in a mixed gas of hydrogen gas and ammonia gas, A III-V nitride semiconductor crystal is epitaxially grown on a group V nitride semiconductor substrate.
上記のIII−Ｖ族窒化物系半導体基板の製造ロットを用い、製造ロット内の各III−Ｖ族窒化物系半導体基板上にIII−Ｖ族窒化物系半導体結晶を同じ条件でエピタキシャル成長させることにより、III−Ｖ族窒化物系半導体デバイスを製造するのが好ましい。 By using the production lot of the above-mentioned group III-V nitride semiconductor substrate and epitaxially growing a group III-V nitride semiconductor crystal on each group III-V nitride semiconductor substrate in the production lot under the same conditions Preferably, a III-V nitride semiconductor device is manufactured.
本発明のIII−Ｖ族窒化物系半導体基板は、基板の熱分解のし易さの指標となる転位密度と水素原子濃度の積が所定のレベル以下であるため、優れた熱安定性を有し、サーマルクリーニングによる表面荒れを抑えることができる。そのため、本発明のIII−Ｖ族窒化物系半導体基板はレーザダイオード（LD）、発光ダイオード（LED）等のIII−Ｖ族窒化物系半導体デバイスに好適である。 The III-V nitride semiconductor substrate of the present invention has excellent thermal stability because the product of the dislocation density and the hydrogen atom concentration, which is an index of the ease of thermal decomposition of the substrate, is below a predetermined level. In addition, surface roughness due to thermal cleaning can be suppressed. Therefore, the group III-V nitride semiconductor substrate of the present invention is suitable for a group III-V nitride semiconductor device such as a laser diode (LD) and a light emitting diode (LED).
また基板の表面荒れを抑えつつサーマルクリーニングを十分に行うことが可能であるため、清浄な基板表面にデバイス構造のエピタキシャル層を成長させることができる。そのため、ウェハ面内のエピタキシャル層が均一になるとともに、ウェハ間のばらつきが少なくなり、発光素子や電子素子を歩留まり良く安定して製造することができる。 Further, since thermal cleaning can be sufficiently performed while suppressing surface roughness of the substrate, an epitaxial layer having a device structure can be grown on a clean substrate surface. For this reason, the epitaxial layer in the wafer surface becomes uniform, and variations between wafers are reduced, so that light-emitting elements and electronic elements can be stably manufactured with high yield.
[1] III−V族窒化物系半導体基板
本発明のIII−V族窒化物系半導体基板の特徴は、表面近傍のIII−Ｖ族窒化物系半導体単結晶中の水素原子濃度[H]（水素原子数/cm3）と単結晶表面における転位密度[D]（個/cm2）との積（[H]×[D]）が１×1025以下であることである。以下特に断りのない限り、水素原子濃度[H]は、SIMS（Secondary Ion Mass Spectrometry）により基板表面の直径に沿って５mm間隔で測定した水素原子濃度の平均値である。また転位密度[D]は、燐酸と硫酸の加熱混合液中に基板を浸漬し、エッチングにより生じたピットを基板の任意の９箇所で計数した場合の平均値である。
[1] Group III-V nitride semiconductor substrate The group III-V nitride semiconductor substrate of the present invention is characterized by the hydrogen atom concentration [H] in the group III-V nitride semiconductor single crystal near the surface (H) ( The product ([H] × [D]) of the number of hydrogen atoms / cm 3 ) and the dislocation density [D] (number / cm 2 ) on the single crystal surface is 1 × 10 25 or less. Unless otherwise specified, the hydrogen atom concentration [H] is an average value of hydrogen atom concentrations measured at intervals of 5 mm along the diameter of the substrate surface by SIMS (Secondary Ion Mass Spectrometry). The dislocation density [D] is an average value when the substrate is immersed in a heated mixed solution of phosphoric acid and sulfuric acid, and pits generated by etching are counted at any nine locations on the substrate.
本発明を適用し得るIII−Ｖ族窒化物系半導体としては、InxGayAl1-x-yＮ（０≦ｘ≦１、０≦ｙ≦１、０≦ｘ＋ｙ≦１）で表される半導体が挙げられる。中でも、強度、製造安定性等、基板材料に求められる特性を満足するという観点から、GaN及びAlGaNが特に好ましい。 The group III-V nitride semiconductor to which the present invention can be applied is a semiconductor represented by In x Ga y Al 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Is mentioned. Among these, GaN and AlGaN are particularly preferable from the viewpoint of satisfying characteristics required for the substrate material such as strength and manufacturing stability.
III−Ｖ族窒化物系半導体結晶のC面は強い極性を有し、III族面の方がＶ族面（窒素面）よりも化学的及び熱的に安定で、デバイスの作製が容易である。このため、基板の表面はC面のIII族面であるのが好ましい。 The C-plane of III-V nitride-based semiconductor crystals has a strong polarity, and the group III plane is more chemically and thermally stable than the group V plane (nitrogen plane), facilitating device fabrication. . For this reason, the surface of the substrate is preferably a C-group III surface.
本発明のIII−V族窒化物系半導体基板は、サファイア等の異種基板にIII−Ｖ族窒化物系半導体層が形成されたテンプレートであっても、III−Ｖ族窒化物系半導体層のみからなる自立基板であってもよい。ここで「自立基板」は、自らの形状を保持できるだけでなく、ハンドリングに不都合が生じない程度の強度を有する基板を意味する。このような強度を有するためには、自立基板の厚さを200μｍ以上とするのが好ましい。また素子形成後の劈開の容易性等を考慮し、自立基板の厚さを１mm以下とするのが好ましい。１mm超では劈開が困難となり、劈開面に凹凸が生じる。その結果、たとえば半導体レーザ等に適用した場合、反射のロスによるデバイス特性の劣化が問題となる。 Even if the group III-V nitride semiconductor substrate of the present invention is a template in which a group III-V nitride semiconductor layer is formed on a dissimilar substrate such as sapphire, the group III-V nitride semiconductor substrate is composed only of the group III-V nitride semiconductor layer. It may be a free-standing substrate. Here, the “self-standing substrate” means a substrate that can not only hold its own shape but also has a strength that does not cause inconvenience in handling. In order to have such strength, the thickness of the self-supporting substrate is preferably 200 μm or more. In consideration of easiness of cleavage after element formation, etc., the thickness of the freestanding substrate is preferably 1 mm or less. If it exceeds 1 mm, cleavage will be difficult, and the cleavage surface will be uneven. As a result, when applied to, for example, a semiconductor laser, degradation of device characteristics due to reflection loss becomes a problem.
III−Ｖ族窒化物系半導体層は六方晶系結晶及び立方晶系結晶のいずれでも良いが、六方晶系結晶の方が好ましい。六方晶系のIII-Ｖ族窒化物系半導体結晶は立方晶系の結晶に比べ安定であるため、結晶性の高いIII-Ｖ族窒化物系半導体結晶のエピタキシャル層を厚く形成することが可能であり、デバイスを作製する際の自由度を高くすることができる。 The III-V nitride semiconductor layer may be either a hexagonal crystal or a cubic crystal, but a hexagonal crystal is preferred. Since hexagonal group III-V nitride semiconductor crystals are more stable than cubic crystals, it is possible to form a thick epitaxial layer of III-V group nitride semiconductor crystals with high crystallinity. Yes, the degree of freedom in manufacturing the device can be increased.
本発明のIII−Ｖ族窒化物系半導体基板は、結晶成長で得られたままの基板でもそれに研磨加工を施した基板でも良く、また結晶成長で得られた基板に脱水素処理を施した基板でもそれに研磨加工を施した基板でも良い。脱水素処理は、基板を真空中、窒素中等の水素を含まない条件下で、数百度程度の温度に所定時間保持することにより、結晶中に固溶した水素を抜く処理であり、p型GaNの活性化のため広く用いられている処理である。 The group III-V nitride semiconductor substrate of the present invention may be a substrate obtained by crystal growth or a substrate subjected to polishing processing, or a substrate obtained by subjecting the substrate obtained by crystal growth to dehydrogenation treatment. However, it may be a substrate subjected to polishing processing. The dehydrogenation process is a process for removing hydrogen dissolved in the crystal by holding the substrate at a temperature of several hundred degrees for a predetermined time under a condition that does not contain hydrogen, such as in vacuum or nitrogen. This process is widely used for the activation of.
[2] III−V族窒化物系半導体基板の製造方法
III−Ｖ族窒化物系半導体結晶を成長させる方法として、MOVPE法、MBE法、HVPE法等の公知の方法を用いることができる。中でもHVPE法は結晶成長速度が速く、基板の作製に適しているので好ましい。
[2] Method for producing group III-V nitride semiconductor substrate
As a method for growing a III-V nitride semiconductor crystal, a known method such as MOVPE method, MBE method, HVPE method or the like can be used. Among them, the HVPE method is preferable because it has a high crystal growth rate and is suitable for manufacturing a substrate.
本発明の基板の導電型は、目的とするデバイスに合わせて適宜制御すべきであり、一律に決めることはできない。例えば、Si、S、O等をドープしたｎ型、MgやZn等をドープしたp型及びFe、Ni、Ｃｒ等の遷移金属原子をドープした半絶縁型が挙げられる。 The conductivity type of the substrate of the present invention should be appropriately controlled according to the target device, and cannot be determined uniformly. For example, an n-type doped with Si, S, O, etc., a p-type doped with Mg, Zn, etc., and a semi-insulating type doped with transition metal atoms such as Fe, Ni, Cr, etc.
本発明のIII−Ｖ族窒化物系半導体基板は、表面を鏡面研磨するのが望ましい。一般に、アズグロウンのIII−Ｖ族窒化物系半導体エピタキシャル表面には、ヒロック等の大きな凹凸や、ステップバンチングによって現れると思われる微少な凹凸が多数存在している。これらは、その上に成長させるエピタキシャル層のモフォロジを悪化させたり、膜厚、組成等を不均一にする要因となるばかりでなく、デバイス作製工程においても、フォトリソグラフィ工程の露光精度を低下させる要因となる。このため、基板表面は平坦な鏡面であるのが好ましい。 The surface of the III-V nitride semiconductor substrate of the present invention is preferably mirror-polished. In general, the as-grown III-V nitride semiconductor epitaxial surface has a large number of large irregularities such as hillocks and minute irregularities that appear to be caused by step bunching. These factors not only deteriorate the morphology of the epitaxial layer grown on it, but also cause the film thickness, composition, etc. to be non-uniform, and also reduce the exposure accuracy of the photolithography process in the device fabrication process. It becomes. For this reason, the substrate surface is preferably a flat mirror surface.
本明細書において使用する用語「転位」は、結晶成長で生じた転位のみならず、結晶成長後に研磨加工等により導入された欠陥も含む。鏡面研磨した基板の表面には加工ダメージ層が残留している場合がある。従って、転位密度を低減して表面荒れの生じにくい基板を得るためには、鏡面研磨後の加工ダメージ層をウェットエッチング、ドライエッチング、歪除去アニール等により除去するのが望ましい。 The term “dislocation” used in this specification includes not only dislocations generated by crystal growth but also defects introduced by polishing or the like after crystal growth. A processing damage layer may remain on the surface of the mirror-polished substrate. Therefore, in order to reduce the dislocation density and obtain a substrate that is less prone to surface roughness, it is desirable to remove the processing damage layer after mirror polishing by wet etching, dry etching, strain removal annealing, or the like.
鏡面研磨加工後の基板表面の平坦度は、算術平均粗さRaで10 nm以下であるのが好ましい。なお算術平均粗さRaは基板表面の50μｍ×50μｍの範囲を測定して求めたものである。サーマルクリーニングによる表面荒れは、基板の表面粗さにも依存しており、算術平均粗さRaが10 nmを超えると、[H]×[D]の値を低く抑えてもサーマルクリーニングにより表面荒れが発生することがある。 The flatness of the substrate surface after mirror polishing is preferably 10 nm or less in terms of arithmetic average roughness Ra. The arithmetic average roughness Ra is obtained by measuring a 50 μm × 50 μm range of the substrate surface. The surface roughness due to thermal cleaning also depends on the surface roughness of the substrate. When the arithmetic average roughness Ra exceeds 10 nm, the surface roughness is caused by thermal cleaning even if the value of [H] x [D] is kept low. May occur.
III−Ｖ族窒化物系半導体基板の裏面も平坦に鏡面研磨するのが望ましい。III−Ｖ族窒化物系半導体の自立基板は、異種の下地基板にヘテロエピタキシャル成長させた後に下地基板を剥離して得られるので、剥離したままでは裏面が梨地状に荒れていたり、下地基板の一部が付着していたりすることが多い。また基板の反りに起因して、平坦でない場合もある。このため、基板上にヘテロエピタキシャル層を成長させる際に基板の温度分布が不均一になり、その結果ヘテロエピタキシャル層の均一性が低下したり、再現性が悪化したりする。 It is desirable that the rear surface of the group III-V nitride semiconductor substrate be mirror-polished flat. Since the free-standing substrate of the III-V nitride semiconductor is obtained by heteroepitaxial growth on a different type of base substrate and then peeling off the base substrate, the back surface is roughened in a satin state as it is peeled off. Part is often attached. Further, it may not be flat due to warpage of the substrate. For this reason, when the heteroepitaxial layer is grown on the substrate, the temperature distribution of the substrate becomes nonuniform, and as a result, the uniformity of the heteroepitaxial layer is lowered or the reproducibility is deteriorated.
本発明のIII−V族窒化物系半導体基板を製造する際、例えば脱水素処理を行ったり、転位密度を低減するためにELO法（特許文献３）やVAS法（特許文献４）等を組合せたりしても良い。また下地基板はサファイアに限られず、GaAs、Si、ZrB2、ZnO等のGaN系エピタキシャル成長用基板として報告されている全ての基板を使用することができる。 When manufacturing the group III-V nitride semiconductor substrate of the present invention, for example, the dehydrogenation process is performed, or the ELO method (Patent Document 3) or the VAS method (Patent Document 4) is combined to reduce the dislocation density. You may do it. The underlying substrate is not limited to sapphire, and any substrate reported as a GaN-based epitaxial growth substrate such as GaAs, Si, ZrB 2 , or ZnO can be used.
[3] III−V族窒化物系半導体デバイス及びその製造方法
上記の通り、III−V族窒化物系半導体基板に鏡面研磨加工を施すと、基板表面にダメージを受けて欠陥が生じる。従って、鏡面研磨した基板表面に直接エピタキシャル層を成長させると、基板表面の欠陥の影響により、エピタキシャル層の表面状態が悪化する。このため、エピタキシャル成長前に、基板表面にサーマルクリーニングを行う。サーマルクリーニングの温度は1200℃以下である。1200℃超では基板表面の欠陥がかえって増大し、その上に形成するデバイスの性能が悪化する。サーマルクリーニング温度の下限は550℃が好ましい。550℃未満では基板表面の清浄化が十分に行われない。サーマルクリーニング時間は温度に応じて異なるが、一般に５〜30分程度で良い。
[3] Group III-V nitride semiconductor device and manufacturing method thereof As described above, when the III-V nitride semiconductor substrate is mirror-polished, the substrate surface is damaged and a defect is generated. Therefore, when the epitaxial layer is directly grown on the mirror-polished substrate surface, the surface state of the epitaxial layer is deteriorated due to the influence of defects on the substrate surface. For this reason, thermal cleaning is performed on the substrate surface before epitaxial growth. Thermal cleaning temperature is 1200 ° C or less. If it exceeds 1200 ° C., defects on the substrate surface will increase, and the performance of the device formed thereon will deteriorate. The lower limit of the thermal cleaning temperature is preferably 550 ° C. Below 550 ° C, the substrate surface is not sufficiently cleaned. The thermal cleaning time varies depending on the temperature, but generally it may be about 5 to 30 minutes.
サーマルクリーニングは、(a) アンモニアガス、又は(b) アンモニアガスと水素ガス、窒素ガス等との混合ガスの雰囲気中で行うのが好ましい。特に好ましいサーマルクリーニング雰囲気は、アンモニアガスと水素ガスの混合ガスである。アンモニアガスと水素ガスの混合ガス中のアンモニアガス／水素ガスの比は１／20〜20／１が好ましい。アンモニアガス／水素ガスの比が１／20未満ではエッチング反応が進みすぎて、表面荒れが生じやすく、また20／1超では、基板表面の改質効果が低くなるという問題が生じる。 The thermal cleaning is preferably performed in an atmosphere of (a) ammonia gas or (b) a mixed gas of ammonia gas and hydrogen gas, nitrogen gas, or the like. A particularly preferable thermal cleaning atmosphere is a mixed gas of ammonia gas and hydrogen gas. The ratio of ammonia gas / hydrogen gas in the mixed gas of ammonia gas and hydrogen gas is preferably 1/20 to 20/1. If the ratio of ammonia gas / hydrogen gas is less than 1/20, the etching reaction proceeds too much and surface roughness tends to occur, and if it exceeds 20/1, the effect of modifying the substrate surface becomes low.
サーマルクリーニングにより欠陥を除去した基板上にデバイス構造のエピタキシャル層を成長させる。エピタキシャル層の成長方法は特に制限されず、MOVPE法、MBE法、HVPE法等の公知の方法を適宜用いてよい。 An epitaxial layer having a device structure is grown on the substrate from which defects have been removed by thermal cleaning. The growth method of the epitaxial layer is not particularly limited, and a known method such as MOVPE method, MBE method, HVPE method or the like may be appropriately used.
本発明を以下の実施例によりさらに詳細に説明するが、本発明はそれらに限定されるものではない。 The present invention will be described in more detail with reference to the following examples, but the present invention is not limited thereto.
実施例１
MOVPE法、MBE法又はHVPE法により故意に成長条件を変えて、転位密度及び水素原子濃度が異なるGaNテンプレート及びGaN自立基板を15種類作製した。各基板の製造条件を表１に示す。VAS法で成長させたGaN自立基板の表面には、鏡面研磨を施した。
Example 1
By intentionally changing the growth conditions by MOVPE, MBE, or HVPE, 15 types of GaN templates and GaN free-standing substrates with different dislocation densities and hydrogen atom concentrations were fabricated. The manufacturing conditions for each substrate are shown in Table 1. The surface of the GaN free-standing substrate grown by the VAS method was mirror polished.
MOVPE法又はMBE法によるGaNテンプレートは、サファイア下地基板上にGaN低温成長バッファ層を介してGaN層を成長させることにより作製した。またHVPE法によるGaN基板としては、ELO法を用いたGaN基板（ELO基板）と、VAS法を用いたGaN自立基板（VAS自立基板）の２種類を作製した。 A GaN template by MOVPE or MBE was prepared by growing a GaN layer on a sapphire base substrate through a GaN low-temperature growth buffer layer. Two types of GaN substrates using the HVPE method were prepared: a GaN substrate using the ELO method (ELO substrate) and a GaN free-standing substrate using the VAS method (VAS free-standing substrate).
ELO基板は、MOVPE法で作製したGaNテンプレート上に、ストライプ状のSiO2マスクを設け、トリメチルガリウム（TMG）及びNH3を原料ガスとしてMOVPE法によりGaN層を成長させた後、GaCl及びNH3を原料ガスとしてHVPE法によりさらにGaN層を成長させて作製した。 The ELO substrate is provided with a striped SiO 2 mask on a GaN template fabricated by the MOVPE method, and after growing a GaN layer by the MOVPE method using trimethylgallium (TMG) and NH 3 as source gases, the GaCl and NH 3 A GaN layer was further grown by HVPE using as a source gas.
VAS自立基板は、MOVPE法で作製したGaNテンプレート上に金属Tiの薄膜を蒸着し、20％のNH3を含有するH2気流中で熱処理を施すことにより金属Ti薄膜を微細な孔が高密度に形成されたTiN薄膜とした後、HVPE法によりGaN層を成長させて作製した。 VAS free-standing substrate is a metal Ti thin film deposited on a GaN template fabricated by the MOVPE method and heat-treated in a H 2 stream containing 20% NH 3. After forming the TiN thin film formed in GaN, a GaN layer was grown by the HVPE method.
得られた基板の結晶中の水素原子濃度[H]をSIMS分析により求めた。基板表面における転位密度[D]は、GaN基板を燐酸と硫酸の加熱混合液中でエッチングし、現れたエッチピットを計数することにより求めた。各GaN基板の種類及び特性を表２に示す。 The hydrogen atom concentration [H] in the crystal of the obtained substrate was determined by SIMS analysis. The dislocation density [D] on the substrate surface was determined by etching the GaN substrate in a heated mixed solution of phosphoric acid and sulfuric acid and counting the number of etch pits that appeared. Table 2 shows the types and characteristics of each GaN substrate.
各GaN基板を、抵抗加熱方式の横型MOVPE炉内において、NH3とH2の混合気流（NH3：H2＝１：１）中、常圧下1150℃で20分間加熱し、サーマルクリーニングを行った。上記熱処理条件は、一般に用いられているサーマルクリーニングの中で特に厳しい条件、すなわちクリーニング効果が高い反面、基板の表面荒れが生じる危険性も高い条件である。 Each GaN substrate is heated in a mixed gas stream of NH 3 and H 2 (NH 3 : H 2 = 1: 1) at 1150 ° C. for 20 minutes in a resistance heating horizontal MOVPE furnace to perform thermal cleaning. It was. The heat treatment conditions are particularly severe conditions in the thermal cleaning generally used, that is, a condition that the cleaning effect is high, but the risk of the substrate surface being rough is also high.
熱処理した各基板を急冷した後、炉から取り出して表面状態をノマルスキー顕微鏡で観察し、表面荒れの有無を判定した。表面荒れが無しとはGaN基板の表面が平坦なままの状態であることを示し、表面荒れが有りとはGaN基板表面が鮫肌状の状態（さらに荒れが進行すると、サーマルピットと呼ばれるピットがびっしりと形成された状態）になったことを示す。各基板の表面荒れの評価結果を表２に示す。さらに各基板の結晶中の水素原子濃度[H]と基板表面における転位密度[D]を図１に示す。 After each heat-treated substrate was rapidly cooled, it was taken out from the furnace and the surface state was observed with a Nomarski microscope to determine the presence or absence of surface roughness. No surface roughness means that the surface of the GaN substrate remains flat. If there is surface roughness, the surface of the GaN substrate has a skin-like state (if the roughness further advances, the pits called thermal pits are packed. And the formed state). Table 2 shows the evaluation results of the surface roughness of each substrate. Further, FIG. 1 shows the hydrogen atom concentration [H] in the crystal of each substrate and the dislocation density [D] on the substrate surface.
表２及び図１から明らかなように、GaN基板の水素原子濃度が低いほど、表面荒れが生じにくい傾向が見られるが、水素原子濃度が低くても転位密度が高いと表面荒れが生じることが分かる。同様に、GaN基板の転位密度が低いほど、表面荒れが生じにくい傾向が見られるが、転位密度が低くても水素原子濃度が高いと表面荒れが生じることが分かる。すなわち、GaN基板にサーマルクリーニングによる表面荒れを生じさせないためには、その水素原子濃度を低く、かつ転位密度を低くすることが必要であることが分かる。以上の検討から、GaN基板にサーマルクリーニングにより表面荒れを生じさせないための境界条件は、水素原子濃度と転位密度との積（[H]×[D]）が１×1025以下であることが分かった。さらに、GaN層の成長方法や厚さは、基板の荒れやすさと直接関係がないことも分かった。 As is clear from Table 2 and FIG. 1, the lower the hydrogen atom concentration of the GaN substrate, the less the surface roughness tends to occur. However, even if the hydrogen atom concentration is low, the surface roughness may occur when the dislocation density is high. I understand. Similarly, as the dislocation density of the GaN substrate is lower, the surface roughness tends to be less likely to occur, but it can be seen that even if the dislocation density is low, the surface roughness occurs when the hydrogen atom concentration is high. That is, it can be seen that it is necessary to reduce the hydrogen atom concentration and the dislocation density in order not to cause surface roughness due to thermal cleaning on the GaN substrate. From the above examination, the boundary condition for preventing the surface roughness of the GaN substrate by thermal cleaning is that the product ([H] × [D]) of the hydrogen atom concentration and the dislocation density is 1 × 10 25 or less. I understood. It was also found that the growth method and thickness of the GaN layer had no direct relationship with the roughness of the substrate.
実施例２
面方位をｍ軸方向に0.2°オフさせた直径２インチのＣ面の単結晶サファイア下地基板を用い、この基板に対して、水素ガス雰囲気中で1200℃で10分間サーマルクリーニングを行い、表面を清浄化した。サファイア下地基板の温度を600℃に下げ、当該基板上に、トリメチルガリウム（TMG）とNH3を原料ガスとし、成長圧力を常圧としてMOVPE法によりGaN低温バッファ層を20 nm成長させた。次に下地基板の温度を1050℃まで昇温して、GaN低温バッファ層を1050℃で５分間熱処理して、微結晶化させた（この熱処理工程により、次に成長するGaN結晶の初期の核発生密度を減少させることができ、結果として転位密度を比較的低減することができた。）。得られた基板上に引き続き原料ガスを供給することにより、GaNエピタキシャル層を４μｍ成長させた。その際、キャリアガスとして水素と窒素の混合ガスを用い、結晶の成長速度を約４μｍ／時とした。成長したGaN層を炉内で800℃まで冷却したところで、脱水素処理と同様の効果を得るため、雰囲気ガスを窒素ガスのみに切り替え、水素ガスを含まない雰囲気中で100℃以下になるまで約３時間かけて徐冷した。こうして、比較的低転位かつ含有水素濃度の低いGaNテンプレートを得た。このGaNテンプレートの表面を50μｍ×50μｍの範囲で測定した算術平均粗さRaは、任意のどこの点を測定しても、２nm以下であった。
Example 2
Using a C-plane single crystal sapphire base substrate with a diameter of 2 inches with the plane orientation turned off by 0.2 ° in the m-axis direction, this substrate was subjected to thermal cleaning at 1200 ° C for 10 minutes in a hydrogen gas atmosphere. Cleaned. The temperature of the sapphire base substrate was lowered to 600 ° C., and a GaN low-temperature buffer layer was grown to 20 nm on the substrate by MOVPE using trimethylgallium (TMG) and NH 3 as source gases and a growth pressure of normal pressure. Next, the temperature of the base substrate was raised to 1050 ° C., and the GaN low-temperature buffer layer was heat-treated at 1050 ° C. for 5 minutes to be microcrystallized (the initial nucleus of the next grown GaN crystal by this heat treatment step). The generation density could be reduced, and as a result, the dislocation density could be reduced relatively.) By continuously supplying a source gas onto the obtained substrate, a GaN epitaxial layer was grown by 4 μm. At that time, a mixed gas of hydrogen and nitrogen was used as a carrier gas, and the crystal growth rate was about 4 μm / hour. When the grown GaN layer is cooled down to 800 ° C in the furnace, the atmosphere gas is switched to only nitrogen gas in order to obtain the same effect as the dehydrogenation treatment. It was gradually cooled over 3 hours. Thus, a GaN template having a relatively low dislocation and a low hydrogen concentration was obtained. The arithmetic average roughness Ra measured on the surface of the GaN template in a range of 50 μm × 50 μm was 2 nm or less, regardless of where the arbitrary point was measured.
このGaNテンプレートの表面における転位密度は、燐酸と硫酸の加熱混合液中に基板を浸漬し、エッチングにより生じたピットを計数することにより求めた。その結果、このGaNテンプレートの面内転位密度は（１±１）×10８個/cm2であった。GaNテンプレートの表面近傍の水素原子濃度をSIMSにより基板の直径に沿って５mm間隔で測定したところ、８×1016水素原子数/cm3未満であった。８×1016水素原子数/cm3はSIMSの検出下限であるので、このGaNテンプレートの表面近傍の水素原子濃度はSIMSの検出下限未満であることが分かる。以上の結果から、本実施例のGaNテンプレートの[H]×[D]は約８×1024未満であった。 The dislocation density on the surface of the GaN template was determined by immersing the substrate in a heated mixed solution of phosphoric acid and sulfuric acid and counting the pits generated by etching. As a result, the in-plane dislocation density of this GaN template was (1 ± 1) × 10 8 pieces / cm 2 . The hydrogen atom concentration in the vicinity of the surface of the GaN template was measured at 5 mm intervals along the diameter of the substrate by SIMS and found to be less than 8 × 10 16 hydrogen atoms / cm 3 . Since 8 × 10 16 hydrogen atoms / cm 3 is the SIMS detection lower limit, it can be seen that the hydrogen atom concentration near the surface of the GaN template is lower than the SIMS detection lower limit. From the above results, [H] × [D] of the GaN template of this example was less than about 8 × 10 24 .
比較例１
面方位をｍ軸方向に0.2°オフさせた直径２インチのＣ面の単結晶サファイア下地基板を用い、この基板に対して、水素ガス雰囲気中で1200℃で10分間サーマルクリーニングを行い、表面を清浄化した。サファイア下地基板の温度を600℃に下げ、当該基板上に、TMGとNH3を原料ガスとし、成長圧力を常圧としてMOVPE法によりGaN低温バッファ層を20 nmの厚さに成長させた。次に下地基板の温度を1050℃まで昇温して、GaN層を２μｍの厚さに成長させた（低温バッファ層の熱処理は行わなかった。）。成長時のキャリアガスとしては、水素と窒素の混合ガスを用い、結晶の成長速度は約４μｍ／時とした。成長したGaN層を、成長雰囲気と同様のアンモニアと水素及び窒素の混合ガス中で100℃まで冷却し、GaNテンプレートを得た。このGaNテンプレートの表面を50μｍ×50μｍの範囲で測定した算術平均粗さRaは実施例２と遜色なかった。
Comparative Example 1
Using a C-plane single crystal sapphire base substrate with a diameter of 2 inches with the plane orientation turned off by 0.2 ° in the m-axis direction, this substrate was subjected to thermal cleaning at 1200 ° C for 10 minutes in a hydrogen gas atmosphere. Cleaned. The temperature of the sapphire base substrate was lowered to 600 ° C., and a GaN low-temperature buffer layer was grown on the substrate to a thickness of 20 nm by MOVPE using TMG and NH 3 as source gases and a growth pressure of normal pressure. Next, the temperature of the base substrate was raised to 1050 ° C., and a GaN layer was grown to a thickness of 2 μm (the low-temperature buffer layer was not heat-treated). As a carrier gas during growth, a mixed gas of hydrogen and nitrogen was used, and the crystal growth rate was about 4 μm / hour. The grown GaN layer was cooled to 100 ° C. in a mixed gas of ammonia, hydrogen and nitrogen similar to the growth atmosphere to obtain a GaN template. The arithmetic average roughness Ra measured on the surface of this GaN template in the range of 50 μm × 50 μm was not inferior to Example 2.
GaNテンプレートの表面転位密度及び表面近傍の水素原子濃度を、実施例２と同様にして求めた。その結果、GaNテンプレートの面内の転位密度は（２±１）×10９個/cm2であり、GaNエピタキシャル層中の水素原子濃度は１×1017水素原子数/cm3であった。以上の結果から、比較例１のGaNテンプレートの[H]×[D]は約２×1026であった。 The surface dislocation density and the hydrogen atom concentration near the surface of the GaN template were determined in the same manner as in Example 2. As a result, the in-plane dislocation density of the GaN template was (2 ± 1) × 10 9 atoms / cm 2 , and the hydrogen atom concentration in the GaN epitaxial layer was 1 × 10 17 hydrogen atoms / cm 3 . From the above results, [H] × [D] of the GaN template of Comparative Example 1 was about 2 × 10 26 .
（評価）
実施例２及び比較例１のGaNテンプレートの各々を半分に割り、半円状の実施例２のGaNテンプレートと半円状の比較例１のGaNテンプレートとを組み合わせて、基板サセプタ上に並べ、MOVPE反応容器内にセットした。これらのGaNテンプレートをNH3とH2との混合気流（NH3：H2＝１：２）中で1100℃まで昇温し、20分間保持してサーマルクリーニングを行い、表面を清浄化した。基板上にTMGとNH3を供給して、GaN層を２μｍの厚さにホモエピタキシャル成長させた。その際、成長圧力を常圧とし、キャリアガスとして水素と窒素の混合ガスを用いた。
(Evaluation)
Each of the GaN templates of Example 2 and Comparative Example 1 was divided in half, and the semicircular GaN template of Example 2 and the semicircular GaN template of Comparative Example 1 were combined and arranged on a substrate susceptor. It set in the reaction container. These GaN templates were heated to 1100 ° C. in a mixed gas stream of NH 3 and H 2 (NH 3 : H 2 = 1: 2), held for 20 minutes, and subjected to thermal cleaning to clean the surface. TMG and NH 3 were supplied onto the substrate, and the GaN layer was homoepitaxially grown to a thickness of 2 μm. At that time, the growth pressure was normal pressure, and a mixed gas of hydrogen and nitrogen was used as a carrier gas.
GaNのホモエピタキシャル成長を行った各GaNテンプレートを取り出し、投光器を用いて目視で表面観察を行ったところ、実施例２のGaNテンプレートの上に成長させたGaN層の表面は曇りのない鏡面であったのに対し、比較例１のGaNテンプレートの上に成長させたGaN層表面はうっすらと曇っていた。各GaN層の表面をノマルスキー顕微鏡で観察したところ、実施例２のGaN層表面には、図２に示す通り、モフォロジは観察されなかった。一方、比較例１のGaN層表面には、図３に示すように、サーマルピットと同形状の凹凸が多数存在していた。これは、GaNのホモエピタキシャル成長前に比較例１のGaNテンプレート表面が荒れてしまい、荒れた表面上にエピタキシャル成長させたことにより現れたモフォロジであると推定される。 Each GaN template on which GaN homoepitaxial growth was performed was taken out and visually observed using a projector. As a result, the surface of the GaN layer grown on the GaN template of Example 2 was a mirror surface with no haze. On the other hand, the surface of the GaN layer grown on the GaN template of Comparative Example 1 was slightly cloudy. When the surface of each GaN layer was observed with a Nomarski microscope, morphology was not observed on the surface of the GaN layer of Example 2 as shown in FIG. On the other hand, as shown in FIG. 3, the surface of the GaN layer of Comparative Example 1 had many irregularities having the same shape as the thermal pit. This is presumed to be a morphology that appears when the surface of the GaN template of Comparative Example 1 is roughened before homoepitaxial growth of GaN and epitaxially grown on the roughened surface.
実施例３
直径２インチの単結晶サファイア下地基板のC面上に、TMGとNH3を原料ガスとしてMOVPE法によりアンドープGaN層を300 nmの厚さに成長させた。このアンドープGaN層上に、金属Tiの薄膜を20 nmの厚さに蒸着した。得られた基板を電気炉に入れ、20％のNH3を含有するH2気流中で1050℃で20分間熱処理した。その結果、GaN層の一部がエッチングされて高密度の空隙（ボイド層）が発生し、またTi層は窒化されてサブミクロンの微細な穴が高密度に形成されたTiN層に変化した。
Example 3
An undoped GaN layer was grown to a thickness of 300 nm on the C-plane of a single-crystal sapphire substrate with a diameter of 2 inches by MOVPE using TMG and NH 3 as source gases. A metal Ti thin film was deposited on the undoped GaN layer to a thickness of 20 nm. The obtained substrate was put in an electric furnace and heat-treated at 1050 ° C. for 20 minutes in an H 2 stream containing 20% NH 3 . As a result, a part of the GaN layer was etched to form a high-density void (void layer), and the Ti layer was nitrided to change to a TiN layer in which fine submicron holes were formed at a high density.
この基板をHVPE炉に入れ、キャリアガス中に８×10-3atmのGaCl及び4.8×10-2atmのNH3からなる原料ガスを含有する供給ガス用いて、GaN層を600μｍの厚さに成長させた。キャリアガスとして、GaN層表面の水素原子濃度を低くするため、成長の前半ではH2を５％含有するＮ2ガスを用い、約400μｍの厚さになった段階で、N2ガスのみに切り替えた。GaN層の成長条件は常圧及び1080℃の基板温度であった。またGaN結晶の成長工程において、ドーピング原料ガスとしてSiH2Cl2を基板領域に供給することによりSiをドープした。成長が終了した後、HVPE装置を冷却する過程で、GaN層はボイド層を境に下地基板から自然に剥離し、GaNの自立基板が得られた。 This substrate is put in an HVPE furnace, and a GaN layer is formed to a thickness of 600 μm using a supply gas containing a source gas composed of 8 × 10 −3 atm GaCl and 4.8 × 10 −2 atm NH 3 in a carrier gas. Grown up. In order to reduce the hydrogen atom concentration on the surface of the GaN layer as the carrier gas, N 2 gas containing 5% H 2 was used in the first half of the growth and switched to only N 2 gas when the thickness reached about 400 μm. It was. The growth conditions of the GaN layer were normal pressure and a substrate temperature of 1080 ° C. In the GaN crystal growth process, Si was doped by supplying SiH 2 Cl 2 as a doping source gas to the substrate region. After the growth was completed, in the process of cooling the HVPE device, the GaN layer naturally separated from the underlying substrate with the void layer as a boundary, and a GaN free-standing substrate was obtained.
得られた自立基板の表面及び裏面をそれぞれ研磨により除去し、両面とも鏡面状とした。表面側の除去厚さは100μｍであり、裏面側の除去厚さは70μｍであり、最終厚さは430μｍであった。また同じ条件で、10枚のGaN自立基板を作製した。 The front and back surfaces of the obtained free-standing substrate were each removed by polishing, and both surfaces were mirror-like. The removal thickness on the front side was 100 μm, the removal thickness on the back side was 70 μm, and the final thickness was 430 μm. In addition, 10 GaN free-standing substrates were fabricated under the same conditions.
得られたGaN自立基板の中から１枚を抜き取り、SIMSにより基板表面近傍の水素原子濃度を基板の直径に沿って５mm間隔で測定した。その結果、GaN結晶中の水素原子濃度は、いずれの点においてもSIMSの検出下限（８×1016水素原子数/cm3）未満に収まっていた。またGaN自立基板の表面転位密度を、燐酸と硫酸の加熱混合液中に基板を浸漬し、エッチングにより生じたピットを計数することによって求めた。その結果、GaN自立基板の面内転位密度は（4.2±１）×106個/cm2であった。以上の結果から、GaN自立基板の[H]×[D]は約3.4×1023以下であった。 One of the obtained GaN free-standing substrates was extracted, and the hydrogen atom concentration near the substrate surface was measured at 5 mm intervals along the diameter of the substrate by SIMS. As a result, the hydrogen atom concentration in the GaN crystal was below the SIMS detection limit (8 × 10 16 hydrogen atoms / cm 3 ) at any point. The surface dislocation density of the GaN free-standing substrate was determined by immersing the substrate in a heated mixed solution of phosphoric acid and sulfuric acid and counting the pits generated by etching. As a result, the in-plane dislocation density of the GaN free-standing substrate was (4.2 ± 1) × 10 6 pieces / cm 2 . From the above results, [H] × [D] of the GaN free-standing substrate was about 3.4 × 10 23 or less.
上記GaN自立基板から６枚を選び、同時成長が可能なMOVPE成長装置を用い、全数同時にLED構造のエピタキシャル層を成長させた。原料ガスとしてTMG、TMA（トリメチルアルミニウム）、TMI（トリメチルインジウム）及びNH3を用いた。まずGaN自立基板をNH3とH2との混合気流（NH3：H2＝１：２）中で1150℃まで昇温し、その温度に５分間保持した後、第一層の成長に必要なIII族原料ガスから順に流し、各エピタキシャル層を成長させた。成長したエピタキシャルウエハの構造は、基板側から順に、厚さ１μｍのn-GaN層、In0.15Ga0.85N／GaN-３-MQW活性層（Well層の厚さ３nm、障壁層の厚さ10 nm）、厚さ40 nmのp-Al0.1Ga0.9Ｎ層、及び厚さ500 nmのp-GaN層からなるものであった。MQW層は温度を800℃まで下げて成長させた。それ以外の層の成長温度は1150℃であった。成長圧力はすべて常圧とした。 Six of the above GaN free-standing substrates were selected, and an epitaxial layer with an LED structure was grown at the same time using a MOVPE growth apparatus capable of simultaneous growth. TMG, TMA (trimethylaluminum), TMI (trimethylindium), and NH 3 were used as source gases. First, the GaN free-standing substrate is heated to 1150 ° C in a mixed gas stream of NH 3 and H 2 (NH 3 : H 2 = 1: 2), held at that temperature for 5 minutes, and then necessary for the growth of the first layer Each epitaxial layer was grown by flowing in order from the Group III source gas. The structure of the grown epitaxial wafer consists of an n-GaN layer with a thickness of 1 μm, an In 0.15 Ga 0.85 N / GaN-3-MQW active layer (Well layer thickness 3 nm, barrier layer thickness 10 nm in order from the substrate side). ), A p-Al 0.1 Ga 0.9 N layer having a thickness of 40 nm, and a p-GaN layer having a thickness of 500 nm. The MQW layer was grown at a temperature reduced to 800 ° C. The growth temperature of the other layers was 1150 ° C. All growth pressures were normal.
成長したエピタキシャル層の表面状態を、全数の基板についてノマルスキー顕微鏡で観察した。その結果、いずれの表面もきれいな鏡面であり、サーマルクリーニングにより表面荒れが発生した基板は１枚もなかった。 The surface state of the grown epitaxial layer was observed with a Nomarski microscope for all the substrates. As a result, all the surfaces were clean mirror surfaces, and no substrate was roughened by the thermal cleaning.
以上本発明を実施例により詳細に説明したが、これらは例示であり、本発明の技術的思想の範囲内で種々の変更が可能である。例えば、脱水素工程を独立に設けたり、転位密度の低減のために従来から知られているSiO2等のマスクを用いるELO技術を組合せて用いても良い。実施例では下地基板にサファイアを用いたが、その他にGaAsやSi、ZrB2、ZnO等の基板も使用可能である。 The present invention has been described in detail with reference to the embodiments. However, these are merely examples, and various modifications can be made within the scope of the technical idea of the present invention. For example, a dehydrogenation step may be provided independently, or a conventionally known ELO technique using a mask such as SiO 2 may be used in combination for reducing the dislocation density. In the embodiment, sapphire is used as the base substrate, but other substrates such as GaAs, Si, ZrB 2 , and ZnO can also be used.
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