JP2009208989A - Compound semiconductor substrate and method for producing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate in which dislocations in the whole element layer can be reduced uniformly within the surface and the area of the low dislocation region can be simply enlarged. <P>SOLUTION: The compound semiconductor substrate is prepared by the steps of: forming a SiC layer 2 on a Si substrate 1 by a CVD method; forming an interlayer 3 comprising an In<SB>W</SB>Ga<SB>x</SB>Al<SB>1-w-x</SB>N single crystal (0≤w<1, 0≤x<1, w+x<1) having a plurality of pits 5 of an inverted hexagonal pyramid shape or an inverted hexagonal truncated cone shape having a depth which reaches an interface with the SiC layer 2 by an MOCVD method; and forming a nitride semiconductor single crystal layer 4 composed of an In<SB>y</SB>Ga<SB>z</SB>Al<SB>1-y-z</SB>N single crystal (0≤y<1, 0≤z<1, y+z<1) by an MOCVD method. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a compound semiconductor substrate suitably used for next-generation optical devices, electronic devices, and the like, and a method for manufacturing the same.

Nitride-based compound semiconductors have a wide band gap and are expected to realize devices that exceed the performance of silicon semiconductors in terms of breakdown voltage, on-resistance, high-temperature operating characteristics, and the like.
Blue LED (light-emitting diode) and blue-violet LD (laser diode) have already been commercialized as applications of nitride compound semiconductors to optical devices. As applications to electronic devices, high-speed and high-output HFETs (Heterostructure Field-Effect Transistors) and the like are in the practical stage.

  In any field, improvement in device performance requires improvement of crystal quality, that is, reduction of dislocations. In particular, in LDs and HFETs that require a high breakdown voltage, the demand for reducing dislocations is very strict.

  In response to such a requirement, for example, Patent Document 1 discloses that after etching the first GaN-based compound semiconductor formed on the substrate into an island state so that the exposed portions of the substrate are scattered, A method is described in which a second GaN compound semiconductor is grown using one GaN compound semiconductor as a nucleus, and an element layer made of the GaN compound semiconductor is formed thereon. Accordingly, it is described that the threading dislocation in the vertical direction of the second GaN-based compound semiconductor on the exposed portion of the substrate does not occur, and the crystallinity can be improved.

  Patent Document 2 discloses a compound semiconductor substrate including a first nitride compound semiconductor layer, a second nitride compound semiconductor layer having an uneven surface, and a third nitride compound semiconductor layer. It is disclosed that the generation of cracks in the portion of the third nitride compound semiconductor layer located on the concave portion of the nitride compound semiconductor layer is suppressed, the dislocation density is reduced, and the crystallinity is improved.

JP 2000-91253 A JP 2007-201379 A

  However, in the methods described in Patent Documents 1 and 2, a low dislocation (low defect) region can be formed in a part of the element layer, but the entire element layer is uniformly reduced in the plane. However, there is a limit to increasing the area of the low dislocation region. In any method, the substrate exposed portion or the concave portion is formed by etching, so that the manufacturing process becomes complicated.

  The present invention has been made to solve the above technical problem, and the entire element layer can be uniformly reduced in the plane, and the area of the low dislocation region can be easily increased. An object of the present invention is to provide a compound semiconductor substrate and a manufacturing method thereof.

The compound semiconductor substrate according to the present invention is formed on a SiC layer formed on a Si substrate and the SiC layer, and an In _W Ga _x Al _1-wx N single crystal (0 ≦ w <1, 0 ≦ x < 1, and w + x <1) consisting of the intermediate layer, formed on the intermediate layer, made of _{in y Ga z Al 1-yz} N single crystal (0 ≦ y <1,0 ≦ z <1, y + z <1) A nitride semiconductor single crystal layer, wherein the intermediate layer has a plurality of inverted hexagonal pyramid-shaped or inverted hexagonal truncated pyramid-shaped pits extending from the surface to the interface with the SiC layer. Features.
By adopting such a configuration, the entire element layer can be uniformly reduced in plane and the area of the low dislocation region can be increased in the compound semiconductor substrate.

The pits preferably have a density of 10 ⁸ pieces / cm ² or more on the surface of the intermediate layer.
By setting the pit density as described above, the occurrence of dislocations at the initial growth stage of the nitride semiconductor single crystal layer can be effectively reduced.

  In a preferred embodiment of the compound semiconductor, the intermediate layer is an AlN layer (w = 0, x = 0), and the nitride semiconductor single crystal layer is a GaN layer (y = 0, z = 1).

  Further, the film thickness of the intermediate layer is preferably 10 to 50 nm in consideration of the influence on pit formation from which the low dislocation effect as described above is obtained.

The method for manufacturing a compound semiconductor substrate according to the present invention includes a step of forming a SiC layer on a Si substrate by a CVD method, and an inverted hexagonal pyramid having a depth reaching the interface with the SiC layer on the SiC layer. _{Alternatively,} a step of forming an intermediate layer made of In _W Ga _x Al _{1 -wx} N single crystal (0 ≦ w <1, 0 ≦ x <1, w + x <1) having a plurality of inverted hexagonal truncated pyramid pits by MOCVD. If, on the intermediate layer, formed by _{in y Ga z Al 1-yz} N single crystal (0 ≦ y <1,0 ≦ z <1, y + z <1) MOCVD method nitride semiconductor single crystal layer consisting of And a process.
According to such a manufacturing method, since a process such as etching for forming pits is not required, the above-described compound semiconductor substrate according to the present invention can be obtained without complicating the manufacturing process.

In the manufacturing method, the intermediate layer is preferably an AlN layer (w = 0, x = 0), and the nitride semiconductor single crystal layer is preferably a GaN layer (y = 0, z = 1).
Moreover, it is preferable that the film thickness of the said intermediate | middle layer shall be 10-50 nm.

According to the present invention, the entire element layer can be uniformly dislocated in the plane, the area of the low dislocation region can be increased, and the area of the low dislocation region can be easily increased. A compound semiconductor substrate can be provided.
Therefore, the compound semiconductor substrate according to the present invention can be suitably used for a light-emitting diode, a laser element, an electronic element capable of high-speed and high-temperature operation, and further expected to be applied to next-generation optical devices and electronic devices. It can contribute to the improvement of the element function.

Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a schematic diagram of a layer structure of a compound semiconductor substrate according to the present invention.
In the compound semiconductor substrate shown in FIG. 1, an SiC layer 2, an intermediate layer 3, and a nitride semiconductor single crystal layer 4 are sequentially stacked on an Si substrate 1.

For the Si substrate 1, a Si single crystal whose surface crystal plane orientation is {111} is preferably used. Here, the plane orientation {111} includes a fine inclination (several degrees to several tens of degrees) of the crystal plane orientation {111} and a crystal plane orientation of a higher-order plane index such as {211}.
By using such a Si substrate, generation of anti-phase boundary defects is reduced, and electric field concentration on the defects can be reduced.
Moreover, the manufacturing method of the Si substrate 1 is not particularly limited. Those produced by the Czochralski (CZ) method or those produced by the floating zone (FZ) method may be used. A crystal layer may be formed.
The Si substrate 1 may be, for example, an n-type substrate having a carrier concentration of 10 ¹⁶ to 10 ²¹ / cm ³ (resistivity: about 1 to 0.00001 le cm).

An SiC layer 2 is formed on the Si substrate 1. This SiC layer 2 can be formed by epitaxial growth using a well-known CVD method.
The SiC layer 2 serves as a base for the formation of the intermediate layer 3, and thus a SiC bulk substrate can be used. However, the SiC layer 2 is formed on the Si substrate 1 from the viewpoint of increasing the diameter of the substrate. It is preferable.

The intermediate layer 3 formed on the SiC layer 2 is made of In _W Ga _x Al _1-wx N single crystal (0 ≦ w <1, 0 ≦ x <1, w + x <1).
Then, on the intermediate layer _{3, In y Ga z Al 1-} yz N single crystal (0 ≦ y <1,0 ≦ z <1, y + z <1) nitride semiconductor single crystal layer 4 made of is formed The
The intermediate layer 3 is a layer in which pits 5 to be described in detail below are formed, and at the same time plays a role of relaxing crystal lattice mismatch between the SiC layer 2 and the nitride semiconductor single crystal layer 4.

_{In W Ga x Al 1-wx} N single crystal of the intermediate layer 3 is AlN (w = 0, x = 0), In y Ga z Al 1-yz N single crystal of a nitride semiconductor single crystal layer 4 Is preferably GaN (y = 0, z = 1).
Since AlN has good wettability with SiC, it is suitable for improving the quality of the intermediate layer 3 and can improve the quality of the nitride semiconductor single crystal layer 4 formed thereon.
In addition, GaN easily controls electrical characteristics by doping, and is suitable for application to optical devices or electronic devices.

  The intermediate layer 3 and the nitride semiconductor single crystal layer 4 are formed by, for example, a CVD method such as MOCVD (Metal Organic Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition), a vapor deposition method using a laser beam, or an atmospheric gas. It can form by the sputtering method etc. which used.

The intermediate layer 3 has a reverse depth from the surface (the interface when the nitride semiconductor single crystal layer 4 is formed on the intermediate layer 3) 3 a to the interface 3 b with the SiC layer 2. Pit 5 having a pyramid shape or an inverted hexagonal frustum shape is formed.
The term “pit” as used herein refers to a very small depression (concave part) having a facet surface with a crystal and having a diameter on the surface of the intermediate layer 3 on the order of 10 to several hundred nm.
By forming the pits as described above, the entire nitride semiconductor single crystal layer 4 serving as the element layer formed on the intermediate layer 3 can be uniformly reduced in dislocation, and the area of the low dislocation region can be increased. Can be planned.

Usually, when the nitride semiconductor single crystal layer 4 is grown on the intermediate layer 3 having a flat surface, dislocations introduced at the initial stage of growth are in a direction perpendicular to the interface 3a, that is, the surface of the nitride semiconductor single crystal layer 4 It grows in the direction.
On the other hand, in the present invention, by forming a plurality of pits 5 as described above in the intermediate layer 3, a nitride semiconductor unit grown on the surface of the intermediate layer 3 where the pits 5 are not formed. The crystal grows laterally (ELO: Epitaxial Lateral Overgrowth) so as to fill the pit 5. Also, the dislocations introduced at the initial stage of the growth of the nitride semiconductor single crystal layer 4 have an angle with respect to the stacking direction of the intermediate layer 3 due to the facet surface of the inverted hexagonal pyramid or inverted hexagonal pyramidal pits 5. It extends in the direction of (tilted).
Thereby, it is estimated that the dislocation density in the nitride semiconductor single crystal layer 4 is greatly reduced.

  When the depth of the pit 5 does not reach from the surface 3a of the intermediate layer 3 to the interface 3b with the SiC layer 2, the above-described dislocation reduction effect at the initial growth stage of the nitride semiconductor single crystal layer 4 is sufficiently obtained. I can't.

The thickness of the intermediate layer 3 is preferably 10 to 50 nm.
When the film thickness exceeds 50 nm, it becomes difficult to form pits having a depth reaching from the surface 3a of the intermediate layer 3 to the interface 3b with the SiC layer 2.
On the other hand, when the film thickness is less than 10 nm, it is too thin to obtain a sufficient function as an intermediate layer.

The pit density on the surface 3a of the intermediate layer 3 is preferably 10 ⁸ pieces / cm ² or more. This pit density can be measured by observing the cross section of the intermediate layer 3 with an electron microscope.
When the pit density is less than 10 ⁸ / cm ² , the above-described dislocation reduction effect at the initial growth stage of the nitride semiconductor single crystal cannot be obtained sufficiently.

The compound semiconductor substrate according to the present invention as described above can be manufactured, for example, through the following steps.
First, an SiC layer 2 is formed on a Si substrate 1 produced by the CZ method by epitaxial growth using a well-known CVD method.
Next, the growth temperature, pressure, carrier flow rate, raw material supply amount, etc. are adjusted on the SiC layer 2 by MOCVD, and the nucleation density and the growth rate in the stacking direction / plane direction are controlled. An intermediate layer 3 having an inverted hexagonal pyramid-like or inverted hexagonal pyramid-like pit 5 having a depth reaching from the surface 3 a to the interface 3 b with the SiC layer is formed on the SiC layer 2.
The compound semiconductor substrate according to the present invention is obtained by forming the nitride semiconductor single crystal layer 4 by MOCVD on the intermediate layer 3 in which the pits 5 are formed.
According to the manufacturing method according to the present invention, the pits 5 of the intermediate layer 3 are not formed by etching, but are formed when film formation is performed while controlling growth conditions. There is no complication.

EXAMPLES Hereinafter, although this invention is demonstrated further more concretely based on an Example, this invention is not restrict | limited by the following Example.
[Example 1]
A SiC / Si substrate obtained by epitaxially growing a cubic SiC layer having a thickness of 700 nm on a Si (111) substrate having a diameter of 3 inches was prepared and set in a MOCVD apparatus for nitride growth.
After cleaning this SiC / Si substrate at a substrate temperature of 1000 ° C. in a hydrogen atmosphere, trimethylaluminum (TMA) and ammonia are simultaneously supplied as raw materials at a substrate temperature of 1200 ° C., and the growth time is controlled to a thickness of 40 nm. An AlN intermediate layer having an inverted hexagonal pyramid-shaped or inverted hexagonal truncated pyramid-shaped pit formed to reach the interface with the SiC layer was deposited.
Further, the substrate temperature was lowered to 1000 ° C., trimethylgallium (TMG) and ammonia were supplied as raw materials, and a GaN layer having a thickness of 700 nm was epitaxially grown to obtain a compound semiconductor substrate.

When the GaN layer was evaluated by X-ray diffraction (XRD), the full width at half maximum for (0002) or (10-10) was 400 seconds.
When the cross section of the obtained compound semiconductor substrate was observed with an electron microscope, the pit density on the surface of the AlN intermediate layer was on the order of 10 ⁸ pieces / cm ² .
Further, when these pits were observed, it was confirmed that the diameter was on the order of several tens to several hundreds nm, and the depth reached the surface of the SiC layer.

[Comparative Examples 1-3]
By adjusting the growth temperature and growth time of the AlN intermediate layer, the thickness of the AlN intermediate layer and the pit density on the surface were changed as shown in Comparative Examples 1 to 3 in Table 1, and otherwise, Example 1 and Similarly, a GaN layer was formed on the SiC / Si substrate.
In Comparative Example 1, the growth temperature was increased and the pit density was decreased. In Comparative Example 2, the growth temperature was set lower than that of Comparative Example 1 to reduce the pit density. In Comparative Example 3, the growth time was lengthened and the pit density was reduced.
About each GaN layer, the half value width with respect to (0002) or (10-10) in X-ray diffraction (XRD) was measured. Note that the narrower the half-value width of X-ray diffraction, the lower the crystal dislocation density and the better the crystallinity.
Further, the film thickness, pit density and depth of the AlN intermediate layer were observed with an electron microscope.
These results are shown in Table 1 together with Example 1.

As a result of observation of the pits, the lower the pit density, the smaller the pits (Comparative Examples 1 and 2), and the thick AlN intermediate layer (Comparative Example 3). It was confirmed that the thickness did not reach the surface of the SiC layer.
Further, as shown in Table 1, when the thickness of the AlN intermediate layer was the same (Example 1, Comparative Examples 1 and 2), it was recognized that the higher the pit density, the better the crystallinity of the GaN layer.
On the other hand, when the thickness of the AlN intermediate layer is thick as in the prior art (Comparative Example 3), pits having a large diameter were filled, the pit density was reduced, and the crystallinity of the GaN layer was lowered.

It is the schematic of the layer structure of the compound semiconductor substrate which concerns on embodiment of this invention.

Explanation of symbols

1 Si substrate 2 SiC layer 3 Intermediate layer 4 Nitride semiconductor single crystal layer 5 Pit

Claims (7)

A SiC layer formed on the Si substrate;
An intermediate layer formed on the SiC layer and made of In _W Ga _x Al _1-wx N single crystal (0 ≦ w <1, 0 ≦ x <1, w + x <1);
Wherein formed on the intermediate layer, and an _{In y Ga z Al 1-yz} N single crystal (0 ≦ y <1,0 ≦ z <1, y + z <1) formed of a nitride semiconductor single crystal layer,
A compound semiconductor substrate comprising a plurality of inverted hexagonal pyramid-shaped or inverted hexagonal truncated pyramid pits having a depth reaching from the surface thereof to the interface with the SiC layer. ^2. The compound semiconductor substrate according to claim 1, wherein the density of the pits on the surface of the intermediate layer is 10 ⁸ pieces / cm ² or more.   3. The intermediate layer is an AlN layer (w = 0, x = 0), and the nitride semiconductor single crystal layer is a GaN layer (y = 0, z = 1). Compound semiconductor substrate.   The compound semiconductor substrate according to claim 1, wherein the intermediate layer has a thickness of 10 to 50 nm. Forming a SiC layer on the Si substrate by a CVD method;
An In _W Ga _x Al _1-wx N single crystal having a plurality of inverted hexagonal pyramid-shaped or inverted hexagonal pyramid-shaped pits reaching the interface with the SiC layer (0 ≦ w <1, Forming an intermediate layer of 0 ≦ x <1, w + x <1) by MOCVD;
On the intermediate layer, a step of forming the _{In y Ga z Al 1-yz} N single crystal (0 ≦ y <1,0 ≦ z <1, y + z <1) MOCVD method nitride semiconductor single crystal layer consisting of A method for producing a compound semiconductor substrate, comprising:   6. The compound semiconductor according to claim 5, wherein the intermediate layer is an AlN layer (w = 0, x = 0), and the nitride semiconductor single crystal layer is a GaN layer (y = 0, z = 1). A method for manufacturing a substrate.   The method of manufacturing a compound semiconductor substrate according to claim 5 or 6, wherein the thickness of the intermediate layer is 10 to 50 nm.

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