JP4802010B2 - Semiconductor integrated circuit and method for testing semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having a plurality of semiconductor circuits having different operation clocks and a method for testing the semiconductor integrated circuit.

  In recent years, the performance of semiconductor integrated circuits has been remarkably improved, and large scale, high integration, and high operation speed have been achieved. The increase in operating speed is realized by increasing the frequency of the clock signal. In particular, semiconductor products having an actual operating frequency of several GHz have been developed by improving semiconductor device manufacturing techniques.

  In order to guarantee the performance of such a high-speed operation semiconductor integrated circuit, it is indispensable to perform an operation test at the same frequency as the actual operation frequency actually used before shipping the semiconductor integrated circuit. .

  As a technique for performing an operation test of a semiconductor integrated circuit, a scan path design for fault diagnosis has been proposed, and a semiconductor integrated circuit capable of performing a delay pulse test using a high frequency equivalent to an internal clock has been proposed. (For example, see Patent Document 1 below.)

  Furthermore, with the high integration of semiconductor integrated circuits, the number of semiconductor circuits that are arranged in the semiconductor integrated circuit and operate at high speed is also increasing. As a method for testing the operation speed of a plurality of semiconductor circuits having different operation speeds, for example, a method of performing a test by inserting a plurality of PLL circuits has been proposed.

  FIG. 12 is an explanatory diagram showing a circuit for performing an operation test of a conventional semiconductor integrated circuit. In FIG. 12, PLL circuits 1203a to 1203c are connected to the respective semiconductor circuits 1201a to 1201c via setting circuits 1202a to 1202c. The PLL circuits 1203a to 1203c, for example, generate an operation clock having a frequency equivalent to the operation speed of the semiconductor circuits 1201a to 1201c to be tested by using the frequency of the external clock input from the LSI tester. As shown in FIG. 12, by providing a plurality of PLL circuits 1203, it is possible to perform an operation test on a plurality of semiconductor circuits having different operation speeds (see Non-Patent Document 1 below).

JP-A-8-201481 “High-Frequency, At-Speed Scan Testing”, Xijang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderkech, Bruce Swamp, and,

  However, in the above-described prior art, in order to perform an operation test of a semiconductor circuit that operates at high speed, the same number of PLL circuits as the semiconductor circuit are required. In addition, a circuit for controlling the PLL circuit and external pins are required in proportion to the number of PLL circuits, which increases the number of parts. Furthermore, with the increase in the number of parts, there are problems that the manufacturing cost increases and the element area of the semiconductor integrated circuit increases.

  On the other hand, in order to reduce the number of parts and the element area of the semiconductor integrated circuit, the number of PLL circuits is reduced. Therefore, the semiconductor circuit to which the PLL circuit is not connected cannot perform an operation test of the semiconductor circuit, and there is a problem that the reliability of the semiconductor integrated circuit is impaired.

  In order to solve the above-described problems caused by the prior art, the present invention provides a semiconductor integrated circuit and a semiconductor integrated circuit capable of reducing the number of components and the element area of the semiconductor integrated circuit and improving the reliability of the performance of the semiconductor integrated circuit. An object is to provide a method for testing a circuit.

  In order to solve the above-described problems and achieve the object, a semiconductor integrated circuit and a semiconductor integrated circuit test method according to the present invention include a plurality of semiconductor circuits having different operation clocks. The operation mode in which the plurality of semiconductor circuits operate or the test mode in which the operation of the plurality of semiconductor circuits is tested is set, and when the test mode is set, An operation clock of a semiconductor circuit to be tested is generated from the inside and supplied to the plurality of semiconductor circuits.

  According to the present invention, it is possible to share an operation clock generation source used for an operation test of a plurality of semiconductor circuits.

  In the above invention, when the test mode is set by the setting circuit, the test target semiconductor circuit is selected from the plurality of semiconductor circuits, and an operation clock of the test target semiconductor circuit is generated. And it is good also as supplying only to the semiconductor circuit used as the said test object.

  According to the present invention, it is possible to prevent an operation test from being performed with different operation clocks.

  In the above invention, a clock lower than an operation clock of the other semiconductor circuit may be supplied to a semiconductor circuit other than the semiconductor circuit to be tested.

  According to the present invention, it is possible to prevent other semiconductor circuits other than the semiconductor circuit to be tested from entering an indefinite state, and to adversely affect the operation test (for example, making it difficult to compress the test result in the Built in self test). Can be prevented.

  According to the semiconductor integrated circuit and the semiconductor integrated circuit testing method of the present invention, it is possible to reduce the number of components and the element area of the semiconductor integrated circuit and to improve the reliability of the performance of the semiconductor integrated circuit. .

  Exemplary embodiments of a semiconductor integrated circuit and a method for testing a semiconductor integrated circuit according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
(Circuit configuration of semiconductor integrated circuit)
First, the circuit configuration of the semiconductor integrated circuit according to the first embodiment of the present invention will be described. FIG. 1 is an explanatory diagram showing the circuit configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit 100 includes semiconductor circuits 101a to 101c, setting circuits 102a to 102c, and a PLL circuit (clock generation circuit) 103.

  The semiconductor circuits 101a to 101c are circuits that operate at different operation speeds. Specifically, for example, the semiconductor circuit 101a operates at 533 MHz, the semiconductor circuit 101b operates at 400 MHz, and the semiconductor circuit 101c operates at 300 MHz.

  The setting circuits 102a to 102c are a plurality of semiconductor circuits 101a to 101c that are either one of an operation mode in which the semiconductor circuits 101a to 101c operate or a test mode in which the operation of the semiconductor circuits 101a to 101c is tested. Set to mode. For example, when a signal for switching the setting circuit 102a to the test mode (test mode signal) is input to the input terminal 104 connected to the setting circuit 102a, the mode is set to the test mode.

  The test mode signal can be input using an LSI tester, for example. Specifically, the test mode is set when the signal input from the LSI tester to the input terminal 104 is at a relatively high level (hereinafter referred to as “1”). When the signal input to the input terminal 104 is at a relatively low level (hereinafter referred to as “0”), the operation mode is set.

  Specifically, the mode is set, for example, by switching the connection of the circuits in the setting circuits 102a to 102c. More specifically, when a test mode signal is input to the input terminal 104 (test mode), it is connected to the output side of the PLL circuit 103, and in other cases (operation mode), the input terminals 105a to 105c. Connected to the side. Specifically, for example, a selector or the like can be used for the setting circuits 102a to 102c. The operation in the operation mode or test mode will be described later.

  When the setting circuit 102a to 102c sets the test mode, the PLL circuit 103 generates an operation clock for the semiconductor circuits 101a to 101c to be tested from the plurality of semiconductor circuits 101a to 101c, and thereby the plurality of semiconductor circuits 101a to 101c. Specifically, for example, when the semiconductor circuits 101a to 101c to be tested are the semiconductor circuit 101a, the PLL circuit 103 generates an operation clock having a frequency of 533 MHz. Then, the generated operation clock is supplied to each of the semiconductor circuits 101a to 101c via the setting circuits 102a to 102c.

  Next, the operation in the operation mode of the semiconductor integrated circuit 100 described above will be described. FIG. 2 is an explanatory diagram showing the operation in the operation mode of the semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 2, dotted arrows 201 to 203 indicate the flow of the external clock input from the input terminals 105a to 105c. In the operation mode, an operation clock equivalent to the operation speed of each of the semiconductor circuits 101a to 101c is input to the input terminals 105a to 105c. Specifically, for example, an external clock of 533 MHz is input to the input terminal 105a. The input external clock is supplied to the semiconductor circuit 101a through the setting circuit 102a.

  Next, the operation of the semiconductor integrated circuit 100 in the test mode will be described. 3 and 4 are explanatory diagrams showing the operation in the test mode of the semiconductor integrated circuit according to the first embodiment of the present invention. Specifically, FIG. 3 shows the case where the semiconductor circuit to be tested is the semiconductor circuit 101a (533 MHz), and FIG. 4 shows the case where the semiconductor circuit to be tested is the semiconductor circuit 105c (300 MHz).

  In FIG. 3, a dotted arrow 301 indicates the flow of the 533 MHz operation clock output from the PLL circuit 103. When an external clock having a frequency of 33 MHz is input from the LSI tester to the input terminal 106, the PLL circuit 103 generates an operation clock having a frequency of 533 MHz. The semiconductor integrated circuit 100 shares the generation source of the operation clock, and the generated operation clock is supplied to the semiconductor circuits 101a to 101c via the setting circuits 102a to 102c, respectively. The semiconductor circuit 101a performs an operation speed test using the supplied operation clock. Then, the test result is output to the LSI tester.

  In the example of FIG. 3, an operation clock of 533 MHz is supplied to each of the semiconductor circuits 101a to 101c. However, the operation clocks in the operation mode of the semiconductor circuits 101b and 101c are 400 MHz and 300 MHz, respectively. Different. Therefore, the operation test of the semiconductor circuits 101b and 101c is performed using the operation clock of each frequency while changing the frequency of the external clock input to the PLL circuit 103.

  Next, the case where the semiconductor circuit to be tested is 101c will be described with reference to FIG. In FIG. 4, a dotted arrow 401 indicates the flow of the 300 MHz operation clock output from the PLL circuit 103. For example, when an external clock having a frequency of 18 MHz is input from the LSI tester to the input terminal 106, the PLL circuit 103 generates an operation clock of 300 MHz. The generated operation clock is supplied to the semiconductor circuits 101a to 101c via the setting circuits 102a to 102c, respectively.

  The semiconductor circuit 101c performs an operation speed test using the supplied operation clock. Then, the test result is output to the LSI tester. Further, an operation test of the semiconductor circuit 101b is also performed with an operation clock of 400 MHz.

(Semiconductor integrated circuit test procedure)
Next, a test processing procedure for the semiconductor integrated circuit according to the first embodiment of the present invention will be described. FIG. 5 is a flowchart showing a test processing procedure of the semiconductor integrated circuit according to the first embodiment of the present invention. Here, the semiconductor circuit 101a will be described as a circuit to be tested. In the flowchart of FIG. 5, first, after waiting for a test mode signal to be input (step S501: Yes), the setting circuits 102a to 102c are set to the test mode (step S502).

  Then, after waiting for an external clock to be input to the input terminal 106 (step S503: Yes), an operation clock (533 MHz) corresponding to the input external clock is generated (step S504). Next, the generated operation clock is supplied to the semiconductor circuits 101a to 101c via the setting circuits 102a to 102c (step S505). Then, an operation test of the semiconductor circuit 101a to be tested is performed (step S506). Then, the test result is output to the LSI tester (step S507). As a result, the series of operations is completed.

  When the operation test of the semiconductor circuit 101a is completed, the same processing is performed on the semiconductor circuits 101b and 101c to perform the operation test. Regarding these processes, in step S503, only the frequency of the input clock and the operation frequency generated in step S504 are different, and the other processes are the same, so the description is omitted.

  As described above, according to the semiconductor integrated circuit and the semiconductor integrated circuit testing method according to the first embodiment, it is possible to share the generation source of the operation clock used for the operation test of the plurality of semiconductor circuits. Therefore, the number of parts and the element area of the semiconductor integrated circuit can be reduced.

(Embodiment 2)
(Circuit configuration of semiconductor integrated circuit)
Next, a circuit configuration of the semiconductor integrated circuit according to the second embodiment of the present invention will be described. In the first embodiment, an operation clock having the same frequency as the operation clock of the semiconductor circuits 101a to 101c to be tested is generated, the operation clock is supplied to each of the semiconductor circuits 101a to 101c, and an operation test is performed.

  In the configuration of the first embodiment, it is considered that the semiconductor circuit 101 (for example, 101b and 101c) to which an operation clock having a frequency higher than the operation speed in the test mode is input is in an indefinite state, which may hinder the operation test. . Therefore, in the second embodiment, a selection circuit for selecting an operation clock is provided, the operation clock is supplied only to the semiconductor circuit 101 (for example, 101a) to be tested, and the other semiconductor circuits 101 (for example, 101b and 101c). In this example, an operation clock having a frequency lower than the operation speed in the test mode is supplied.

  FIG. 6 is an explanatory diagram showing the circuit configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. The difference from the first embodiment is that a decoder and a selection circuit are provided. In FIG. 6, a semiconductor integrated circuit 600 includes a plurality of semiconductor circuits 101 (101a to 101c), a plurality of setting circuits 102 (102a to 102c), a PLL circuit 103, a decoder 601 and a plurality of selection circuits 602 (602a to 602a). 602c). Description of the semiconductor circuit 101, the setting circuit 102, and the PLL circuit 103 is omitted because the contents overlap with those in the first embodiment.

  When the setting circuits 102a to 102c set the test mode, the selection circuits 602a to 602c select the semiconductor circuits 101a to 101c to be tested from the plurality of semiconductor circuits 101a to 101c. Specifically, signals are input to input terminals 603, 604a, and 604b connected to the decoder 601, and signals are output to the selection circuits 602a to 602c, respectively. Signals input to the input terminals 603, 604a, and 604b will be described later. The selection circuits 602a to 602c receive an input of a signal output from the decoder 601 and switch an internal circuit.

  Next, signals input to the decoder 601 or output from the decoder 601 will be described. FIG. 7A is an explanatory diagram of a relationship between a signal input to the decoder and an output signal. FIG. 7B is an explanatory diagram of a correspondence relationship between input and output terminals. In FIGS. 7A and 7B, TM, I1, and I2 are input terminals, and O1, O2, and O3 are output terminals.

  In FIG. 7A, when “1” is input to TM, “0” is input to I1, and “0” is input to I2, “1” is output to O1, “0” is output to O2, and “0” is output to O3. The Further, when “0” is input to TM, the semiconductor integrated circuit 600 enters an operation mode, and regardless of the input of I1 and I2 (or does not accept the input of I1 and I2), O1, O2, and O3 , “1” is output. The signal input to the TM is the same signal as the test mode signal input to the input terminal 104.

  Next, the operation in the operation mode of the semiconductor integrated circuit 600 according to the second embodiment of the present invention will be described. FIG. 8 is an explanatory diagram showing the operation in the operation mode of the semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 8, arrows 801 to 803 indicate the flow of the external clock input from the input terminal 105. When “0” is input to the TM (input terminal 603) of the decoder 601, the circuits of the selection circuits 602 a to 602 c are connected to the output side of the setting circuit 102.

  The external clock input from the input terminals 105a to 105c is supplied to the semiconductor circuits 101a to 101c via the setting circuits 102a to 102c and the selection circuits 602a to 602c. For example, a selector or the like can be used for the selection circuits 602a to 602c.

  Next, the operation of the semiconductor integrated circuit 600 in the test mode will be described. 9 and 10 are explanatory diagrams showing the operation in the test mode of the semiconductor integrated circuit according to the second embodiment of the present invention. Specifically, FIG. 9 shows the case where the semiconductor circuit 101 to be tested is the semiconductor circuit 101a (533 MHz), and FIG. 10 shows the case where the semiconductor circuit 101 to be tested is the semiconductor circuit 101c (300 MHz). .

  In FIG. 9, a dotted arrow 901 indicates the flow of the 533 MHz operation clock generated by the PLL circuit 103. When the signal input to the decoder 601 is “1” for TM, “0” for I1, and “0” for I2, the semiconductor integrated circuit 600 is set to the test mode, and the selection circuit 602a is connected to the setting circuit 101a. Connected. The selection circuits 602b and 602c are connected to input terminals 605b and 605c, respectively.

  For example, when an external clock having a frequency of 33 MHz is input from the LSI tester to the input terminal 106, the PLL circuit 103 generates an operation clock of 533 MHz. The generated operation clock is supplied to the semiconductor circuit 101a through the setting circuit 102a and the selection circuit 602a. At this time, an external clock having a frequency lower than the operation speed of the semiconductor circuits 105b and 105c input from the input terminals 605b and 605c is supplied to the semiconductor circuits 101b and 101c. Thereby, it is possible to prevent other semiconductor circuits other than the semiconductor circuit to be tested from entering an indefinite state, and to prevent adverse effects on the operation test. The semiconductor circuit 101a performs an operation speed test using the supplied operation clock. Then, the test result is output to the LSI tester.

  Next, the case where the semiconductor circuit to be tested is 101c will be described with reference to FIG. In FIG. 10, a dotted arrow 1001 indicates the flow of the 300 MHz operation clock output from the PLL circuit 103, and dotted arrows 1002 and 1003 indicate the flow of the operation clock supplied to the semiconductor circuits 101a and 101b. Show. Here, the operation clock input from the input terminals 605a and 605b is an operation clock having a frequency lower than the operation speed of the semiconductor circuits 101a and 101b.

  For example, when an external clock having a frequency of 18 MHz is input from the LSI tester to the input terminal 106, the PLL circuit 103 generates an operation clock of 300 MHz. The generated operation clock is supplied to the semiconductor circuit 101c via the setting circuit 102c. At this time, an external clock having a frequency lower than the operation speed of the semiconductor circuits 105a and 105b input from the input terminals 605a and 605b is supplied to the semiconductor circuits 101a and 101b. Thereby, it is possible to prevent other semiconductor circuits other than the semiconductor circuit to be tested from entering an indefinite state, and to prevent adverse effects on the operation test. The semiconductor circuit 101c performs an operation speed test using the supplied operation clock. Then, the test result is output to the LSI tester.

(Semiconductor integrated circuit test procedure)
Next, a test processing procedure for the semiconductor integrated circuit according to the second embodiment of the present invention will be described. FIG. 11 is a flowchart showing a test processing procedure of the semiconductor integrated circuit according to the second embodiment of the present invention. Here, the semiconductor circuit 101a will be described as a circuit to be tested. In the flowchart of FIG. 11, first, after waiting for a test mode signal to be input (step S1101: Yes), the setting circuit 102 is set to the test mode (step S1102).

  Then, after waiting for the selection signal to be input, if it is input (step S1103: Yes), the semiconductor circuit to be tested is selected (step S1104). Here, specifically, the selection of the semiconductor circuit is performed, for example, by connecting the internal circuit of the selection circuit 602a to the output side of the setting circuit 102a.

  Then, after waiting for an external clock to be input to the input terminal 106 (step S1105: Yes), an operation clock (533 MHz) corresponding to the input clock is generated (step S1106). Next, an operation clock is supplied to the semiconductor circuits 101a to 101c via the selection circuits 602a to 602c (step S1107).

  Here, as the operation clock to be supplied, the operation clock generated in step S1106 is supplied to the semiconductor circuit 101a. The semiconductor circuits 101b and 101c are supplied with an operation clock having a frequency lower than that of the semiconductor circuits 101b and 101c input from the input terminals 505b and 505c.

  Next, an operation test of the semiconductor circuit 101a to be tested is performed (step S1108). Then, the test result is output to the LSI tester (step S1109). As a result, the series of operations is completed.

  When the operation test of the semiconductor circuit 101a is completed, the input of the decoder 601 is changed, the same processing is performed on the semiconductor circuits 101b and 101c, and the operation test is performed. Regarding these processes, in step S1105, only the frequency of the input clock and the operation clock generated in step S1106 are different.

  As described above, according to the semiconductor integrated circuit and the semiconductor integrated circuit testing method according to the second embodiment, it is possible to share the generation source of the operation clock used for the operation test of a plurality of semiconductor circuits. In addition, it is possible to prevent other semiconductor circuits other than the semiconductor circuit to be tested from entering an indefinite state, and to prevent adverse effects on the operation test. Therefore, the number of components and the element area of the semiconductor integrated circuit can be reduced, and the performance reliability of the semiconductor integrated circuit can be improved.

  In each of the first and second embodiments, the case where there is one PLL circuit has been described as an example. However, the number of PLL circuits may be plural as long as it is smaller than the number of semiconductor circuits to be tested. .

(Appendix 1) In a semiconductor integrated circuit having a plurality of semiconductor circuits having different operation clocks,
A setting circuit for setting the plurality of semiconductor circuits to an operation mode in which the plurality of semiconductor circuits operate or a test mode for testing the operation of the plurality of semiconductor circuits;
A clock generation circuit that generates an operation clock of a semiconductor circuit to be tested from the plurality of semiconductor circuits and supplies the operation clock to the plurality of semiconductor circuits when the test mode is set by the setting circuit;
A semiconductor integrated circuit comprising:

(Supplementary Note 2) When the test mode is set by the setting circuit, the selection circuit includes a selection circuit that selects the semiconductor circuit to be tested from the plurality of semiconductor circuits,
The clock generation circuit includes:
The semiconductor integrated circuit according to appendix 1, wherein an operation clock of the semiconductor circuit to be tested is generated and supplied only to the semiconductor circuit to be tested.

(Supplementary note 3) The semiconductor integrated circuit according to supplementary note 1 or 2, wherein a clock lower than an operation clock of the other semiconductor circuit is supplied to a semiconductor circuit other than the semiconductor circuit to be tested.

(Supplementary note 4) The semiconductor integrated circuit according to any one of supplementary notes 1 to 3, wherein the clock generation circuit is a PLL circuit.

(Supplementary note 5) The semiconductor integrated circuit according to any one of supplementary notes 1 to 4, wherein the number of the clock generation circuits is smaller than the number of the semiconductor circuits.

(Supplementary Note 6) A semiconductor integrated circuit test method for testing a plurality of semiconductor circuits having different operation clocks in a semiconductor integrated circuit,
A setting step of setting the plurality of semiconductor circuits to a test mode for testing the operation of the plurality of semiconductor circuits;
A supply step of generating an operation clock of a semiconductor circuit to be tested from the plurality of semiconductor circuits and supplying the operation clock to the plurality of semiconductor circuits when the test mode is set by the setting step;
A method for testing a semiconductor integrated circuit, comprising:

(Appendix 7) When the test mode is set by the setting step, the method includes a selection step of selecting the semiconductor circuit to be tested from the plurality of semiconductor circuits,
The supply step includes
The semiconductor integrated circuit testing method according to appendix 6, wherein an operation clock of the semiconductor circuit to be tested is generated and supplied only to the semiconductor circuit to be tested.

(Supplementary note 8) The semiconductor according to supplementary note 6 or 7, further comprising a step of supplying a clock lower than an operation clock of the other semiconductor circuit to another semiconductor circuit other than the semiconductor circuit to be tested. Integrated circuit testing method.

  As described above, the semiconductor integrated circuit and the semiconductor integrated circuit test method according to the present invention are useful for the operation test of the semiconductor integrated circuit, and are particularly suitable for a semiconductor integrated circuit having a plurality of operation clocks.

1 is an explanatory diagram showing a circuit configuration of a semiconductor integrated circuit according to a first embodiment of the present invention; It is explanatory drawing shown about the operation | movement at the time of the operation mode of the semiconductor integrated circuit concerning Embodiment 1 of this invention. It is explanatory drawing shown about the operation | movement at the time of the test mode (533 MHz) of the semiconductor integrated circuit concerning Embodiment 1 of this invention. It is explanatory drawing shown about the operation | movement at the time of the test mode (300 MHz) of the semiconductor integrated circuit concerning Embodiment 1 of this invention. 4 is a flowchart showing a test processing procedure for the semiconductor integrated circuit according to the first embodiment of the present invention; It is explanatory drawing shown about the circuit structure of the semiconductor integrated circuit concerning Embodiment 2 of this invention. It is explanatory drawing shown about the relationship between the signal input into a decoder, and the output signal. FIG. 7 is an explanatory diagram illustrating a correspondence relationship between input and output terminals illustrated in FIG. It is explanatory drawing which shows the operation | movement at the time of the operation mode of the semiconductor integrated circuit concerning Embodiment 2 of this invention. It is explanatory drawing shown about the operation | movement at the time of the test mode (533 MHz) of the semiconductor integrated circuit concerning Embodiment 2 of this invention. It is explanatory drawing shown about the operation | movement at the time of the test mode (300 MHz) of the semiconductor integrated circuit concerning Embodiment 2 of this invention. It is a flowchart shown about the test processing procedure of the semiconductor integrated circuit concerning Embodiment 2 of this invention. It is explanatory drawing shown about the circuit which performs the operation test of the conventional semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor integrated circuit 101a, 101b, 101c Semiconductor circuit 102a, 102b, 102c Setting circuit 103 PLL circuit 104 Input terminal 105 Input terminal 600 Semiconductor integrated circuit 601 Decoder 602a, 602b, 602c Selection circuit

Claims (5)

In a semiconductor integrated circuit having a plurality of semiconductor circuits having different operation clocks,
A setting circuit for setting the plurality of semiconductor circuits to an operation mode in which the plurality of semiconductor circuits operate or a test mode for testing the operation of the plurality of semiconductor circuits;
A clock generation circuit that generates an operation clock of a semiconductor circuit to be tested from the plurality of semiconductor circuits and supplies the operation clock to the plurality of semiconductor circuits when the test mode is set by the setting circuit;
A semiconductor integrated circuit comprising: In a semiconductor integrated circuit having a plurality of semiconductor circuits having different operation clocks,
A setting circuit for setting the plurality of semiconductor circuits to an operation mode in which the plurality of semiconductor circuits operate or a test mode for testing the operation of the plurality of semiconductor circuits;
When the test mode is set by the setting circuit, a selection circuit that selects the semiconductor circuit to be tested from the plurality of semiconductor circuits;
When the test mode is set by the setting circuit, the operation circuit of the semiconductor circuit to be tested selected from the plurality of semiconductor circuits by the selection circuit is generated, and the semiconductor circuit to be tested A clock generation circuit that supplies only to
Semiconductors integrated circuits you comprising: a.   2. A clock having a frequency lower than the frequency of an operation clock of the other semiconductor circuit is supplied from the outside to each of the other semiconductor circuits other than the semiconductor circuit to be tested. 3. The semiconductor integrated circuit according to 2.   The semiconductor integrated circuit according to claim 1, wherein the clock generation circuit is a PLL circuit. A test method of a semiconductor integrated circuit for testing a plurality of semiconductor circuits having different operation clocks in a semiconductor integrated circuit,
A setting step of setting the plurality of semiconductor circuits to a test mode for testing the operation of the plurality of semiconductor circuits;
A supply step of generating an operation clock of a semiconductor circuit to be tested from the plurality of semiconductor circuits and supplying the operation clock to the plurality of semiconductor circuits when the test mode is set by the setting step;
A method for testing a semiconductor integrated circuit, comprising:

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