JP4799262B2 - Power detection circuit - Google Patents

Description

  The present invention relates to a power supply detection circuit provided when circuits having different power supply voltages are connected, and in particular, an internal circuit that operates with a power supply voltage at a low voltage level and an external interface that operates with a power supply voltage at a high voltage level. The present invention relates to a power supply detection circuit in a circuit configuration of a multi-power supply system.

  A power supply voltage detection circuit 100 used in the semiconductor integrated circuit disclosed in Patent Document 1 is shown in FIG. The power supply voltage detection circuit 100 detects the power supply voltage of the control system power supply 500 under the output system power supply 600. The control system power supply 500 is connected to the gate of the N-channel transistor 400 via a resistor 410. The drain of the N-channel transistor 400 is connected to the output power source 600 via the resistor 350. Further, it is connected to the output terminal 440 via the buffer circuits 360 to 390. When the control system power supply 500 falls below the threshold voltage of the N channel transistor 400, the N channel transistor 400 is turned off, and a high level signal having the voltage level of the output system power supply 600 is output to the output terminal 440. Is done.

JP-A-6-19412 (FIG. 4)

  By the way, in the power supply voltage detection circuit of Patent Document 1, when the power supply 500 of the control system rises above the threshold voltage of the N channel transistor 400, the N channel transistor 400 is turned on and a low level signal is output to the output terminal 440. Is done.

  However, in this case, a current path through the resistor 350 and the N-channel transistor 400 is formed from the output power source 600 toward the ground potential, and a through current flows. This state is, for example, a period during which the semiconductor integrated circuit is powered on and in an operating state. During the operation of the semiconductor integrated circuit, a through current constantly flows, which is a problem.

  The present invention has been made in view of the above-described background art, and when a circuit having a different power supply voltage is connected, the power supply voltage is configured under a power supply voltage having a higher voltage level, and the power supply state of the power supply voltage having a lower voltage level is changed. An object of the present invention is to provide a power supply detection circuit capable of detecting with low current consumption.

In order to achieve the above object, a power supply detection circuit according to the present invention includes a first PMOS transistor that connects a first power supply voltage and an output terminal, and whether or not a second power supply voltage lower than the first power supply voltage is supplied. And a first and second terminals for holding signal levels complementary to each other, and the first PMOS transistor is controlled according to the voltage level of the second power supply voltage in the power supply state. A reset unit that connects the latch unit for setting the terminal to the first power supply voltage and the second power supply voltage and is turned on according to the second power supply voltage at a low voltage level in a non-powered state to form a discharge path of the first terminal The reset unit includes a second PMOS transistor in which a gate terminal and a drain terminal are connected to the second power supply voltage, and a discharge path is formed from the source terminal to the drain terminal. Provided, the first terminal is characterized in that it is connected to the gate terminal of the 1PMOS transistor.

In the power supply detection circuit of the present invention, when the power supply detection circuit operating at the first power supply voltage detects the presence or absence of power supply of the second power supply voltage whose voltage level in the power supply state is lower than the first power supply voltage, The power supply detection circuit is configured by connecting a first terminal of a latch unit including first and second terminals having mutually complementary signal levels to a gate terminal of a first PMOS transistor. In the latch unit, the first terminal is set to the first power supply voltage according to the voltage level of the second power supply voltage in the power supply state. The reset part connected to the second power supply voltage forms a discharge path of the first terminal according to the second power supply voltage at the low voltage level in the non-powered state, and the latch part is reset.
The reset unit includes a second PMOS transistor having a gate terminal and a drain terminal connected to the second power supply voltage, and a discharge path formed from the source terminal toward the drain terminal.

  Thus, when the second power supply voltage is supplied, the first terminal of the latch unit is set to the first power supply voltage according to the voltage level in the power supply state. The first PMOS transistor is turned off by biasing the gate terminal of the first PMOS transistor to the first power supply voltage. At this time, since the reset unit is kept nonconductive, the charge charged in the gate terminal of the first PMOS transistor is not discharged. A steady through current does not flow in the power supply state of the second power supply voltage.

  When the second power supply voltage is not supplied, the reset unit is turned on according to the low voltage level in the non-power supply state. A discharge path for discharging the first terminal is formed. When the gate terminal of the first PMOS transistor is biased to a voltage level lower than the first power supply voltage, the first PMOS transistor is turned on. At this time, since the first terminal of the latch unit is not set, no charge is supplied to the gate terminal of the first PMOS transistor. A steady through current does not flow when the second power supply voltage is not supplied.

  According to the present invention, when circuits with different power supply voltages are connected, a set / set of latch units configured under a power supply voltage with a higher voltage level and switched according to the power supply state of the power supply voltage with a lower voltage level. It is possible to provide a power supply detection circuit that can perform reset switching without flowing an unnecessary through current and can detect a power supply with low current consumption.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a power supply detection circuit according to the present invention will be described below in detail with reference to FIGS. FIG. 1 shows a schematic diagram of a semiconductor integrated circuit device 1 to which the present invention is applied. The semiconductor integrated circuit device 1 is an LSI that operates using two or more types of power supply voltages. That is, an internal power supply wiring 3 that supplies power for an internal circuit that operates at an internal power supply voltage VDD at a low voltage level, and an external power supply wiring 2 that supplies power for an interface circuit that operates at an external power supply voltage VDE at a high voltage level. And.

  When the external power supply voltage VDE and the internal power supply voltage VDD are supplied from the outside to the semiconductor integrated circuit device 1, the external power supply voltage VDE is supplied in advance, and then the internal power supply voltage VDD is supplied. There are many cases. When the external power supply voltage VDE is supplied to the semiconductor integrated circuit device 1 and the internal power supply voltage VDD is generated by reducing the external power supply voltage VDE inside the semiconductor integrated circuit device 1, the external power supply voltage VDE is supplied. An internal power supply voltage VDD is generated. In any case, the semiconductor integrated circuit device 1 is supplied with the lower internal power supply voltage VDD after being supplied with the higher external power supply voltage VDE. Then, there is a period in which only the external power supply voltage VDE is supplied and the internal power supply voltage VDD is set to 0 (V). During this period, the interface circuit is operable and an output signal of the internal circuit can be output to the outside. However, since the internal circuit is in a stopped state, the output signal of the internal circuit is an error signal. Then, if an error signal of the internal circuit is output to the outside via the interface circuit during the period, another LSI may malfunction due to the error signal.

  Therefore, in order to output a normal signal from the interface circuit, the semiconductor integrated circuit device 1 includes a power supply detection circuit that detects whether or not the internal power supply voltage VDD is supplied, and the signal is supplied after the supply of the internal power supply voltage VDD is performed. Must be output. The power supply detection circuit needs to be configured to be operable by the external power supply voltage VDE supplied in advance. The power supply detection circuit needs to reduce power consumption as much as possible.

  FIG. 2 shows a circuit diagram of the power supply detection circuit 10 according to the present embodiment. The power supply detection circuit 10 is a circuit that detects whether the internal power supply voltage VDD of the semiconductor integrated circuit device 1 is supplied based on the external power supply voltage VDE. The power supply detection circuit 10 includes a latch unit 11, a reset unit 12, a PMOS transistor QP1, and NMOS transistors QN1 and QN2.

  The latch unit 11 includes PMOS transistors QP2 and QP3. The external power supply voltage VDE is supplied to the source terminal of the PMOS transistor QP2, the gate terminal is connected to the first terminal NP, and the drain terminal is connected to the second terminal NB. Further, the external power supply voltage VDE is supplied to the source terminal of the PMOS transistor QP3, the gate terminal is connected to the second terminal NB, and the drain terminal is connected to the first terminal NP. The first terminal NP and the second terminal NB are terminals having complementary signal levels.

  The reset unit 12 includes a voltage step-down unit 13 on the discharge path from the first terminal NP to the source terminal of the PMOS transistor QP4. The voltage step-down unit 13 includes so-called diode-connected transistors D1 to Dn connected in n stages in series. The drain terminal of the transistor D1 is connected to the first terminal NP. The source terminal of the transistor Dn is connected to the source terminal of the PMOS transistor QP4 via the node NC.

  The voltage of the node NC is a voltage obtained by stepping down the voltage of the first terminal NP by the step-down voltage VDR by the voltage step-down unit 13. The value of the step-down voltage VDR is a value obtained by multiplying the threshold voltage values of the transistors D1 to Dn by the number of stages of the transistors. The value of the step-down voltage VDR is determined such that when the voltage at the first terminal NP is the external power supply voltage VDE, the voltage at the node NC that is stepped down from the external power supply voltage VDE by the step-down voltage VDR is equal to or lower than the internal power supply voltage VDD. . That is, the number of stages of the transistors D1 to Dn is determined so that the step-down voltage VDR is equal to or higher than the voltage obtained by subtracting the internal power supply voltage VDD from the external power supply voltage VDE. The internal power supply voltage VDD is supplied to the gate terminal and drain terminal of the PMOS transistor QP4.

  The external power supply voltage VDE is supplied to the source terminal of the PMOS transistor QP1, the gate terminal is connected to the first terminal NP, and the drain terminal is connected to the drain terminal of the NMOS transistor QN1 and the output terminal CREF. Further, the low level reference voltage VSS is supplied to the source terminal of the NMOS transistor QN1, and the gate terminal is connected to the third terminal NN. Further, the low level reference voltage VSS is supplied to the source terminal of the NMOS transistor QN2, the internal power supply voltage VDD is supplied to the gate terminal, and the drain terminal is connected to the second terminal NB. The NMOS transistor QN2 is a transistor that becomes conductive in response to the supply of the internal power supply voltage VDD and forms a discharge path of the second terminal NB.

  The operation will be described. The power supply detection circuit 10 is a circuit that detects whether or not the internal power supply voltage VDD is supplied and outputs an output signal CREF. The latch unit 11 is a circuit that controls the gate potential of the PMOS transistor QP1. In response to the supply of the internal power supply voltage VDD, the latch unit 11 is set, and the external power supply voltage VDE is supplied to the first terminal NP. Further, in response to the internal power supply voltage VDD being in a non-powered state, a discharge path of the first terminal NP is formed in the reset unit 12, the latch unit 11 is reset, and the voltage of the first terminal NP is 0 ( V).

  The operation of the semiconductor integrated circuit device 1 including the power supply detection circuit 10 at the time of startup will be described. In the initial state at time t0 in FIG. 3, the internal power supply voltage VDD and the external power supply voltage VDE are not supplied to the power supply detection circuit 10. At this time, the first terminal NP and the second terminal NB are in a floating state, and the latch unit 11 is in an indefinite state. In addition, the potential of the third terminal NN is reduced to 0 (V) due to the supply of the internal power supply voltage VDD to the previous circuit portion being cut off.

  A case where power is supplied in the order of the external power supply voltage VDE and the internal power supply voltage VDD from the initial state will be described. As shown in FIG. 3, the external power supply voltage VDE is supplied to the power supply detection circuit 10 at time t1. At this time, the internal power supply voltage VDD is in a non-powered state.

  The operation of the reset unit 12 will be described. In the non-powered state of the internal power supply voltage VDD, a voltage of 0 (V) is applied to the gate of the PMOS transistor QP4. Therefore, when the PMOS transistor QP4 is turned on, a discharge path for discharging the first terminal NP is formed. Then, even when the potential of the first terminal NP is charged up to the external power supply voltage VDE, the potential of the first terminal NP can be lowered by the discharge path.

  When the potential of the first terminal NP drops to a potential lower than the external power supply voltage VDE by the threshold voltage VthP due to the conduction of the PMOS transistor QP4, the PMOS transistor QP1 becomes conductive. Since the voltage at the third terminal NN, which is the gate voltage of the NMOS transistor QN1, is 0 (V), the NMOS transistor QN1 is completely non-conductive. Therefore, the external power supply voltage VDE is supplied to the output terminal CREF, and the output signal CREF transitions to a high level (arrow Y1).

  When the potential of the first terminal NP is lowered to a potential lower than the external power supply voltage VDE by the threshold voltage VthP due to the conduction of the PMOS transistor QP4, the PMOS transistor QP2 is conducted in the latch unit 11. Then, the PMOS transistor QP3 transitions to a non-conductive state, and the charging path of the external power supply voltage VDE to the first terminal NP is interrupted. After the PMOS transistor QP3 is turned off, the potential of the first terminal NP is finally lowered to 0 (V) by the discharge path of the reset unit 12.

  Thus, when the internal power supply voltage VDD is in a non-powered state, a discharge path of the first terminal NP is formed in the reset unit 12, the latch unit 11 is in a reset state, and the voltage of the first terminal NP is 0 (V ). The power supply detection circuit 10 outputs a high level output signal CREF for notifying that the internal power supply voltage VDD is in a non-powered state. At this time, since the PMOS transistor QP3, which is a charging path of the external power supply voltage VDE to the first terminal NP, is made non-conductive, there is no steady current, so that current consumption can be reduced.

  Next, at time t2 (FIG. 3), the internal power supply voltage VDD is supplied. When the internal power supply voltage VDD is supplied, the NMOS transistor QN2 becomes conductive and a discharge path for the second terminal NB is formed. Then, the PMOS transistor QP3 of the latch unit 11 transitions to a conductive state, and a path for supplying the external power supply voltage VDE to the first terminal NP is formed. The PMOS transistor QP2 transitions to a non-conduction state.

  The operation of the reset unit 12 will be described. At time t2, the potential of the node NC is set to 0 (V) by the discharge path of the reset unit 12. The internal power supply voltage VDD is applied to the gate of the PMOS transistor QP4. Therefore, the PMOS transistor QP4 is completely turned off, and the discharge path for discharging the first terminal NP is completely cut off. Therefore, the first terminal NP is charged to the external power supply voltage VDE through the charging path of the PMOS transistor QP3. Then, since the gate terminal of the PMOS transistor QP1 is biased to the external power supply voltage VDE, the PMOS transistor QP1 is completely turned off. Since the internal power supply voltage VDD is applied to the gate of the NMOS transistor QN1, the NMOS transistor QN1 is turned on. Therefore, the low level reference voltage VSS is supplied to the output terminal CREF, and the output signal CREF transitions to the low level (arrow Y2).

  The operation of the voltage step-down unit 13 will be described. By the voltage step-down unit 13, the potential of the node NC is maintained at a potential lower than the potential of the first terminal NP by the step-down voltage VDR. The value of the step-down voltage VDR is determined so that the voltage at the node NC is equal to or lower than the internal power supply voltage VDD when the voltage at the first terminal NP is the external power supply voltage VDE. Therefore, even after the first terminal NP is charged to the external power supply voltage VDE, the potential of the node NC is maintained at a value equal to or lower than the internal power supply voltage VDD, so that the PMOS transistor QP4 is maintained in a completely non-conductive state. That is, it is possible to maintain a state in which the discharge path between the first terminal NP and the third terminal NN is completely cut off.

  As described above, when the internal power supply voltage VDD is in the power supply state, the latch unit 11 is set and the external power supply voltage VDE is supplied to the first terminal NP. Further, since the PMOS transistor QP4 is completely turned off, the discharge path of the first terminal NP is completely cut off. The power supply detection circuit 10 outputs a low level output signal CREF for notifying that the internal power supply voltage VDD is in a power supply state. At this time, since the PMOS transistor QP4, which is a discharge path from the first terminal NP, is completely non-conductive, there is no steady current, so that current consumption can be reduced.

  Further, the external power supply voltage VDE is supplied to the gate terminal of the PMOS transistor QP1 instead of the internal power supply voltage VDD. Here, considering the case where the internal power supply voltage VDD is supplied to the gate of the PMOS transistor QP1, the external power supply voltage VDE is applied to the source terminal of the PMOS transistor QP1, so that the PMOS transistor QP1 is not completely turned off. . Then, firstly, there is a problem that a through current flows from the external power supply voltage VDE to the lower reference voltage VSS and consumes a steady current. Second, since the output level of the output signal CREF is determined by the resistance voltage dividing ratio between the PMOS transistor QP1 and the NMOS transistor QN1, there is a problem that an optimum ratio design between the PMOS transistor QP1 and the NMOS transistor QN1 is required.

  However, in the power supply detection circuit 10 according to the present embodiment, the PMOS transistor QP1 is completely turned off by supplying the external power supply voltage VDE instead of the internal power supply voltage VDD to the gate terminal of the PMOS transistor QP1. it can. Therefore, first, generation of a through current can be prevented, and low power consumption can be achieved. Second, since the output level of the output signal CREF can be determined regardless of the resistance voltage dividing ratio, the ratio design between the PMOS transistor QP1 and the NMOS transistor QN1 can be facilitated.

  Then, the semiconductor integrated circuit device 1 detects that the supply of the internal power supply voltage VDD is started at time t2 in response to the output signal CREF transitioning to a low level. Then, the semiconductor integrated circuit device 1 starts output from the interface circuit after time t2. This prevents an error signal from being output from the semiconductor integrated circuit device 1.

  As described above in detail, according to the power supply detection circuit 10 according to the present embodiment, when the internal power supply voltage VDD is not supplied, an operation of applying 0 (V) to the gate of the PMOS transistor QP1 is performed. CREF is set to the high level. Then, the PMOS transistor QP3, which is a charging path of the external power supply voltage VDE to the first terminal NP, is completely turned off, so that there is no steady current. Further, when the internal power supply voltage VDD is supplied, the operation of applying the external power supply voltage VDE to the gate of the PMOS transistor QP1 makes the output signal CREF low level. Then, by making the PMOS transistor QP4, which is a discharge path from the first terminal NP, completely non-conductive, there is no steady current, so that current consumption can be reduced. Therefore, power supply detection can be performed with low current consumption without flowing unnecessary through current.

  In addition, when the internal power supply voltage VDD is supplied, the power supply detection circuit 10 supplies the external power supply voltage VDE instead of the internal power supply voltage VDD to the gate terminal of the PMOS transistor QP1, thereby completely turning off the PMOS transistor QP1. be able to. Therefore, generation of a through current can be prevented and low power consumption can be achieved. Further, since the output level of the output signal CREF can be determined regardless of the resistance voltage dividing ratio between the PMOS transistor QP1 and the NMOS transistor QN1, the ratio design between the PMOS transistor QP1 and the NMOS transistor QN1 can be facilitated.

  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. In the power supply detection circuit 10 according to the present embodiment, the voltage step-down unit 13 is configured by the transistors D1 to Dn, but is not limited thereto. Needless to say, a diode may be used instead of the transistor.

  The external power supply voltage VDE is an example of the first power supply voltage, the PMOS transistor QP1 is an example of the first PMOS transistor, the internal power supply voltage VDD is an example of the second power supply voltage, the PMOS transistor QP4 is an example of the second PMOS transistor, and the NMOS transistor QN2 is An example of the set unit and the first NMOS transistor, the PMOS transistor QP2 is an example of a third PMOS transistor, and the PMOS transistor QP3 is an example of a fourth PMOS transistor.

Here, the means for solving the problems in the background art according to the technical idea of the present invention are listed below.
(Supplementary Note 1) A power supply that includes a first PMOS transistor that connects a first power supply voltage and an output terminal, and that controls conduction of the first PMOS transistor according to whether or not a second power supply voltage lower than the first power supply voltage is supplied. A detection circuit comprising first and second terminals for holding complementary signal levels, wherein the first terminal is set to the first power supply voltage according to the voltage level of the second power supply voltage in a power supply state. And a reset unit that is connected to the second power supply voltage and is turned on according to the second power supply voltage at a low voltage level in a non-powered state and forms a discharge path of the first terminal, The power supply detection circuit according to claim 1, wherein the first terminal is connected to a gate terminal of the first PMOS transistor.
(Additional remark 2) The said reset part is provided with the 2nd PMOS transistor by which a gate terminal and a drain terminal are connected to the said 2nd power supply voltage, and the said discharge path is formed toward a drain terminal from a source terminal. The power supply detection circuit according to 1.
(Supplementary note 3) The power supply detection circuit according to supplementary note 2, further comprising a voltage step-down unit in the discharge path from the first terminal to the source terminal of the second PMOS transistor.
(Supplementary note 4) The power supply detection circuit according to supplementary note 3, wherein the step-down voltage by the voltage step-down unit is at least a voltage obtained by subtracting the second power supply voltage from the first power supply voltage.
(Additional remark 5) The said voltage step-down part is provided with at least 1 diode element, The power supply detection circuit of Additional remark 3 characterized by the above-mentioned.
(Additional remark 6) The said 2nd power supply voltage is connected, It conducts according to the said 2nd power supply voltage in the voltage level of an electric power feeding state, The set part which forms the discharge path of the said 2nd terminal is provided, It is characterized by the above-mentioned. The power supply detection circuit according to attachment 1.
(Additional remark 7) The said setting part is equipped with the 1st NMOS transistor by which a gate terminal is connected to the said 2nd power supply voltage, The power supply detection circuit of Additional remark 6 characterized by the above-mentioned.
(Supplementary Note 8) The latch unit includes a third PMOS transistor having a source terminal connected to the first power supply voltage, a gate terminal connected to the first terminal, and a drain terminal connected to the second terminal; The power supply detection circuit according to claim 1, further comprising: a fourth PMOS transistor connected to the first power supply voltage, having a gate terminal connected to the second terminal and a drain terminal connected to the first terminal.

It is a figure which shows the semiconductor device with which this invention is applied. It is a figure which shows the circuit diagram of embodiment. It is a timing diagram at the time of starting. It is a circuit diagram of background art.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 10 Power supply detection circuit 11 Latch part 12 Reset part 13 Voltage step-down part NB 2nd terminal NP 1st terminal QN1 and QN2 NMOS transistor QP1 thru | or QP4 PMOS transistor VDD Internal power supply voltage VDE External power supply voltage VDR Step-down voltage VSS Low level Reference voltage

Claims (4)

A power supply detection circuit that includes a first PMOS transistor that connects a first power supply voltage and an output terminal, and that controls conduction of the first PMOS transistor according to whether or not a second power supply voltage lower than the first power supply voltage is supplied. And
A latch unit that includes first and second terminals that hold mutually complementary signal levels, and sets the first terminal to the first power supply voltage according to the voltage level of the second power supply voltage in a power supply state;
A reset unit that is connected to the second power supply voltage and that conducts according to the second power supply voltage at a low voltage level in a non-powered state, and forms a discharge path of the first terminal;
The reset unit
A second PMOS transistor having a gate terminal and a drain terminal connected to the second power supply voltage, the discharge path being formed from the source terminal toward the drain terminal;
The power supply detection circuit according to claim 1, wherein the first terminal is connected to a gate terminal of the first PMOS transistor. The power supply detection circuit according to claim 1 , further comprising a voltage step-down unit in the discharge path from the first terminal to the source terminal of the second PMOS transistor. The power supply detection circuit according to claim 2 , wherein the step-down voltage by the voltage step-down unit is at least a voltage obtained by subtracting the second power supply voltage from the first power supply voltage.   2. The device according to claim 1, further comprising: a set unit that is connected to the second power supply voltage and that conducts according to the second power supply voltage at a voltage level in a power supply state and forms a discharge path of the second terminal. The power supply detection circuit described.

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