JP4798094B2 - Electro-optic device - Google Patents

Description

  The present invention relates to an electro-optical device using an electro-optical material such as liquid crystal.

  Conventionally, in an electro-optical device in which an electro-optical material such as liquid crystal is sandwiched between a pair of substrates and an optical circuit formed on one substrate is used to change the optical characteristics of the liquid crystal or the like, display is performed on the substrate. Are provided with a plurality of transistors, a scanning line, a data line, a pixel electrode, a storage capacitor, a layer for shielding incident light from the outside, and a layer for insulating these electrodes and wiring (for example, patents) Reference 1).

  A source electrode of the transistor is electrically connected to the pixel electrode through a plurality of contact holes and a relay electrode layer formed in the insulating film. In addition, a fixed electrode layer for inputting a common potential from the outside is electrically connected to one electrode of the storage capacitor formed to maintain optical characteristics such as liquid crystal through another relay electrode layer Has been. The fixed electrode layer is formed in a matrix on the one substrate. Each pixel electrode is connected in a matrix to the fixed electrode layers of the upper, lower, left and right pixels.

  One of the plurality of relay electrode layers connected to the pixel electrode is formed in the same layer as the fixed electrode layer. At this time, two contact holes are formed in the formation region of the relay electrode layer that is the same layer as the fixed electrode layer. One is a contact hole for connecting the relay electrode layer to the pixel electrode, and the other is a contact hole for connecting the relay electrode to the semiconductor layer (drain electrode or source electrode) of the transistor. In this case, since the relay electrode layer and the fixed electrode layer are formed in the same layer, it is necessary to electrically separate them. For this reason, as the size (planar dimension) of the unit pixel formed on the substrate, at least the size of the relay electrode layer, the size of the two contact holes, and the space for separating the relay electrode layer and the fixed electrode layer are laid out. It is necessary to secure as much size as possible.

  Further, the relay electrode layer directly connected to the pixel electrode is connected to the transistor through another relay electrode layer formed on a layer different from the relay electrode layer, and the fixed electrode layer is one electrode forming a storage capacitor. Are connected to the other relay electrode layer through the same relay electrode layer. Therefore, it is necessary to secure a size for laying out the relay electrode layers formed of the separate layers and a space for separating them around the relay electrode layer. In addition, the size of the light shielding portion that defines the aperture ratio of the pixel is also restricted by the size of the relay electrode layer, the width of the fixed electrode layer, and the size of the space for separating the relay electrode layer and the fixed electrode layer. Yes.

JP 2004-170909 A

  In such an electro-optical device, in order to obtain a high-quality image, it is required to reduce the pixel pitch and improve the aperture ratio. However, in the conventional electro-optical device, the matrix-like fixed electrode layer, the relay electrode layer that is the same layer as the fixed electrode layer, a space for electrically separating them, and another relay electrode layer and those layers It is necessary to secure a space for separating. For this reason, it is difficult to realize a narrow pixel pitch and a high aperture ratio. In particular, around the relay electrode layer directly connected to the pixel electrode, it is necessary to secure a space for forming a contact hole, a wiring line for the fixed electrode layer, and a space for electrical separation. This increases the area occupied by the layout, which is a major obstacle to realizing a narrow pitch and a high aperture ratio of the pixels. In addition, as a method for realizing this, one electrode of the storage capacitor is formed by a layer other than the layer constituting the transistor, the scanning line, the data line, and the fixed electrode layer, or the relay electrode layer is formed in multiple layers. There is a method of increasing the number of layouts, but this method complicates the manufacturing process and causes problems such as a decrease in yield.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an electro-optical device capable of realizing a narrow pixel pitch and a high aperture ratio without complicating the manufacturing process. To provide an apparatus.

A first invention for achieving such an object relates to an electro-optical device having the following basic configuration. That is, among a pair of substrates facing each other through the electro-optic material layer,
On one of the substrates, for supplying a plurality of data lines adjacent a picture element electrode, and the transistor control the picture element electrodes, a storage capacitor electrically connected to the pixel electrode, the electrodeposition position storage capacitor , Side by side
The fixed electrode layer divided between the data lines, one electrode of the storage capacitor and the fixed electrode layer
Capacitance relay electrode layer in the same layer as the data line, a first relay electrode layer in the same layer as the data line, and a layer above the first relay electrode layer formed in a divided portion of the fixed electrode layer, which are electrically connected Second relay electrode
And a layered structure including the layers. The pixel electrode and the semiconductor layer of the transistor are electrically connected via the first relay electrode layer and the second relay electrode layer .

The line width in the data line direction in the second relay electrode layer is a direction intersecting the data line direction.
It is characterized in that it is set to be larger than the line width in the data line direction in the fixed electrode layer of the portion extending in the direction .
Further, the second invention is provided on one substrate of a pair of substrates opposed via the electro-optic material layer,
The scanning lines formed along the first direction, the data lines formed along the second direction intersecting the first direction, and the intersections of the scanning lines and the data lines are provided. A pixel electrode;
The pixel electrode and the semiconductor layer of the transistor have a stacked structure including a transistor that controls switching of the pixel electrode, a storage capacitor, and a fixed electrode layer that supplies a potential to the storage capacitor. The relay electrode layer and the fixed electrode layer are electrically connected via the second relay electrode layer that is higher than the first relay electrode divided between the data lines adjacent in the first direction, and the second The line width in the second direction of the relay electrode layer extends in the first direction of the fixed electrode layer on the pixel side where the pixel electrode connected to the second relay electrode layer via the contact hole is arranged. The line width is set to be larger than the line width in the second direction, and one electrode of the storage capacitor and the fixed electrode layer are electrically connected via the capacitor relay electrode layer in the same layer as the data line. It is characterized by that.

In the electro-optical device having the first and second invention configurations, the fixed electrode layer is divided between the adjacent data lines in the first direction (direction intersecting the data line direction) and fixed to the divided portion. In the configuration in which the second relay electrode layer that is the same layer as the fixed electrode layer is formed in a state separated from the electrode layer, the line width in the second direction (data line direction) of the dummy wiring portion in the fixed electrode layer is set to the second relay. Since the line width in the second direction of the electrode layer is set to be smaller than the line width of the pixel in the portion where the dummy wiring portion is disposed in a state where the connection of the pixel electrode is sufficiently secured even when the second relay electrode layer is used. Can widen the second direction. Therefore, the aperture ratio of the pixel is improved.

  The second invention has the following features in the basic configuration. That is, two contact holes having different opening diameters are formed in the upper and lower insulating films of the second relay electrode layer. These two contact holes are arranged in the second direction, and the contact holes having a small opening diameter in the first direction are arranged within the range of the formation width of the contact hole having a large opening diameter. It is a feature.

  In the electro-optical device having the above-described second aspect, the contact holes arranged in the upper layer and the lower layer of the electrode layer are arranged in the second direction, and the contact hole having a large opening diameter is formed in the first direction. By arranging the other contact hole within the width range, the space required in the first direction for arranging the two contact holes is reduced to a certain amount necessary for forming a contact hole having a large opening diameter. can do. Thereby, the space in the first direction necessary for forming the contact hole can be reduced by the amount of misalignment between the two contact holes. Therefore, the pixel pitch in the first direction can be narrowed.

  As described above, according to the electro-optical device of the first invention, it is possible to improve the aperture ratio of the pixel by expanding the pixel aperture in the second direction. The pixel pitch can be reduced in the first direction without complicating the manufacturing process. Further, according to the electro-optical device of the second invention, it is possible to reduce and reduce the space in the first direction necessary for forming the contact hole, thereby complicating the manufacturing process. Without this, the pixel pitch in the first direction can be narrowed.

  Hereinafter, a specific embodiment in which the electro-optical device according to the invention is applied to, for example, an active matrix liquid crystal display device using a liquid crystal material as an electro-optical material will be described in detail with reference to the drawings. However, the present invention is not limited to the application to a liquid crystal display device, and for example, electro-optical devices in general using an electro-optical material, such as an organic EL display device using an organic EL (electro-luminescence) material as an electro-optical material. Widely applicable to.

  Furthermore, the present invention provides an electronic apparatus including the above-described electro-optical device, such as a television, a computer monitor, an in-vehicle monitor, a mobile phone, a mobile terminal, a camera with a monitor (video camera, digital camera, etc.), a touch panel, a POS (Point Of). It can also be applied to electronic devices such as (Sales) terminals.

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration example of a pixel circuit of a liquid crystal display device to which the present invention is applied. In the figure, pixels 1 are two-dimensionally arranged in a matrix on a liquid crystal display panel (not shown). The liquid crystal display panel is configured by sandwiching a liquid crystal material layer between a pair (two sheets) of substrates. Therefore, the pair of substrates are arranged in a state of facing each other with the liquid crystal material layer interposed therebetween. Generally, a pair of board | substrates is comprised using the glass substrate which has a light transmittance. A pixel electrode is formed on one substrate on a pixel-by-pixel basis, and a common electrode common to all pixels is formed on the other substrate facing the substrate. In the following description, a substrate having pixel electrodes is called an array substrate, and a substrate having counter electrodes is called a counter substrate.

  The pixel 1 includes a transistor 2 made of, for example, a TFT (Thin Film Transistor), a liquid crystal cell 3 having a pixel electrode connected to the drain electrode of the transistor 2, and one electrode connected to the drain electrode of the transistor 2. The storage capacity 4 is included. The transistor 2 controls switching of the pixel electrode of the liquid crystal cell 3. Since the liquid crystal cell 3 functions as a dielectric between the pixel electrode and the counter electrode, a liquid crystal capacitor CLC is configured in an equivalent circuit. The storage capacitor 4 is electrically connected to the pixel electrode in order to maintain the potential of the signal voltage applied to the pixel electrode of the liquid crystal cell 3.

  The gate electrode of the transistor 2 is connected to the scanning line 5. The source electrode of the transistor 2 is connected to the data line 6. A plurality of scanning lines 5 are formed along the horizontal direction which is the first direction, and a plurality of data lines 6 are formed along the vertical direction which is the second direction intersecting with the first direction. Is. On the other hand, one pixel 1 is formed at each intersection of the scanning line 5 and the data line 6. The counter electrode of the liquid crystal cell 3 and the other electrode of the storage capacitor 4 are each connected to a common line 7. The common line 7 applies a common voltage Vcom common to each pixel to the counter electrode of the liquid crystal cell 3 and the other electrode of the storage capacitor 4.

  FIG. 2 is a cross-sectional view showing the laminated structure of the array substrate in the liquid crystal display device to which the present invention is applied. FIG. 3 is a plan layout view of the main part of the array substrate according to the first embodiment. In FIG. 2, in order to display all the main components included in the laminated structure of the array substrate, the planar positional relationship of each component is expressed in a state different from the actual structure.

  As shown in the figure, the array substrate 10 is made of, for example, a glass substrate, a quartz substrate, or a silicon substrate, and has a laminated structure including the above-described scanning lines 5, data lines 6, pixel electrodes 11 and the like on the substrate. It has become a thing. This laminated structure is a multilayer wiring structure of a first layer, a second layer, a third layer, a fourth layer, a fifth layer, and a sixth layer in order from the side closer to the array substrate 10 (lower layer side). Among these, the first layer includes the scanning line 5, and the second layer includes the semiconductor layer 12 constituting the transistor 2. The third layer includes one electrode (hereinafter also referred to as “storage capacitor electrode”) 13 of the storage capacitor and the gate electrode 14 of the transistor 2, and the fourth layer includes the data line 6 and the capacitor relay electrode layer 15. And the first relay electrode layer 16. Further, the fifth layer includes the fixed electrode layer 17 and the second relay electrode layer 18, and the sixth layer includes the pixel electrode 11.

  Therefore, the storage capacitor electrode 13 and the gate electrode 14 of the transistor 2 are formed in the same layer (third layer). Similarly, the data line 6, the capacitor relay electrode layer 15, and the first relay electrode layer 16 are formed in the same layer (fourth layer), and the fixed electrode layer 17 and the second relay electrode layer 18 are also in the same layer (first layer). 5 layers). Here, the same layer, that is, the “same layer” refers to layers formed almost simultaneously by the same manufacturing process (film formation process) regardless of whether they are electrically or mechanically connected. Thus, by forming the relay electrode layers 15, 16, and 18 between the pixel electrode 11 and the semiconductor layer 12 in the same layer as the functional layer such as the data layer 6 and the fixed electrode layer 17, the number of layers of the multilayer wiring is increased. Can be simplified and the manufacturing process can be simplified.

  A base insulating film 20 is formed on the surface of the array substrate 10, and the first to sixth multilayer wiring structures are formed on the base insulating film 20. Of the first to sixth layers, the first insulating film 21 is provided between the first layer and the second layer, the second insulating film 22 is provided between the second layer and the third layer, and the third layer is provided. A third insulating film 23 between the fourth layer and the fourth layer; a fourth insulating film 24 between the fourth layer and the fifth layer; and a fifth insulating film 25 between the fifth layer and the sixth layer. Are formed.

  Among these, the film thickness of the fifth insulating film 25 is desirably set to 0.5 times or more the distance between pixel electrodes adjacent in the horizontal direction. For example, when the distance between adjacent pixel electrodes in the horizontal direction is set to 1.0 μm, the thickness of the fifth insulating film 5 is preferably 500 nm or more, and more preferably 750 nm or more. . By sufficiently securing the film thickness of the fifth insulating film 5 in this manner, the parasitic capacitance generated between the relay electrode layer connected to the pixel potential and the pixel electrode of the adjacent pixel is reduced, and the pixel potential is increased. And the common electric potential can be reduced. As a result, it is possible to suppress deterioration of the optical characteristics of the electro-optical material and maintain good image quality.

  Hereinafter, the detailed configuration of the above-described wiring and electrode layers will be described in order from the lower layer side.

  The scanning line 5 is, for example, a simple metal including at least one of metals such as titanium (Ti), chromium (Cr), aluminum (Al), tungsten (W), tantalum (Ta), and molybdenum (Mo). It consists of an alloy, metal silicide, polysilicon, or a laminate of these. A gate electrode 14 of the transistor 2 that drives the pixel is electrically connected to the scanning line 5 through a contact hole 26. The contact hole 26 is formed in a state penetrating the first insulating film 21 and the second insulating film 22 at a position away from the semiconductor layer 12.

  The semiconductor layer 12 is made of, for example, polysilicon, and constitutes the transistor 2 together with the gate electrode 14. The data line 6 is electrically connected to the source electrode (one end portion of the semiconductor layer 12) of the transistor 2 through the contact hole 27. The first relay electrode layer 16 is electrically connected to the drain electrode of the transistor 2 (the other end portion of the semiconductor layer 12) via the contact hole 28. The contact holes 27 and 28 are formed so as to penetrate the second insulating film 22 and the third insulating film 23.

The storage capacitor electrode 13 constitutes a storage capacitor between the electrode 13 and the semiconductor layer 12 facing the electrode 13 through the second insulating film 22. A capacitor relay electrode layer 15 is electrically connected to the storage capacitor electrode 13 through a contact hole 29. The contact hole 29 is formed so as to penetrate the third insulating film 23.

  The capacitor relay electrode layer 15 is between the fixed electrode layer 17 on the upper layer (fifth layer) of the capacitor relay electrode layer 15 and the storage capacitor electrode 13 on the lower layer (third layer) of the capacitor relay electrode layer 15. It relays electrical connections. For this reason, the fixed electrode layer 17 is electrically connected to the capacitive relay electrode layer 15 via the contact hole 30. The contact hole 30 is formed so as to penetrate the fourth insulating film 24.

  The first relay electrode layer 16, together with the second relay electrode layer 18 formed on the upper layer (fifth layer) of the first relay electrode layer 16, the sixth layer pixel electrode 11, the second layer semiconductor layer 12, It relays the electrical connection between them. Therefore, the second relay electrode layer 18 is electrically connected to the first relay electrode layer 16 via the contact hole 31, and the pixel electrode 11 is connected to the second relay electrode layer 18 via the contact hole 32. Electrically connected. The contact hole 31 is formed so as to penetrate the fourth insulating film 24, and the contact hole 32 is formed so as to penetrate the fifth insulating film 25.

  The fixed electrode layer 17 supplies a common potential Vcom serving as a fixed potential to the storage capacitor electrode 13 formed on the array substrate 10. When the array substrate 10 and the counter substrate are bonded together, the fixed electrode layer 17 is vertical. One end or both ends in the direction are electrically connected to the counter electrode on the counter substrate side. The fixed electrode layer 17 includes a main wiring portion 17A along a vertical direction (second direction) parallel to the data lines 6, and a dummy wiring portion 17B along a horizontal direction (first direction) parallel to the scanning lines 5. The dummy wiring portion 17B is formed in a state of projecting from the main wiring portion 17A to one side and the other in the horizontal direction at a position that separates the pixel electrodes 11 adjacent in the vertical direction. The fixed electrode layer 17 is made of a multilayer film containing a low-resistance metal material such as aluminum, titanium, or molybdenum, and includes a light-shielding layer made of a light-shielding material on at least one of the upper and lower layers of the low-resistance metal material. It is out. The light shielding layer is formed using, for example, a low reflection metal simple substance such as tungsten, an alloy, silicide, or the like. Thus, the fixed electrode layer 17 serves as a light shielding layer that blocks unnecessary light transmission in the light shielding region around the pixel electrode 11.

  If the fixed electrode layer 17 also serves as a light shielding layer in this way, it is not necessary to provide a separate process for forming a light shielding film, so that high-quality image quality can be achieved while reducing manufacturing costs and improving yield. Can be realized.

  In the light shielding region around the pixel electrode 11 by the fixed electrode layer 17, the above-described transistor 2, storage capacitor 4, scanning line 5, data line 6 and the like are arranged. For example, if the fixed electrode layer 17 also serves as a light shielding film as described above, the transistor 2 and the data line 6 are formed in a region shielded by the main wiring portion 17A of the fixed electrode layer 17 mainly along the vertical direction. The scanning line 5 is formed in a region shielded by the dummy wiring portion 17B of the fixed electrode layer 17 mainly along the horizontal direction. The storage capacitor 4 is formed in a region shielded from light by the fixed electrode layer 17 near the intersection of the scanning line 5 and the data line 6.

  However, between the data lines 6 adjacent in the horizontal direction (first direction), the dummy wiring portion 17B of the fixed electrode layer 17 is divided in the middle (almost intermediate position), and the fixed electrode layer 17 is divided into this divided portion. In other words, the second relay electrode layer 18 is formed in an island shape in a state in which the gap is formed between the fixed electrode layer 17 and the dummy wiring portion 17B of the fixed electrode layer 17 (interruption portion of the wiring pattern). As a result, the fixed electrode layer 17 forms a stripe-shaped wiring line substantially along the vertical direction. By forming the wiring line with a low-resistance material such as aluminum, a matrix-shaped wiring line is formed. Impedance can be set to the same level as that in which the wiring line is formed. Therefore, the common potential Vcom can be stably supplied to the lower storage capacitor electrode 13.

  The second relay electrode layer 18 is formed in a rectangular shape that is long in the vertical direction (second direction) in plan view, and the vertical line width L1d is a dummy wiring of the fixed electrode layer 17, as will be described in detail later. The point of the first embodiment is that it is set larger than the line width L1c in the vertical direction of the portion 17B. The second relay electrode layer 18 is a dummy wiring portion 17B of the fixed electrode layer 17 when the fixed electrode layer 17 formed on the entire surface of the array substrate 10 is patterned by a lithography technique or the like during the manufacturing process of the liquid crystal display panel. And the second relay electrode layer 18 are formed by removing a gap portion by etching or the like. In addition to the fixed electrode layer 17, the second relay electrode layer 18 also serves as a light shielding layer that blocks unnecessary light transmission in a light shielding region around the pixel electrode 11.

  The contact hole 31 formed in the fourth insulating film 24 below the second relay electrode layer 18 and the contact hole 32 formed in the fifth insulating film 25 above the second relay electrode layer 18 are planar. They are formed side by side at positions adjacent in the vertical direction (second direction). That is, in the formation region of the second relay electrode layer 18, the contact hole 31 is formed outside the pixel, and the contact hole 32 is disposed inside the pixel.

  The pixel electrode 11 is formed of a transparent conductive material such as ITO (Indium Tin Oxide). A plurality of pixel electrodes 11 are provided in a matrix form corresponding to the intersections of the scanning lines 5 and the data lines 6 on the array substrate 10. The periphery of the pixel electrode 11 is surrounded by a fixed electrode layer 17 that also serves as a light shielding layer.

  FIG. 4 is an enlarged plan view of the main part of the array substrate in FIG. Hereinafter, with reference to FIG. 1 to FIG. 3, the configuration of the peripheral portions of the fixed electrode layer 17 and the second relay electrode layer 18 which are the points of the first embodiment will be described in detail based on FIG. 4. .

  As described above, the point of the present invention is that the line width L1c in the vertical direction (second direction) of the dummy wiring portion 17B is set smaller than the line width L1d in the vertical direction of the second relay electrode layer 18. Become. In particular, on the pixel side where the pixel electrode 11 connected to the second relay electrode layer 18 via the contact hole 32 is disposed, the reduced region a indicated by a two-dot chain line in the plan view of FIG. Thus, it is important that the line width L1c of the dummy wiring 17B is reduced.

  Here, the second relay electrode layer 18 needs to be provided in a state of being sufficiently overlapped with the pixel electrode 11, for example, with a width of about 2.0 μm so that the connection with the pixel electrode 11 is sufficiently achieved. is there. Further, since the second relay electrode layer 18 also functions as a light shielding layer in the light shielding region around the pixel electrode 11 together with the fixed electrode layer 17, the pixel electrode of the pixel adjacent in the vertical direction (second direction). It is necessary to overlap the edge of (11) with a width of about 0.5 μm. Therefore, the line width L1d in the vertical direction (second direction) in the second relay electrode layer 18 is set to a value that satisfies the above-described state. For example, contact holes 31 and 32 are connected to the upper and lower sides of the second relay electrode layer 18, and the vertical opening widths L 31 and L 32 of these contact holes 31 and 32 and the contact to the second relay electrode layer 18. A space L2 in consideration of the process margin of the arrangement positions of the holes 31 and 32, and a space in consideration of a change in processing dimension in the manufacturing process set between the end of the contact hole 32 and the end of the pixel electrode 11. If the space L6 is set between the contact hole 31 in consideration of securing a space necessary for processing the pixel electrode 11 adjacent to the pixel electrode 11 and L5, the second relay electrode layer 18 is formed. The required line width L1d is L1d = L31 + L32 + 2 × L2 + L5 + L6.

  On the other hand, since the dummy wiring portion 17B in the fixed electrode layer 17 also functions as a light shielding layer in the light shielding region around the pixel electrode 11, the pixel electrodes 11 in which the edges on both sides are arranged adjacent to each other in the vertical direction. , (11) and the line width L1c should be set so that the pixel electrodes 11, (11) can be electrically separated on the dummy wiring portion 17B. The vertical line width L1c of the dummy wiring portion 17B in the fixed electrode layer 17B for supplying a fixed potential is the opening widths L29 and L30 of the contact holes L29 and L30, the contact hole 29 for the second relay electrode layer 18, Assuming that the space L2 in consideration of the process margin at the 30 arrangement positions, L1c = 2 × L1 + 2 × L2.

  From the above, the line width L1c of the dummy wiring portion 17B is laid out with a width smaller than the line width L1d of the second relay electrode 18 by the dimension of L5 + L6. That is, the second relay electrode 18 needs to be sufficiently overlapped with the pixel electrode 11 so that the connection with the pixel electrode 11 is sufficiently achieved, whereas the dummy wiring portion 17B takes this into consideration. Since there is no need, the overlap width with the pixel electrode 11 can be set small, and the line width L1c can be reduced by this amount. Then, by reducing the vertical line width L1c of the dummy wiring portion 17B, the area a shown in FIG. 3 can be made an opening area, and a high aperture ratio of the pixel can be realized.

  5 is a cross-sectional view in the horizontal direction in FIG. 4, and is an enlarged cross-sectional view of the main part of FIG. In the electro-optical device of the first embodiment, the second relay electrode 18 and the dummy wiring portion 17B of the fixed electrode layer 17 formed in the same layer as the second relay electrode layer 18 are electrically separated from each other. The planar intervals L7 and L8 are formed to be 1.0 μm or less, and the first relay electrode 16 is disposed in the lower layer of the separated region. In particular, it is assumed that the first relay electrode 16 disposed in the lower layer is provided so as to overlap with the distances L7 and L8 in plan view.

  Thereby, when incident light 100 from the outside enters from the pixel electrode 11 side and leaks into the lower layer from the distances L7 and L8 between the fixed electrode layer 17 also serving as a light shielding layer and the second relay electrode layer 18, this incident light 100 is incident on the first relay electrode 16 disposed so as to overlap the intervals L7 and L8 and is shielded from light. As a result, the incident light 100 leaks into the lower layer than the second relay electrode layer 18 and scatters, and further enters the lower layer of the relay electrode 15 or 19, thereby irradiating the TFT with light and degrading element characteristics. It is possible to prevent light from leaking to the opposite side of the substrate and causing a decrease in contrast or the like.

  The dimension Lhc necessary for the horizontal (first direction) layout of the second relay electrode layer 18 is the horizontal line width L9 of the second relay electrode layer 18 and the distance necessary for separation from the fixed electrode layer 17. Lhc = L7 + L8 + L9 when L7 and L8 are combined. For this reason, in order to narrow the layout required in the horizontal direction and reduce the pixel pitch, since L9 depends on the diameter of the contact 31, it is necessary to reduce the distances L7 and L8.

  Here, FIG. 6 shows the experimental results of examining the relationship between the electrode spacings L7 and L8 that can be formed with respect to the film thickness T1 of the fixed electrode layer made of aluminum and the second relay electrode layer. The electrode spacings L7 and L8 that can be formed are a combination of workability by lithography and workability by etching. When a multilayer film containing aluminum is used for the fixed electrode layer and the second relay electrode layer, The electrode spacings L7 and L8 that can be formed differ with respect to the film thickness.

  When the film thickness is set to be high in order to lower the resistance with a high-resistance material or to improve the light shielding property, it is necessary to set the electrode intervals L7 and L8 to a certain value. From the experiment, when the film thickness T1 is 1.0 μm or less, the distances L7 and L8 can be formed with 1.0 μm or less. Therefore, in order to reduce the pitch of the pixels, by defining the film thickness T1 of the fixed electrode layer and the second relay electrode layer to be 1.0 μm or less, the distances L7 and L8 are formed to be 1.0 μm or less and the horizontal direction Narrow pitch can be realized.

  FIG. 7 is a plan view showing the entire configuration of the array substrate 10. As shown in this figure, an image display area 101 in which pixels having the above-described configuration are arranged in a matrix is arranged at the center of the array substrate 10. The vertical length of the main wiring portion 17A in the fixed electrode layer substantially matches the vertical length Lvm of the image display area 101. Although the length Lvm varies depending on the size of the electro-optical device, the main wiring portion 17A is required to have a certain low wiring resistance.

  FIG. 8 is a graph of wiring resistance with respect to the line width L10 of the main wiring portion 17A in the fixed electrode layer 17 made of a laminated film containing aluminum having a thickness of 100 nm when the length Lvm = 15 mm. As shown in this graph, the wiring resistance is substantially proportional to the line width L10 in the range of the line width L10 = 1.0 μm or more. In an electro-optical device having a size in which the length Lvm of the fixed electrode layer in the image display region is short, the line resistance value R1 is 1. E + 03 <R1 <1. E + 04. Therefore, the line width L10 of the main wiring portion 17A can be reduced to 1.0 μm. On the other hand, the upper limit of the line width L10 of the main wiring portion 17A is preferably 2.0 μm or less from the viewpoint of securing the aperture ratio of the pixels. Therefore, the line width L10 (see FIG. 3) of the main wiring portion 17A in the fixed electrode layer 17 is 1.0 μm or more and 2.0 μm or less.

  Further, if the length Lvm is further reduced, the line width of the fixed electrode layer 17 can be reduced. For example, in order to maintain a resistance value (≈ 1.E + 03) comparable to the resistance value when the length Lvm = 15 mm and the line width L10 = 2.0 μm of the main wiring portion 17A, the length Lvm = 10 mm The line width of the fixed electrode layer may be about 1.4 μm.

  FIG. 9 is a graph of the wiring resistance against the film thickness T1 of the fixed electrode layer 17. The fixed electrode layer 17 is made of aluminum having a width of 1.0 μm. As shown in this graph, in the fixed electrode layer (conductive layer including a low-resistance metal wiring), the length in the vertical direction (second direction) in the image display region of the fixed electrode layer is within a range of 80 nm or more. A high-quality image can be obtained by sufficiently satisfying the wiring resistance value (R1) necessary for driving an electro-optical device with Lvm = 15 mm and ensuring that the fixed electrode layer has a film thickness of 80 nm or more. .

Second Embodiment
FIG. 10 is a plan layout view of the main part for explaining the characteristic part of the second embodiment of the present invention. The second embodiment shown in this figure is different from the first embodiment described above in the layout of the second relay electrode layer 18 and the contact holes 31 and 32, and the other configurations are the same.

  That is, in the second embodiment, the contact holes 31 and 32 (see FIG. 2) formed in the upper and lower layers of the second relay electrode layer 18 are arranged in the vertical direction (second direction) in plan view. Is provided. These contact hoses 31 and 32 are formed with different opening diameters. The contact hole 31 having an opening diameter L31a smaller than the opening width L32a in the horizontal direction (first direction) of the contact hole 32 having a large opening diameter is arranged. . For this reason, the contact holes 31 and 32 need to be configured with an opening diameter with a difference equal to or larger than the margin of misalignment in the horizontal direction in these manufacturing processes. In the drawing, the contact hole 32 disposed in the upper layer of the second relay electrode layer 18 is illustrated as being larger than the contact hole 31 disposed in the lower layer.

  Thus, by laying out the other contact hole 31 having a smaller opening diameter inside the opening diameter L32a of one contact hole 32, it is necessary for a planar layout around the island-shaped second relay electrode layer 18. The required dimension Lha in the horizontal direction is a space L2 in consideration of a process margin of the arrangement position of the contact hole 32 with respect to the second relay electrode layer 18, an interval L7 between the second relay electrode layer 18 and the fixed electrode layer 17, When L8, Lha = L32a + 2 × L2 + L7 + L8, and it is not necessary to consider the margin of misalignment between the contact hole 31 and the contact hole 32.

  Furthermore, by increasing the difference in the horizontal opening width between the contact hole 31 and the contact hole 32, the contact hole 31 can be laid out freely within the range of L32a of the diameter of the contact hole 32. For example, even when the first relay electrode 16 (see FIG. 3) connected to the second relay electrode 18 by the contact hole 31 is laid out so that one side thereof overlaps the contact hole 32, the contact hole 31 The contact hole 31 and the first relay electrode 16 are laid out at a distance of the dimension L4 from the end of the one relay electrode 16, and even if the processing dimensions change during the manufacturing process, the horizontal space is not increased. It can be formed with sufficient margin. Therefore, it is possible to reduce the pixel pitch in the horizontal direction.

<Third Embodiment>
FIG. 11 is a plan layout view of the main part for explaining the characteristic part of the third embodiment of the present invention. The third embodiment shown in this figure differs from the second embodiment described above in the layout of the contact holes 29 and 30 connected to the fixed electrode 17, and the other configurations are the same.

That is, in the third embodiment, the lower layer of the fixed electrode layer 17, the capacitor contact Hall 29 and 30 formed in the upper and lower relay electrode layer 15 (see FIG. 2) is a plan view to the vertical direction They are arranged in the (second direction). These contact hall 29 and 30 are formed with different opening diameters. In the drawing, the case where the contact hole 30 disposed in the upper layer of the capacitor relay electrode 15 is larger than the contact hole 29 disposed in the lower layer is illustrated. The second reason is that the contact hole 29 having a small opening diameter is disposed within the range of the width of the opening diameter in the horizontal direction (first direction) in the contact hole 30 having a large opening diameter. This is the same as the relationship between the contact holes 31 and 32 in the embodiment. In the drawing, the contact hole 30 disposed in the upper layer of the capacitor relay electrode 15 is illustrated as being larger than the contact hole 29 disposed in the lower layer.

  By adopting such a configuration, the layout of the contact holes 29 and 30 in the horizontal direction need not take into account the margin of misalignment, as in the case described with the contact holes 31 and 32. In addition, the degree of freedom in layout increases. For example, even when the capacitor electrode 13 connected to the capacitor relay electrode 15 by the contact hole 29 is laid out so as to overlap the contact hole 30, the contact hole 29 has a sufficient margin from the end of the capacitor electrode 14. Can be formed. Therefore, it is possible to reduce the pixel pitch in the horizontal direction.

  In the drawing, the case where the opening diameters of the contact holes 31 and 32 are different as shown in the second embodiment is illustrated. However, the second embodiment may be configured such that the opening diameters of the contact holes 31 and 32 are the same and only the opening diameters of the contact holes 29 and 30 are different. However, the opening diameters of the contact holes 31 and 32 are different from each other as described in the second embodiment, so that the effect of narrowing the pixel pitch in the horizontal direction is enhanced.

  The second and third embodiments described above exemplify cases where the vertical line width of the dummy wiring portion 17B in the fixed electrode layer 17 is smaller than the vertical line width of the second relay electrode 18. . However, the second and third embodiments can be applied to a configuration in which the vertical line width of the dummy wiring portion 17B in the fixed electrode layer 17 and the vertical line width of the second relay electrode 18 are the same. Even in such a case, the pixel pitch in the horizontal direction can be reduced.

It is a circuit diagram which shows the structural example of the pixel circuit of the liquid crystal display device to which this invention is applied. It is sectional drawing which shows the laminated structure of the array board | substrate in the liquid crystal display device to which this invention is applied. FIG. 3 is a plan layout view of the main part of the array substrate according to the first embodiment. FIG. 4 is an enlarged plan view of the main part of FIG. 3. It is sectional drawing of the horizontal direction in FIG. 4, and is sectional drawing which expanded the principal part of FIG. It is a graph which shows the relationship of the electrode space | interval L7 and L8 which can be formed with respect to the film thickness T1 of the fixed electrode layer which consists of aluminum, and a 2nd relay electrode layer. It is a top view which shows the whole structure of an array board | substrate. It is a graph of wiring resistance with respect to line width L10 of the main wiring part in a fixed electrode layer. It is a graph of wiring resistance with respect to film thickness T1 of a fixed electrode layer. It is a plane layout figure of the principal part for demonstrating the characteristic part of 2nd Embodiment. It is a plane layout figure of the principal part for demonstrating the characteristic part of 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Pixel, 2 ... Transistor, 3 ... Liquid crystal cell, 4 ... Storage capacitor, 5 ... Scan line, 6 ... Data line, 10 ... Array substrate, 11 ... Pixel electrode, 12 ... Semiconductor layer, 13 ... Storage capacitor electrode, 14 ... Gate electrode, 15, 16, 18 ... Relay electrode layer, 17 ... Fixed electrode layer, 20-25 ... Insulating film, 26-32 ... Contact hole

Claims (4)

On one of the pair of substrates facing each other through the electro-optic material layer,
A plurality of adjacent data lines;
A pixel electrode;
A transistor for controlling the pixel electrode;
A storage capacitor electrically connected to the pixel electrode ;
A fixed electrode layer divided between adjacent data lines for supplying a potential to the storage capacitor ;
Same as the data line, which electrically connects one electrode of the storage capacitor and the fixed electrode layer.
A capacitive relay electrode layer of layers;
A first relay electrode layer in the same layer as the data line;
The second relay power formed above the first relay electrode layer and formed in the divided portion of the fixed electrode layer.
Have a layered structure comprising a cathode layer, the,
The first relay electrode layer and the second relay electrode layer are formed of the pixel electrode and the transistor.
Electrically connecting the semiconductor layer,
The line width in the data line direction in the second relay electrode layer intersects the data line direction.
The line width of the fixed electrode layer extending in the direction is larger than the line width in the data line direction.
The specified electro-optical device. 2. The electro-optical device according to claim 1, wherein two contact holes having different opening diameters are arranged in the data line direction in each of the upper and lower insulating films of the capacitive relay electrode layer. On one of the pair of substrates facing each other through the electro-optic material layer,
A scan line formed along a first direction;
A data line formed along a second direction intersecting the first direction;
Pixel electrodes provided corresponding to intersections of the scanning lines and the data lines;
A transistor for switching control of the pixel electrode;
Storage capacity,
Wherein an electric potential to the storage capacitor have a layered structure comprising a fixed electrode layer supplies,
The pixel electrode and the semiconductor layer of the transistor include a first relay electrode layer that is the same layer as the data line, and the first electrode in which the fixed electrode layer is divided between adjacent data lines in the first direction. Electrically connected via a second relay electrode layer above the relay electrode,
The line width in the second direction of the second relay electrode layer is such that the first electrode of the fixed electrode layer is arranged on the pixel side where the pixel electrode connected to the second relay electrode layer via a contact hole is disposed. Is set larger than the line width in the second direction of the portion extending in the direction of
Wherein one electrode of the storage capacitor and the fixed electrode layer, that is electrically connected via a capacitor relay electrode layer of the data line and the same layer
Electrical optical device. Two contact holes with different opening diameters are formed in the upper and lower insulating films of the second relay electrode layer, the two contact holes are arranged in the second direction, and the first The contact hole having a small opening diameter in the direction is arranged within the range of the formation width of the contact hole having a large opening diameter.
The electro-optical device according to claim 3 .

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