CN102830563B - Panel periphery connection structure and display device - Google Patents

Panel periphery connection structure and display device Download PDF

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Publication number
CN102830563B
CN102830563B CN201210330910.7A CN201210330910A CN102830563B CN 102830563 B CN102830563 B CN 102830563B CN 201210330910 A CN201210330910 A CN 201210330910A CN 102830563 B CN102830563 B CN 102830563B
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layer
electrode layer
signal output
electrode
syndeton
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CN102830563A (en
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金相秦
黄炳相
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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  • Thin Film Transistor (AREA)

Abstract

The invention discloses a panel periphery connection structure. The panel periphery connection structure comprises two signal output layers formed on a substrate, insulation layers positioned on the signal output layers, a second electrode layer arranged on the uppermost insulation layer, and a first electrode layer positioned below one signal output layer, wherein the second electrode layer is conductively connected with the two signal output layers through a conductive through hole respectively; the first electrode layer is provided with an outer edge horizontally protruding from the surface of the signal output layers above the first electrode layer; and the second electrode layer is conductively connected with the outer edge of the first electrode layer through a peripheral conductive through hole. The invention further discloses a display device comprising the connection structure. Therefore, the image greening phenomenon of the display device caused by poor connection can be improved.

Description

Panel periphery syndeton and display device
Technical field
The present invention relates to display technique field, relate in particular to a kind of panel periphery syndeton and display device.
Background technology
Present thin-film transistor LCD device (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) technology is in order to produce high-quality product, need to introduce high-precision Refinement operation and new technology, technique between each layer and design are also more complicated, therefore make technologic design margin not enough, and it is bad and have influence on the quality of product easily to produce product.For example present senior super Wei Chang changes (Advanced super Dimension Switch, ADS) the peripheral syndeton of the TFT-LCD panel of pattern is (as shown in the dotted line circle in Fig. 1, described peripheral syndeton is mainly positioned at four external angles of panel need to realize the position that grid layer public electrode connecting portion is connected with source-drain electrode layer public electrode connecting portion), as shown in Figures 2 and 3, described peripheral syndeton comprises the grid layer public electrode connecting portion 102 on substrate 101, gate insulator 103, source-drain electrode layer public electrode connecting portion 104, insulation course (passivation layer) 105 and electrode layer 106, utilize via hole 107(Via Hole) electrode layer 106 is electrically connected to grid layer public electrode connecting portion 102 and source-drain electrode layer public electrode connecting portion 104, so that signal is outputed on periphery loop.But, due to structure and existing TN(Twisted Nematic between the structure more complicated of this kind of TFT-LCD and its each layer) structure of TFT-LCD is different, therefore bad (as the large area of panel causes the low and profile anomaly of homogeneity, make electrode layer disappearance and break) of above-mentioned coupling part possibility of occurring is quite large.Due to above-mentioned bad existence, on after the product that complete can bring out phenomenons such as affecting the picture of picture grade general green (Greenish) while detecting and occur, become one of reason reducing product quality.
Certainly, by improving the mode of technique, can make great efforts to address this problem, but due to the maximization of panel and the reasons such as equilibrium response of technique, only by process improving, will address this problem completely sizable difficulty.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention is: provide a kind of array base palte and display device, to improve the general green phenomenon of the display device picture causing due to bad connection.
(2) technical scheme
For addressing the above problem, the invention provides a kind of panel periphery syndeton, comprise the two layer signal output layers that are formed on substrate, be positioned at the insulation course on every layer signal output layer and be located at the second electrode lay on the superiors' insulation course, described the second electrode lay is connected with described two layer signal output layer conductions respectively by conductive via, described panel periphery syndeton also comprises the first electrode layer that is positioned at signal output layer below described in one deck, described the first electrode layer has the outer rim beyond the laterally projecting signal output layer aspect in top, described the second electrode lay is connected with the outer rim conduction of described the first electrode layer by peripheral conductive via.
Preferably, described two layer signal output layers comprise grid layer public electrode connecting portion and source-drain electrode layer public electrode connecting portion.
Preferably, described the first electrode layer is positioned at described grid layer public electrode connecting portion below.
Preferably, described the first electrode layer is positioned at described source-drain electrode layer public electrode connecting portion below.
Preferably, described the first electrode layer and the second electrode lay are indium tin oxide semiconductor film.
On the other hand, the present invention also provides a kind of display device, comprises display panel, it is characterized in that, described display panel comprises above-mentioned panel periphery syndeton.
Preferably, described two layer signal output layers comprise grid layer public electrode connecting portion and source-drain electrode layer public electrode connecting portion.
(3) beneficial effect
The present invention can effectively prevent because the peripheral loose contact problem that electrode layer disappearance etc. causes, and then reduces the possibility that the general phenomenon such as green occurs display, improves display picture quality;
The present invention was applied to the TFT-LCD of ADS and HADS pattern when upper, without appending technological process, can realize.
Accompanying drawing explanation
Fig. 1 is the position view of panel periphery syndeton on whole panel;
Fig. 2 is the floor map of prior art panel periphery syndeton;
Fig. 3 is the cut-open view of the sectional structure at A-A place in Fig. 2;
Fig. 4 is the floor map of the embodiment of the present invention one panel periphery syndeton;
Fig. 5 is the cut-open view of the embodiment of the present invention one panel periphery syndeton;
Fig. 6 is the cut-open view of the embodiment of the present invention two panel periphery syndetons;
Wherein: 101: substrate; 102: grid layer public electrode connecting portion; 103: gate insulator; 104: source-drain electrode layer public electrode connecting portion; 105: insulation course; 106: electrode layer; 107: via hole;
201: substrate; 202: grid layer public electrode connecting portion; 203: insulation course; 204: source-drain electrode layer public electrode connecting portion; 205: the second electrode lay; 206: conductive via; 207: the first electrode layers; 207a: the first electrode layer outer rim; 208: peripheral conductive via;
301: substrate; 302: grid layer public electrode connecting portion; 303: insulation course; 304: source-drain electrode layer public electrode connecting portion; 305: the second electrode lay; 306: conductive via; 307: the first electrode layers; 307a: the first electrode layer outer rim; 308: peripheral conductive via.
Embodiment
Below in conjunction with drawings and Examples, that the present invention is described in detail is as follows.
Embodiment mono-:
As shown in Figure 4 and Figure 5, the present embodiment has been recorded a kind of panel periphery syndeton, comprise the two layer signal output layers that are formed on substrate 201, be positioned at the insulation course 203 on every layer signal output layer and be located at the second electrode lay 205 on the superiors' insulation course 203, described the second electrode lay 205 is connected with described two layer signal output layer conductions respectively by conductive via 206, for carrying out the signal transmission of panel and peripheral circuit, described panel periphery syndeton also comprises the first electrode layer 207 that is positioned at signal output layer below described in one deck, described the first electrode layer 207 has the outer rim 207a beyond the laterally projecting signal output layer aspect in top, described the second electrode lay 205 is connected with the outer rim 207a conduction of described the first electrode layer 207 by peripheral conductive via 208.
In the present embodiment, described two layer signal output layers comprise grid layer public electrode connecting portion 202 and source-drain electrode layer public electrode connecting portion 204.
In the present embodiment, described the first electrode layer 207 is positioned at described grid layer public electrode connecting portion 202 belows.
In the present embodiment, described the first electrode layer 207 and the second electrode lay 205 are indium tin oxide semiconductor film.
In the present embodiment, even if the second electrode lay 205 produces bad with direct-connected conductive via 206 parts of grid layer public electrode connecting portion 202, the second electrode lay 205 also can be electrically connected to described grid layer public electrode connecting portion 202 by peripheral conductive via 208 and the first electrode layer 207, therefore, can prevent that the general green picture quality that waits that the second electrode lay 205 and 202 loose contacts of grid layer public electrode connecting portion cause is bad.
Embodiment bis-:
The panel periphery syndeton of the present embodiment and the structure of embodiment mono-are basic identical, also comprise the grid layer public electrode connecting portion 302 and the source-drain electrode layer public electrode connecting portion 304 that are formed on substrate 301, be positioned at the insulation course 303 on described grid layer public electrode connecting portion 302 and source-drain electrode layer public electrode connecting portion 304, be located at the second electrode lay 305 and the first electrode layer 307 on the superiors' insulation course 303, described the second electrode lay 305 is connected with source-drain electrode layer public electrode connecting portion 304 conductions with described grid layer public electrode connecting portion 302 respectively by conductive via 306, described the first electrode layer 307 has the outer rim 307a beyond the laterally projecting signal output layer aspect in top, described the second electrode lay 305 is connected with the outer rim 307a conduction of described the first electrode layer 307 by peripheral conductive via 308.
Be with embodiment mono-difference, as shown in Figure 6, the first electrode layer 307 described in the present embodiment is positioned at described source-drain electrode layer public electrode connecting portion 304 belows.
In the present embodiment, even if the second electrode lay 305 partly produces bad with source-drain electrode layer public electrode connecting portion 304 direct-connected conductive vias, the second electrode lay 305 also can be electrically connected to described source-drain electrode layer public electrode connecting portion 304 by peripheral conductive via 308 and the first electrode layer 307, therefore, can prevent that the general green picture quality that waits that loose contact causes is bad.
Certainly, except the structure shown in embodiment mono-and embodiment bis-, other can be suitable for by all structures that two layer signal transport layers partly overlapped and connect with the second electrode lay, as long as have living space, uses the first electrode layer to design.
Embodiment tri-:
The present embodiment has been recorded a kind of display device, comprises display panel, and described display panel comprises the panel periphery syndeton described in embodiment mono-.
In the present embodiment, described display panel is the liquid crystal panel of ADS pattern, and described the first electrode layer is the common electrode layer that is positioned at described grid layer public electrode connecting portion below.
Embodiment tetra-:
The present embodiment has been recorded a kind of display device, comprises display panel, and described display panel comprises the panel periphery syndeton described in embodiment bis-.
In the present embodiment, described display panel is the liquid crystal panel of HADS pattern, and described the first electrode layer is the pixel electrode layer that is positioned at described source-drain electrode layer public electrode connecting portion below.
By embodiment tri-and embodiment tetra-, can find out, the present invention is particularly suitable on the TFT-LCD of ADS and HADS pattern, because be originally just arranged with electrode layer as public electrode at grid layer public electrode connecting portion in the peripheral syndeton of the TFT-LCD of ADS pattern, in the peripheral syndeton of the TFT-LCD of HADS pattern, under original source-drain electrode layer public electrode connecting portion, be also provided with electrode layer as pixel electrode, therefore for the present invention, add and do not need to append technological process man-hour and just can form described the first electrode layer.
Above embodiment is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.

Claims (6)

1. a panel periphery syndeton, comprise the two layer signal output layers that are formed on substrate, be positioned at the insulation course on every layer signal output layer and be located at the second electrode lay on the superiors' insulation course, described the second electrode lay is connected with described two layer signal output layer conductions respectively by conductive via, it is characterized in that, described panel periphery syndeton also comprises the first electrode layer of any layer signal output layer below that is arranged in described two layer signal output layers, described the first electrode layer has the outer rim beyond the laterally projecting signal output layer aspect in top, thereby described the second electrode lay is connected with the outer rim conduction of described the first electrode layer by peripheral conductive via with a described layer signal output layer conduction of described the first electrode layer top and is connected.
2. panel periphery syndeton as claimed in claim 1, is characterized in that, described two layer signal output layers comprise grid layer public electrode connecting portion and source-drain electrode layer public electrode connecting portion.
3. panel periphery syndeton as claimed in claim 2, is characterized in that, described the first electrode layer is positioned at described grid layer public electrode connecting portion below.
4. panel periphery syndeton as claimed in claim 2, is characterized in that, described the first electrode layer is positioned at described source-drain electrode layer public electrode connecting portion below.
5. the panel periphery syndeton as described in any one in claim 1-4, is characterized in that, described the first electrode layer and the second electrode lay are indium tin oxide semiconductor film.
6. a display device, comprises display panel, it is characterized in that, described display panel comprises the arbitrary described panel periphery syndeton of claim 1 to 5.
CN201210330910.7A 2012-09-07 2012-09-07 Panel periphery connection structure and display device Active CN102830563B (en)

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CN105428371B (en) * 2015-12-24 2019-06-25 深圳市华星光电技术有限公司 Display panel and thin-film transistor array base-plate
CN105785677B (en) * 2016-05-11 2019-06-07 深圳市华星光电技术有限公司 The manufacturing method of display device and its display panel, display panel

Citations (3)

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Publication number Priority date Publication date Assignee Title
CN100373538C (en) * 2000-09-14 2008-03-05 株式会社半导体能源研究所 Semiconductor device and its method for production
CN101458412A (en) * 2007-12-14 2009-06-17 乐金显示有限公司 Electrically-driven liquid crystal lens and stereoscopic display device using the same
CN202771136U (en) * 2012-09-07 2013-03-06 京东方科技集团股份有限公司 Panel peripheral connecting structure and display device

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Publication number Priority date Publication date Assignee Title
KR100354905B1 (en) * 1998-07-23 2003-06-12 삼성전자 주식회사 LCD Display
JP4798094B2 (en) * 2007-07-31 2011-10-19 ソニー株式会社 Electro-optic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100373538C (en) * 2000-09-14 2008-03-05 株式会社半导体能源研究所 Semiconductor device and its method for production
CN101458412A (en) * 2007-12-14 2009-06-17 乐金显示有限公司 Electrically-driven liquid crystal lens and stereoscopic display device using the same
CN202771136U (en) * 2012-09-07 2013-03-06 京东方科技集团股份有限公司 Panel peripheral connecting structure and display device

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