CN202771136U - Panel peripheral connecting structure and display device - Google Patents
Panel peripheral connecting structure and display device Download PDFInfo
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- CN202771136U CN202771136U CN201220456513.XU CN201220456513U CN202771136U CN 202771136 U CN202771136 U CN 202771136U CN 201220456513 U CN201220456513 U CN 201220456513U CN 202771136 U CN202771136 U CN 202771136U
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Abstract
The utility model discloses a panel peripheral connecting structure and a display device. The panel peripheral connecting structure comprises two signal output layers, insulation layers and a second electrode layer, wherein the two signal output layers are formed on a substrate, and the insulation layers are respectively arranged on each signal output layer, and the second electrode layer is arranged on the topmost insulation layer. The second electrode layer is connected with the two signal output layers in a conductive mode through conductive via holes. The panel peripheral connecting structure further comprises a first electrode layer arranged under one signal output layer. The first electrode layer is provided with an outer edge which horizontally protrudes out of the layer face of the above signal output layer. The second electrode layer is connected with the outer edge of the first electrode layer in a conductive mode through peripheral conductive via holes. The utility model further discloses a display device which includes the connecting structure. The panel peripheral connecting structure can improve the phenomenon that frames of the display device turn green due to poor connection.
Description
Technical field
The utility model relates to the display technique field, relates in particular to a kind of panel periphery syndeton and display device.
Background technology
Present thin-film transistor LCD device (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) technology is in order to produce high-quality product, need to introduce high-precision Refinement operation and new technology, technique between each layer and design are also more complicated, therefore so that technologic design margin is not enough, and it is bad and have influence on the quality of product to produce easily product.For example present senior super Wei Chang changes (Advanced super Dimension Switch, ADS) the peripheral syndeton of the TFT-LCD panel of pattern is (shown in the dotted line circle among Fig. 1, described peripheral syndeton mainly is positioned at the position that four external angles of panel need to realize that grid layer public electrode connecting portion is connected with source-drain electrode layer public electrode connecting portion), as shown in Figures 2 and 3, described peripheral syndeton comprises the grid layer public electrode connecting portion 102 on the substrate 101, gate insulator 103, source-drain electrode layer public electrode connecting portion 104, insulation course (passivation layer) 105 and electrode layer 106, utilize via hole 107(Via Hole) come so that electrode layer 106 is electrically connected with grid layer public electrode connecting portion 102 and source-drain electrode layer public electrode connecting portion 104, so that signal is outputed on the peripheral loop.But, because structure and existing TN(Twisted Nematic between the structure more complicated of this kind TFT-LCD and its each layer) structure of TFT-LCD is different, therefore the possibility of bad (large tracts of land such as panel causes homogeneity lowly to reach profile anomaly, breaks so that electrode layer lacks) generation of above-mentioned coupling part is quite large.Because above-mentioned bad existence, on after the product of finishing can bring out the phenomenon generations such as the picture that affects the picture grade general green (Greenish) when detecting, become one of reason of reduction product quality.
Certainly, can make great efforts to address this problem by the mode of improving technique, but owing to the maximization of panel and the reasons such as equilibrium response of technique, only will address this problem completely sizable difficulty by process improving.
The utility model content
The technical matters that (one) will solve
The technical problems to be solved in the utility model is: provide a kind of array base palte and display device, to improve the general green phenomenon of display device picture that causes owing to bad connection.
(2) technical scheme
For addressing the above problem, the utility model provides a kind of panel periphery syndeton, comprise the two layer signal output layers that are formed on the substrate, be positioned at the insulation course on every layer signal output layer and be located at the second electrode lay on the superiors' insulation course, described the second electrode lay is connected with described two layer signal output layers conduction respectively by conductive via, described panel periphery syndeton also comprises the first electrode layer that is positioned at the described signal output layer of one deck below, described the first electrode layer has laterally projecting outer rim beyond the signal output layer aspect of top, and described the second electrode lay is connected with the outer rim conduction of described the first electrode layer by peripheral conductive via.
Preferably, described two layer signal output layers comprise grid layer public electrode connecting portion and source-drain electrode layer public electrode connecting portion.
Preferably, described the first electrode layer is positioned at described grid layer public electrode connecting portion below.
Preferably, described the first electrode layer is positioned at described source-drain electrode layer public electrode connecting portion below.
Preferably, described the first electrode layer and the second electrode lay are the indium tin oxide semiconductor film.
On the other hand, the utility model also provides a kind of display device, comprises display panel, it is characterized in that, described display panel comprises above-mentioned panel periphery syndeton.
Preferably, described two layer signal output layers comprise grid layer public electrode connecting portion and source-drain electrode layer public electrode connecting portion.
(3) beneficial effect
The utility model can effectively prevent because the peripheral loose contact problem that electrode layer disappearance etc. causes, and then reduces the possibility that the general phenomenon such as green occurs display, improves the display picture quality;
The utility model was applied to the TFT-LCD of ADS and HADS pattern when upper, and need not to append technological process can realize.
Description of drawings
Fig. 1 is the position view of panel periphery syndeton on whole panel;
Fig. 2 is the floor map of prior art panel periphery syndeton;
Fig. 3 is the cut-open view of the sectional structure at A-A place among Fig. 2;
Fig. 4 is the floor map of the peripheral syndeton of the utility model embodiment one panel;
Fig. 5 is the cut-open view of the peripheral syndeton of the utility model embodiment one panel;
Fig. 6 is the cut-open view of the utility model embodiment two panel periphery syndetons;
Wherein: 101: substrate; 102: grid layer public electrode connecting portion; 103: gate insulator; 104: source-drain electrode layer public electrode connecting portion; 105: insulation course; 106: electrode layer; 107: via hole;
201: substrate; 202: grid layer public electrode connecting portion; 203: insulation course; 204: source-drain electrode layer public electrode connecting portion; 205: the second electrode lay; 206: conductive via; 207: the first electrode layers; 207a: the first electrode layer outer rim; 208: peripheral conductive via;
301: substrate; 302: grid layer public electrode connecting portion; 303: insulation course; 304: source-drain electrode layer public electrode connecting portion; 305: the second electrode lay; 306: conductive via; 307: the first electrode layers; 307a: the first electrode layer outer rim; 308: peripheral conductive via.
Embodiment
The utility model is elaborated as follows below in conjunction with drawings and Examples.
Embodiment one:
As shown in Figure 4 and Figure 5, present embodiment has been put down in writing a kind of panel periphery syndeton, comprise the two layer signal output layers that are formed on the substrate 201, be positioned at the insulation course 203 on every layer signal output layer and be located at the second electrode lay 205 on the superiors' insulation course 203, described the second electrode lay 205 is connected with described two layer signal output layers conduction respectively by conductive via 206, be used for carrying out the signal transmission of panel and peripheral circuit, described panel periphery syndeton also comprises the first electrode layer 207 that is positioned at the described signal output layer of one deck below, described the first electrode layer 207 has laterally projecting outer rim 207a beyond the signal output layer aspect of top, and described the second electrode lay 205 is connected with the outer rim 207a conduction of described the first electrode layer 207 by peripheral conductive via 208.
In the present embodiment, described two layer signal output layers comprise grid layer public electrode connecting portion 202 and source-drain electrode layer public electrode connecting portion 204.
In the present embodiment, described the first electrode layer 207 is positioned at described grid layer public electrode connecting portion 202 belows.
In the present embodiment, described the first electrode layer 207 and the second electrode lay 205 are the indium tin oxide semiconductor film.
In the present embodiment, even the second electrode lay 205 produces bad with grid layer public electrode connecting portion 202 direct-connected conductive via 206 parts, the second electrode lay 205 also can be electrically connected with described grid layer public electrode connecting portion 202 by peripheral conductive via 208 and the first electrode layer 207, therefore, can prevent that the general green picture quality that waits that the second electrode lay 205 and 202 loose contacts of grid layer public electrode connecting portion cause is bad.
Embodiment two:
The panel periphery syndeton of present embodiment and the structure of embodiment one are basic identical, also comprise the grid layer public electrode connecting portion 302 and the source-drain electrode layer public electrode connecting portion 304 that are formed on the substrate 301, be positioned at the insulation course 303 on described grid layer public electrode connecting portion 302 and the source-drain electrode layer public electrode connecting portion 304, be located at the second electrode lay 305 and the first electrode layer 307 on the superiors' insulation course 303, described the second electrode lay 305 is connected conduction with described grid layer public electrode connecting portion 302 respectively by conductive via 306 and is connected with source-drain electrode layer public electrode connecting portion, described the first electrode layer 307 has laterally projecting outer rim 307a beyond the signal output layer aspect of top, and described the second electrode lay 305 is connected with the outer rim 307a conduction of described the first electrode layer 307 by peripheral conductive via 308.
Be that with embodiment one difference as shown in Figure 6, the first electrode layer 307 described in the present embodiment is positioned at described source-drain electrode layer public electrode connecting portion 304 belows.
In the present embodiment, even the second electrode lay 305 partly produces bad with source-drain electrode layer public electrode connecting portion 304 direct-connected conductive vias, the second electrode lay 305 also can be electrically connected with described source-drain electrode layer public electrode connecting portion 304 by peripheral conductive via 308 and the first electrode layer 307, therefore, can prevent that the general green picture quality that waits that loose contact causes is bad.
Certainly, except the structure shown in embodiment one and the embodiment two, other uses the first electrode layer to design by two layer signal transport layers being overlapped and can being suitable for all structures that the second electrode lay connects as long as have living space.
Embodiment three:
Present embodiment has been put down in writing a kind of display device, comprises display panel, and described display panel comprises embodiment one described panel periphery syndeton.
In the present embodiment, described display panel is the liquid crystal panel of ADS pattern, and described the first electrode layer is the common electrode layer that is positioned at described grid layer public electrode connecting portion below.
Embodiment four:
Present embodiment has been put down in writing a kind of display device, comprises display panel, and described display panel comprises embodiment two described panel periphery syndetons.
In the present embodiment, described display panel is the liquid crystal panel of HADS pattern, and described the first electrode layer is the pixel electrode layer that is positioned at described source-drain electrode layer public electrode connecting portion below.
Can find out by embodiment three and embodiment four, the utility model is particularly suitable for being applied on the TFT-LCD of ADS and HADS pattern, because in the peripheral syndeton of the TFT-LCD of ADS pattern, originally just be arranged with electrode layer as public electrode at grid layer public electrode connecting portion, in the peripheral syndeton of the TFT-LCD of HADS pattern, also be provided with electrode layer as pixel electrode under the original source-drain electrode layer public electrode connecting portion, therefore for the utility model, adding does not need to append technological process man-hour and just can form described the first electrode layer.
Above embodiment only is used for explanation the utility model; and be not limitation of the utility model; the those of ordinary skill in relevant technologies field; in the situation that does not break away from spirit and scope of the present utility model; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present utility model, and scope of patent protection of the present utility model should be defined by the claims.
Claims (6)
1. panel periphery syndeton, comprise the two layer signal output layers that are formed on the substrate, be positioned at the insulation course on every layer signal output layer and be located at the second electrode lay on the superiors' insulation course, described the second electrode lay is connected with described two layer signal output layers conduction respectively by conductive via, it is characterized in that, described panel periphery syndeton also comprises the first electrode layer that is positioned at the described signal output layer of one deck below, described the first electrode layer has laterally projecting outer rim beyond the signal output layer aspect of top, and described the second electrode lay is connected with the outer rim conduction of described the first electrode layer by peripheral conductive via.
2. panel periphery syndeton as claimed in claim 1 is characterized in that, described two layer signal output layers comprise grid layer public electrode connecting portion and source-drain electrode layer public electrode connecting portion.
3. panel periphery syndeton as claimed in claim 2 is characterized in that, described the first electrode layer is positioned at described grid layer public electrode connecting portion below.
4. panel periphery syndeton as claimed in claim 2 is characterized in that, described the first electrode layer is positioned at described source-drain electrode layer public electrode connecting portion below.
5. such as each described panel periphery syndeton among the claim 1-4, it is characterized in that described the first electrode layer and the second electrode lay are the indium tin oxide semiconductor film.
6. a display device comprises display panel, it is characterized in that, described display panel comprises the arbitrary described panel periphery syndeton of claim 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220456513.XU CN202771136U (en) | 2012-09-07 | 2012-09-07 | Panel peripheral connecting structure and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220456513.XU CN202771136U (en) | 2012-09-07 | 2012-09-07 | Panel peripheral connecting structure and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202771136U true CN202771136U (en) | 2013-03-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201220456513.XU Expired - Lifetime CN202771136U (en) | 2012-09-07 | 2012-09-07 | Panel peripheral connecting structure and display device |
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| CN (1) | CN202771136U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102830563A (en) * | 2012-09-07 | 2012-12-19 | 京东方科技集团股份有限公司 | Panel periphery connection structure and display device |
| CN104460156A (en) * | 2014-10-07 | 2015-03-25 | 友达光电股份有限公司 | Display panel and method for manufacturing the same |
-
2012
- 2012-09-07 CN CN201220456513.XU patent/CN202771136U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102830563A (en) * | 2012-09-07 | 2012-12-19 | 京东方科技集团股份有限公司 | Panel periphery connection structure and display device |
| CN102830563B (en) * | 2012-09-07 | 2014-11-26 | 京东方科技集团股份有限公司 | Panel periphery connection structure and display device |
| CN104460156A (en) * | 2014-10-07 | 2015-03-25 | 友达光电股份有限公司 | Display panel and method for manufacturing the same |
| CN104460156B (en) * | 2014-10-07 | 2017-07-07 | 友达光电股份有限公司 | Display panel and method for manufacturing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130306 |