JP4797519B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a defective mark forming method thereof, and more particularly to a semiconductor device that forms a defective mark after measuring electrical characteristics and a defective mark forming method thereof.

  In the manufacture of a semiconductor device, after processing on a wafer is completed, the wafer is separated into chips and an assembly process is performed. Before the wafer is separated into chips, electrical measurements of individual chips are performed. This electrical measurement is performed by a wafer tester, and a defect mark is formed on the surface of the chip that does not satisfy the standard.

  The defect mark is formed by an inker attached to the wafer tester. When forming a defective mark, the core provided inside the inker is moved up and down. When the middle core reaches the lowermost end, an ink ball is formed at the tip, which adheres to the surface of the defective chip. In this way, a defect mark is formed (see, for example, Patent Document 1).

JP-A-7-94557

  The size of the defective mark depends on the stage height variation of the wafer tester, the wafer thickness variation, various parameters of the inker apparatus, the ink remaining amount of the inker, the ink drying time, and the like. For this reason, it is not easy to form defect marks with good reproducibility for a long time.

  In the defective mark formation described above, an excessive amount of ink may be supplied to the surface of the defective chip. Then, the ink may overflow from the chip surface and flow out to the adjacent chip. If it does so, there existed a problem that the visibility which distinguishes a non-defective chip and a defective chip deteriorates.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to improve the visibility for distinguishing a good chip from a defective chip in forming a defective mark after electrical measurement of a wafer.

The method of manufacturing a semiconductor device according to the present invention, on the dicing line of the surface of the wafer having a plurality of semiconductor chips, so as to surround the outer periphery of the semiconductor chip, a high convex realm from the surface of the semiconductor chip forming, electrically measuring the plurality of semiconductor chips, resulting in adhering the ink to the surface of the semiconductor chip judged not to satisfy the standard, see containing and forming a defective mark, convex This region is formed in contact with the side surface of the semiconductor chip, and no convex region is formed at the end of the side surface of the semiconductor chip .

  According to the present invention, in forming a defective mark after electrical measurement of a wafer, it is possible to improve visibility for distinguishing between a non-defective chip and a defective chip.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment 1 FIG.
A semiconductor device according to this embodiment will be described. The semiconductor device described here is one in which processing on a wafer is completed and a plurality of semiconductor chips are formed on the wafer. A perspective view of the wafer surface is shown in FIG. A semiconductor chip 2 is formed on the surface of the wafer 1. A plurality of semiconductor chips are formed adjacent to this. Each semiconductor chip is provided with a circuit element (here, mainly the semiconductor chip 2 will be described, and a chip adjacent to the semiconductor chip 2 will be simplified in description and illustration).
A dicing line 3 having a width of several tens of μm is provided between adjacent semiconductor chips. A plating frame 4 having a width of several μm and a height of several μm is provided at the center along the dicing line 3. The surface of the plating frame 4 is higher than the surface of the semiconductor chip 2.
That is, a convex region higher than the surface of the semiconductor chip 2 is provided on the dicing line 3 on the surface of the wafer 1 so as to surround the outer periphery of the semiconductor chip 2. This area is formed after the processing on the wafer is completed.

Next, a defect mark forming method for the semiconductor device according to the present embodiment will be described.
After the processing of the semiconductor device on the wafer is completed, electrical measurement is performed in the wafer state. The wafer is placed on a stage of a wafer tester (not shown), and electrical measurement of each chip is performed. As a result, a semiconductor chip that satisfies the standard is determined to be a non-defective chip, and a semiconductor chip that does not satisfy the standard is determined to be a defective chip. Here, it is assumed that the semiconductor chip 2 shown in FIG. 1 is determined to be a defective chip.

Next, after the electrical measurement described above, a defect mark is formed on the surface of the defective chip. This is performed by an inker attached to the wafer tester. FIG. 2A shows a schematic diagram of the inker. The inker includes an inker main body 5 (portion indicated by a dotted line), an ink fountain 6 connected to the inker, an inker nozzle 7 and the like. Ink fountain 6 stores ink for forming defective marks. An inker nozzle 7 is provided below the ink fountain 6. An opening for discharging ink is provided at the tip.
FIG. 2B shows an enlarged view of the vicinity of the lower portion of the ink fountain 6. A core 8 is provided through the inside of the ink fountain 6 and toward the tip of the inker nozzle 7. When forming a defective mark, the inner core 8 is stroked along the inker nozzle 7 on the surface of the defective chip. When the core 8 reaches the lowermost end, an ink ball 9 is formed at the tip of the core 8. This is adhered to the surface of the semiconductor chip 2 to form a defective mark.

As a result, a defect mark 10 is formed on the surface of the semiconductor chip 2 as shown in FIG.
As described above, the convex plating frame 4 higher than the surface of the semiconductor chip 2 is provided so as to surround the outer periphery of the semiconductor chip 2. For this reason, even when a large amount of ink is supplied to the surface of the semiconductor chip 2, the ink spreads over the entire surface of the chip. Thereby, it is possible to prevent the ink from flowing out to the adjacent chip of the semiconductor chip 2. Therefore, it is possible to improve the visibility for distinguishing good chips from defective chips.
In addition, since the ink spreads over the entire surface of the chip, the contrast with the chip to which no ink is attached increases. Thereby, the visibility of a non-defective chip and a defective chip can be improved.

  Further, the plating frame 4 is provided at the center of the dicing line 3. For this reason, the plating frame 4 is removed when dicing. Thereby, when assembling the semiconductor chip into the package, it is possible to prevent the wire wiring from coming into contact with the plating frame and causing a short circuit failure.

Embodiment 2. FIG.
A semiconductor device according to this embodiment will be described. Here, the points different from the first embodiment will be mainly described.
FIG. 4 is a perspective view of the semiconductor device according to the present embodiment. A plating frame 4 a is provided along the dicing line 3 so as to contact the side surface of the semiconductor chip 2. That is, a convex region is provided on the surface of the wafer 1 so as to be in contact with the side surface of the semiconductor chip 2. This is formed after the processing on the wafer is completed.
With the above structure, when the defective mark 10 is formed, even when a large amount of ink is supplied to the surface of the semiconductor chip 2, the ink is prevented from flowing out of the plating frame 4a. Can do.

  The plating frame is provided so as to contact the side surface of the semiconductor chip 2. For this reason, the plating frame 4 a is connected to the side surface of the semiconductor chip 2 even after the wafer 1 is diced. Thereby, the mechanical strength after being separated into chips can be improved. That is, the plating frame 4a can be used as a reinforcing frame for preventing chip cracking after dicing.

Furthermore, the plating frame 4a has a structure in which the four corners of the semiconductor chip 2 are cut. That is, no convex region is provided at the end of the semiconductor chip 2.
With the above structure, deformation / cracking due to chip warpage can be suppressed in the semiconductor chip assembly process.

Further, a concave region 11 having a depth of several μm is provided on the dicing line 3 so as to contact the end of the semiconductor chip 2. That is, the concave region 11 is provided on the surface of the wafer 1 so as to contact a portion where the plating frame 4a is not provided.
With the above structure, even when the ink flows out from the end portion of the semiconductor chip 2 in forming the defective mark, the concave region 11 becomes the ink tray. Thereby, it is possible to effectively suppress the outflow of ink to the adjacent chip.
Other configurations and defective mark forming methods are the same as those in the first embodiment, and thus description thereof is omitted.

Embodiment 3 FIG.
A semiconductor device according to this embodiment will be described. Here, the points different from the first and second embodiments will be mainly described.
FIG. 5 is a perspective view of the semiconductor device according to the present embodiment. A first groove 12 is provided on the surface of the semiconductor chip 2 in the vicinity of the end of the outer periphery thereof. This groove is provided so as to surround a region inside the outer peripheral portion of the semiconductor chip 2.
The dicing line 3 is provided such that the surface height is lower than the surface of the semiconductor chip 2. A second groove 13 having a width of several μm and a depth of several μm is provided along the dicing line 3 at the center thereof. That is, a concave region lower than the surface of the semiconductor chip 2 is provided on the surface of the wafer 1 having a plurality of semiconductor chips so as to surround the semiconductor chip 2. At this time, the top surface of the semiconductor chip 2 is the highest, and then the bottom surface of the first groove 12, the surface of the dicing line 3, and the bottom surface of the second groove 13 are formed in this order. Further, the first groove 12 and the second groove 13 are formed after the processing on the wafer is finished.

  With the above structure, when a large amount of ink is supplied to the surface of a defective chip in forming a defective mark, the ink flows into the first groove 12. Thereby, it is possible to prevent the ink from flowing out to the adjacent chip of the semiconductor chip 2.

  Further, when a larger amount of ink is supplied to the surface of the defective chip, even if the ink overflows from the first groove 12, the ink flows to the surface of the dicing line 3 and further flows into the second groove 13. Thereby, it is possible to more effectively suppress the ink from flowing into the adjacent chip than in the first and second embodiments.

In the third embodiment, the dicing line 3 and the second groove 13 are provided so as to be lower than the surface of the semiconductor chip 2. However, as shown in the first embodiment, a plating frame higher than the surface of the semiconductor chip 2 may be formed along the dicing line 3.
Even with such a structure, when ink overflows from the first groove 12, it is possible to prevent the ink from flowing out to the adjacent chip.
Other configurations and defective mark forming methods are the same as those in the first embodiment, and thus description thereof is omitted.

Embodiment 4 FIG.
A semiconductor device according to this embodiment will be described. Here, it demonstrates centering on a different point from Embodiment 1-3.
FIG. 6 is a perspective view of the semiconductor device according to the present embodiment. Here, only the semiconductor chip 2 is shown, and illustration of a semiconductor chip and a dicing line adjacent thereto is omitted.
A hydrophilic region 14 is provided on the surface of the semiconductor chip 2. The surface of this region is coated with a highly hydrophilic material. A water repellent region 15 is provided on the surface of the semiconductor chip 2 so as to surround the hydrophilic region 14. The surface of this region is coated with a material having high water repellency.
That is, a hydrophilic region 14 is provided in a region inside the surface of the semiconductor chip 2, and a region having a relatively higher water repellency than the hydrophilic region 14 is provided on the outer periphery of the surface of the semiconductor chip 2 so as to surround the region. (Water-repellent region 15) was provided. These regions are formed after the processing on the wafer is completed.

With the above structure, a certain amount of ink is absorbed by the hydrophilic region 14 even when a large amount of ink is supplied to the surface of the semiconductor chip 2 when forming a defective mark. Thereby, it can suppress that an ink spreads to an adjacent chip. Further, even if the ink spreads in the water repellent area 15, the ink is bounced in this area and returned to the hydrophilic area 14. Accordingly, ink can be prevented from flowing out to the adjacent chip of the semiconductor chip 2.
Other configurations and defective mark forming methods are the same as those in the first embodiment, and thus description thereof is omitted.

FIG. 3 illustrates a semiconductor device according to Embodiment 1; The figure which shows the structure of an inker. FIG. 3 illustrates a semiconductor device according to Embodiment 1; FIG. 6 illustrates a semiconductor device according to Embodiment 2; FIG. 6 illustrates a semiconductor device according to Embodiment 3; FIG. 6 shows a semiconductor device according to Embodiment 4;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer, 2 Semiconductor chip, 3 Dicing line, 4, 4a Plating frame, 5 Inker body, 6 Ink fountain, 7 Inker nozzle, 8 Core, 10 Defect mark, 11 Concave area, 12 1st groove | channel, 13 2nd Groove, 14 hydrophilic region, 15 water-repellent region.

Claims (3)

On the dicing line of the surface of the wafer having a plurality of semiconductor chips, so as to surround the outer periphery of the semiconductor chip, and forming a high convex realm from the surface of the semiconductor chip,
Electrically measuring the plurality of semiconductor chips, and as a result, attaching ink to the surface of the semiconductor chip determined not to meet the standard, and forming a defective mark;
Only including,
Forming the convex region in contact with a side surface of the semiconductor chip;
A method of manufacturing a semiconductor device , wherein the convex region is not formed at an end of a side surface of the semiconductor chip . 2. The method of manufacturing a semiconductor device according to claim 1 , wherein a concave region lower than the surface of the semiconductor chip is formed on the surface of the wafer so as to contact a portion where the convex region is not provided. . A convex region higher than the surface of the semiconductor chip or a concave region lower than the surface of the semiconductor chip so as to surround the outer peripheral portion of the semiconductor chip on a dicing line on the surface of the wafer having a plurality of semiconductor chips. Forming a step;
Electrically measuring the plurality of semiconductor chips, and as a result, attaching ink to the surface of the semiconductor chip determined not to meet the standard, and forming a defective mark;
Including
Wherein on the surface of the semiconductor chip, said to surround the area inside the outer peripheral portion of the semiconductor chip, a manufacturing method of a semi-conductor device you and forming a concave area.

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