JP4796359B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize the miniatulization and low cost of a semiconductor device including an H bridge circuit. <P>SOLUTION: A PMOS transistor MP1 and an NMOS transistor MN1 are mounted on a die pad DP1 integrated with an external lead DD1, and a PMOS transistor MP2 and an NMOS transistor MN2 are mounted on a die pad DP2 integrated with an external lead DD2, for example. Gate terminals G of the MP1, MP2, MN1, and MN2 are respectively connected with external leads GG1, GG2, GG3, and GG4, and source terminals S of the MP1 and MP2 are connected in common with an external lead SS1, and source terminals S of the MP1 and MP2 are connected in common with an external lead SS1, and further source terminals S of the MN1 and MN2 are connected in common with an external lead SS2. The H bridge circuit is hereby realized with only one package, and since pad disposition and signal disposition on the surface of each MOS transistor are point symmetrical, an assembling cost is realized. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including a bridge circuit composed of power transistors.

  For example, a so-called H-bridge circuit constituted by two PMOS transistors and two NMOS transistors is widely known. Such H-bridge circuits are used in a wide range of fields. Typical applications include drive circuits for various motors included in automobiles and printers, motors for hard disk drives, and drive circuits for magnetic heads. .

  For example, a power transistor such as a power MOSFET (Metal Oxide Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is used in the H-bridge circuit as described above. Therefore, the entity of the H-bridge circuit is realized, for example, by wiring discrete transistors on a dielectric substrate. For example, a mounting example of a commonly used H bridge circuit is shown below.

  FIG. 7 is a circuit diagram illustrating an example of an H-bridge circuit. FIG. 8 is a top view showing a mounting example of an H bridge circuit included in a conventional semiconductor device studied as a premise of the present invention. The H bridge circuit shown in FIG. 7 includes, for example, two PMOS transistors MP1 and MP2 and two NMOS transistors MN1 and MN2. The sources of MP1 and MP2 are connected to the common node SS1, and the sources of MN1 and MN2 are connected to the common node SS2. The drain of MP1 and the drain of MN1 are connected to a common node DD1, and the drain of MP2 and the drain of MN2 are connected to a common node DD2. Note that the gate nodes of MP1, MP2, MN1, and MN2 are GG1, GG2, GG3, and GG4, respectively.

  And the H bridge circuit of FIG. 7 is implement | achieved by the mounting system as shown, for example in FIG. In FIG. 8, the package device Pch_PKG including the two PMOS transistors MP1 and MP2 in FIG. 7 and the package device Nch_PKG including the two NMOS transistors MN1 and MN2 in FIG. . Each of the MOS transistors MP1, MP2, MN1, and MN2 is, for example, a vertical power MOS transistor having a source terminal and a gate terminal on the front surface and a drain terminal on the back surface.

  In the package device Pch_PKG, the source terminal and gate terminal of MP1 are wire-bonded to the external leads S1 and G1, respectively, and the source terminal and gate terminal of MP2 are wire-bonded to the external leads S2 and G2, respectively. The drain terminal of MP1 is connected to two external leads D1 via a die pad, and the drain terminal of MP2 is connected to two external leads D2 via a die pad. Thus, Pch_PKG has a configuration including eight external leads.

  On the other hand, the package device Nch_PKG is also wired in the same manner as Pch_PKG, and has a configuration including eight external leads S1, G1, S2, G2, D1 (two), D2 (two). 7 is formed by connecting external leads S1 and S2 of Pch_PKG on a dielectric substrate or the like, and node SS2 of FIG. 7 is connected by connecting external leads S1 and S2 of Nch_PKG. It is formed. Further, the two external leads D1 of Pch_PKG and the two external leads D1 of Nch_PKG are connected to form the node DD1 of FIG. 7, and the two external leads D2 of Pch_PKG and the two external leads of Nch_PKG are formed. The node DD2 of FIG. 7 is formed by connecting D2.

  In addition to the one shown in FIG. 8, the H-bridge circuit mounting method is, for example, a method in which four package devices corresponding to four transistors are wired on a dielectric substrate, or a transistor module. There is something that uses. In the transistor module, for example, four transistors are molded in a single row, and in some cases, the sources of two transistors of the same channel type are bonded to a common external lead, and 10 or 12 external leads in a single row are connected. It has the shape that it has. If these 10 or 12 external leads are wired on a dielectric substrate, an H-bridge circuit can be realized.

  As described above, the conventional H-bridge circuit requires a plurality of package devices or requires wiring on a dielectric substrate or the like, so that it is difficult to reduce the size. Under such circumstances, the H-bridge circuit has recently been used as an antenna drive circuit in a keyless entry system of an automobile, for example, and in such a case, downsizing is particularly required. Of course, it is also necessary to reduce manufacturing costs and mounting costs.

  Accordingly, an object of the present invention is to realize miniaturization of a semiconductor device including an H bridge circuit. Another object of the present invention is to realize cost reduction of a semiconductor device including a plurality of semiconductor chips in a package.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device according to the present invention is configured by one package having eight or more (preferably eight) external leads. The package includes at least four power transistors each realized by an individual semiconductor chip, and is connected using bonding wires or the like in the package, thereby realizing an H-bridge circuit. ing. That is, a total of four terminals that are control input terminals of the four power transistors and connection terminals between the four power transistors are connected to the eight external leads, respectively. As a result, it is possible to reduce the size of the H-bridge circuit composed of power transistors. Further, it is possible to reduce the mounting cost when the H bridge circuit is mounted and used on the system, and to reduce each manufacturing cost necessary for realizing the H bridge circuit.

  In addition, such a semiconductor device has, for example, a configuration in which four vertical power transistors having terminals on the back surface of a chip and two die pads are used, and two vertical power transistors are mounted on each die pad. It is good to. As a result, one end of the two power transistors can be connected in common on each die pad, so that the commonly connected die pad can be connected to an external lead, or a configuration in which the die pad and the external lead are integrated can be used. For example, the number of bonding wires on the chip surface can be reduced. As a result, the connection assignment between the terminals on the semiconductor chip and the external leads and the wire bonding process thereof are facilitated, and the H bridge circuit can be efficiently realized with one package.

  Further, in such a semiconductor chip, the pad arrangement and the signal arrangement provided on the surface thereof are preferably point-symmetric with respect to the center point of the semiconductor chip when viewed from the surface. In other words, the semiconductor chip configuration may be such that the pad arrangement and the signal arrangement do not change even if the semiconductor chip is rotated 180 degrees. This eliminates the cost loss associated with the semiconductor chip orientation adjustment in the die bonding process within the assembly process, and the signal pads are provided in a point-symmetric relationship, so flexibility in selecting external leads to be connected. It also has.

  The merit of using such a point-symmetric semiconductor chip is not limited to the H-bridge circuit as described above, but a plurality of semiconductor chips are mounted in one package, and each semiconductor chip is bonded by wire bonding or the like. The present invention can be widely applied to semiconductor devices in which common wiring between terminals is performed.

  To briefly explain the effects obtained by typical inventions among inventions disclosed in this application, it is possible to reduce the size or cost of a semiconductor device including an H-bridge circuit. In addition, the cost of a semiconductor device including a plurality of semiconductor chips in the package can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1A and 1B are outline views showing a configuration example of a semiconductor device according to an embodiment of the present invention, where FIG. 1A is a side view and FIG. 1B is a top view. As shown in FIGS. 1A and 1B, the semiconductor device of the present embodiment has a package shape called SOP (Small Outline Package), for example, and has eight external leads. The SOP is a typical package shape in the case where a plurality of power transistors are included inside, but the semiconductor device of the present embodiment is not particularly limited to this, and both sides are viewed from the top as in the SOP. It suffices to have a package shape with external leads.

  2 is a top view showing an example of the internal configuration of the semiconductor device of FIG. 1. FIGS. 2A and 2B show configurations in which the signal arrangement of the external leads is different. The semiconductor device shown in FIGS. 2A and 2B has a configuration in which four power transistors are mounted in one package and eight external leads are provided. The four power transistors are the vertical PMOS transistors MP1 (first power transistor) and MP2 (second power transistor) and the vertical NMOS transistors MN1 (third power transistor) and MN2 (fourth) described above with reference to FIG. Power transistor). Then, by connecting each terminal of these MOS transistors MP1, MP2, MN1, and MN2 to external leads, the H bridge circuit shown in FIG. 7 is realized in one package.

  In FIG. 2A, four external leads are provided on each of the upper side and the lower side when the package is viewed from above. The upper four external leads are GG3, SS2, GG4, and DD2 in order from the left corresponding to each node in FIG. The lower four external leads are DD1, GG1, SS1, and GG2 in order from the left corresponding to each node in FIG. MN1 and MP1 are die-bonded by solder or the like on a die pad (tab, first die pad) DP1 integrated (or connected) with the external lead DD1, respectively. MP1 is mounted side by side. MN2 and MP2 are each die-bonded on the die pad (second die pad) DP2 integrated with the external lead DD2 by solder or the like, and MN2 is mounted on the upper side and MP2 is mounted on the lower side as viewed from above. DP1 and DP2 are arranged such that DP1 is arranged on the left side and DP2 is arranged on the right side as viewed from above.

  MP1 has a gate terminal (control input terminal) connected to an external lead GG1 (first external lead) by a bonding wire BW, and a source terminal (first terminal) connected to an external lead SS1 (fifth external lead) by a BW. Is done. MP2 has a gate terminal connected to the external lead GG2 (second external lead) by a bonding wire BW, and a source terminal connected to the external lead SS1 common to the source terminal of MP1 by BW. On the other hand, the gate terminal of MN1 is connected to the external lead GG3 (third external lead) by the bonding wire BW, and the source terminal is connected to the external lead SS2 (sixth external lead) by BW. The gate terminal of MN2 is connected to the external lead GG4 (fourth external lead) by the bonding wire BW, and the source terminal is connected to the external lead SS2 common to the source terminal of MN1 by BW.

  As described above, the drain terminals (second terminals) of MN1 and MP1 are connected to the external lead DD1 (seventh external lead) through the die pad DP1. Similarly, the drain terminals of MN2 and MP2 are connected to the external lead DD2 (eighth external lead) via the die pad DP2. As can be seen from FIG. 2A, the bonding wires BW do not intersect with each other, and a short length is sufficient. Therefore, the wire bonding process can be performed easily or efficiently, and the performance of the semiconductor device is not deteriorated due to the bonding wire.

  On the other hand, the semiconductor device of FIG. 2B has four external leads on the upper side and the lower side, respectively, as in FIG. 2A, but the above-described die pad compared to FIG. The shapes of DP1 and DP2 are slightly different, and accordingly, the signal arrangement of the external leads is different. In FIG. 2B, the upper four external leads are GG3, SS2, DD2, GG4 in order from the left, and the lower four external leads are GG1, DD1, SS1, It is GG2.

  That is, in FIGS. 2A and 2B, the external leads GG4 and DD2 are interchanged, and the external leads DD1 and GG1 are interchanged. This is such that DP1 and DP2 in FIG. 2 (a) are integrated with the left and right external leads, whereas DP1 and DP2 in FIG. This is because the shape is integrated with the second external lead from the right. These two shapes are not particularly different in terms of effects, and any of them may be used as necessary. In FIG. 2B, the configuration other than this is the same as in FIG.

  As described above, when a semiconductor device as shown in FIGS. 2A and 2B is used, a reduction in size can be realized as compared with the configuration as shown in FIG. In addition, since the number of packages may be half, the manufacturing cost and the mounting cost can be reduced.

  3 is a top view showing another example of the internal configuration of the semiconductor device of FIG. 1. FIGS. 3A and 3B show configurations in which the signal arrangement of the external leads is different. The semiconductor device shown in FIGS. 3A and 3B has a configuration in which four power transistors are mounted in one package and eight external leads are provided. The four power transistors are MOS transistors MP1, MP2, MN1, and MN2 having different terminal arrangements from the vertical MOS transistors MP1, MP2, MN1, and MN2 described above with reference to FIG.

  That is, in FIG. 8, when the MOS transistor is viewed from above, a source terminal is provided on one of the right side and the left side, and a gate terminal is provided on the other side. On the other hand, the MOS transistors MP1, MP2, MN1, and MN2 in FIGS. 3A and 3B have a gate terminal at the center and source terminals on the right and left sides as viewed from above. It has a configuration. In other words, even when the MOS transistor is viewed from the top surface and rotated by 180 degrees with respect to the center point, the same terminal (pad) arrangement and signal arrangement are obtained. Then, by connecting each terminal of such MOS transistors MP1, MP2, MN1, and MN2 to an external lead, the H bridge circuit shown in FIG. 7 is realized in one package.

  In FIG. 3A, four external leads are provided on each of the upper side and the lower side when the package is viewed from above. The upper four external leads are GG3, SS2, GG4, and DD2 in order from the left. The lower four external leads are DD1, GG1, SS1, and GG2 in order from the left. MN1 and MP1 are die-bonded by solder or the like on a die pad DP1 integrated (or connected) with an external lead DD1, and MN1 is mounted on the upper side and MP1 is mounted on the lower side as viewed from above. . MN2 and MP2 are each die-bonded on the die pad DP2 integrated with the external lead DD2 by solder or the like, and MN2 is mounted on the upper side and MP2 is mounted on the lower side as viewed from above. DP1 and DP2 are arranged such that DP1 is arranged on the left side and DP2 is arranged on the right side as viewed from above.

  In MP1, the gate terminal is connected to the external lead GG1 by a bonding wire BW, and the source terminal on the right side as viewed from above is connected to the external lead SS1 by BW. The gate terminal of MP2 is connected to the external lead GG2 by a bonding wire BW, and the source terminal on the left side as viewed from above is connected to the external lead SS1 common to the source terminal of MP1 by BW. On the other hand, the gate terminal of MN1 is connected to the external lead GG3 by the bonding wire BW, and the source terminal on the right side as viewed from above is connected to the external lead SS2 by BW. The gate terminal of MN2 is connected to the external lead GG4 by a bonding wire BW, and the source terminal on the left side as viewed from above is connected to the external lead SS2 common to the source terminal of MN1 by BW.

  The drain terminals of MN1 and MP1 are connected to the external lead DD1 via the die pad DP1 as described above. Similarly, the drain terminals of MN2 and MP2 are connected to the external lead DD2 via the die pad DP2. As can be seen from FIG. 3A, the bonding wires BW do not intersect with each other, and a short length is sufficient. Therefore, the wire bonding process can be performed easily or efficiently, and the performance of the semiconductor device is not deteriorated due to the bonding wire.

  On the other hand, the semiconductor device of FIG. 3B includes four external leads on the upper side and the lower side, respectively, as in FIG. 3A, but the above-described die pad as compared with FIG. The shapes of DP1 and DP2 are slightly different, and accordingly, the signal arrangement of the external leads is different. In FIG. 3B, the upper four external leads are GG3, SS2, DD2, GG4 in order from the left, and the lower four external leads are GG1, DD1, SS1, It is GG2.

  That is, in FIGS. 3A and 3B, the external leads GG4 and DD2 are interchanged, and the external leads DD1 and GG1 are interchanged. This is such that DP1 and DP2 in FIG. 3A are integrated with the left and right external leads, whereas DP1 and DP2 in FIG. This is because the shape is integrated with the second external lead from the right. These two shapes are not particularly different in terms of effects, and any of them may be used as necessary. In FIG. 3B, the configuration other than this is the same as that in FIG.

  As described above, when a semiconductor device as shown in FIGS. 3A and 3B is used, a reduction in size can be realized as compared with the configuration shown in FIG. In addition, since the number of packages may be half, the manufacturing cost and the mounting cost can be reduced. Furthermore, as compared with the configuration example of FIGS. 2A and 2B, it is possible to further reduce the manufacturing cost as described below.

  4 is a flowchart showing an example of an assembly process in the semiconductor device of FIGS. 2 and 3, wherein (a) is a flowchart of the semiconductor device of FIG. 2, and (b) is a flowchart of the semiconductor device of FIG. FIG. In FIG. 4A, first, a semiconductor wafer is diced and separated into semiconductor chips. In the semiconductor device of FIG. 2, for example, a semiconductor wafer on which PMOS transistors MP1 and MP2 that are respectively the same semiconductor chip are formed and a semiconductor wafer on which NMOS transistors MN1 and MN2 that are respectively the same semiconductor chip are formed are used. Each of these semiconductor wafers is diced to obtain a PMOS transistor semiconductor chip and an NMOS transistor semiconductor chip.

  Next, in S400a, the semiconductor chip diced on the die pad is die-bonded using a die bonding apparatus. At this time, in the semiconductor device of FIG. 2, for example, four die bonding steps are required by four die bonding apparatuses. That is, in the semiconductor device of FIG. 2, the chip mounting directions of MP1 and MP2 are different by 180 degrees, and MN1 and MN2 are similarly different. Therefore, in practice, two semiconductor wafers of PMOS transistors are used, and one semiconductor wafer is installed in a form rotated by 180 degrees. Then, die bonding is performed individually by making each semiconductor wafer correspond to a die bonding apparatus. Similarly, two semiconductor wafers of NMOS transistors are used, and die bonding is performed individually by making each semiconductor wafer correspond to a die bonding apparatus.

  Thus, after the MOS transistors MP1, MP2, MN1, and MN2 in FIG. 2 are individually die-bonded, the terminals of the MOS transistor and the external leads are wire-bonded with the signal assignment as described in FIG. The Subsequently, the die pad on which the semiconductor chip is mounted and a part of the lead are sealed with the package resin, and the external lead serving as the lead outside the package resin is cut and molded. Next, the product is packed and shipped through an inspection process such as sorting.

  On the other hand, in FIG. 4B, first, the semiconductor wafer is diced as in FIG. 4A, and then in S400b, die bonding is performed by a die bonding apparatus. At this time, when the semiconductor device of FIG. 3 is used, unlike the case of FIG. 2, for example, two die bonding steps by two die bonding apparatuses are sufficient.

  That is, in the semiconductor device of FIG. 3, since the terminals (pads) of the MOS transistors are point-symmetric as described above, the MP1 and MP2 chip mounting directions are the same, and MN1 and MN2 are also the same. . Therefore, in practice, one semiconductor wafer for PMOS transistors and one semiconductor wafer for NMOS transistors are used, and a die bonding apparatus is associated with each semiconductor wafer. Then, MP1 and MP2 of FIG. 3 are continuously die-bonded by one die bonding apparatus, and MN1 and MN2 of FIG. 3 are continuously die-bonded by the other die bonding apparatus.

  In this way, after the MOS transistors MP1, MP2, MN1, and MN2 in FIG. 3 are die-bonded, the terminals of the MOS transistor and the external leads are wire-bonded with the signal assignment as described in FIG. Subsequently, the die pad on which the semiconductor chip is mounted and a part of the lead are sealed with the package resin, and the external lead serving as the lead outside the package resin is cut and molded. Next, the product is packed and shipped through an inspection process such as sorting.

  As described above, by using the semiconductor device of FIG. 3 and performing the assembly process as shown in FIG. 4B, the time required for the die bonding process is shortened compared to the case of using the semiconductor device of FIG. In addition, the number of die bonding apparatuses required can be reduced. Thereby, a reduction in manufacturing cost can be realized.

  This effect is not limited to the semiconductor device of FIG. For example, a semiconductor device in which a plurality of semiconductor chips are mounted in one package, and the pad arrangement and signal arrangement of all or most of the semiconductor chips are pointed with respect to the center point when each semiconductor chip is viewed from the top surface. A similar effect can be obtained if the semiconductor device has a symmetrical relationship. That is, since it is point-symmetric, there is no cost loss associated with the adjustment of the direction of the semiconductor chip, and since there is a signal pad in a point-symmetric relationship, it has flexibility in selecting external leads to be connected. .

  An example of such a semiconductor chip is a discrete transistor element having a small number of signal pads, such as the vertical MOS transistor of FIG. For example, in the case of a bipolar transistor, an emitter pad may be provided at the center of the chip surface, a base pad on both sides thereof, and a collector pad on the back surface of the chip.

  5A and 5B are top views showing an example of a configuration in which the semiconductor device of FIGS. 2A and 3A is applied. FIG. 5A is an application example of FIG. 2A and FIG. This is an application example of (a). The semiconductor device shown in FIGS. 5A and 5B has, for example, an SOP 16-pin package shape. The configuration example of FIG. 5 (a) has two configurations of FIG. 2 (a) on the left and right, and the configuration example of FIG. 5 (b) has the configuration of FIG. 3 (a) on the left and right. Two are provided. Therefore, each configuration example has a configuration in which two H-bridge circuits in FIG. 7 are provided in one package.

  For example, when two H-bridge circuits are used in a certain system, the use of the semiconductor device in FIG. 5 can reduce the size of the system, the mounting cost, and the manufacturing cost of the semiconductor device. I can plan. However, since eight semiconductor chips are mounted in one package, in some cases, the yield of the semiconductor device is lowered, and there is a concern that the manufacturing cost of the semiconductor device is increased accordingly.

6 is a cross-sectional view showing an example of a main part of the semiconductor chip in the semiconductor device of FIG. 3, wherein (a) is a cross-sectional view of an NMOS transistor, and (b) is a cross-sectional view of the PMOS transistor. is there. The vertical power NMOS transistors MN1 and MN2 shown in FIG. 6A include a semiconductor substrate 60a made of, for example, n ⁺ -type silicon (Si) single crystal, and a drain electrode (drain terminal) D is formed on the back surface thereof. Is formed. The drain electrode D is formed by depositing a metal such as gold (Au), for example, and is connected to the die pad as described above. On the other hand, an epitaxial layer 61a made of, for example, n ⁻ type silicon single crystal is formed on the main surface of the semiconductor substrate 60a. In this epitaxial layer 61a, a p ⁻ type semiconductor region 62a and an n ⁺ type semiconductor region 64a thereon are formed.

  And, such an epitaxial layer 61a has a trench (trench) dug in the thickness direction, and a gate oxide film 65a is formed on the inner wall surface of the epitaxial layer 61a. A polysilicon gate layer is formed in the trench via the gate oxide film 65a. 66a is embedded. As a result, a vertical power NMOS transistor is formed in which the semiconductor region 64a is a source region, the semiconductor region 62a is a channel formation region, and the epitaxial layer 61a and the semiconductor substrate 60a are drain regions.

A plurality of such trenches are formed in the lateral direction of the epitaxial layer 61a. The semiconductor region 64a between adjacent trenches is separated by a p ⁺ type semiconductor region 63a formed in the region. At the center of the semiconductor chip surface, a gate electrode (gate terminal) G is formed using a metal 67a such as aluminum AL, and the gate electrode G and a polysilicon gate layer 66a embedded in each trench are in contact with each other. Connected through. On the other hand, on both sides of the gate electrode G on the semiconductor chip surface, a source electrode (source terminal) S is formed using a metal 67a such as aluminum AL. The source electrode S is connected to the semiconductor region 64a and the semiconductor region 63a, whereby voltage supply to the source region and back bias to the channel formation region are performed.

Note that the gate electrode G and the source electrode S are protected by a protective film 68a such as PIQ (Polyimide Isoquino Quinosalination) except for a portion exposed as a pad. A p ⁻ type semiconductor region 69a for improving the breakdown voltage of the semiconductor chip is formed in the epitaxial layer 61a located under the gate electrode G. Further, although not shown, the two source electrodes S are electrically connected in the metal layer.

The vertical power PMOS transistors MP1 and MP2 shown in FIG. 6B include a semiconductor substrate 60b made of, for example, p ⁺ type silicon (Si) single crystal, and a drain electrode (drain terminal) D is formed on the back surface thereof. Is formed. The drain electrode D is formed by depositing a metal such as gold (Au), for example, and is connected to the die pad as described above. On the other hand, an epitaxial layer 61b made of, for example, ap ⁻ type silicon single crystal is formed on the main surface of the semiconductor substrate 60b. In the epitaxial layer 61b, an n ⁻ type semiconductor region 62b and a p ⁺ type semiconductor region 64b thereon are formed.

  Such an epitaxial layer 61b has a trench (trench) formed in the thickness direction, a gate oxide film 65b is formed on the inner wall surface thereof, and a polysilicon gate layer 66b via the gate oxide film 65b in the trench. Is embedded. Thus, a vertical power PMOS transistor is formed in which the semiconductor region 64b is a source region, the semiconductor region 62b is a channel formation region, and the epitaxial layer 61b and the semiconductor substrate 60b are drain regions.

A plurality of such trenches are formed in the lateral direction of the epitaxial layer 61b. The semiconductor region 64b between adjacent trenches is separated by an n ⁺ type semiconductor region 63b formed in the region. At the center of the semiconductor chip surface, a gate electrode G is formed using a metal 67b such as aluminum AL, and the gate electrode G and a polysilicon gate layer 66b embedded in each trench are connected via a contact. The On the other hand, the source electrode S is formed on both sides of the gate electrode G on the semiconductor chip surface using a metal 67b such as aluminum AL. The source electrode S is connected to the semiconductor region 64b and the semiconductor region 63b, whereby voltage supply to the source region and back bias to the channel formation region are performed.

Note that the gate electrode G and the source electrode S are protected by a protective film 68b such as PIQ (Polyimide Isoquino Quinosalination) except for portions exposed as pads. Further, an n ⁻ type semiconductor region 69b for improving the breakdown voltage of the semiconductor chip is formed in the epitaxial layer 61b located under the gate electrode G. Further, although not shown, the two source electrodes S are electrically connected in the metal layer.

  As described above, by forming a vertical power MOS transistor using the trench gate structure, the transistor unit region can be miniaturized and highly integrated, and the semiconductor chip can be miniaturized. Since the pad arrangement and signal arrangement of the semiconductor chip can be realized with point symmetry, the manufacturing cost as described in FIG. 4 can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The semiconductor device of the present invention is a particularly useful technique when applied to a semiconductor device in which an H-bridge circuit using a power transistor is realized in a single package. The present invention is not limited to this, and a plurality of semiconductor chips are provided in a single package. The present invention can be widely applied to semiconductor devices including the semiconductor device.

1A is a side view of a semiconductor device according to an embodiment of the present invention, and FIG. FIGS. 2A and 2B are top views showing an example of the internal configuration of the semiconductor device of FIG. 1. FIGS. 2A and 2B show configurations in which signal arrangements of external leads are different. FIG. 4 is a top view showing another example of the internal configuration of the semiconductor device of FIG. 1, and (a) and (b) show configurations in which signal arrangement of external leads is different. FIG. 4 is a flowchart showing an example of the assembly process in the semiconductor device of FIGS. 2 and 3, wherein (a) is a flowchart of the semiconductor device of FIG. 2 and (b) is a flowchart of the semiconductor device of FIG. 3A and 3B are top views showing a configuration example in which the semiconductor device of FIGS. 2A and 3A is applied, where FIG. 2A is an application example of FIG. 2A and FIG. 3B is an application example of FIG. It is an example. FIG. 4 is a cross-sectional view illustrating an example of a main part of the semiconductor chip in the semiconductor device of FIG. 3, (a) is a cross-sectional view of an NMOS transistor, and (b) is a cross-sectional view of a PMOS transistor. It is a circuit diagram which shows an example of an H bridge circuit. FIG. 10 is a top view showing a mounting example of an H bridge circuit included in a conventional semiconductor device studied as a premise of the present invention.

Explanation of symbols

60a, 60b Semiconductor substrate 61a, 61b Epitaxial layer 62a-64a, 62b-64b Semiconductor region 65a, 65b Oxide film 66a, 66b Polysilicon gate layer 67a, 67b Metal layer 68a, 68b Protective film 69a, 69b Semiconductor region MP PMOS transistor MN NMOS transistor DP die pad BW bonding wire GG, SS, DD External lead S Source terminal G Gate terminal D Drain terminal

Claims (12)

The first power transistor includes a first source terminal and a first gate terminal on the first main surface, and a first back surface of the first power transistor on the first back surface opposite to the first main surface. A first semiconductor chip having a drain terminal;
A second source terminal of the second power transistor and a second gate terminal on the second main surface; and a second back surface of the second power transistor on the second back surface opposite to the second main surface. A second semiconductor chip having a drain terminal;
A third power transistor including a third power terminal on a third main surface, a third source terminal and a third gate terminal of the third power transistor, and a third back surface of the third power transistor opposite to the third main surface; A third semiconductor chip having a drain terminal;
A fourth power transistor including a fourth power terminal, a fourth source terminal and a fourth gate terminal of the fourth power transistor on a fourth main surface, and a fourth back surface of the fourth power transistor opposite to the fourth main surface; A fourth semiconductor chip having a drain terminal;
A first die pad on which the first semiconductor chip and the third semiconductor chip are mounted;
A second die pad having the second semiconductor chip and the fourth semiconductor chip mounted on an upper surface;
A plurality of external leads disposed around the first die pad and the second die pad and electrically connected to the first, second, third, and fourth semiconductor chips;
In plan view, it has a first side, a second side facing the first side, a third side intersecting the first side, and a fourth side facing the third side, A sealing body that seals part of each of the second, third, and fourth semiconductor chips, and the plurality of external leads,
The plurality of external leads includes a first source lead, a second source lead, a first gate lead, a second gate lead, a third gate lead, and a fourth gate lead,
The first source lead, the first gate lead, and the second gate lead are disposed along the first side,
The first source lead is located between the first gate lead and the second gate lead;
The second source lead, the third gate lead, and the fourth gate lead are disposed along the second side;
The second source lead is located between the third gate lead and the fourth gate lead;
The first die pad is disposed between the first side and the second side so as to be closer to the third side than the fourth side,
The second die pad is disposed between the first die pad and the fourth side between the first side and the second side,
The first semiconductor chip is closer to the first side than the second side on the first die pad, and the first source terminal is closer to the second die pad than the first gate terminal. Mounted to be
The second semiconductor chip is closer to the first side than the second side on the second die pad, and the second source terminal is closer to the first die pad than the second gate terminal. Mounted to be
The third semiconductor chip is located on the first die pad between the first semiconductor chip and the second side, and the third source terminal is more on the second die pad than the third gate terminal. It is mounted to be close,
The fourth semiconductor chip is located on the second die pad between the second semiconductor chip and the second side, and the fourth source terminal is more on the first die pad than the fourth gate terminal. It is mounted to be close,
The first source terminal and the second source terminal are electrically connected to the first source lead by a bonding wire,
The semiconductor device, wherein the third source terminal and the fourth source terminal are electrically connected to the second source lead by a bonding wire. The semiconductor device according to claim 1,
The first semiconductor chip further includes a fifth source terminal,
The second semiconductor chip further includes a sixth source terminal,
The third semiconductor chip further includes a seventh source terminal,
The fourth semiconductor chip further includes an eighth source terminal,
The first gate terminal is disposed between the first source terminal and the fifth source terminal;
The second gate terminal is disposed between the second source terminal and the sixth source terminal;
The third gate terminal is disposed between the third source terminal and the seventh source terminal;
The semiconductor device, wherein the fourth gate terminal is disposed between the fourth source terminal and the eighth source terminal. The semiconductor device according to claim 2,
The first power transistor and the second power transistor are vertical PMOS transistors,
The semiconductor device, wherein the third power transistor and the fourth power transistor are vertical NMOS transistors. The semiconductor device according to claim 3.
Each of the first, second, third, and fourth semiconductor chips includes a semiconductor substrate made of a silicon single crystal,
An epitaxial layer made of silicon single crystal is formed on the semiconductor substrate,
The epitaxial layer has a first semiconductor region, a second semiconductor region, and a plurality of trenches formed in a thickness direction thereof,
A gate oxide film is formed on each inner wall surface of the plurality of trenches,
Since the polysilicon gate layer is buried through the gate oxide film, the first semiconductor region becomes a source region, the second semiconductor region becomes a channel formation region, the epitaxial layer and the semiconductor substrate become a drain region. A semiconductor device having a trench gate structure. The semiconductor device according to claim 4,
Each of the first, second, third, and fourth gate terminals is electrically connected to the polysilicon gate layer. The semiconductor device according to claim 1,
The plurality of external leads further includes a first drain lead and a second drain lead,
The first drain lead is connected to the first die pad and disposed along the first side;
The semiconductor device according to claim 1, wherein the second drain lead is connected to the second die pad and disposed along the second side. The semiconductor device according to claim 6.
The first drain lead is disposed between the first gate lead and the second gate lead;
The semiconductor device according to claim 1, wherein the second drain lead is disposed between the third gate lead and the fourth gate lead. The semiconductor device according to claim 1,
The first gate terminal is electrically connected to the first gate lead by a bonding wire,
The second gate terminal is electrically connected to the second gate lead by a bonding wire,
The third gate terminal is electrically connected to the third gate lead by a bonding wire,
The semiconductor device, wherein the fourth gate terminal is electrically connected to the fourth gate lead by a bonding wire. The semiconductor device according to claim 8,
A semiconductor device comprising an H-bridge circuit in the semiconductor device. The semiconductor device according to claim 1,
The first drain terminal and the third drain terminal are electrically connected via the first die pad,
The semiconductor device, wherein the second drain terminal and the fourth drain terminal are electrically connected through the second die pad. The semiconductor device according to claim 10.
Each of the first back surface of the first semiconductor chip and the third back surface of the third semiconductor chip is electrically connected to the first die pad via solder,
Each of the second back surface of the second semiconductor chip and the fourth back surface of the fourth semiconductor chip is electrically connected to the second die pad via solder. The semiconductor device according to claim 1,
The semiconductor device has a package shape of SOP.

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