JP2930079B1 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2930079B1
JP2930079B1 JP22324798A JP22324798A JP2930079B1 JP 2930079 B1 JP2930079 B1 JP 2930079B1 JP 22324798 A JP22324798 A JP 22324798A JP 22324798 A JP22324798 A JP 22324798A JP 2930079 B1 JP2930079 B1 JP 2930079B1
Authority
JP
Japan
Prior art keywords
semiconductor element
bonding
bonding pads
semiconductor device
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22324798A
Other languages
Japanese (ja)
Other versions
JP2000058744A (en
Inventor
和美 高畠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP22324798A priority Critical patent/JP2930079B1/en
Application granted granted Critical
Publication of JP2930079B1 publication Critical patent/JP2930079B1/en
Publication of JP2000058744A publication Critical patent/JP2000058744A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

【要約】 【課題】 支持基板上に搭載される複数個の半導体素子
の占有面積を減少させて装置全体サイズの小型化を図
り、かつボンディングパッド間やボンディングパッドと
リードとの間を接続するボンディングワイヤの交差をな
くして電気的信頼性を向上させた半導体装置を提供す
る。 【解決手段】 電力用半導体素子（第１半導体素子）２
０と制御用半導体素子（第２半導体素子）４０とが支持
基板１０上に重ね合わせられて配設されている。さら
に、リード１１〜１５の配列方向に一致させて、同一方
向に電力用半導体素子２０のボンディングパッド（第１
ボンディングパッド）２３Ｓ、２３Ｇ１〜２３Ｇ３、制
御用半導体素子４０のボンディングパッド（第２及び第
３ボンディングパッド）４１Ｐ，４２Ｐのそれぞれを配
設する。ボンディングワイヤ５０〜５２はすべてほぼ同
一方向に引き出されている。Abstract: PROBLEM TO BE SOLVED: To reduce the occupied area of a plurality of semiconductor elements mounted on a support substrate to reduce the size of the entire device, and to bond between bonding pads or between bonding pads and leads. Provided is a semiconductor device having improved electrical reliability by eliminating crossing of wires. SOLUTION: A power semiconductor element (first semiconductor element) 2
0 and a control semiconductor element (second semiconductor element) 40 are arranged on the support substrate 10 so as to overlap each other. Further, the bonding pads of the power semiconductor element 20 (the first pads) are aligned in the same direction with the arrangement direction of the leads 11 to 15.
Bonding pads 23S, 23G1 to 23G3, and bonding pads (second and third bonding pads) 41P, 42P of the control semiconductor element 40 are provided, respectively. The bonding wires 50 to 52 are all drawn out in almost the same direction.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特に、支持基板上に複数個の半導体素子を搭載し、
これら支持基板及び複数個の半導体素子を封止体で封止
する半導体装置に関する。さらに詳細には、本発明は、
装置全体の小型化を実現させることができ、半導体素子
間や半導体素子とリードとの間の電気的信頼性を向上さ
せることができる半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of semiconductor elements mounted on a support substrate.
The present invention relates to a semiconductor device in which the support substrate and a plurality of semiconductor elements are sealed with a sealing body. More specifically, the present invention provides
The present invention relates to a semiconductor device capable of realizing miniaturization of the entire device and improving electrical reliability between semiconductor elements or between a semiconductor element and a lead.

【０００２】[0002]

【従来の技術】図３は本発明の先行技術に係る半導体装
置の封止体の一部を取り除いた平面図である。図３に示
すように、半導体装置は、支持基板１上に電力用半導体
素子２及び制御用半導体素子４を搭載し、これら支持基
板１、電力用半導体素子２及び制御用半導体素子４を樹
脂封止体６で封止している。2. Description of the Related Art FIG. 3 is a plan view of a semiconductor device according to the prior art of the present invention, in which a part of a sealing body is removed. As shown in FIG. 3, the semiconductor device has a power semiconductor element 2 and a control semiconductor element 4 mounted on a support substrate 1 and seals the support substrate 1, the power semiconductor element 2 and the control semiconductor element 4 with a resin. It is sealed with a stopper 6.

【０００３】支持基板１は方形状の平面形状を有してお
り、支持基板１の下側の一辺に沿って複数本のリード１
Ｒ1〜１Ｒ5が配列されている。この支持基板１は放熱板
及び電源板としても使用されている。支持基板１の上側
には樹脂封止体６にビス取付用穴を形成するための貫通
穴１Ｈが配設されている。The support substrate 1 has a rectangular planar shape, and a plurality of leads 1 are formed along one lower side of the support substrate 1.
R 1 to 1R 5 are arranged. This support substrate 1 is also used as a heat sink and a power supply plate. Above the support substrate 1, a through hole 1H for forming a screw mounting hole in the resin sealing body 6 is provided.

【０００４】図中、左側の電力用半導体素子２は、例え
ばパワーＭＯＳＦＥＴで構成されている。制御用半導体
素子４は、パワーＭＯＳＦＥＴの制御を行うモノリシッ
クＩＣ素子であり、複数の低電圧駆動のトランジスタで
構成されている。[0004] In the figure, the power semiconductor element 2 on the left side is composed of, for example, a power MOSFET. The control semiconductor element 4 is a monolithic IC element for controlling a power MOSFET, and is composed of a plurality of low-voltage driven transistors.

【０００５】電力用半導体素子２は支持基板１に電気的
に接続されており、支持基板１から電力用半導体素子２
のドレイン電流が出力されている。支持基板１にはリー
ド１Ｒ1が一体的に形成されている。電力用半導体素子
２の表面上にはソース用ボンディングパッド２Ｓ、ゲー
ト用ボンディングパッド２Ｇのそれぞれが配設されてい
る。ソース用ボンディングパッド２Ｓは接続体（ボンデ
ィングワイヤ）５を通してリード１Ｒ2に電気的に接続
されている。ソース用ボンディングパッド２Ｓ及びリー
ド１Ｒ2を介して電力用半導体素子２の大電流のソース
電流が流れる。[0005] The power semiconductor element 2 is electrically connected to the support substrate 1.
Is output. Lead 1R 1 is formed integrally with the supporting substrate 1. On the surface of the power semiconductor element 2, a source bonding pad 2S and a gate bonding pad 2G are provided. Bonding pads 2S for source is electrically connected to the lead 1R 2 through the connecting member (bonding wires) 5. Through the source bonding pad 2S and lead 1R 2 flows source current of a large current of the power semiconductor device 2.

【０００６】制御用半導体素子４の表面上には複数のボ
ンディングパッド４Ｐが配設されており、この制御用半
導体素子４の所定のボンディングパッド４Ｐは接続体５
を通して電力用半導体素子２のゲート用ボンディングパ
ッド２Ｇに電気的に接続されている。ゲート用ボンディ
ングパッド２Ｇには制御用半導体素子４から導通、非導
通の制御を行う制御信号が供給されている。A plurality of bonding pads 4P are provided on the surface of the control semiconductor element 4, and the predetermined bonding pads 4P of the control semiconductor element 4
Through the gate bonding pad 2 </ b> G of the power semiconductor element 2. A control signal for controlling conduction / non-conduction is supplied from the control semiconductor element 4 to the gate bonding pad 2G.

【０００７】支持基板１からは電力用半導体素子２の大
電流のドレイン電流が出力されるので、制御用半導体素
子４は支持基板１と絶縁分離を行うために支持基板１上
に絶縁基板３を介して搭載されている。絶縁基板３には
例えばセラミックス基板又は樹脂基板が使用されてい
る。[0007] Since a large drain current of the power semiconductor element 2 is output from the support substrate 1, the control semiconductor element 4 places the insulating substrate 3 on the support substrate 1 in order to perform insulation separation from the support substrate 1. Has been mounted via. As the insulating substrate 3, for example, a ceramic substrate or a resin substrate is used.

【０００８】樹脂封止体６は支持基板１、電力用半導体
素子２、制御用半導体素子４、リード１Ｒ1〜１Ｒ5のそ
れぞれのインナーリード部を被覆する。樹脂封止体６は
トランスファモールド法で成型されている。[0008] Resin molded body 6 support substrate 1, the power semiconductor device 2, the control semiconductor element 4, to cover the respective inner lead portions of the lead 1R 1 ~1R 5. The resin sealing body 6 is formed by a transfer molding method.

【０００９】[0009]

【発明が解決しようとする課題】前述の図３に示す半導
体装置においては、以下の点について配慮がなされてい
ない。In the semiconductor device shown in FIG. 3, no consideration is given to the following points.

【００１０】（１）大電力化を目的としてパワーＭＯＳ
ＦＥＴ等の電力用半導体素子２のサイズを大きくする
と、この電力用半導体素子２のサイズの増加に伴い、支
持基板１のサイズが大型化され、結果的に半導体装置の
全体サイズが大型化されてしまう。(1) Power MOS for high power
When the size of the power semiconductor element 2 such as an FET is increased, the size of the support substrate 1 is increased with the increase in the size of the power semiconductor element 2, and as a result, the overall size of the semiconductor device is increased. I will.

【００１１】（２）電力用半導体素子２のソース用ボン
ディングパッド２Ｓとリード１Ｒ2との間を接続するボ
ンディングワイヤ５、制御用半導体素子４のボンディン
グパッド４Ｐとリード１Ｒ2〜１Ｒ5のそれぞれとの間を
接続するボンディングワイヤ５、電力用半導体素子２の
ゲート用ボンディングパッド２Ｇと制御用半導体素子４
のボンディングパッド４Ｐとの間を接続するボンディン
グワイヤ５の引出方向はいずれもばらばらである。この
ため、ボンディングワイヤ５の交差による短絡を防止す
るためにボンディングワイヤ５間を広く設定する必要が
あり、ゲート用ボンディングパッド２Ｇの間隔、ボンデ
ィングパッド４Ｐの間隔、リード１Ｒ2〜１Ｒ5の配列間
隔がいずれも広がってしまうので、半導体装置の全体サ
イズが大型化されてしまう。[0011] (2) and each of the bonding wires 5, bonding pads 4P of control semiconductor element 4 and the lead 1R 2 ～1R 5 that connects the source bonding pad 2S lead 1R 2 of the power semiconductor element 2 Bonding wire 5 connecting between the semiconductor chip, the bonding pad 2G for the gate of the power semiconductor element 2 and the control semiconductor element 4
The directions in which the bonding wires 5 are connected to the bonding pads 4P are different from each other. Therefore, it is necessary to set wide between the bonding wire 5 in order to prevent a short circuit due to crossing of the bonding wire 5, the interval of the gate bonding pad 2G, spacing of the bonding pads 4P, the arrangement interval of the lead 1R 2 ~1R 5 Are all spread, and the overall size of the semiconductor device is increased.

【００１２】本発明は上記課題を解決するためになされ
たものである。The present invention has been made to solve the above problems.

【００１３】従って、本発明の目的は、支持基板上に搭
載される複数個の半導体素子の占有面積を減少させて装
置全体サイズの小型化を図ることを目的とする。Accordingly, it is an object of the present invention to reduce the area occupied by a plurality of semiconductor elements mounted on a support substrate and to reduce the overall size of the device.

【００１４】本発明の他の目的は、ボンディングパッド
間やボンディングパッドとリードとの間を接続するボン
ディングワイヤの交差による短絡をなくして電気的信頼
性を向上させることができる半導体装置を提供すること
である。Another object of the present invention is to provide a semiconductor device capable of improving electrical reliability by eliminating a short circuit due to intersection of bonding wires connecting between bonding pads or between bonding pads and leads. It is.

【００１５】本発明のさらに他の目的は、組立作業時
（いわゆる後工程）におけるボンディング作業が容易
で、製造歩留まりが高い半導体装置を提供することであ
る。Still another object of the present invention is to provide a semiconductor device which can easily perform a bonding operation during an assembling operation (so-called post-process) and has a high production yield.

【００１６】[0016]

【課題を解決するための手段】上記課題を解決するため
に、本発明の第１の特徴は、半導体装置において、実質
的に方形状平面を有する支持基板と、この支持基板の一
辺に沿って配列された複数本のリードと、支持基板の一
表面上に搭載され、複数個の第１ボンディングパッドを
有する第１半導体素子と、第１ボンディングパッドより
も内側の領域において第１半導体素子の表面上に搭載さ
れ、複数個の第２ボンディングパッド及び複数個の第３
ボンディングパッドを有する第２半導体素子と、リード
と第１ボンディングパッドの少なくとも１との間を電気
的に接続する第１接続体と、リードと第２ボンディング
パッドとの間を電気的に接続する第２接続体と、第１接
続体が接続されたボンディングパッドを除く残余の第１
ボンディングパッドと第３ボンディングパッドとの間を
電気的に接続する第３接続体とを備えたことを特徴とす
る。ここで、複数個の第１ボンディングパッドは、第１
半導体素子の表面上にリードの配列方向と同一方向に配
列され、第２ボンディングパッドは、第２半導体素子の
表面上にリードの配列方向と同一方向に配列されてい
る。さらに、第３ボンディングパッドは、第２半導体素
子の表面上に第２ボンディングパッドの配列方向と同一
方向に配列されている。なお、「実質的に方形状」とは
方形の角部が面取りされていたり、角部にアール（ｒ）
や切り欠き部等が付いていてもかまわず、また方形を構
成する辺の一部に僅かな段差等がある場合をも許容する
意である。つまり、本発明における、この「方形」はリ
ード及び第１乃至第３ボンディングパッドの配列方向を
規定するだけの意味を持つにすぎないことに留意すべき
である。Means for Solving the Problems In order to solve the above-mentioned problems, a first feature of the present invention is that a semiconductor device includes a support substrate having a substantially rectangular plane, and a support substrate along one side of the support substrate. A plurality of arranged leads, a first semiconductor element mounted on one surface of the support substrate and having a plurality of first bonding pads, and a surface of the first semiconductor element in a region inside the first bonding pads. A plurality of second bonding pads and a plurality of third bonding pads
A second semiconductor element having a bonding pad; a first connector for electrically connecting between the lead and at least one of the first bonding pads; and a second connector for electrically connecting between the lead and the second bonding pad. 2 connection body, and the remaining first except for the bonding pad to which the first connection body is connected.
And a third connection body for electrically connecting the bonding pad and the third bonding pad. Here, the plurality of first bonding pads are the first bonding pads.
The second bonding pads are arranged on the surface of the semiconductor element in the same direction as the arrangement direction of the leads, and the second bonding pads are arranged on the surface of the second semiconductor element in the same direction as the arrangement direction of the leads. Further, the third bonding pads are arranged on the surface of the second semiconductor element in the same direction as the arrangement direction of the second bonding pads. In addition, the “substantially square shape” means that a square corner is chamfered or the corner is round (r).
Or a notch or the like, and it is intended to allow a case where there is a slight step or the like in a part of the side constituting the square. In other words, it should be noted that in the present invention, this “square” has only a meaning that defines the arrangement direction of the leads and the first to third bonding pads.

【００１７】本発明の第１の特徴において、第１，第２
及び第３接続体としては、金ワイヤ、アルミニウムワイ
ヤ、銅ワイヤ等のボンディングワイヤ若しくはこれらの
合金からなるボンディングワイヤが実用的に使用でき
る。また、第１，第２及び第３接続体としては、金もし
くはアルミニウム等の金属の帯やテープを用いても良
い。また、本発明の第１の特徴における第１半導体素子
と第２半導体素子との間は、双方の電気的な絶縁を行
い、双方の機械的な接合を行うために絶縁性接着剤によ
って接着することが好ましい。According to a first feature of the present invention, the first and second
As the third connection body, a bonding wire such as a gold wire, an aluminum wire, or a copper wire or a bonding wire made of an alloy thereof can be practically used. Further, as the first, second, and third connection bodies, a metal band or tape such as gold or aluminum may be used. Further, the first semiconductor element and the second semiconductor element according to the first aspect of the present invention are electrically insulated from each other, and are bonded to each other by an insulating adhesive in order to mechanically join the both. Is preferred.

【００１８】このように構成される半導体装置において
は、第１半導体素子上に第２半導体素子を重ね合わせ、
第１半導体素子と第２半導体素子との重複部分の占有面
積を半減できるので、支持基板のサイズを減少させるこ
とができ、装置全体サイズの小型化を図ることができ
る。In the semiconductor device configured as described above, the second semiconductor element is superimposed on the first semiconductor element.
Since the area occupied by the overlapping portion of the first semiconductor element and the second semiconductor element can be reduced by half, the size of the support substrate can be reduced, and the overall size of the device can be reduced.

【００１９】さらに、半導体装置においては、第１半導
体素子の第１ボンディングパッドの配列方向、第２半導
体素子の第２及び第３ボンディングパッドの配列方向の
それぞれをリードの配列方向と一致させているので、リ
ードのインナーリード部分と第１ボンディングパッドと
の間、リードのインナーリード部分と第２ボンディング
パッドとの間、第１ボンディングパッドと第３ボンディ
ングパッドとの間を各々電気的に接続する接続体は、い
ずれもリードが長手方向に延在する方向（リード配列方
向に対して直交方向）にほぼ一致して引き出すことがで
きる。従って、接続体の交差による短絡を減少させるこ
とができ、電気的不良を減少させることができる。加え
て、この電気的不良の減少により、隣接した接続体の相
互の間隔を相対的に縮小することができる。このため、
第１半導体素子上の第１ボンディングパッドの相互の間
隔、第２半導体素子上の第２ボンディングパッドの相互
の間隔及び第３ボンディングパッドの相互の間隔、リー
ド間の相互の間隔のいずれをも縮小することができる。
従って、本発明の第１の特徴によれば、第１半導体素子
及び第２半導体素子のチップサイズの小型化を図ること
ができ、装置全体サイズ（パッケージサイズ）の小型化
を図ることができる。Further, in the semiconductor device, the arrangement direction of the first bonding pads of the first semiconductor element and the arrangement direction of the second and third bonding pads of the second semiconductor element are made to coincide with the arrangement direction of the leads. Therefore, a connection for electrically connecting between the inner lead portion of the lead and the first bonding pad, between the inner lead portion of the lead and the second bonding pad, and between the first and third bonding pads. The body can be pulled out substantially in the direction in which the leads extend in the longitudinal direction (the direction perpendicular to the lead arrangement direction). Therefore, it is possible to reduce a short circuit due to the intersection of the connection bodies, and it is possible to reduce an electric failure. In addition, due to the reduction of the electrical failure, the distance between adjacent connectors can be relatively reduced. For this reason,
The distance between the first bonding pads on the first semiconductor element, the distance between the second bonding pads on the second semiconductor element, the distance between the third bonding pads, and the distance between the leads are all reduced. can do.
Therefore, according to the first feature of the present invention, the chip size of the first semiconductor element and the second semiconductor element can be reduced, and the overall size (package size) of the device can be reduced.

【００２０】本発明の第２の特徴は、第１の特徴の半導
体装置において、第１半導体素子は電力用半導体素子で
あり、第２半導体素子は第１半導体素子を制御する制御
用半導体素子であり、第１接続体の断面積が第２及び第
３接続体の断面積より大きく形成されたことを特徴とす
る。ここで、電力用半導体素子としてはパワーＭＯＳＦ
ＥＴ、パワーバイポーラトランジスタ（パワーＢＪ
Ｔ）、パワーＳＩＴ、ＩＧＢＴ、ＧＴＯサイリスタ、Ｓ
Ｉサイリスタ等のディスクリートデバイス、もしくはこ
れらのディスクリートデバイスからなるパワー１Ｃが使
用できる。制御用半導体素子としては、ｐＭＯＳ集積回
路，ｎＭＯＳ集積回路，ＣＭＯＳ集積回路，バイポーラ
集積回路、ＢｉＣＭＯＳ集積回路、ＳＩＴ集積回路等の
種々のモノリシックＩＣを採用することが出来る。According to a second feature of the present invention, in the semiconductor device according to the first feature, the first semiconductor element is a power semiconductor element, and the second semiconductor element is a control semiconductor element for controlling the first semiconductor element. In this case, the cross-sectional area of the first connector is formed larger than the cross-sectional areas of the second and third connectors. Here, power MOSF is used as the power semiconductor element.
ET, power bipolar transistor (power BJ
T), power SIT, IGBT, GTO thyristor, S
A discrete device such as an I-thyristor, or a power 1C composed of these discrete devices can be used. Various monolithic ICs such as a pMOS integrated circuit, an nMOS integrated circuit, a CMOS integrated circuit, a bipolar integrated circuit, a BiCMOS integrated circuit, and an SIT integrated circuit can be used as the control semiconductor element.

【００２１】このように構成される半導体装置において
は、第１半導体素子である電力用半導体素子の出力端子
（若しくは入力端子）として使用される第１ボンディン
グパッドうちの１とリードとの間を接続する第１接続体
の断面積が大きく設定されているので、半導体装置の定
格電流容量を増加させることができる。さらに、その他
の第２及び第３接続体の断面積が小さく設定されている
ので、第２ボンディングパッド、第２ボンディングパッ
ド及び第１接続体が接続されたボンディングパッドを除
く第１ボンディングパッドのそれぞれのサイズを減少さ
せることができ、第１半導体素子、第２半導体素子のチ
ップサイズの小型化を図ることができる。従って、半導
体装置の小型化をより一層図ることができる。In the semiconductor device configured as described above, one of the first bonding pads used as an output terminal (or input terminal) of the power semiconductor element as the first semiconductor element is connected to the lead. Since the cross-sectional area of the first connection body is set large, the rated current capacity of the semiconductor device can be increased. Further, since the cross-sectional areas of the other second and third connection bodies are set to be small, each of the first bonding pads except for the second bonding pad, the second bonding pad, and the bonding pad to which the first connection body is connected, respectively. Can be reduced, and the chip size of the first semiconductor element and the second semiconductor element can be reduced. Therefore, the size of the semiconductor device can be further reduced.

【００２２】[0022]

【発明の実施の形態】以下、本発明の実施の形態を図面
を参照し説明する。図１は本発明の実施の形態に係る半
導体装置の封止体の一部を取り除き見やすくした平面図
であり、図２は図１のＦ２−Ｆ２切断線部分で切った半
導体装置の断面図である。本実施の形態に係る半導体装
置は、樹脂封止型半導体装置であり、樹脂封止体内部に
配設された複数の半導体素子（半導体チップ）が重ね合
わされた点、並びに各半導体素子のボンディングパッド
とリードのインナーリード部分との配置レイアウトを最
適に設定した点に主たる特徴を備えている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention in which a part of a sealing body is removed to make it easier to see. FIG. 2 is a cross-sectional view of the semiconductor device taken along a line F2-F2 in FIG. is there. The semiconductor device according to the present embodiment is a resin-encapsulated semiconductor device, in which a plurality of semiconductor elements (semiconductor chips) provided inside a resin-encapsulated body are superimposed, and a bonding pad of each semiconductor element is provided. The main feature is that the layout of the lead and the inner lead portion is optimally set.

【００２３】すなわち、図１及び図２に示すように、半
導体装置は、ほぼ方形状平面を有する支持基板１０と、
この支持基板１０の一辺（図１中、下辺）に沿って配列
された複数本のリード１１〜１５と、支持基板１０の一
表面上に搭載され、複数個の第１ボンディングパッド２
３Ｓ、２３Ｇ１〜２３Ｇ３を有する第１半導体素子（電
力用半導体素子）２０と、第１ボンディングパッド２３
Ｓ、２３Ｇ１〜２３Ｇ３よりも内側の領域において第１
半導体素子２０の表面上に搭載され、複数個の第２ボン
ディングパッド４１Ｐ及び複数個の第３ボンディングパ
ッド４２Ｐを有する第２半導体素子（制御用半導体素
子）４０と、リード１１と第１ボンディングパッド２３
Ｓとの間を電気的に接続する第１接続体（ボンディング
ワイヤ）５０と、リード１２〜１５と第２ボンディング
パッド４１Ｐとの間を電気的に接続する第２接続体（ボ
ンディングワイヤ）５２と、第１ボンディングパッド２
３Ｇ１〜２３Ｇ３と第３ボンディングパッド４２Ｐとの
間を電気的に接続する第３接続体（ボンディングワイ
ヤ）５１とを備えて構築されている。ここで、複数個の
第１ボンディングパッド２３Ｓ、２３Ｇ１〜２３Ｇ３
は、第１半導体素子２０の表面上にリード１１〜１５の
配列方向（図１中、左右方向）と同一方向に配列され、
第２ボンディングパッド４１Ｐは、第２半導体素子４０
の表面上にリード１１〜１５の配列方向と同一方向に配
列されている。さらに、第３ボンディングパッド４２Ｐ
は、第２半導体素子４０の表面上に第２ボンディングパ
ッド４１Ｐの配列方向と同一方向に配列されている。支
持基板１０、電力用半導体素子２０、制御用半導体素子
４０、リード１１〜１５のそれぞれのインナーリード部
は樹脂封止体６０で封止されている。That is, as shown in FIGS. 1 and 2, the semiconductor device comprises a support substrate 10 having a substantially square plane,
A plurality of leads 11 to 15 arranged along one side (lower side in FIG. 1) of the support substrate 10 and a plurality of first bonding pads 2 mounted on one surface of the support substrate 10
3S, first semiconductor element (power semiconductor element) 20 having 23G1 to 23G3, and first bonding pad 23
S, first in an area inside of 23G1 to 23G3
A second semiconductor element (control semiconductor element) 40 mounted on the surface of the semiconductor element 20 and having a plurality of second bonding pads 41P and a plurality of third bonding pads 42P; a lead 11 and a first bonding pad 23
A first connection body (bonding wire) 50 for electrically connecting S and a second connection body (bonding wire) 52 for electrically connecting between the leads 12 to 15 and the second bonding pad 41P. , First bonding pad 2
The third connection body (bonding wire) 51 electrically connects the 3G1 to 23G3 and the third bonding pad 42P. Here, the plurality of first bonding pads 23S, 23G1 to 23G3
Are arranged on the surface of the first semiconductor element 20 in the same direction as the arrangement direction of the leads 11 to 15 (the horizontal direction in FIG. 1),
The second bonding pad 41P is connected to the second semiconductor element 40.
Are arranged in the same direction as the arrangement direction of the leads 11 to 15. Further, the third bonding pad 42P
Are arranged on the surface of the second semiconductor element 40 in the same direction as the arrangement direction of the second bonding pads 41P. The inner lead portions of the support substrate 10, the power semiconductor element 20, the control semiconductor element 40, and the leads 11 to 15 are sealed with a resin sealing body 60.

【００２４】図１中及び図２中上側に示すように、支持
基板１０には樹脂封止体６０にビス挿入用穴６１を形成
するための貫通穴１６が配設されている。ビス挿入用穴
６１は図示しない回路基板や実装装置に半導体装置を取
り付けるための取付用穴である。さらに、支持基板１０
にはこの支持基板１０と樹脂封止体６０との間の密着性
を向上させるための段差部１８が配設されている。段差
部１８は図１中、両側にそれぞれ配設されている。支持
基板１０は、本実施の形態において放熱板及び電源板を
兼ねており、さらにリード１１と一体に形成されるの
で、リードフレーム材料、例えば４２アロイ（42%Ni-Fe
合金）、５０アロイ（50%Ni-Fe合金）、銅、銅合金のい
ずれかの材料で形成されることが好ましい。As shown in FIGS. 1 and 2, a through hole 16 for forming a screw insertion hole 61 in a resin sealing body 60 is provided in the support substrate 10. The screw insertion hole 61 is a mounting hole for mounting the semiconductor device on a circuit board or a mounting device (not shown). Further, the supporting substrate 10
Is provided with a step 18 for improving the adhesion between the support substrate 10 and the resin sealing body 60. The steps 18 are provided on both sides in FIG. In the present embodiment, the support substrate 10 also serves as a heat sink and a power supply plate, and is formed integrally with the leads 11, so that a lead frame material, for example, a 42 alloy (42% Ni-Fe
Alloy), 50 alloy (50% Ni-Fe alloy), copper, or a copper alloy.

【００２５】リード１１は、図１中、左端において支持
基板１０にインナーリード部分を連結し（一体に形成
し）、この連結部分で折り曲げられ支持基板１０表面よ
りも高い位置に配設されている。リード１１は主に電力
用半導体素子２０から所定の大電流出力（パワーＭＯＳ
ＦＥＴのドレイン電流）を取り出す（若しくは大電流入
力を取り入れる）。リード１１のアウターリード部分は
図１中、下側に向かって引き延ばされている。The lead 11 connects the inner lead portion to the support substrate 10 at the left end in FIG. 1 (formed integrally), is bent at this connection portion, and is disposed at a position higher than the surface of the support substrate 10. . The lead 11 mainly outputs a predetermined large current output (power MOS) from the power semiconductor element 20.
(Drain current of FET) is taken out (or a large current input is taken in). The outer lead portion of the lead 11 is extended downward in FIG.

【００２６】リード１２〜１５はリード１１に対してほ
ぼ平行に所定間隔で配列されている。これらのリード１
２〜１５はそれぞれのインナーリード部分に連接してい
るが、支持基板１０とは独立に構成されている。このイ
ンナーリード部分は、アウターリード部分よりもリード
幅を広く設定してあり、ボンディングワイヤ５０、５２
のそれぞれがボンディングされるボンディングエリアと
して使用されている。The leads 12 to 15 are arranged at predetermined intervals substantially parallel to the leads 11. These leads 1
2 to 15 are connected to the respective inner lead portions, but are configured independently of the support substrate 10. The inner lead portion has a wider lead width than the outer lead portion.
Are used as bonding areas for bonding.

【００２７】高電圧・大電流の出力特性を有する電力用
半導体素子２０は本実施の形態においては絶縁ゲート型
トランジスタ素子（パワーＭＯＳＦＥＴ）で構成されて
いる。電力用半導体素子２０は、図２に示すように、単
結晶シリコン基板を主体とする半導体基板２０Ｓと、こ
の半導体基板２０Ｓの表面（図２中、半導体基板２０Ｓ
の上側の表面）上に順次形成された第１絶縁膜２１Ａ、
ソース配線２２、第２絶縁膜２１Ｂ、ゲート配線２３、
第３絶縁膜２１Ｃ、第４絶縁膜２１Ｄのそれぞれと、半
導体基板２０Ｓ裏面（図２中、半導体基板２０Ｓの下側
の表面）上に形成された裏面電極（ドレイン電極）２６
とを備えて構築されている。In the present embodiment, the power semiconductor device 20 having output characteristics of high voltage and large current is constituted by an insulated gate transistor device (power MOSFET). As shown in FIG. 2, the power semiconductor element 20 includes a semiconductor substrate 20S mainly composed of a single crystal silicon substrate and a surface of the semiconductor substrate 20S (in FIG. 2, the semiconductor substrate 20S
First insulating film 21A sequentially formed on the upper surface of
Source wiring 22, second insulating film 21B, gate wiring 23,
Each of the third insulating film 21C and the fourth insulating film 21D, and a back electrode (drain electrode) 26 formed on the back surface of the semiconductor substrate 20S (the lower surface of the semiconductor substrate 20S in FIG. 2).
It is built with.

【００２８】図示しないが、半導体基板２０Ｓの表面部
分にはソース領域、ドレイン領域及びボディ領域（ベー
ス領域）を形成するためのｎ型導電型及びｐ型導電型の
複数種類の半導体領域が形成されている。ソース領域は
ボディ領域（ベース領域）の表面に、ボディ・コンタク
ト領域と共に形成されている。ソース領域とボディ領域
（ベース領域）とは互いに反対導電型で、ボディ領域
（ベース領域）とボディ・コンタクト領域とは互いに同
導電型である。これらの半導体領域は、周知のフォトリ
ソグラフィー法、イオン注入法、不純物拡散法やエピタ
キシャル成長法により形成すればよい。半導体基板２０
Ｓの大半はドレイン領域（もしくはドリフト領域）とし
て使用され、半導体基板２０Ｓの裏面に形成された裏面
電極２６を通してドレイン領域（若しくはドレインコン
タクト領域）からのドレイン電流が出力される。この裏
面電極２６は導電性接着層３０を介して支持基板１０の
表面に電気的かつ機械的に接続されており、結果的に電
力用半導体素子２０は支持基板１０の表面上に固着され
ている。導電性接着層３０には例えば半田が使用されて
いる。Although not shown, a plurality of types of n-type and p-type semiconductor regions for forming a source region, a drain region and a body region (base region) are formed on the surface of the semiconductor substrate 20S. ing. The source region is formed on the surface of the body region (base region) together with the body contact region. The source region and the body region (base region) have opposite conductivity types, and the body region (base region) and the body contact region have the same conductivity type. These semiconductor regions may be formed by well-known photolithography, ion implantation, impurity diffusion, or epitaxial growth. Semiconductor substrate 20
Most of S is used as a drain region (or a drift region), and a drain current from a drain region (or a drain contact region) is output through a back electrode 26 formed on the back surface of the semiconductor substrate 20S. The back electrode 26 is electrically and mechanically connected to the surface of the support substrate 10 via the conductive adhesive layer 30, so that the power semiconductor element 20 is fixed on the surface of the support substrate 10. . For example, solder is used for the conductive adhesive layer 30.

【００２９】ソース配線２２は、第１絶縁膜２１Ａ上に
おいて、一端側を図１に示す第１ボンディングパッド
（ソース用ボンディングパッド）２３Ｓに電気的に接続
し、他端側をパワーＭＯＳＦＥＴのソース領域（及びボ
ディ領域）に電気的に接続している。本実施の形態にお
いて、ソース配線２２と第１ボンディングパッド２３Ｓ
とは別の導電層で形成されており、第１ボンディングパ
ッド２３Ｓはソース配線２２の上層に配設された第１ボ
ンディングパッド（ゲート用ボンディングパッド）２３
Ｇ１〜２３Ｇ３と同一の金属材料からなる導電層で形成
されている。ソース配線２２、第１ボンディングパッド
２３Ｓはいずれも例えばアルミニウム合金を主体として
形成されている。第１ボンディングパッド２３Ｓは、図
１中、電力用半導体素子２０の上辺Ａから下辺Ｂに向か
い左辺Ｃに沿って細長いストライプ形状の平面形状を有
している。この第１ボンディングパッド２３Ｓのストラ
イプ方向のほぼ延長上にはリード１２のインナーリード
部分が配設されており、リード１２とほぼ平行に引き出
された第１ボンディングワイヤ（第１接続体）５０を通
して第１ボンディングパッド２３Ｓとリード１２との間
が電気的に接続されている。第１ボンディングワイヤ５
０は、電流容量を高めるために、他のボンディングワイ
ヤ５１、５２のそれぞれに比べてワイヤ径の太いものを
使用する。第１ボンディングワイヤ５０には金ワイヤ、
アルミニウムワイヤ、銅ワイヤのいずれかのワイヤ若し
くはそれらの合金ワイヤが実用的に使用できる。大電流
用には、第１ボンディングワイヤ５０の代わりに金もし
くはアルミニウムの帯５０を用いても良い。One end of the source wiring 22 is electrically connected to the first bonding pad (bonding pad for source) 23S shown in FIG. 1 on the first insulating film 21A, and the other end is the source region of the power MOSFET. (And the body region). In the present embodiment, the source wiring 22 and the first bonding pad 23S
The first bonding pad 23S is a first bonding pad (gate bonding pad) 23 disposed above the source wiring 22.
It is formed of a conductive layer made of the same metal material as G1 to G3. Each of the source wiring 22 and the first bonding pad 23S is formed mainly of, for example, an aluminum alloy. In FIG. 1, the first bonding pad 23S has a strip-like planar shape extending along the left side C from the upper side A to the lower side B of the power semiconductor element 20. An inner lead portion of the lead 12 is disposed on the first bonding pad 23S substantially extending in the stripe direction, and the inner bonding portion of the first bonding pad 23S is passed through a first bonding wire (first connection body) 50 drawn substantially parallel to the lead 12. One bonding pad 23S and the lead 12 are electrically connected. First bonding wire 5
In order to increase the current capacity, 0 uses a wire having a larger wire diameter than each of the other bonding wires 51 and 52. A gold wire is used as the first bonding wire 50,
Any of aluminum wire and copper wire or their alloy wire can be used practically. For a large current, a gold or aluminum band 50 may be used instead of the first bonding wire 50.

【００３０】ソース配線２２は、図１に示すように、他
端側が電力用半導体素子２０の上辺Ａ、下辺Ｂのそれぞ
れに沿ってフィンガー部として延在されたものを上下方
向に複数本平行に配列し、一端側が第１ボンディングパ
ッド２３Ｓとの接続部分でこれら複数本のフィンガ部を
まとめた櫛歯形状の平面形状を有している。As shown in FIG. 1, a plurality of source wirings 22 each having the other end extending as a finger portion along each of the upper side A and the lower side B of the power semiconductor element 20 are arranged in parallel in the vertical direction. They are arranged, and one end side has a comb-shaped planar shape in which these plural finger portions are put together at a connection portion with the first bonding pad 23S.

【００３１】ゲート配線２３は、第１絶縁膜２１Ｂ上に
おいて、一端側を図１及び図２に示す第１ボンディング
パッド（ゲート用ボンディングパッド）２３Ｇ１〜２３
Ｇ３に電気的に接続し、他端側をパワーＭＯＳＦＥＴの
ゲート電極に電気的に接続している。本実施の形態にお
いて、ゲート配線２３と第１ボンディングパッド２３Ｇ
１〜２３Ｇ３とは同一導電層で形成されている。第１ボ
ンディングパッド２３Ｇ１〜２３Ｇ３は、それぞれ方形
状の平面形状を有し、図１中、電力用半導体素子２０の
左辺Ｃから右辺Ｄに向かい上辺Ａに沿って所定間隔で配
列されている。One end of the gate wiring 23 on the first insulating film 21B is a first bonding pad (gate bonding pad) 23G1 to 23G23 shown in FIGS.
G3, and the other end is electrically connected to the gate electrode of the power MOSFET. In the present embodiment, gate wiring 23 and first bonding pad 23G
1 to 23G3 are formed of the same conductive layer. The first bonding pads 23G1 to 23G3 each have a square planar shape, and are arranged at predetermined intervals along the upper side A from the left side C to the right side D of the power semiconductor element 20 in FIG.

【００３２】ゲート配線２３は、図１に示すように、他
端側が電力用半導体素子２０の左辺Ｃ、右辺Ｄのそれぞ
れに沿ってフィンガー部として延在されたものを左右方
向に複数本平行に配列し、一端側が第１ボンディングパ
ッド２３Ｇ１〜２３Ｇ３のそれぞれの接続部分でこれら
複数本のフィンガー部をまとめた櫛歯形状の平面形状を
有している。As shown in FIG. 1, a plurality of gate wirings 23 each having the other end extending as a finger portion along each of the left side C and the right side D of the power semiconductor element 20 are arranged in parallel in the left-right direction. They are arranged, and one end side has a comb-shaped planar shape in which the plurality of finger portions are combined at respective connection portions of the first bonding pads 23G1 to 23G3.

【００３３】図示しないが、半導体基板２０Ｓと第１絶
縁膜２１Ａとの間には、半導体基板２０Ｓ表面側から上
層に向かってゲート絶縁膜、ゲート電極のそれぞれが順
次配設されている。ゲート絶縁膜は例えば熱酸化法（ド
ライ酸化法若しくは塩酸酸化法等）で成膜された酸化シ
リコン膜で形成されている。ゲート電極は例えば気相成
長法（ＣＶＤ法）で成膜された不純物添加多結晶シリコ
ン膜（ドープドポリシリコン膜）で形成されている。ま
た、ゲート電極にはタングステン（Ｗ）、モリブデン
（Ｍｏ）等の高融点金属、これらのシリサイドやポリサ
イド膜を用いても良い。Although not shown, a gate insulating film and a gate electrode are sequentially disposed between the semiconductor substrate 20S and the first insulating film 21A from the surface of the semiconductor substrate 20S toward the upper layer. The gate insulating film is formed of, for example, a silicon oxide film formed by a thermal oxidation method (a dry oxidation method, a hydrochloric acid oxidation method, or the like). The gate electrode is formed of, for example, an impurity-doped polycrystalline silicon film (doped polysilicon film) formed by a vapor deposition method (CVD method). Further, a high melting point metal such as tungsten (W) or molybdenum (Mo), or a silicide or polycide film thereof may be used for the gate electrode.

【００３４】第１絶縁膜２１Ａは、図示しないゲート電
極とソース配線２２との間の層間絶縁膜として形成さ
れ、例えばＣＶＤ法やスパッタリング法で成膜された酸
化シリコン膜で形成されている。第２絶縁膜２１Ｂは、
ソース配線２２とゲート配線２３との間の層間絶縁膜と
して形成され、例えばＣＶＤ法やスパッタリング法で成
膜された酸化シリコン膜で形成されている。第３絶縁膜
２１Ｃは、ボンディングパッド２３Ｓ、２３Ｇ１〜２３
Ｇ３のそれぞれの領域を除き、ゲート配線２３上に保護
膜として形成され、例えばＣＶＤ法やスパッタリング法
で成膜された酸化シリコン膜又は窒化シリコン膜で形成
されている。The first insulating film 21A is formed as an interlayer insulating film between a gate electrode (not shown) and the source wiring 22, and is formed of, for example, a silicon oxide film formed by a CVD method or a sputtering method. The second insulating film 21B is
It is formed as an interlayer insulating film between the source wiring 22 and the gate wiring 23, and is formed of, for example, a silicon oxide film formed by a CVD method or a sputtering method. The third insulating film 21C includes bonding pads 23S, 23G1 to 23G.
Except for each region of G3, it is formed as a protective film on the gate wiring 23, and is formed of, for example, a silicon oxide film or a silicon nitride film formed by a CVD method or a sputtering method.

【００３５】第４絶縁膜２１Ｄは、第３絶縁膜２１Ｃと
同様にボンディングパッド２３Ｓ、２３Ｇ１〜２３Ｇ３
のそれぞれの領域を除き、第３絶縁膜２１Ｃ上に形成さ
れている。図２に示すように、第４絶縁膜２１Ｄは、電
力用半導体素子２０の最終保護膜として形成され、この
直上には別の制御用半導体素子４０が搭載される。この
第４絶縁膜２１Ｄには、種々の材料及び方法が採用でき
る。基本的には例えばスピン・オン・グラス（ＳＯＧ）
法、ＣＶＤ法やスパッタリング法で成膜された酸化シリ
コン膜又は窒化シリコン膜で第４絶縁膜２１Ｄを形成し
てもよい。しかし、第４絶縁膜２１Ｄとしては、ラミネ
ート法で張り付けられた、又はポッティング法で滴下塗
布された樹脂膜、例えばポリイミド系樹脂膜で形成する
ことが好ましい。この種の樹脂膜は電力用半導体素子２
０と制御用半導体素子４０との間に発生する応力を緩和
させることができ、特に電力用半導体素子２０の表面部
分を保護することができる。この第４絶縁膜２１Ｄ上に
おいて、電力用半導体素子２０の第１ボンディングパッ
ド２３Ｓと第１ボンディングパッド２３Ｇ１〜２３Ｇ３
のそれぞれとで周囲を囲まれた領域内、すなわち図１中
右下部分のソース配線２２及びゲート配線２３が配設さ
れた領域は制御用半導体素子４０の搭載領域として使用
されている。The fourth insulating film 21D has bonding pads 23S, 23G1 to 23G3 similarly to the third insulating film 21C.
Are formed on the third insulating film 21C except for the respective regions. As shown in FIG. 2, the fourth insulating film 21D is formed as a final protective film of the power semiconductor element 20, and another control semiconductor element 40 is mounted immediately above the fourth insulating film 21D. Various materials and methods can be used for the fourth insulating film 21D. Basically, for example, spin-on-glass (SOG)
The fourth insulating film 21D may be formed of a silicon oxide film or a silicon nitride film formed by a method, a CVD method, or a sputtering method. However, it is preferable that the fourth insulating film 21D be formed of a resin film adhered by a laminating method or dropped and applied by a potting method, for example, a polyimide resin film. This kind of resin film is used for the power semiconductor element 2
The stress generated between the power semiconductor element 20 and the control semiconductor element 40 can be reduced, and in particular, the surface portion of the power semiconductor element 20 can be protected. On the fourth insulating film 21D, the first bonding pads 23S and the first bonding pads 23G1 to 23G3 of the power semiconductor element 20 are formed.
Each of the regions surrounded by each of the above, that is, the region where the source wiring 22 and the gate wiring 23 are disposed in the lower right portion in FIG. 1 is used as a mounting region of the control semiconductor element 40.

【００３６】なお、電力用半導体素子２０には他にパワ
ーバイポーラトランジスタ（パワーＢＪＴ）、パワーＳ
ＩＴ、ＩＧＢＴ、ＧＴＯサイリスタ、ＳＩサイリスタ等
のパワーデバイス、もしくはこれらのパワーデバイスか
らなるパワー１Ｃが使用できる。The power semiconductor element 20 includes a power bipolar transistor (power BJT) and a power S
Power devices such as IT, IGBT, GTO thyristor, and SI thyristor, or power 1C composed of these power devices can be used.

【００３７】制御用半導体素子４０は、電力用半導体素
子２０の制御を行うモノリシックＩＣ素子であり、複数
の低電圧駆動のトランジスタを備える。モノリシックＩ
ＣとしてはｐＭＯＳ集積回路，ｎＭＯＳ集積回路，ＣＭ
ＯＳ集積回路，バイポーラ集積回路、ＢｉＣＭＯＳ集積
回路、ＳＩＴ集積回路等の種々の集積回路を採用するこ
とが出来る。制御用半導体素子４０は、単結晶シリコン
からなる半導体基板４０Ｓと、この半導体基板４０Ｓの
表面上に順次形成された第１絶縁膜４１Ａ、配線（複数
層の配線層を備えてもよい。）４２、第２絶縁膜４１Ｂ
のそれぞれとで構築されている。The control semiconductor element 40 is a monolithic IC element for controlling the power semiconductor element 20, and includes a plurality of low-voltage driven transistors. Monolithic I
C is pMOS integrated circuit, nMOS integrated circuit, CM
Various integrated circuits such as an OS integrated circuit, a bipolar integrated circuit, a BiCMOS integrated circuit, and a SIT integrated circuit can be employed. The control semiconductor element 40 includes a semiconductor substrate 40S made of single-crystal silicon, a first insulating film 41A sequentially formed on the surface of the semiconductor substrate 40S, and wiring (may include a plurality of wiring layers). , Second insulating film 41B
Are built with each of the

【００３８】図示しないが、電力用半導体素子２０の半
導体基板２０Ｓと同様に、半導体基板４０Ｓの表面部分
には周知の不純物拡散法やエピタキシャル成長法等によ
りｎ型及びｐ型の複数種類の半導体領域が形成されてい
る。ｐＭＯＳ集積回路，ｎＭＯＳ集積回路，ＣＭＯＳ集
積回路であれば、ＭＯＳＦＥＴのソース領域、ドレイン
領域等が形成され、バイポーラ集積回路であれば、ＢＪ
Ｔのエミッタ領域、ベース領域、コレクタ領域等が形成
されることになる。半導体基板４０Ｓは絶縁性接着層３
１を介して半導体基板２０Ｓの搭載領域上に固着されて
いる。絶縁性接着層３１には例えば熱硬化性エポキシ系
樹脂接着剤が使用されている。熱硬化性エポキシ系樹脂
接着剤は、半導体基板２０Ｓ上の搭載領域にその領域か
らはみ出さないように例えばスクリーン印刷で塗布さ
れ、この塗布された表面上に制御用半導体素子４０を搭
載後に加熱により硬化させられる。Although not shown, similarly to the semiconductor substrate 20S of the power semiconductor element 20, a plurality of types of n-type and p-type semiconductor regions are formed on the surface of the semiconductor substrate 40S by a well-known impurity diffusion method, an epitaxial growth method, or the like. Is formed. In the case of a pMOS integrated circuit, an nMOS integrated circuit, or a CMOS integrated circuit, a source region and a drain region of a MOSFET are formed. In the case of a bipolar integrated circuit, a BJ is formed.
An emitter region, a base region, a collector region and the like of T are formed. The semiconductor substrate 40S has the insulating adhesive layer 3
1 and is fixed on the mounting area of the semiconductor substrate 20S. For the insulating adhesive layer 31, for example, a thermosetting epoxy resin adhesive is used. The thermosetting epoxy resin adhesive is applied to the mounting area on the semiconductor substrate 20S by, for example, screen printing so as not to protrude from the area, and after mounting the control semiconductor element 40 on the coated surface, heating is performed. Cured.

【００３９】図２に示した配線４２は、第１絶縁膜４１
Ａ上において、一端側を図１に示すいずれかの第２及び
第３ボンディングパッド（信号入出力用ボンディングパ
ッド）４１Ｐ、４２Ｐに電気的に接続し、他端側をトラ
ンジスタのソース領域、ドレイン領域又はゲート電極
（又は、エミッタ領域、ベース領域、コレクタ領域）等
に電気的に接続している。本実施の形態において、配線
４２とボンディングパッド４２Ｐとは同一導電層で形成
されており、配線４２、第２及び第３ボンディングパッ
ド４１Ｐ，４２Ｐのそれぞれは例えばアルミニウム合金
を主体として形成されている。第２ボンディングパッド
４１Ｐは、方形状の平面形状を有し、図１中、制御用半
導体素子４０の左辺ｃから右辺ｄに向かい下辺ｂに沿っ
て複数個配列されている。第３ボンディングパッド４２
Ｐは、同じく方形状の平面形状を有し、図１中、制御用
半導体素子４０の左辺ｃから右辺ｄに向かい上辺ａに沿
って複数個配列されている。制御用半導体素子４０の上
辺ａ、下辺ｂ、左辺ｃ、右辺ｄのそれぞれは電力用半導
体素子２０の上辺Ａ、下辺Ｂ、左辺Ｃ、右辺Ｄのそれぞ
れに対応しており、制御用半導体素子４０の上辺ａ、下
辺ｂ、電力用半導体素子２０の上辺Ａ、下辺Ｂのそれぞ
れに沿ってリード１１〜１５のそれぞれが配列されてい
る。The wiring 42 shown in FIG.
1A, one end is electrically connected to one of the second and third bonding pads (signal input / output bonding pads) 41P and 42P shown in FIG. 1, and the other end is a source region and a drain region of a transistor. Alternatively, it is electrically connected to a gate electrode (or an emitter region, a base region, a collector region) or the like. In the present embodiment, the wiring 42 and the bonding pad 42P are formed of the same conductive layer, and each of the wiring 42 and the second and third bonding pads 41P, 42P is formed mainly of, for example, an aluminum alloy. The second bonding pads 41P have a square planar shape, and a plurality of the second bonding pads 41P are arranged along the lower side b from the left side c to the right side d of the control semiconductor element 40 in FIG. Third bonding pad 42
P also has a square planar shape, and a plurality of Ps are arranged along the upper side a from the left side c to the right side d of the control semiconductor element 40 in FIG. The upper side a, the lower side b, the left side c, and the right side d of the control semiconductor element 40 correspond to the upper side A, the lower side B, the left side C, and the right side D of the power semiconductor element 20, respectively. Each of the leads 11 to 15 is arranged along each of the upper side a, the lower side b, and the upper side A and the lower side B of the power semiconductor element 20.

【００４０】制御用半導体素子４０の上辺ａに沿って配
列された第３ボンディングパッド４２Ｐのそれぞれと電
力用半導体素子２０の上辺Ａに沿って配列された第１ボ
ンディングパッド２３Ｇ１〜２３Ｇ３のそれぞれとの間
は各々第３ボンディングワイヤ５１により電気的に接続
されている。制御用半導体素子４０の下辺ｂに沿って配
列された第２ボンディングパッド４１Ｐのそれぞれとリ
ード１２〜１５のそれぞれのインナーリード部との間は
第２ボンディングワイヤ５２により電気的に接続されて
いる。第２及び第３ボンディングワイヤ５１、５２はい
ずれも前述の電力用半導体素子２０の第１ボンディング
パッド２３Ｓとリード１２のインナーリード部との間を
接続する第１ボンディングワイヤ５０に対してほぼ平行
に、すなわち交差による短絡を生じることなくボンディ
ングされている。第２及び第３ボンディングワイヤ５
１、５２には第１ボンディングワイヤ５０に比べてワイ
ヤ径の細いものが使用されている。これらの第２及び第
３ボンディングワイヤ５１、５２には金ワイヤ、アルミ
ニウムワイヤ、銅ワイヤのいずれかのワイヤ若しくはそ
れらの合金ワイヤが実用的に使用できる。Each of the third bonding pads 42P arranged along the upper side a of the control semiconductor element 40 and each of the first bonding pads 23G1 to 23G3 arranged along the upper side A of the power semiconductor element 20 is formed. The spaces are electrically connected by third bonding wires 51, respectively. Each of the second bonding pads 41P arranged along the lower side b of the control semiconductor element 40 and each of the inner leads of the leads 12 to 15 are electrically connected by the second bonding wires 52. Each of the second and third bonding wires 51 and 52 is substantially parallel to the first bonding wire 50 connecting between the first bonding pad 23S of the power semiconductor element 20 and the inner lead portion of the lead 12. That is, bonding is performed without causing a short circuit due to crossing. Second and third bonding wires 5
Wires 1 and 52 having a smaller wire diameter than the first bonding wire 50 are used. Any of a gold wire, an aluminum wire, a copper wire, or an alloy wire thereof can be practically used for the second and third bonding wires 51 and 52.

【００４１】第１絶縁膜４１Ａは、図示しないトランジ
スタと配線４２との間の層間絶縁膜として形成され、例
えばＣＶＤ法やスパッタリング法で成膜された酸化シリ
コン膜で形成されている。第２絶縁膜４１Ｂは、第２及
び第３ボンディングパッド４１Ｐ，４２Ｐの領域を除
き、配線４２上に最終保護膜として形成され、例えばＣ
ＶＤ法やスパッタリング法で成膜された酸化シリコン膜
又は窒化シリコン膜で形成されている。The first insulating film 41A is formed as an interlayer insulating film between a transistor (not shown) and the wiring 42, and is formed of, for example, a silicon oxide film formed by a CVD method or a sputtering method. The second insulating film 41B is formed as a final protective film on the wiring 42 except for the regions of the second and third bonding pads 41P and 42P.
It is formed of a silicon oxide film or a silicon nitride film formed by a VD method or a sputtering method.

【００４２】樹脂封止体６０はトランスファモールド法
により成型されている。樹脂封止体６０には例えば熱硬
化性エポキシ系樹脂が使用されている。The resin sealing body 60 is formed by a transfer molding method. For example, a thermosetting epoxy resin is used for the resin sealing body 60.

【００４３】このように構成される半導体装置において
は、以下の効果を得ることができる。In the semiconductor device configured as described above, the following effects can be obtained.

【００４４】（１）電力用半導体素子（第１半導体素
子）２０上に制御用半導体素子（第２半導体素子）４０
を重ね合わせ、電力用半導体素子２０と制御用半導体素
子４０との重複部分の占有面積を半減できるので、支持
基板１０のサイズを減少させることができ、半導体装置
の装置全体サイズの小型化を図ることができる。(1) A control semiconductor element (second semiconductor element) 40 on a power semiconductor element (first semiconductor element) 20
Can be overlapped, and the area occupied by the overlapping portion between the power semiconductor element 20 and the control semiconductor element 40 can be reduced by half, so that the size of the support substrate 10 can be reduced and the overall size of the semiconductor device can be reduced be able to.

【００４５】（２）電力用半導体素子２０の第１ボンデ
ィングパッド（ソース用ボンディングパッド）２３Ｓ、
第１ボンディングパッド（ゲート用ボンディングパッ
ド）２３Ｇ１〜２３Ｇ３のそれぞれの配列方向、制御用
半導体素子４０の第２及び第３ボンディングパッド（信
号入出力用ボンディングパッド）４１Ｐ，４２Ｐの配列
方向をいずれもリード１１〜１５の配列方向と一致させ
たので、リード１２と第１ボンディングパッド２３Ｓと
の間を電気的に接続する第１ボンディングワイヤ５０、
第１ボンディングパッド２３Ｇ１〜２３Ｇ３のそれぞれ
と第３ボンディングパッド４２Ｐとの間を電気的に接続
する第３ボンディングワイヤ５１、第２ボンディングパ
ッド４１Ｐとリード１２〜１５のそれぞれのインナーリ
ード部との間を電気的に接続する第２ボンディングワイ
ヤ５２はいずれもリード１１〜１５の延在方向（リード
配列方向に対して交差方向）にほぼ一致して引き出すこ
とができる。従って、第１乃至第３ボンディングワイヤ
５０〜５２の交差による短絡を減少させ、電気的不良を
減少させることができる。さらに、電気的不良の減少に
より隣接ボンディングワイヤ間隔、特に電力用半導体素
子２０の第１ボンディングパッド２３Ｇ１〜２３Ｇ３の
それぞれの間隔、制御用半導体素子４０の第２及び第３
ボンディングパッド４１Ｐ，４２Ｐの間隔を縮小し、こ
れらの縮小に応じてリード１１〜１５の配列間隔を縮小
することができるので、半導体装置の装置全体の小型化
を図ることができる。(2) The first bonding pads (source bonding pads) 23S of the power semiconductor element 20;
The arrangement directions of the first bonding pads (gate bonding pads) 23G1 to 23G3 and the arrangement directions of the second and third bonding pads (signal input / output bonding pads) 41P and 42P of the control semiconductor element 40 are both read. Since the alignment direction is matched with the arrangement direction of the first to fifth bonding pads 11 to 15, the first bonding wires 50 for electrically connecting the leads 12 and the first bonding pads 23S are provided.
A third bonding wire 51 for electrically connecting each of the first bonding pads 23G1 to 23G3 and the third bonding pad 42P, and a connection between the second bonding pad 41P and each of the inner lead portions of the leads 12 to 15 are provided. The second bonding wires 52 to be electrically connected can be pulled out substantially in the extending direction of the leads 11 to 15 (the direction crossing the lead arrangement direction). Therefore, it is possible to reduce a short circuit due to the intersection of the first to third bonding wires 50 to 52 and reduce an electrical failure. Further, the distance between adjacent bonding wires, in particular, the distance between the first bonding pads 23G1 to 23G3 of the power semiconductor element 20, the second and third positions of the control semiconductor element 40,
Since the spacing between the bonding pads 41P and 42P can be reduced and the spacing between the leads 11 to 15 can be reduced in accordance with the reduction, the overall size of the semiconductor device can be reduced.

【００４６】（３）電力用半導体素子２０の出力端子と
して使用される第１ボンディングパッド（ソース用ボン
ディングパッド）２３Ｓとリード１２との間を接続する
第１ボンディングワイヤ５０のワイヤ径が太く設定され
ているので、電流容量を増加させることができる。(3) The wire diameter of the first bonding wire 50 connecting between the first bonding pad (source bonding pad) 23S used as the output terminal of the power semiconductor element 20 and the lead 12 is set to be large. Therefore, the current capacity can be increased.

【００４７】（４）電力用半導体素子２０の第１ボンデ
ィングパッド（ゲート用ボンディングパッド）２３Ｇ１
〜２３Ｇ３のそれぞれと制御用半導体素子（モノリシッ
クＩＣ素子）４０の第３ボンディングパッド（信号入出
力用ボンディングパッド）４２Ｐとの間を接続する第３
ボンディングワイヤ５１、第２ボンディングパッド４１
Ｐとリード１２〜１５のそれぞれとの間を接続する第２
ボンディングワイヤ５２のワイヤ径が細く設定されてい
るので、ボンディングエリアを縮小することができ、第
１ボンディングパッド２３Ｇ１〜２３Ｇ３、第２及び第
３ボンディングパッドの４１Ｐ，４２Ｐのそれぞれの面
積を縮小することができる。従って、電力用半導体素子
２０、制御用半導体素子４０のそれぞれのチップサイズ
の小型化を図ることができるので、半導体装置の装置全
体の小型化を図ることができる。(4) First bonding pad (gate bonding pad) 23G1 of power semiconductor element 20
To 23G3 and a third bonding pad (signal input / output bonding pad) 42P of the control semiconductor element (monolithic IC element) 40
Bonding wire 51, second bonding pad 41
Second connecting between P and each of leads 12 to 15
Since the wire diameter of the bonding wire 52 is set to be small, the bonding area can be reduced, and the respective areas of the first bonding pads 23G1 to 23G3 and the second and third bonding pads 41P and 42P can be reduced. Can be. Therefore, the chip size of each of the power semiconductor element 20 and the control semiconductor element 40 can be reduced, so that the overall size of the semiconductor device can be reduced.

【００４８】（５）電力用半導体素子２０と制御用半導
体素子４０との間が、絶縁性接着層３１とそれに加えて
電力用半導体素子２０の第３絶縁膜２１Ｃ及び第４絶縁
膜２１Ｄとで絶縁分離されているので、双方の電気的絶
縁性を高めることができる。(5) The space between the power semiconductor element 20 and the control semiconductor element 40 is defined by the insulating adhesive layer 31 and, in addition, the third insulating film 21C and the fourth insulating film 21D of the power semiconductor element 20. Since they are insulated and separated, the electrical insulation between them can be enhanced.

【００４９】[0049]

【発明の効果】本発明は、支持基板上に搭載される複数
個の半導体素子の占有面積を減少させて装置全体サイズ
の小型化を図ることができる。According to the present invention, the area occupied by a plurality of semiconductor elements mounted on a supporting substrate can be reduced, and the overall size of the device can be reduced.

【００５０】本発明によれば、ボンディングパッド間や
ボンディングパッドとリードとの間を接続するボンディ
ングワイヤの交差が無く電気的信頼性が向上した半導体
装置を提供することができる。According to the present invention, it is possible to provide a semiconductor device having improved electrical reliability without crossing of bonding wires connecting between bonding pads or between bonding pads and leads.

【００５１】本発明によれば、組立作業時（いわゆる後
工程）におけるボンディング作業が容易で、製造歩留ま
りが高い半導体装置を提供することができる。According to the present invention, it is possible to provide a semiconductor device in which the bonding operation during the assembly operation (so-called post-process) is easy and the production yield is high.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態に係る封止体の一部を取り
除いた半導体装置の平面図である。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention from which a part of a sealing body is removed.

【図２】本発明の実施の形態に係る半導体装置の断面図
である。FIG. 2 is a sectional view of the semiconductor device according to the embodiment of the present invention;

【図３】本発明の先行技術に係る封止体の一部を取り除
いた半導体装置の平面図である。FIG. 3 is a plan view of a semiconductor device with a part of a sealing body according to the prior art of the present invention removed.

【符号の説明】[Explanation of symbols]

１０ 支持基板 １１〜１５ リード ２０，４０ 半導体素子 ２０Ｓ，４０Ｓ 半導体基板 ２１Ａ〜２１Ｄ，４１Ａ，４１Ｂ 絶縁膜 ２２ ソース配線 ２３ ゲート配線 ２３Ｓ ソース用ボンディングパッド（第１ボンディン
グパッド） ２３Ｇ１〜２３Ｇ３ ゲート用ボンディングパッド(第
１ボンディングパッド) ２６ 裏面電極 ３０ 導電性接着層 ３１ 絶縁性接着層 ４２ 配線 ４１Ｐ 第２ボンディングパッド（入出力信号用ボンデ
ィングパッド） ４２Ｐ 第３ボンディングパッド（入出力信号用ボンデ
ィングパッド） ５０ 第１ボンディングワイヤ ５１ 第２ボンディングワイヤ ５２ 第３ボンディングワイヤ ６０ 樹脂封止体Reference Signs List 10 Support substrate 11 to 15 Lead 20, 40 Semiconductor element 20S, 40S Semiconductor substrate 21A to 21D, 41A, 41B Insulating film 22 Source wiring 23 Gate wiring 23S Source bonding pad (first bonding pad) 23G1 to 23G3 Gate bonding pad (First bonding pad) 26 back electrode 30 conductive adhesive layer 31 insulating adhesive layer 42 wiring 41P second bonding pad (input / output signal bonding pad) 42P third bonding pad (input / output signal bonding pad) 50 first Bonding wire 51 Second bonding wire 52 Third bonding wire 60 Resin sealing body

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 実質的に方形状平面を有する支持基板
と、 前記支持基板の一辺に沿って配列された複数本のリード
と、 前記支持基板の一表面上に搭載され、表面上に前記リー
ドの配列方向と同一方向に配列された複数個の第１ボン
ディングパッドを有する第１半導体素子と、 前記第１ボンディングパッドよりも内側の領域において
前記第１半導体素子の表面上に搭載され、表面上に前記
リードの配列方向と同一方向に配列された複数個の第２
ボンディングパッドと、該第２ボンディングパッドの配
列方向と同一方向に配列された複数個の第３ボンディン
グパッドを有する第２半導体素子と、 前記リードと前記第１ボンディングパッドの少なくとも
１との間を電気的に接続する第１接続体と、 前記リードと前記第２ボンディングパッドとの間を電気
的に接続する第２接続体と、 前記第１接続体が接続されたボンディングパッドを除く
前記第１ボンディングパッドと前記第３ボンディングパ
ッドとの間を電気的に接続する第３接続体と、 を備えたことを特徴とする半導体装置。A support substrate having a substantially rectangular flat surface; a plurality of leads arranged along one side of the support substrate; and a lead mounted on one surface of the support substrate and on the surface. A first semiconductor element having a plurality of first bonding pads arranged in the same direction as the arrangement direction of the first semiconductor element; a first semiconductor element mounted on a surface of the first semiconductor element in a region inside the first bonding pad; A plurality of second leads arranged in the same direction as the arrangement direction of the leads.
A second semiconductor element having a bonding pad, a plurality of third bonding pads arranged in the same direction as the arrangement direction of the second bonding pad, and an electric connection between the lead and at least one of the first bonding pads. A first connection body for electrically connecting the first connection body, a second connection body for electrically connecting the lead and the second bonding pad, and the first bonding except for a bonding pad to which the first connection body is connected. And a third connector for electrically connecting the pad and the third bonding pad. 【請求項２】 前記第１半導体素子は電力用半導体素子
であり、 前記第２半導体素子は前記第１半導体素子を制御する制
御用半導体素子であり、 前記第１接続体の断面積が前記第２及び第３接続体の断
面積より大きく形成されたことを特徴とする請求項１に
記載の半導体装置。2. The semiconductor device according to claim 1, wherein the first semiconductor device is a power semiconductor device, the second semiconductor device is a control semiconductor device for controlling the first semiconductor device, and a cross-sectional area of the first connector is the first semiconductor device. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed to be larger than a cross-sectional area of the second and third connection bodies.
JP22324798A 1998-08-06 1998-08-06 Semiconductor device Expired - Fee Related JP2930079B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22324798A JP2930079B1 (en) 1998-08-06 1998-08-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22324798A JP2930079B1 (en) 1998-08-06 1998-08-06 Semiconductor device

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Publication Number Publication Date
JP2930079B1 true JP2930079B1 (en) 1999-08-03
JP2000058744A JP2000058744A (en) 2000-02-25

Family

ID=16795114

Family Applications (1)

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JP22324798A Expired - Fee Related JP2930079B1 (en) 1998-08-06 1998-08-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2930079B1 (en)

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JP2001110986A (en) * 1999-09-13 2001-04-20 Fairchild Korea Semiconductor Kk Power element with multi-chip package structure and manufacturing method thereof
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JP4146607B2 (en) * 2000-07-28 2008-09-10 三菱電機株式会社 Power module
JP5014534B2 (en) * 2001-04-13 2012-08-29 オンセミコンダクター・トレーディング・リミテッド MOSFET
JP2009164288A (en) * 2007-12-28 2009-07-23 Sanken Electric Co Ltd Semiconductor element and semiconductor device
JP5341473B2 (en) * 2008-10-31 2013-11-13 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Semiconductor device and manufacturing method thereof
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110986A (en) * 1999-09-13 2001-04-20 Fairchild Korea Semiconductor Kk Power element with multi-chip package structure and manufacturing method thereof
US8519546B2 (en) 2011-02-24 2013-08-27 Stmicroelectronics S.R.L. Stacked multi-die electronic device with interposed electrically conductive strap

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