JPH04129233A - Semiconductor h bridge circuit - Google Patents
Semiconductor h bridge circuitInfo
- Publication number
- JPH04129233A JPH04129233A JP2251253A JP25125390A JPH04129233A JP H04129233 A JPH04129233 A JP H04129233A JP 2251253 A JP2251253 A JP 2251253A JP 25125390 A JP25125390 A JP 25125390A JP H04129233 A JPH04129233 A JP H04129233A
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- series
- semiconductor
- bridge circuit
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 108091006146 Channels Proteins 0.000 claims description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 13
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 238000007789 sealing Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【発明の詳細な説明】
〔概要〕
電動機等のインダクタンス負荷を駆動制御する８１９７
９回路に関し、特にリードフレーム上にマウント形成さ
れる半導体８７９７９回路に関し、前記課題を解消する
ためになされたもので、プリントと配線板装着時におけ
る実装面積を縮小化できると共に装着作業の簡略化がで
きるは８１９７９回路を提案することを目的とし、
個別の半導体チップで形成される導電形の異なる二つの
トランジスタを各々直列に接続すると共に、当該直列接
続した二つのトランジスタを一の電源と他の電源との間
に並列接続し、前記二つのトランジスタの直列接続にお
ける各接続中点相互間にインダクタンス負荷を接続し、
前記二つのトランジスタの各駆動状態に基づきインダク
タンス負荷に電流を供給する８１９７９回路において、
前記二つのトランジスタの各直列接続端間を共通のリー
ドフレームを介して各々直列接続するものである。[Detailed Description of the Invention] [Summary] 8197 that drives and controls inductance loads such as electric motors
This was done in order to solve the above-mentioned problems regarding the 87979 circuit, especially the semiconductor 87979 circuit mounted on a lead frame, and it is possible to reduce the mounting area during printing and mounting on a wiring board, and to simplify the mounting work. The purpose is to propose an 81979 circuit in which two transistors of different conductivity types formed on individual semiconductor chips are connected in series, and the two series-connected transistors are connected to one power source and another power source. and an inductance load is connected between the middle points of each connection in the series connection of the two transistors,
In an 81979 circuit that supplies current to an inductance load based on each driving state of the two transistors,
The series connection ends of the two transistors are connected in series via a common lead frame.
本発明は、電動機等のインダクタンス負荷を駆動制御す
る８１９７９回路に関し、特にリードフレーム上にマウ
ント形成される半導体８７９７９回路に関する。The present invention relates to an 81979 circuit for driving and controlling an inductance load such as an electric motor, and more particularly to a semiconductor 87979 circuit mounted on a lead frame.
近年、８１９７９回路は、モータドライブ等のインダク
タンス（Ｌ）負荷ドライブに使用され、ドライブ制御の
高精度化から特に重要なものとなってきている。In recent years, the 81979 circuit has been used for inductance (L) load drives such as motor drives, and has become particularly important as drive control becomes more precise.
この８１９７９回路は、ＮチャネルＭＯ８ＦＥＴ又はＮ
ＰＮトランジスタを４個組合せて構成し、またＰチャネ
ルＭＯ８ＦＥＴ、ＰＮＰトランジスタを２個とＮチャネ
ルＭＯ８ＦＥＴ。This 81979 circuit is an N-channel MO8FET or an N-channel MO8FET.
It consists of a combination of four PN transistors, a P-channel MO8FET, two PNP transistors, and an N-channel MO8FET.
ＮＰＮ）ランジスタを２個と各々組合せて構成されるこ
とから、各素子相互間の接続配線が複雑化し、パッケー
ジが大型化することとなる。従って接続配線を簡略化す
ると共に、高密度実装が可能な半導体８７９７９回路が
要求される。Since the device is constructed by combining two (NPN) transistors, the interconnections between the elements become complicated and the package becomes large. Therefore, there is a need for a semiconductor 87979 circuit that simplifies the connection wiring and allows for high-density packaging.
従来、この種の８１９７９回路として第８図及び第９図
に示すものがあった。前記各図において従来の８１９７
９回路は、各々の素子として個別形成されたＰチャネル
ＦＥＴ Ｑ （又はＱ３、）とＮチャネルＦＥＴ
Ｑ （又はＱ４、）とを配線板３０上に直列にボン
ディング接続すると共に、この直接接続の接続中点相互
間にインダクタンス負荷りを接続する構成である。Conventionally, there have been 81979 circuits of this type as shown in FIGS. 8 and 9. In each of the above figures, the conventional 8197
9 circuits include a P-channel FET Q (or Q3,) and an N-channel FET formed individually as each element.
Q (or Q4,) are bonded in series on the wiring board 30, and an inductance load is connected between the connection midpoints of this direct connection.
前記ＰチャネルＦＥＴＱＱ 及びＮチャ１１ゝ ３１
ネルＦＥＴ Ｑ 、Ｑ のゲートに入力される制
２１４制
御信号に基づいてインダクタンス負荷りの励磁方向を切
替え、また０Ｎ−ＯＦＦ制御を行なう。Based on the control signal 214 input to the gates of the P-channel FET QQ and the N-channel FET Q, Q, the excitation direction of the inductance load is switched and ON-OFF control is performed.
なお、前記ＰチャネルＦＥＴ Ｑ ＳＱ とＮチ
ャネルＦＥＴ Ｑ 、Ｑ との組合せ以外にＰＮ
Ｐ ）ランジスタとＮＰＮ ）ランジスタとの組合せ等
により８１９７９回路を構成していた。In addition to the combination of the P-channel FET Q SQ and the N-channel FETs Q and Q, PN
The 81979 circuit was composed of a combination of P) transistors and NPN) transistors.
従来の８１９７９回路は以上にように構成されていたこ
とから、独立に形成された単体としてのＦＥＴやトラン
ジスタにおける端子相互間の接続関係及びリードフレー
ムが複雑なものとなり、またパッケージも大きなものと
なる課題を有していた。Since the conventional 81979 circuit was configured as described above, the connection relationship between the terminals of the independently formed single FET and transistor and the lead frame were complicated, and the package was also large. I had an issue.
本発明は前記課題を解消するためになされたもので、プ
リントと配線板装着時における実装面積を縮小化できる
と共に装着作業の簡略化ができるはＨブリッジ回路を提
案することを目的とする。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to propose an H-bridge circuit that can reduce the mounting area during printing and mounting on a wiring board, and simplify the mounting work.
第１図は本発明の原理説明図を示す。 FIG. 1 shows a diagram explaining the principle of the present invention.
同図において本発明に係る半導体Ｈブリッジ回路回路は
、個別の半導体チップで形成される導電形の異なる二つ
のトランジスタ（Ｑ、、Ｑ ）、（Ｑ３、Ｑ４）を各々
直列に接続すると共に、当該直列接続した二つのトラン
ジスタ（Ｑ 、Ｑ ）、、 （Ｑ ＳＱ ）
を一の電源（Ｖ ）と他の電源（Ｖ２）との間に並列
接続し、■
前記二つのトランジスタ（Ｑ３、Ｑ４）、（Ｑ３、Ｑ４
）の直列接続における各接続中点相互間にインダクタン
ス負荷（Ｌ）を接続し、前記二つのトランジスタ（Ｑ
ＳＱ）、（Ｑ３、Ｑ４）の各駆動状態に基づきインダ
クタンス負荷（Ｌ）に電流を供給するＨブリッジ回路に
おいて、前記二つのトランジスタ（Ｑ３、Ｑ４）、（Ｑ
３、Ｑ４）の各直列接続端（Ｔ、Ｔ）、（Ｔ、Ｔ）間を
共通のリードフレーム（１０，２０）を介して各々直列
接続するものである。In the figure, the semiconductor H-bridge circuit according to the present invention connects in series two transistors (Q, , Q), (Q3, Q4) of different conductivity types formed by individual semiconductor chips, and Two transistors connected in series (Q, Q), (Q SQ)
are connected in parallel between one power supply (V) and the other power supply (V2), and the two transistors (Q3, Q4), (Q3, Q4
), an inductance load (L) is connected between the connection midpoints of the series connection of the two transistors (Q
In the H-bridge circuit that supplies current to the inductance load (L) based on each drive state of the transistors (Q3, Q4) and (Q3, Q4), the two transistors (Q3, Q4) and (Q
3, Q4), the series connection ends (T, T), (T, T) are connected in series via a common lead frame (10, 20).
本発明においては個別の半導体チップで形成される導電
形の異なる二つのトランジスタの直列接続を共通のリー
ドフレームを介して接続することにより、二つのトラン
ジスタの共通する電位レベルにおける各端子を接続する
ことができることとなり、リードフレームを簡略化でき
る。また、共通のリードフレームで直接に二つのトラン
ジスタを直列接続することから、配線板への実装作業を
簡略化できる。In the present invention, two transistors of different conductivity types formed on separate semiconductor chips are connected in series through a common lead frame, thereby connecting respective terminals of the two transistors at a common potential level. This allows the lead frame to be simplified. Furthermore, since the two transistors are directly connected in series using a common lead frame, the mounting work on the wiring board can be simplified.
（ａ）本発明の一実施例
以下、本発明の一実施例を第２図ないし第４図及び第７
図に基づいて説明する。前記第２図は本実施例全体概略
構成図、第３図は本実施例部分拡大図、第４図は第２図
中のＡ−Ａ線拡大断面図を示す。(a) One embodiment of the present invention An embodiment of the present invention will be described below with reference to FIGS. 2 to 4 and 7.
This will be explained based on the diagram. 2 is a schematic diagram of the overall configuration of this embodiment, FIG. 3 is a partially enlarged view of this embodiment, and FIG. 4 is an enlarged sectional view taken along the line A--A in FIG. 2.
前記各図において本実施例に係る半導体Ｈブリッジ回路
は、ＰチャネルＭＯ８ＦＥＴ（以下、Ｐ−ＭＯＳ Ｆ
ＥＴ）Ｑ （又はＱ３）とＮチャネルＭＯＳ ＦＥ
Ｔ （以下、Ｎ−ＭＯＳＦＥＴ）Ｑ２ （又はＱ４）と
をモールド樹脂封止領域３０中に隣接して実装し、前記
Ｐ−ＭＯ８ＦＥＴ ＱｌとＮ−ＭＯＳ ＦＥＴ
Ｑ２との各ドレインをリードフレーム１０を介して接続
すると共に、前記Ｐ−ＭＯ８ＦＥＴ Ｑ３とＮ−ＭＯ
Ｓ ＦＥＴＱ４との各ドレインをリードフレーム２０
を介して接続し、各Ｐ−ＭＯ８゜Ｎ−ＭＯＳの各ＦＥＴ
Ｑ１〜Ｑ４の各ゲート、ソースをモールド樹脂封止領域
３０上の対応するり−ドフレーム１１〜１４．２１〜２
４にボンディングワイヤ１０１〜１０４．２０１〜２０
４により接続する構成である。In each of the above figures, the semiconductor H-bridge circuit according to this embodiment is a P-channel MO8FET (hereinafter referred to as P-MOS FET).
ET) Q (or Q3) and N-channel MOS FE
T (hereinafter referred to as N-MOSFET) Q2 (or Q4) is mounted adjacently in the molded resin sealing area 30, and the P-MO8FET Ql and N-MOSFET
The drains of the P-MO8FET Q2 and the N-MO8FET are connected via the lead frame 10, and the P-MO8FET Q3 and the N-MO
Connect each drain of S FETQ4 to the lead frame 20
each FET of each P-MO8°N-MOS
The respective gates and sources of Q1 to Q4 are connected to the corresponding board frames 11 to 14 and 21 to 2 on the molded resin sealing region 30.
4 bonding wires 101-104.201-20
4.
次に、前記構成に基づ（本実施例回路の実装・結線動作
について説明する。Next, the mounting and wiring operations of the circuit of this embodiment will be explained based on the above configuration.
まず、前記Ｐ−ＭＯ３ＦＥＴ Ｑ、及びＮ−ＭＯＳ
ＦＥＴ Ｑ２をモールド樹脂封止領域３０中に形成
されるリードフレーム１０上に各サブストレーｈｓＵＢ
を接触させてマウントすると共に、前記Ｐ−ＭＯ８ＦＥ
Ｔ Ｑ３及びＮ−ＭＯＳ ＦＥＴ Ｑ４をＩＪ−
ドア１／−ム２０上に各サブストレートＳＵＢを接触さ
せてマウントする。前記マウントによりＰ−ＭＯＳ
ＦＥＴＱｌ及びＮ−ＭＯＳ ＦＥＴ Ｑ２の各ドレ
インＤ、Ｄ２はリードフレーム１０を介して接続される
こととなる。また、前記Ｐ−ＭＯ８ＦＥＴＱ３及びＮ−
ＭＯＳ ＦＥＴ Ｑ４の各ドレインＤ ＳＤ ４
はリードフレーム２０を介して接続される。First, the P-MO3FET Q and the N-MOS
FET Q2 is placed on each substray hsUB on the lead frame 10 formed in the molded resin sealing area 30.
At the same time, the P-MO8FE is mounted in contact with the P-MO8FE.
T Q3 and N-MOS FET Q4 to IJ-
Mount each substrate SUB in contact on the door 1/-20. The mount allows P-MOS
The drains D and D2 of the FET Ql and the N-MOS FET Q2 are connected via the lead frame 10. In addition, the P-MO8FETQ3 and N-
Each drain D SD 4 of MOS FET Q4
are connected via a lead frame 20.
また、前記各Ｐ−ＭＯ３，Ｎ−ＭＯ３ＦＥＴＱ１〜Ｑ４
は各ゲート０１〜Ｇ４及びソースｓ１〜Ｓ４を対応する
リードフレーム１１〜１４．２１〜２４にワイヤボンデ
ィング接続されることにより、実装を完了する。In addition, each of the P-MO3, N-MO3FETQ1 to Q4
The mounting is completed by connecting each gate 01-G4 and source s1-S4 to the corresponding lead frame 11-14 and 21-24 by wire bonding.
さらに、前記実装された本実施例回路の動作は次の通り
である。Furthermore, the operation of the implemented circuit of this embodiment is as follows.
前記第４図においてＰ−ＭＯＳ ＦＥＴ Ｑ。In FIG. 4, P-MOS FET Q.
はゲートＧ１に所定レベルの電圧が印加されると、ｎ−
ウェル中にｐ形のチャネル（斜線部分）の伝導層が形成
されることとなり、ソース電極Ｓ１及びアルミ配線層Ａ
７からＰ形波散層−チャネルＰ層−Ｐ＋層−サブストレ
ートＳＵＢを介してリードフレーム１０のドレインＤＩ
へ正孔が移動して電流が流れることとなる。When a voltage of a predetermined level is applied to the gate G1, n-
A p-type channel (hatched area) conductive layer is formed in the well, and the source electrode S1 and aluminum wiring layer A
7 to the drain DI of the lead frame 10 via the P-type dispersion layer-channel P layer-P+ layer-substrate SUB
Holes move to the hole, causing current to flow.
同様にして前記Ｎ −Ｍ ＯＳ Ｆ Ｅ Ｔ Ｑ
２についてもゲートＧ２に所定の電圧が印加されるとド
レインＤ２からソース電極Ｓ２へチャネルを介して電子
が移動して電流が流れることとなる。Similarly, the N-MOS FETQ
2 as well, when a predetermined voltage is applied to the gate G2, electrons move from the drain D2 to the source electrode S2 via the channel, causing a current to flow.
前記Ｐ−ＭＯ８ＦＥＴ Ｑｌ及びＮ−ＭＯ８ＦＥＴＱ
２の共通ドレインがチップ下面側に形成されることから
、各チップをリードフレーム１０上に実装するだけで別
途ワイヤボンディング接続することなく各ドレインを接
続することができることとなる
また、Ｐ −Ｍ ＯＳ Ｆ Ｅ Ｔ Ｑ ３及びＮ
−ＭＯＳ ＦＥＴ Ｑ４の接続においても、前記Ｐ
−ＭＯ８ＦＥＴ Ｑｌ及びＮ−ＭＯＳＦＥＴ Ｑ２の
接続と同様に各ドレインを接続できることとなる。Said P-MO8FET Ql and N-MO8FETQ
Since the common drains of the two chips are formed on the bottom side of the chip, it is possible to connect each drain by simply mounting each chip on the lead frame 10 without making separate wire bonding connections. F E T Q 3 and N
- Also in the connection of MOS FET Q4, the above P
-Each drain can be connected in the same way as the connection of MO8FET Ql and N-MOSFET Q2.
（ｂ）本発明の他の実施例 第５図に本発明の他実施例全体概略構成図を示す。(b) Other embodiments of the present invention FIG. 5 shows a schematic diagram of the overall configuration of another embodiment of the present invention.
同図において他の実施例回路はモールド樹脂封止領域３
０の表面側に形成されリードフレーム１０上にＰ −Ｍ
ＯＳ Ｆ Ｅ Ｔ Ｑ ｌをマウントし、同じ表
面側のリードフレーム２０上にＰ−ＭＯＳＦＥＴ Ｑ３
をマウントすると共に、前記モールド樹脂封止領域３０
の裏面側のリードフレーム１０上にＮ −Ｍ ＯＳ
Ｆ Ｅ Ｔ Ｑ ２をマウントし、同じ裏面側のリー
ドフレーム２０上にＮ−ＭＯ８ＦＥＴＱ４をマウントす
る構成である。In the figure, another example circuit is a molded resin sealed area 3.
P-M is formed on the surface side of lead frame 10.
Mount the OS FET Q1 and place the P-MOSFET Q3 on the lead frame 20 on the same surface side.
At the same time, the mold resin sealing area 30 is mounted.
N-M OS is placed on the lead frame 10 on the back side of the
The structure is such that the FET Q2 is mounted and the N-MO8FETQ4 is mounted on the lead frame 20 on the same back side.
このように、リードフレーム１０．２０の表面上にマウ
ントされたＰ−ＭＯＳ ＦＥＴＱ 及びＮ−ＭＯＳ
ＦＥＴ Ｑ ＳＰ−ＭＯＳｉ２
ＦＥＴ Ｑ 及びＮ−ＭＯＳ ＦＥＴ Ｑ４（
７）各ドレインＤ ｔ ”” Ｄ ４が共通のリードフ
レームを介して接続され、各ドレインＤ −Ｄ４とリ
ードフレーム１０．２０との間にワイヤボンディング接
続を行なうことなく接続することができることとなる。In this way, the P-MOS FETQ and N-MOS mounted on the surface of the lead frame 10.20
FET Q SP-MOSi2 FET Q and N-MOS FET Q4 (
7) Each drain D t "" D 4 is connected via a common lead frame, so that the connection can be made without making a wire bonding connection between each drain D - D4 and the lead frame 10.20. .
なお、Ｐ−ＭＯＳ、Ｎ−ＭＯＳの各ＦＥＴＱ１〜Ｑ の
各ゲートＧ −Ｇ 、ソースＳ１〜Ｓ４と対応する
リードフレーム１１〜１４．２１〜２４との間はワイヤ
ボンディングにより接続される。Note that the gates GG and sources S1 to S4 of the P-MOS and N-MOS FETs Q1 to Q and the corresponding lead frames 11 to 14 and 21 to 24 are connected by wire bonding.
前記のようにリードフレームの表裏面にＰ−ＭＯＳ、Ｎ
−ＭＯＳ（７）各ＦＥＴＱ１〜Ｑ４を実装することによ
り、配線が簡略化できると共に実装密度をさらに向上さ
せることができる。As mentioned above, P-MOS, N
-MOS (7) By mounting each of the FETs Q1 to Q4, the wiring can be simplified and the packaging density can be further improved.
（ｃ）本発明のその他の実施例
第６図に本発明のその他の実施例全体概略構成図を示す
。(c) Other Embodiments of the Present Invention FIG. 6 shows a general schematic diagram of another embodiment of the present invention.
同図においてその他の実施例回路はモールド樹脂封止領
域３０の表裏面におけるリードフレーム１０．２０．３
０．４０上に８ケのＭＯＳＦＥＴをマウント実装する構
成である。この他の実施例回路の回路構成図を第７図に
示す。In the figure, other example circuits are lead frames 10, 20, 3 on the front and back surfaces of the molded resin sealing area 30.
This is a configuration in which 8 MOSFETs are mounted on a 0.40mm. A circuit configuration diagram of this other embodiment circuit is shown in FIG.
このように、多相モータＭの制御に用いられるＨブリッ
ジ回路の実装密度もさらに向上させることができること
となる。In this way, the mounting density of the H-bridge circuit used to control the multiphase motor M can also be further improved.
なお、前記各実施例においては共通するリードフレーム
を介してＰ−ＭＯＳ ＦＥＴとＮ−ＭＯＳ ＦＥＴ
とを接続する構成としたが、ＰＮＰ トランジスタとＮ
ＰＮ トランジスタとをリードフレームを介して接続し
てＨブリッジ回路を構成することもできる。また、ＰＮ
ＰトランジスタとＮ−ＭＯＳ ＦＥＴとをリードフレ
ームを介して接続してＨブリッジ回路を構成することが
できる。In each of the above embodiments, the P-MOS FET and the N-MOS FET are connected via a common lead frame.
However, the PNP transistor and the N
An H-bridge circuit can also be configured by connecting a PN transistor via a lead frame. Also, P.N.
An H-bridge circuit can be configured by connecting a P transistor and an N-MOS FET via a lead frame.
以上説明したように、本発明においては個別の半導体チ
ップで形成される導電形の異なる二つのトランジスタの
直列接続を共通のリードフレームを介して接続すること
により、二つのトランジスタの共通する電位レベルにお
ける各端子を接続することができることとなり、リード
フレームを簡酪化できる。また、共通のリードフレーム
で直接に二つのトランジスタを直列接続することから、
配線板への実装作業を簡略化できるという効果を有する
。As explained above, in the present invention, by connecting two transistors of different conductivity types formed on individual semiconductor chips in series through a common lead frame, a common potential level of the two transistors can be maintained. Since each terminal can be connected, the lead frame can be simplified. In addition, since two transistors are directly connected in series using a common lead frame,
This has the effect of simplifying the mounting work on the wiring board.
第１図は本発明の原理説明図、
第２図は本発明の一実施例全体概略構成図、第３図は第
２図記載実施例の部分拡大図、第４図は第２図記載実施
例のＡ−Ａ線部分拡大断面図、
第５図は本発明の他の実施例全体概略構成図、第６図は
本発明のその他の実施例全体概略構成図、
第７図は第６図記載実施例の回路構成図、第８図はＨブ
リッジ回路の構成図、
第９図は従来のＨブリッジ回路の概略構成図である。
Ｑ ％Ｑ３・・・Ｐ−ＭＯＳ ＦＥＴ （）ランジス
り）
Ｑ２、Ｑ４・・Ｐ−ＭＯＳ ＦＥＴ
（トランジス
タ）
Ｔ −Ｔ４・・・接続端
３０・・・モールド樹脂封止領域
１０１〜１０４．２０１〜２０４
グワイヤ
Ｌ・・・インダクタンス負荷
・ホンデインFig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an overall schematic diagram of an embodiment of the present invention, Fig. 3 is a partially enlarged view of the embodiment shown in Fig. 2, and Fig. 4 is an implementation of the embodiment shown in Fig. 2. FIG. 5 is a schematic diagram of the overall configuration of another embodiment of the present invention; FIG. 6 is a schematic diagram of the entire configuration of another embodiment of the present invention; FIG. A circuit configuration diagram of the described embodiment, FIG. 8 is a configuration diagram of an H-bridge circuit, and FIG. 9 is a schematic configuration diagram of a conventional H-bridge circuit. Q %Q3...P-MOS FET () Q2, Q4...P-MOS FET (transistor) T-T4...Connection end 30...Mold resin sealing area 101~104.201~ 204 Gwire L...Inductance load/Hondain
Claims (1)
Ｑ＿３、Ｑ＿４）を各々直列に接続すると共に、当該直
列接続した二つのトランジスタ（Ｑ＿１、Ｑ＿２）、（
Ｑ＿３、Ｑ＿４）を一の電源（Ｖ＿１）と他の電源（Ｖ
＿２）との間に並列接続し、前記二つのトランジスタ（
Ｑ＿１、Ｑ＿２）、（Ｑ＿３、Ｑ＿４）の直列接続にお
ける各接続中点相互間にインダクタンス負荷（Ｌ）を接
続し、前記二つのトランジスタ（Ｑ＿１、Ｑ＿２）、（
Ｑ＿３、Ｑ＿４）の各駆動状態に基づきインダクタンス
負荷（Ｌ）に電流を供給するＨブリッジ回路において、 前記二つのトランジスタ（Ｑ＿１、Ｑ＿２）、（Ｑ＿３
、Ｑ＿４）の各直列接続端（Ｔ＿１、Ｔ＿２）、（Ｔ＿
２、Ｔ＿３）間を共通のリードフレーム（１０、２０）
を介して接続することを 特徴とする半導体Ｈブリッジ回路。 ２、前記請求項１記載の半導体Ｈブリッジ回路において
、 前記異なる導電形の二つのトランジスタ（Ｑ＿１、Ｑ＿
２）、（Ｑ＿３、Ｑ＿４）は共通するリードフレーム（
１０又は２０）の各表・裏面に設けられ、前記リードフ
レーム（１０又は２０）を介して各接続端（Ｔ＿１、Ｔ
＿２）、（Ｔ＿３、Ｔ＿４）を各々直列接続することを 特徴とする半導体Ｈブリッジ回路。 ３、前記請求項１又は２記載の半導体Ｈブリッジ回路に
おいて 前記導電形の異なる二つのトランジスタ（Ｑ＿１、Ｑ＿
２）、（Ｑ＿３、Ｑ＿４）はＰ形チャネルＦＥＴとＮ形
チャネルＦＥＴとを直列接続することを特徴とする半導
体Ｈブリッジ回路。 ４、前記請求項１又は２記載の半導体Ｈブリッジ回路に
おいて、 前記異なる導電形の二つのトランジスタ（Ｑ＿１、Ｑ＿
２）、（Ｑ＿３、Ｑ＿４）はＰＮＰ形トランジスタとＮ
ＰＮ形トランジスタとを直列接続することを特徴とする
半導体Ｈブリッジ回路。 ５、前記請求項１又は２記載の半導体Ｈブリッジ回路に
おいて、 前記異なる導電形の二つのトランジスタ（Ｑ＿１、Ｑ＿
２）、（Ｑ＿３、Ｑ＿４）はＰＮＰ形トランジスタとＮ
チャンネルＦＥＴとを直列接続することを特徴とする半
導体Ｈブリッジ回路。[Claims] 1. Two transistors (Q_1, Q_2) of different conductivity types formed on individual semiconductor chips, (
Q_3, Q_4) are connected in series, and the two series-connected transistors (Q_1, Q_2), (
Q_3, Q_4) from one power supply (V_1) and the other power supply (V
_2), and the two transistors (
An inductance load (L) is connected between each connection center point in the series connection of Q_1, Q_2), (Q_3, Q_4), and the two transistors (Q_1, Q_2), (
In the H-bridge circuit that supplies current to the inductance load (L) based on each drive state of the two transistors (Q_1, Q_2), (Q_3)
, Q_4), each series connection terminal (T_1, T_2), (T_
2, T_3) with a common lead frame (10, 20)
A semiconductor H-bridge circuit characterized in that it is connected via. 2. In the semiconductor H-bridge circuit according to claim 1, the two transistors of different conductivity types (Q_1, Q_
2), (Q_3, Q_4) are common lead frames (
10 or 20), and each connection end (T_1, T
_2), (T_3, T_4) are each connected in series. 3. In the semiconductor H-bridge circuit according to claim 1 or 2, the two transistors of different conductivity types (Q_1, Q_
2), (Q_3, Q_4) are semiconductor H-bridge circuits characterized by connecting a P-type channel FET and an N-type channel FET in series. 4. In the semiconductor H-bridge circuit according to claim 1 or 2, the two transistors of different conductivity types (Q_1, Q_
2), (Q_3, Q_4) are PNP type transistors and N
A semiconductor H-bridge circuit characterized by connecting a PN type transistor in series. 5. In the semiconductor H-bridge circuit according to claim 1 or 2, the two transistors of different conductivity types (Q_1, Q_
2), (Q_3, Q_4) are PNP type transistors and N
A semiconductor H-bridge circuit characterized by connecting a channel FET in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2251253A JPH04129233A (en) | 1990-09-19 | 1990-09-19 | Semiconductor h bridge circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2251253A JPH04129233A (en) | 1990-09-19 | 1990-09-19 | Semiconductor h bridge circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04129233A true JPH04129233A (en) | 1992-04-30 |
Family
ID=17220020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2251253A Pending JPH04129233A (en) | 1990-09-19 | 1990-09-19 | Semiconductor h bridge circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04129233A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006060255A (en) * | 2005-11-07 | 2006-03-02 | Nec Electronics Corp | Leadless package semiconductor device |
| JP2006066712A (en) * | 2004-08-27 | 2006-03-09 | Sanyo Electric Co Ltd | Circuit device with full bridge circuit packaged therein and data recording apparatus using the same |
| JP2007073581A (en) * | 2005-09-05 | 2007-03-22 | Renesas Technology Corp | Semiconductor device |
| JP2009065201A (en) * | 2008-11-20 | 2009-03-26 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
| JP2011108946A (en) * | 2009-11-19 | 2011-06-02 | Aisin Seiki Co Ltd | Method of mounting transistor, and electronic component |
-
1990
- 1990-09-19 JP JP2251253A patent/JPH04129233A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006066712A (en) * | 2004-08-27 | 2006-03-09 | Sanyo Electric Co Ltd | Circuit device with full bridge circuit packaged therein and data recording apparatus using the same |
| JP4587743B2 (en) * | 2004-08-27 | 2010-11-24 | 三洋電機株式会社 | Circuit equipment |
| JP2007073581A (en) * | 2005-09-05 | 2007-03-22 | Renesas Technology Corp | Semiconductor device |
| JP2006060255A (en) * | 2005-11-07 | 2006-03-02 | Nec Electronics Corp | Leadless package semiconductor device |
| JP2009065201A (en) * | 2008-11-20 | 2009-03-26 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
| JP2011108946A (en) * | 2009-11-19 | 2011-06-02 | Aisin Seiki Co Ltd | Method of mounting transistor, and electronic component |
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