JP4788478B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device having a vertical overflow barrier structure that discharges excess charges in the depth direction of a semiconductor.

  A solid-state imaging device (also referred to as a solid-state imaging device or an image sensor) having a charge generation unit (sensor unit) including a plurality of photoelectric conversion elements (photodiodes or the like) in an imaging unit is used as a means for capturing an image in various fields. It's being used.

  In general, solid-state imaging devices receive light incident from the light-receiving surface with each light-receiving element composed of photodiodes, etc., perform photoelectric conversion, detect the generated charges with a detection circuit, then amplify and output sequentially To do.

  As one configuration example of the solid-state imaging device, a P-type impurity (P well) as a second conductivity type semiconductor layer is formed on an N-type silicon substrate (first conductivity type semiconductor substrate), and the second conductivity A sensor unit (light receiving unit) including a charge storage layer (hereinafter also referred to as a first sensor region) formed by ion-implanting a first conductivity type impurity into a type semiconductor layer is formed. Signal charges obtained by receiving light and performing photoelectric conversion are accumulated in the charge accumulation layer.

  By the way, in a general solid-state imaging device, excessive charges are generated by strong light from a high illuminance portion of a subject, and the reproduced image is damaged by the excessive charges, and a blooming phenomenon and a smear phenomenon occur.

  As an example of a method for solving this problem, a method of providing an overflow drain between adjacent channels and absorbing excess charge by this overflow drain, or a vertical overflow barrier provided with an overflow drain in the depth direction of the sensor A method of using an (OFB: Over Flow Barrier) structure and absorbing excess charges with a vertical (depth direction) overflow drain is considered (for example, see Patent Documents 1 to 3).

  The former method, in which an overflow drain is provided between adjacent channels, causes a problem of lowering the aperture ratio, whereas the latter method using a vertical overflow barrier structure causes excess charge to be obtained without reducing the aperture ratio. There is an advantage that can be absorbed.

Japanese Patent No. 2576813 JP 2001-185711 A JP 2000-091550 A

  FIG. 7 is a diagram for explaining a conventional CCD solid-state imaging device having a vertical overflow barrier structure. Here, FIG. 7A is a diagram showing an impurity configuration of a cross section in the sensor horizontal direction of the unit cell. FIG. 7B is a diagram showing a potential profile in the depth direction in the unit cell, and FIG. 7C is a diagram showing signal charge accumulation characteristics.

  As shown in FIG. 7A, in the unit cell, a first P well region PW1 of a P type semiconductor well is formed on the surface of a semiconductor substrate NSUB made of, for example, N − type silicon, and on the first P well region PW1. The first conductive type semiconductor region, the signal charge readout unit RO for reading out the signal charges accumulated in the photosensitive unit SENS, the transfer register CCD (Charge Coupled Device), and the channel as the element isolation unit The stop CS is formed in the horizontal direction in this order, and the structure of the base is the same as that of IT (interline) -CCD.

  The first P well region PW1 is a semiconductor region of a second conductivity type different from the first conductivity type of the photosensitive portion SENS, and its junction depth is shallow below the photosensitive portion SENS and is a transfer register CCD which is a transfer region. The overflow barrier region OFB is formed in the entire lower portion of the photosensitive portion SENS.

  The photosensitive portion SENS is a photodiode-type photosensitive element, and includes an N + type semiconductor region as a first conductivity type selectively formed on a surface of a region having a shallow junction depth of the first P well region PW1. It functions as a charge accumulation region for generating and accumulating charges.

  The channel stop portion CS is formed on the surface of the first P well region PW1 so as to surround the photosensitive portion SENS and is made of a P + type semiconductor region.

  The transfer register CCD has a structure in which a buried channel BC is provided on a second P well region PW2 formed on the first P well region PW1. Between the buried channel BC and the photosensitive portion SENS in the sensor surface portion, the signal charge reading portion RO connecting the photosensitive portion SENS and the transfer register CCD is formed by interposing the second P well region PW2. It is like that.

  The second P well region PW2 of the signal charge readout portion RO is formed of a P − type semiconductor region having a concentration lower than the impurity concentration of the channel stop portion CS.

  A silicon oxide film (not shown) that covers the semiconductor surface is formed on the sensor surface, and the reading electrode and the transfer electrode are arranged so as to cover the buried channel BC and the signal charge reading portion RO with the silicon oxide film interposed therebetween. An electrode EL that is also used is formed.

  However, in the conventional vertical overflow drain, the electronic barrier shutter is performed by adjusting the height of the overflow barrier with the substrate potential. In addition, since the overflow barrier is formed deep in the substrate, it is formed thin and horizontally with a uniform concentration. In addition, the vertical transfer path and the photodiode are completely depleted for charge transfer.

  Therefore, the coupling between the surface P + at the GND (ground) level and the overflow barrier is weak, and when the charge accumulates in the photodiode exceeding the saturation level, the overflow barrier is gradually increased as compared with when the charge is empty. The barrier potential of the region fluctuates (see, for example, paragraphs 6 to 12 of Patent Document 1). As a result, the practical saturation increases following the electron concentration.

  As shown in FIG. 7C, the dependence of charge accumulation and light amount in a solid-state imaging device having a vertical overflow drain structure increases with a constant proportion, usually proportional, according to the amount of light. A saturation level is reached at a certain point. There, excess electrons are swept away by the substrate.

  However, the potential profile is not invariant and changes depending on the amount of signal charge accumulated in the photosensitive portion SENS. When the amount of signal charge increases, the barrier potential also moves upward in FIG. 7B. That is, the potential barrier of the overflow barrier region OFB rises.

  As a result, even if the overflow is started, not all the signal charges exceeding the barrier at the start of charge accumulation are absorbed by the semiconductor substrate NSUB, and a part is accumulated in the photosensitive portion SENS. . That is, in practice, if the light quantity continues to increase above the saturation level, the signal charge continues to accumulate beyond the saturation level.

  For this reason, it is not possible to completely eliminate all excess charges from the photosensitive portion SENS to the semiconductor substrate NSUB. As a result, as shown in FIG. The signal charge will rise slightly. When such characteristics exist, various problems related to these characteristics also arise. Such a characteristic is generally called a knee characteristic.

  In other words, in general, an intense light exceeding the saturation signal level is also present in the subject image, and light exceeding the saturation signal level accumulated in the photodiode is transferred to the charge transfer path (transfer register CCD). ). If it cannot be carried, it will overflow the pixels above and below the charge transfer path, causing a phenomenon similar to blooming in the charge transfer path.

  On the other hand, the signal charge above the saturation signal level is rarely used as an actual image and exceeds the dynamic range of the output signal, so that it is forcibly clipped in the subsequent signal processing. Thus, charge accumulation due to knee characteristics is a wasteful charge.

  However, in practice, the useless charge must not overflow in the charge transfer path, so it is common to take the ability to carry charge in the charge transfer path, for example, twice the saturation level.

  Therefore, it is necessary to increase the width of the charge transfer path in order to improve the capacity of the charge transfer path for carrying the knee component signal charge. As a result, the area of the photodiode is reduced, which hinders miniaturization. Further, it is possible to increase the transfer capability by increasing the amplitude of the electrode, but in this case, the power consumption is increased.

  The problem related to these charge transfer paths is applicable not only to the vertical transfer register V-CCD but also to the horizontal transfer register H-CCD.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a mechanism capable of improving knee characteristics at the time of excess charge in a solid-state imaging device having a vertical overflow barrier structure.

In the mechanism according to the present invention, the potential barrier of the overflow barrier region depending on the amount of signal charge accumulated in the charge accumulation region is formed around the overflow barrier region which is the second conductivity type semiconductor region below the charge accumulation region. A device structure provided with a potential fluctuation suppressing semiconductor region for suppressing fluctuation was used. This potential fluctuation suppressing semiconductor region is a region formed of the second conductivity type having a higher concentration than the overflow barrier region formed of the second conductivity type semiconductor region.

  Various device structures can be adopted for the device structure including such a potential variation suppressing semiconductor region. First, an element isolation region for isolation from an adjacent unit cell is a potential variation suppressing semiconductor. A structure that also serves as a region is preferable. By doing so, it is not necessary to provide a potential variation suppressing semiconductor region separately from the element isolation region, so that the device structure of the present invention can be realized without increasing the element area.

  In addition, the potential fluctuation suppressing semiconductor region may be formed so as to surround only a part of the overflow barrier region. However, in order to suppress the potential fluctuation, the potential fluctuation suppressing semiconductor region is arranged around the entire overflow barrier region. It is effective to form so as to surround.

  For this purpose, it is possible to adopt a method in which only the first potential fluctuation suppressing semiconductor region that is also used as the element isolation region is formed so as to surround the entire periphery of the overflow barrier region below the charge storage region.

  In this case, in the case of a CCD type solid-state imaging device, the potential fluctuation suppressing semiconductor region is also used as an element isolation region only under the charge storage region in order to reduce the influence of signal charge reading and transfer. The first potential fluctuation suppressing semiconductor region may surround the entire periphery of the overflow barrier region.

  Alternatively, by providing two types of potential fluctuation suppressing semiconductor regions, the first potential fluctuation suppressing semiconductor region that is also used as the element isolation region surrounds one side of the overflow barrier region, and the signal charge reading unit, It is also conceivable that a second potential fluctuation suppressing semiconductor region is provided also below the charge transfer portion, and the second potential fluctuation suppressing semiconductor region surrounds the other side of the overflow barrier region.

  In this case, in order to reduce the influence of the second potential fluctuation suppressing semiconductor region on signal charge reading and charge transfer, the second potential fluctuation suppressing semiconductor region extends below the charge transfer portion. Instead, it is preferable to keep it under the signal charge reading portion.

  When two types of potential fluctuation suppressing semiconductor regions are provided, the second potential fluctuation suppressing semiconductor region is connected to the first potential fluctuation suppressing semiconductor region so as to substantially surround the entire periphery of the overflow barrier region. The second potential fluctuation suppressing semiconductor region can be separated from the first potential fluctuation suppressing semiconductor region so as not to be connected to surround only a part of the overflow barrier region. It is also possible to take a method of forming as follows. Of course, the first potential fluctuation suppressing semiconductor region also used as the element isolation region may be formed so as to surround only a part of the overflow barrier region.

  According to the present invention, since the device structure is provided with the potential fluctuation suppressing semiconductor region for suppressing the fluctuation of the potential barrier depending on the accumulation amount of the signal charge around the overflow barrier region, the signal charge is higher than the saturation level. When trying to accumulate, it is possible to suppress the potential near the overflow barrier region from being affected by the potential variation of the potential variation suppressing semiconductor region and to attempt to vary the barrier potential as compared with the conventional case. As a result, it is possible to suppress knee characteristics resulting from the accumulation of signal charges exceeding the saturation level. Since the knee characteristic can be suppressed, various problems related to the knee characteristic can be solved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Overall configuration of imaging device>
FIG. 1 is a configuration diagram illustrating an embodiment of an imaging apparatus (camera system) that is an example of an electronic apparatus. Here, an example using an interline transfer (IT) type CCD solid-state imaging device is shown. The vertical transfer electrode is shown in the case of a two-field readout method.

  Here, in a general IT type CCD solid-state imaging device, a large number of sensor units (photocells, light receiving sensors) are arranged in a two-dimensional matrix, and a plurality of vertical lines are arranged between photocells in each vertical column. A transfer CCD (V register) is arranged, and a horizontal transfer CCD is usually provided for one line adjacent to the vertical transfer CCD in the last row. This will be specifically described below.

  As shown in the figure, the imaging apparatus 1 of the present embodiment includes an IT-type CCD solid-state imaging element 10 and a drive control unit 50 that is an example of a driving apparatus that drives the CCD solid-state imaging element 10.

  Although not shown, the imaging device 1 includes an imaging device module including an imaging lens (not shown) in addition to the CCD solid-state imaging device 10 and the drive control unit 50 shown in the drawing. In addition, a main unit for generating a video signal based on an imaging signal obtained by an imaging device module and outputting it to a monitor or storing an image in a predetermined storage medium is provided as a whole, for example, a video camera or a digital still camera. Etc. are configured. The imaging device module is preferably provided as a CCD solid-state imaging device 10 and a drive control unit 50 arranged on a single circuit board.

  The processing system of the imaging apparatus 1 is roughly divided into an optical system, an image processing unit, a signal processing system mainly including CODEC (abbreviation of Code / Decode or Compression / Decompression), and image data compressed by CODEC in a predetermined storage. A recording system for recording on a medium, a display system for displaying an image on a predetermined display device such as a liquid crystal display (LCD), and a control system for controlling each part of the imaging apparatus 1 are configured. Needless to say, the imaging device module and the main unit are housed in an exterior case (not shown), and an actual product (finished product) is finished.

  The optical system includes a shutter, a lens that collects a light image of a subject, and an imaging lens that has a diaphragm that adjusts the amount of light of the light image, and a CCD solid-state imaging that photoelectrically converts the collected light image into an electrical signal It is comprised from the element 10. FIG. The light from the subject passes through the shutter and the imaging lens, is adjusted by the diaphragm, and enters the CCD solid-state imaging device 10 with an appropriate brightness. At this time, the imaging lens adjusts the focal position so that an image composed of light from the subject is formed on the CCD solid-state imaging device 10.

  In addition to the drive control unit 50, the control system controls the disk drive device to read the control program stored in the magnetic disk, optical disk, magneto-optical disk, or semiconductor memory, and the read control program or user A central control unit including a CPU (Central Processing Unit) that controls the entire image pickup apparatus 1 based on a command or the like is provided.

  The control system also includes an exposure controller that controls the shutter and the diaphragm so that the brightness of the image sent to the image processing unit is maintained at an appropriate level, and each functional unit from the CCD solid-state imaging device 10 to the image processing unit and the CODEC. A drive control unit 50 having a timing signal generation unit (timing generator; TG) for controlling the operation timing of the camera, and an operation unit for a user to input shutter timing and other commands.

  The central control unit controls the image processing unit, the CODEC, the memory, the exposure controller, and the timing signal generation unit that are connected to the bus of the imaging apparatus 1.

  Here, the drive control unit 50 receives a timing signal generation unit 52 that generates clock pulses, which are various pulse signals for driving the CCD solid-state imaging device 10, and a pulse signal from the timing signal generation unit 52. A driver (drive unit) 54 that converts the drive pulse to drive the CCD solid-state image sensor 10 and a drive power source 56 that supplies power to the CCD solid-state image sensor 10 and the driver 54 are provided.

  As an example, the timing signal generation unit 52 reads the signal charge from the sensor unit (light receiving sensor) 11 to the vertical transfer register 13 and drives the CCD solid-state imaging device 10 in four phases in the vertical direction. Four types of vertical transfer clocks V1 to V4, two types of horizontal transfer clocks H1 and H2 for driving in two phases in the horizontal direction, an electronic shutter pulse XSG, and the like are supplied to the driver 54.

  Based on the read clock ROG received from the timing signal generator 52 and the vertical transfer clocks V1 to V4, the driver 54 drives a binary-level or ternary-level drive pulse (vertical transfer) to drive the vertical transfer register 13 in the vertical transfer mode. Pulses) [Phi] V1 to [Phi] V4 and drive pulses (horizontal transfer pulses) [Phi] H1 and [Phi] H2 for horizontally transferring the horizontal transfer register 15 are generated. Of the drive pulses (vertical transfer pulses) ΦV1 and ΦV3 having ternary levels of L (low) / H (high) / SH (super high), the SH level drive pulse portion corresponding to the read clock ROG is particularly selected. This is called a read pulse ΦROG.

  In the CCD solid-state imaging device 10, a plurality of sensor units 11 serving as pixels are arranged in a two-dimensional matrix, and a plurality of CCD structures vertically extending in the vertical direction corresponding to each light receiving sensor column. An image pickup unit (light receiving unit) 10a in which a transfer register (an example of a first charge transfer unit) 13 is formed is provided. The sensor unit 11 converts incident light into a signal charge having a charge amount corresponding to the amount of light, and accumulates the signal light. Although not shown, an on-chip color filter is provided on the light receiving surface of the sensor unit 11 in order to cope with color imaging.

  In the imaging unit 10a, the signal charge readout that further reads out the signal charges accumulated in the sensor unit 11 as a charge accumulation region to the vertical transfer register 13 as a charge transfer path between the vertical transfer register 13 and each sensor unit 11. A reading gate portion ROG as a portion is interposed, and a channel stop portion as an element isolation region for separating from an adjacent unit cell is provided at a boundary portion of each pixel (unit cell). In particular, a channel stop portion in the horizontal direction between adjacent unit cells is defined as a channel stop portion CS1.

  A horizontal transfer register 15 having a CCD structure extending in the left-right direction in the drawing is formed for one line so as to be connected to the final stage of each vertical transfer register 13 outside the imaging unit 10a. An output amplifier unit 17 as a charge detection unit (or output unit) that converts a charge signal into an electric signal (usually a voltage signal) is connected to the subsequent stage of the horizontal transfer register 15.

  The output amplifier unit 17 accumulates signal charges sequentially injected from the horizontal transfer register 15 in a floating diffusion (not shown), converts the accumulated signal charges into a signal voltage, and is configured by, for example, a transistor circuit having a source follower configuration (not shown). Through the output circuit, a CCD output signal Sout is output from the output terminal tout to the outside of the device.

  On the vertical transfer register 13 extending in the column (vertical) direction (on the light receiving surface side), four types of vertical transfer electrodes 12 (each of which is common to the vertical transfer register 13 at the same vertical position in each column) Are attached so as to form openings (see FIG. 2 to be described later) in the light receiving surface of the sensor unit 11 in a predetermined order in the vertical direction. Has been.

  The four types of vertical transfer electrodes 12 are generally formed so that one sensor portion 11 corresponds to the entirety of one vertical transfer electrode 12 and part of the vertical transfer electrodes 12 on both sides thereof, and is driven and controlled. The signal charges are transferred and driven in the vertical direction by four types of vertical transfer pulses ΦV_1, ΦV_2, ΦV_3, and ΦV_4 supplied from the unit 50.

  That is, two of the four types of vertical transfer electrodes 12 correspond to only one sensor unit 11, and two types of vertical transfer electrodes arranged on both sides of the vertical transfer electrode 12 corresponding to only one sensor unit 11. The transfer electrode 12 is disposed so as to correspond to the sensor units 11 on both sides. Further, the two sensor units 11 are combined into one set (including the final stage on the horizontal transfer register 15 side), and vertical transfer pulses ΦV_1, ΦV_2, ΦV_3, and ΦV_4 are respectively supplied from the drive control unit 50 to the four vertical transfer electrodes 12. It is to be applied.

  In the illustrated example, on the horizontal transfer register 15 side, a vertical transfer electrode 12 is provided for each set corresponding to one set of four vertical transfer registers 13 in the vertical direction, and among them, the vertical transfer electrode 12 is provided at the top in the vertical direction. The sensor unit 11_1 positioned corresponds to the first vertical transfer electrode 12_1 also serving as a read electrode to which the three-level vertical transfer pulse ΦV_1 is applied. Further, a binary level vertical transfer pulse ΦV_2 is applied to the second vertical transfer electrode 12_2 one stage ahead (more on the horizontal transfer register 15 side). Further, the sensor unit 11_3 located at the second stage in the vertical direction further receives the third vertical transfer electrode 12_3 serving also as a read electrode to which the three-level vertical transfer pulse ΦV_3 of the previous stage (more on the horizontal transfer register 15 side) is applied. In other words, a binary level vertical transfer pulse ΦV_4 is applied to the fourth vertical transfer electrode 12_4 closest to the horizontal transfer register 15 side.

  Hereinafter, the vertical transfer electrodes 12_2, 12_4 to which the binary level vertical transfer pulses ΦV_2, ΦV_4 are applied are also referred to as dedicated transfer electrodes (or non-read electrodes) 12A in order to distinguish them from the vertical transfer electrodes 12_1, 12_3 that also serve as read electrodes. The vertical transfer electrodes 12_1 and 12_3 to which the three-level vertical transfer pulses ΦV_1 and ΦV_3 including the pulse ΦROG are applied are also referred to as the read transfer electrode 12B.

  The vertical transfer register 13 is further taken over by the horizontal transfer register 15 via one set of vertical transfer electrodes 12 (transfer electrodes to which ΦV_1 to ΦV_4 are applied) 12_1 to 12_4 in the final stage.

  The horizontal transfer register 15 is formed so that two horizontal transfer electrodes 16 (respectively denoted by reference elements _1 and _2) correspond to each vertical transfer register 13 and are supplied from the drive control unit 50. The signal charges are transferred and driven in the horizontal direction by the two-phase horizontal drive pulses ΦH_1 and ΦH_2.

  A summary of the operation of the imaging apparatus 1 having such a configuration is summarized as follows. That is, the signal charge accumulated in each of the sensor units 11 of the CCD solid-state imaging device 10 is applied with the read pulse ΦROG emitted from the drive control unit 50 to the gate electrode of the read gate unit ROG, and the potential below the gate electrode is By becoming deeper, the data is read to the vertical transfer register 13 through the read gate portion ROG.

  The vertical transfer register 13 of the imaging unit 10a is driven to transfer by four types of vertical transfer pulses ΦV_1 to ΦV_4 corresponding to the four types of vertical transfer electrodes 12. As a result, the signal charges read from each sensor unit 11 are transferred in the vertical direction in order corresponding to one scanning line (one line) and sent to the horizontal transfer register 15.

  The horizontal transfer register 15 sequentially applies signal charges corresponding to one line vertically transferred from each of the plurality of vertical transfer registers 13 based on the two-phase horizontal transfer pulses ΦH_1 and ΦH_2 emitted from the drive control unit 50. Horizontal transfer to the output amplifier unit 17 side.

  The output amplifier unit 17 converts the signal charges sequentially injected from the horizontal transfer register 15 into a signal voltage, and outputs it as a CCD output signal Sout from the output terminal tout. The CCD output signal Sout is taken over by a signal processing system (not shown), and after being subjected to predetermined signal processing, is displayed on a display device or recorded on a storage medium.

  For example, in the first stage of the signal processing system, an amplification amplifier that amplifies an analog imaging signal (CCD output signal Sout) from the CCD solid-state imaging device 10 or a CDS (Correlated) that reduces noise by sampling the amplified imaging signal. A preamplifier unit having a Double Sampling (correlated double sampling) circuit is arranged. Further, an A / D (Analog / Digital) conversion unit that converts an analog signal output from the preamplifier unit into a digital signal and a DSP (a DSP that performs predetermined image processing on the digital signal input from the A / D conversion unit are provided at the subsequent stage. An image processing unit composed of a digital signal processor is arranged.

<Wiring structure of vertical transfer electrode>
FIG. 2 is a diagram showing an example of an arrangement structure of the four types of vertical transfer electrodes 12 of the CCD solid-state imaging device 10 shown in FIG.

  As shown in FIG. 2, in the CCD solid-state imaging device 10 of this embodiment, a plurality of vertical transfer registers (V-CCD) are provided between the sensor units 11 in each vertical column of the sensor units 11 arranged in a two-dimensional matrix. 13 is arranged, and a read gate portion ROG is interposed between each sensor portion 11 and the transfer channel region 13a of the vertical transfer register 13. Further, a channel stop portion CS1 is provided at a horizontal boundary portion of each pixel (unit cell).

  On the light receiving surface (front side of the paper surface) of the vertical transfer register 13, four types of vertical transfer electrodes 12 made of a thin polycrystalline silicon film (Poly) or the like are connected to the vertical transfer register 13 at the same vertical position in each column. The sensor opening 118 is formed in the light receiving surface of the sensor unit 11 and is arranged so as to cover almost the entire surface of the imaging unit 10a (see FIG. 1).

  In the vertical transfer electrode 12, the second and fourth vertical transfer electrodes 12_2 and 12_4 (dedicated transfer electrode 12A) dedicated to vertical transfer are formed of, for example, a first layer (back side of the paper) of a polycrystalline silicon film, and read electrodes The first and third vertical transfer electrodes 12_1 and 12_3 (read transfer electrode 12B) that also serve as 14 are formed of, for example, a second layer (front side of the paper) of a polycrystalline silicon film.

  Here, the vertical transfer electrodes 12 are formed so as to form a two-layer wiring between the pixels 11a, but the combination of the first and second vertical transfer electrodes 12_1 and 12_2 and the inter-pixel 11a A single-layer structure in which two third and fourth vertical transfer electrodes 12_3 and 12_4 are arranged in combination may be used. When wiring with a single layer structure, the wiring width per line becomes narrow and the line resistance increases, so in general, a two-layer wiring that can make the wiring width per line substantially the same as the inter-pixel width is adopted. The

  Each vertical transfer electrode 12 of the vertical transfer register 13 is arranged such that two transfer electrodes correspond to each sensor unit 11 and form a sensor opening 118 in the sensor unit 11 portion. For example, the first and fourth vertical transfer electrodes 12_1 and 12_4 correspond to the sensor unit 11A of every other horizontal line so as to be in contact therewith, and the sensor unit 11B of every other horizontal line is in contact with this. Thus, the second and third vertical transfer electrodes 12_2 and 12_3 are made to correspond. In the vertical transfer register 13 of this example, a four-phase driving method is applied in which four-phase driving pulses ΦV1, ΦV2, ΦV3, and ΦV4 are applied to the vertical transfer electrodes 12_1 to 32_4.

  Here, the dedicated vertical transfer electrodes 12_2 and 12_4 (dedicated transfer electrodes 12A) to which the binary level vertical transfer pulses ΦV_2 and ΦV_4 are supplied are horizontal between the vertical transfer directions of the sensor unit 11 (between pixels 11a). It is formed to extend in the direction. The second vertical transfer electrode 12_2 and the fourth vertical transfer electrode 12_4 have almost the same pattern shape.

  Schematically, the dedicated transfer electrode 12A is provided extending in the horizontal direction between the sensor units 11 adjacent in the vertical direction (between the pixels 11a), and the corresponding dedicated transfer electrode disposed in each vertical transfer register 13 is provided. The lower side is formed in a comb-tooth shape so that 12A is integrally connected.

  On the other hand, vertical transfer pulses ΦV_1 and ΦV_3 at three levels are supplied, and the vertical transfer is configured to function also as the readout electrode 14 (respectively denoted by reference elements _1 and _3). The electrodes 12_1 and 12_3 (read transfer electrode 12B) are formed to extend in the horizontal direction between the vertical transfer directions of the sensor unit 11 (between pixels 11a). The first vertical transfer electrode 12_1 and the third vertical transfer electrode 12_3 have almost the same pattern shape.

  Schematically, the read transfer electrodes 12B are provided so as to extend in the horizontal direction between the sensor units 11 adjacent to each other in the vertical direction (between the pixels 11a), and correspond to the read transfer electrodes disposed in each vertical transfer register 13. The upper side is formed in a comb-tooth shape so that 12B is integrally connected.

  A read gate portion ROG is formed between the transfer channel region 33 a of the vertical transfer register 13 and each sensor unit 11. A gate electrode (referred to as a read electrode 14) of the read gate portion ROG is formed by an extension of the first vertical transfer electrode 12_1 and the third vertical transfer electrode 12_3. That is, in the CCD solid-state imaging device 10, the first vertical transfer electrode 12_1 and the third vertical transfer electrode 12_3 function not only as transfer electrodes for the vertical transfer register 13 but also as read electrodes 14. -ing

  Further, a channel stop portion CS1 for separating the sensor portions 11 is formed between the other side of the vertical rows of the sensor portions 11 and between the sensor portions 11 adjacent in the vertical direction.

<Sensor Structure: First Embodiment>
FIG. 3 is a diagram illustrating an example of a unit cell structure according to the first embodiment. Here, FIG. 3A is a diagram showing an impurity configuration in a horizontal cross section of the sensor, FIG. 3B is a plan view of the zz line in FIG. 3A, and FIG. It is the figure which showed the electric potential distribution of the cross section of a sensor horizontal direction.

  As the sensor unit 11 of this embodiment, a hole storage layer (also referred to as a second sensor region) made of a P + type impurity region is further formed on the charge storage layer 11x on the surface side of the NP diode made of an N + type impurity region. 11y is laminated so-called HAD (Hole Accumulated Diode) structure (see, for example, JP-A-5-335548 and JP-A-2003-78125).

  Here, when compared with the conventional structure shown in FIG. 7, the unit cell of the first embodiment has a channel stop portion CS1 as an element isolation region provided on the sensor surface in a sensor structure having an overflow barrier region OFB. However, it is characterized in that it has a structure that is continuously extended in potential to a place adjacent to the overflow barrier region OFB.

  In particular, the sensor structure of the first embodiment has a structure in which the entire periphery of the overflow barrier region OFB is surrounded by a potential fluctuation suppressing semiconductor region as a difference from the sensor structure of the second embodiment described later. Characterized by points.

  That is, first, as shown in FIGS. 3A and 3B, the channel stop portion CS1 between adjacent unit cells can supply the GND (ground) potential on the surface to the vicinity of the overflow barrier region OFB. As described above, the first P well region PW1 and the second P well region PW2 are connected by a semiconductor region EPCR_1 having a different impurity concentration and not depleted.

  On the other hand, the first P well region PW1 and the second P well region PW2 are also formed on the first P well region PW1 below the read gate portion ROG at a predetermined depth from the sensor surface and connected to the semiconductor region EPCR_1. Semiconductor regions EPCR_2 that have different impurity concentrations and are not depleted are provided.

  Both the semiconductor region EPCR_1 and the semiconductor region EPCR_2 are accumulated in the sensor unit 11 as the charge accumulation region around the overflow barrier region OFB, which is the second conductivity type semiconductor region, below the sensor unit 11 as the charge accumulation region. It functions as a potential fluctuation suppressing semiconductor region EPCR (Electric Potential Change Repression) for suppressing fluctuations in the potential barrier depending on the amount of signal charge. The semiconductor region EPCR_1 is the first potential variation suppressing semiconductor region EPCR, and the semiconductor region EPCR_2 is the second potential variation suppressing semiconductor region EPCR.

  The semiconductor region EPCR_2 stays at the lower part of the read gate portion ROG so that the influence on the transfer efficiency of the signal charge in the vertical transfer register 13 is reduced, and up to the lower part of the buried channel BC constituting the charge vertical transfer register 13. It is better not to extend.

  The presence of the semiconductor region EPCR_2 below the read gate portion ROG makes it easy to be subjected to the modulation of the GND potential to the vertical transfer register 13 by the semiconductor region EPCR_2, and the transfer efficiency may be reduced. In addition, the semiconductor region EPCR_2 This is because the degree of the influence increases and the reduction in transfer efficiency increases when the signal reaches the lower part of the vertical transfer register 13 (buried channel BC).

  In the case of an XY address type solid-state imaging device such as a MOS (Metal Oxide Semiconductor) type or a CMOS (Complementary Metal-Oxide Semiconductor) type, the P well surrounding the pixel can be set to the ground GND, and the overflow barrier region OFB. Can also be connected to ground GND.

  However, in the CCD type solid-state imaging device, the lower side (semiconductor substrate NSUB side) of the second P well region PW2 constituting the vertical transfer register 13 is depleted, and a positive potential is supplied from the ground GND in order to suppress a decrease in transfer efficiency. It is important to keep

  Therefore, it is preferable that the extension range of the semiconductor region EPCR_2 is limited to the lower part of the read gate portion ROG so that the lower side of the second P well region PW2 is not depleted and the transfer efficiency is not deteriorated. .

  That is, in the CCD type solid-state imaging device, it is essential that the lower side of the second P well region PW2 is depleted, and the potential is inclined in the substrate direction indicated by the D1-D2 line in FIG. It is necessary to do.

  The semiconductor region EPCR_1 and the semiconductor region EPCR_2 constitute the entire channel stop portion CS1 between adjacent unit cells in the horizontal direction. The semiconductor region EPCR_1 and the semiconductor region EPCR_2 are deep regions of the sensor unit 11, and the overflow barrier region OFB. The overflow barrier region OFB is configured in the lower part of the sensor unit 11 by surrounding the circuit board with a circle. That is, a device structure is employed in which a semiconductor region EPCR_1 that also serves as the channel stop portion CS1 and a semiconductor region EPCR_2 connected to the semiconductor region EPCR_1 are provided around the overflow barrier region OFB.

  Note that the semiconductor region EPCR_1 and the semiconductor region EPCR_2 may have completely different impurity concentrations, or may be substantially integrated with the same impurity concentration.

  In any case, in the sensor structure of the first embodiment, the overflow barrier region OFB is not the entire first P well region PW1 in the lower part of the sensor unit 11 as in the prior art, but the potential variation suppressing semiconductor region EPCR (this In the example, the semiconductor region EPCR_1 and the semiconductor region EPCR_2) surround the entire periphery, so that the overflow barrier region OFB is positively formed in a part of the lower part of the sensor unit 11.

  As shown in FIG. 3C, the semiconductor region EPCR_1 also serving as the channel stop portion CS1 is set to the ground potential. As a result, the semiconductor region EPCR_2 connected to the semiconductor region EPCR_1 is also set to the ground potential. In this way, in the exposure accumulation state, the potential close to the overflow barrier region OFB can be reliably set to the GND potential.

  In the sensor structure of the first embodiment, the potential fluctuation suppressing semiconductor region EPCR is formed so as to surround the entire periphery of the overflow barrier region OFB at the lower part of the sensor unit 11, so that the entire overflow barrier region OFB is surrounded. Thus, a GND potential is formed.

  The difference from the sensor structure of the third embodiment to be described later is that not only the lower part of the sensor part 11 but also the semiconductor region EPCR_2 provided under the read gate part ROG adjacent to the vertical transfer register 13 is used to overflow. It is characterized in that the barrier region OFB is surrounded by a circle.

  During the exposure charge accumulation time, at least the channel stop portion CS1 is not depleted, and the overflow barrier region OFB is depleted.

  For example, the channel stop CS1 that separates the sensor unit 11 from the vertical transfer register 13 of the adjacent unit cell is continuously provided from the sensor surface to the first P well region PW1 for forming the conventional overflow barrier region OFB. Connect.

Here, the semiconductor region EPCR_1 also serving as the channel stop portion CS1 is generally formed by injecting B of 1E12 to 1E14 / cm ² near the surface. Although the concentration may decrease toward the overflow barrier region OFB, it is set to a P + concentration that does not cause depletion from the sensor surface to the overflow barrier region OFB during the exposure accumulation operation period. For example, the concentration is 5E15 / cm ³ or more. Here, the overflow barrier region OFB is effectively formed of a P layer having a lower concentration than the surroundings.

  Conventionally, as shown in FIG. 7, the overflow barrier region OFB is provided on the entire lower surface of the sensor unit 11. However, in the sensor structure of the first embodiment, if the following conditions are satisfied, the overflow barrier region OFB Is relatively dense.

  Here, the condition of the overflow barrier region OFB is that the concentration is low enough to deplete when a constant voltage (for example, 5 V) is applied to the semiconductor substrate NSUB made of N-type silicon during the exposure accumulation operation period, and the semiconductor substrate It is assumed that the overflow barrier region OFB is completely crushed when, for example, 15V is applied to NSUB as the voltage of the electronic shutter for charge sweeping.

The optimum concentration differs depending on the potential of the second P well region W2 surrounding the overflow barrier region OFB and the channel stop portion CS1 and the size of the overflow barrier region OFB. For example, the overflow barrier region OFB of 0.5 μ □ If it is the region, it may be 5E14 to 1E16 / cm ² .

<About improvement of knee characteristics>
FIG. 4 is a diagram for explaining improvement of knee characteristics by applying the device structure shown in FIG. Here, FIG. 4A is a diagram showing a potential profile in the depth direction in the unit cell, and FIG. 4B is a diagram showing signal charge accumulation characteristics.

  In FIG. 4A, a solid line a is a potential in a state where no signal charge is accumulated in the sensor unit 11 in the central portion passing through the overflow barrier region OFB of the sensor unit 11 indicated by the C1-C2 line in FIG. Indicates. A solid line b indicates a potential in a state where signal charges are accumulated up to a saturation level in the sensor unit 11 in the central portion of the sensor unit 11 indicated by a C1-C2 line in FIG.

  A dotted line c indicates a potential in a portion passing through the channel stop portion CS1 on the semiconductor region EPCR_1 side in the vicinity of the overflow barrier region OFB of the sensor portion 11 indicated by the B1-B2 line in FIG. A dotted line d indicates a potential in a portion penetrating the channel stop portion CS1 on the semiconductor region EPCR_1 side indicated by the A1-A2 line in FIG.

  As apparent from FIG. 4A, a potential barrier having a certain height is formed between the sensor unit 11 and the first P well region PW1.

  Here, in the sensor structure of the first embodiment, when the signal charge is accumulated in the light receiving element (photodiode or the like) of the sensor unit 11, the light exceeding the saturation level is continuously irradiated, and the signal exceeds the potential barrier. When charge is generated in the sensor unit 11, the charge that exceeds the potential barrier flows in the depth direction of the semiconductor substrate NSUB.

  Therefore, excess charge accumulated in the sensor unit 11 flows over the first P well region PW1 to the semiconductor substrate NSUB and is absorbed by the semiconductor substrate NSUB, and there is no need to provide an overflow drain between adjacent channels. As a result, excess charges can be absorbed without reducing the aperture ratio. However, at this time, the barrier potential of the overflow barrier region OFB tends to change.

  However, in the sensor structure according to the first embodiment, the potential distribution that extends the GND potential from the sensor surface to the vicinity of the overflow barrier region OFB is formed by the semiconductor region EPCR_1 that is not depleted. Is suppressed. For this reason, when the signal charge is to be accumulated at the saturation level or higher, the knee characteristic that the potential in the vicinity of the overflow barrier region OFB rises itself and the signal charge is excessively accumulated can be suppressed. That is, it is possible to significantly suppress the barrier potential from changing due to the influence of the GND potential due to the potential fluctuation suppressing semiconductor region EPCR around the overflow barrier region OFB as compared with the conventional case.

  As a result, as shown in FIG. 4B, knee characteristics resulting from accumulation of signal charges exceeding the saturation level can be significantly suppressed, and the saturation signal level is substantially constant with respect to the amount of light. It can be made to be.

  Thus, by adopting the sensor structure of this embodiment, the overflow barrier region OFB provided deep in the substrate below the sensor unit 11 is not affected by electron accumulation, and as a result, the potential barrier does not fluctuate. Knee characteristics can be greatly improved. In particular, in the sensor structure of the first embodiment, a semiconductor region EPCR_2 is provided connected to the semiconductor region EPCR_1 connected to the sensor surface, and the semiconductor region EPCR_1 and the semiconductor region EPCR_2 surround the entire periphery of the overflow barrier region OFB. Therefore, compared with the sensor structure of the second embodiment described later, the effect of suppressing the barrier potential fluctuation is high.

  That is, in the present embodiment, a depleted semiconductor layer is formed by arranging impurities around the overflow barrier region OFB so that the overflow barrier region OFB is connected to the GND potential on the sensor surface during the exposure charge accumulation period. By adopting the sensor structure, it is possible to improve knee characteristics such that the signal charge of the sensor unit 11 continues to be accumulated at a saturation signal level or higher.

  In addition, since the knee characteristic is suppressed, the following additional effects can be enjoyed. That is, since it is not necessary to transfer the charge of the knee component, the amount of charge (saturation + knee component) that has to be carried more than the saturation signal amount is reduced, so that the charge transfer region (not only the vertical transfer register 13 but also the horizontal transfer register 15 Can also reduce the transfer width. Accordingly, the area of the light receiving element such as the photodiode of the sensor unit 11 can be increased, and as a result, the sensitivity can be improved. Alternatively, in the case of the same light receiving sensitivity, miniaturization, that is, higher resolution can be realized.

  Further, since it is not necessary to transfer the charge of the knee component, the voltage amplitude applied to the transfer electrode can be reduced in any of the vertical transfer register 13 and the horizontal transfer register 15, that is, the vertical transfer amplitude is reduced. Therefore, power consumption can be reduced. In addition, since the voltage stress applied to the gate film under the vertical transfer electrode 12 is reduced, the stability of the long-term reliability characteristics is also improved.

  Further, the buried channel BC constituting the vertical transfer register 13 can be further miniaturized, and the vertical transfer width is thereby narrowed, so that smear components can be reduced.

  In the device structure of the present embodiment, a structure is used in which the semiconductor region EPCR_1 for suppressing the fluctuation of the barrier potential depending on the signal charge amount of the overflow barrier region OFB is also used as the channel stop portion CS1 as the element isolation region. Thus, when the device structure of the present embodiment is realized, the area is not increased.

  As a technique, it may be possible to provide a semiconductor region EPCR_1 for suppressing the barrier potential fluctuation separately from the element isolation region (channel stop portion CS1) around the overflow barrier region OFB. In this case, however, the area increases. Therefore, the device structure of this embodiment in which the semiconductor region EPCR_1 also serves as the horizontal channel stop portion CS1 between adjacent unit cells is more advantageous.

<Sensor structure: Second embodiment>
FIG. 5 is a diagram illustrating the structure of the unit cell according to the second embodiment. Here, FIG. 5 (A) and FIG. 5 (B) show a first example of the second embodiment, and FIG. 5 (C) and FIG. 5 (D) show a second example of the second embodiment. . 5A is a diagram showing the impurity structure in the sensor horizontal cross section, and FIG. 5B is a plan view of the zz line in FIG. 5A. Similarly, FIG. 5C is a diagram illustrating an impurity structure in a horizontal cross section of the sensor, and FIG. 5D is a plan view of a zz line in FIG. 5C.

  Similarly to the sensor structure of the first embodiment, the sensor unit 11 of the second embodiment also has a sensor structure having an overflow barrier region OFB as compared with the conventional structure shown in FIG. The channel stop portion CS1 as an element isolation region provided in the device is characterized in that it has a structure in which the potential is continuously extended to a position adjacent to the overflow barrier region OFB.

  In particular, the sensor structure of the second embodiment differs from the sensor structure of the first embodiment described above in that a part of the overflow barrier region OFB is in contact with the potential fluctuation suppressing semiconductor region EPCR, that is, the overflow barrier region. This is characterized in that a part of the OFB is surrounded by a potential fluctuation suppressing semiconductor region EPCR.

  That is, the sensor structure of the first example of the second embodiment shown in FIGS. 5 (A) and 5 (B) and the sensor of the second example of the second embodiment shown in FIGS. 5 (C) and 5 (D). In the structure, first, the first P well region PW1 and the second P well region PW2 are provided so that the channel stop portion CS1 between the adjacent sensor portions 11 can supply the surface GND (ground) potential to the vicinity of the overflow barrier region OFB. Are connected by a non-depleted semiconductor region EPCR_1 having a different impurity concentration.

  On the other hand, in the sensor structure of the first example, the semiconductor region EPCR_1 is formed on the first P well region PW1 below the read gate portion ROG at a predetermined depth from the sensor surface and as shown in FIG. 5B. A semiconductor region EPCR_2 that has a different impurity concentration from that of the first P well region PW1 and the second P well region PW2 and is not depleted is provided so as not to be separated from each other. The comparison with the sensor structure of the first embodiment is characterized in that the semiconductor region EPCR_2 is not connected to the semiconductor region EPCR_1 apart from the semiconductor region EPCR_1.

  Note that the semiconductor region EPCR_1 and the semiconductor region EPCR_2 may have completely different impurity concentrations, or both may have the same impurity concentration.

  Also in the device structure of the second embodiment, the semiconductor region EPCR_1 and the semiconductor region EPCR_2 constitute the entire channel stop portion CS1 between adjacent unit cells in the horizontal direction, and the semiconductor region EPCR_1 and the semiconductor region EPCR_2 Thus, the overflow barrier region OFB is formed below the sensor unit 11 by surrounding a part of the first P well region PW1 in the 11 deep layer regions.

  That is, as shown in FIG. 5B, the semiconductor region EPCR_2 is opposed to the semiconductor region EPCR_1 so as to sandwich the overflow barrier region OFB, and the second P well region PW2 is vertically disposed above and below the overflow barrier region OFB. There exists.

  On the other hand, the sensor structure of the second example is characterized in that the semiconductor region EPCR_2 forming the channel stop portion CS1 is not provided on the first P well region PW1 below the read gate portion ROG.

  Only the semiconductor region EPCR_1 constitutes the entire channel stop portion CS1 between adjacent unit cells in the horizontal direction. This channel stop portion CS1 (semiconductor region EPCR_1) is a deep region of the sensor portion 11 and a part of the first P well region PW1. As a result, the overflow barrier region OFB is formed in the lower part of the sensor unit 11.

  That is, as shown in FIGS. 5C and 5D, the second P well region PW2 exists above and below in the vertical direction passing through the overflow barrier region OFB.

  In any case, in the sensor structure of the second embodiment, the overflow barrier region OFB is not the entirety of the first P well region PW1 in the lower part of the sensor unit 11 as in the prior art, but a part of the periphery in the channel stop unit CS1. Is characterized in that the overflow barrier region OFB is positively formed in a part of the lower part of the sensor unit 11.

  Even in the sensor structure of the second embodiment, the semiconductor region EPCR_1 that also serves as the channel stop portion CS1 is set to the ground potential. Since the semiconductor region EPCR_2 is not connected to the semiconductor region EPCR_1, the semiconductor region EPCR_2 is in a floating state even if the semiconductor region EPCR_1 that also serves as the channel stop portion CS1 is set to the ground potential. By doing this as well, in the exposure accumulation state, the potential near the overflow barrier region OFB can be reliably set to the GND potential as in the sensor structure of the first embodiment.

  Therefore, similarly to the sensor structure of the first embodiment, the fluctuation of the barrier potential due to the influence of the GND potential by the channel stop portion CS1 around the overflow barrier region OFB is greatly suppressed compared to the conventional case. As a result, the knee characteristic resulting from the accumulation of signal charges exceeding the saturation level can be greatly suppressed, and the saturation signal level can be made substantially constant with respect to the amount of light.

  However, in the sensor structure of the second embodiment, since only a part of the first P well region PW1 is surrounded by the deep region of the sensor unit 11, the entire periphery of the first P well region PW1 is surrounded. When compared with the sensor structure of the first embodiment, the barrier potential fluctuation suppressing effect is slightly inferior.

  However, in the sensor structure of the second example of the second embodiment, the non-depleted semiconductor region EPCR_2 is not provided below the read gate portion ROG adjacent to the vertical transfer register 13, and therefore the first embodiment and the second embodiment are not provided. Compared with the sensor structure of the first example of the form, there is an advantage that the device is easily manufactured.

  In addition, since the lower portion of the vertical transfer register 13 can be always depleted by eliminating the modulation of the GND potential to the vertical transfer register 13 by the semiconductor region EPCR_2, the second P of the lower portion of the vertical transfer register 13 is also used during the charge transfer period. There is also an advantage that the state in which the well region PW2 is depleted can be reliably maintained, and the vertical transfer operation can be performed in a state where the transfer efficiency is not lowered by the vertical transfer operation.

<Sensor Structure: Third Embodiment>
FIG. 6 is a diagram illustrating the structure of a unit cell according to the third embodiment. Here, FIG. 6A is a plan view of the sensor surface in the sensor vertical direction, and FIG. 6B is a diagram showing an impurity configuration in the sensor vertical direction cross section of the yy line in FIG. 6A. FIG. 6C is a plan view of the zz line in FIG.

  The sensor unit 11 of the second embodiment is a channel stop unit made of a P-type semiconductor layer that applies a GND potential to the overflow barrier region OFB in the sensor structure having the overflow barrier region OFB as compared with the conventional structure shown in FIG. It is characterized in that CS2 is provided between the pixels 11a to provide the same effect as the sensor structure of the first embodiment or the second embodiment. Although illustration is omitted, the impurity configuration of the sensor horizontal cross section is the same as that of the conventional example.

  That is, first, as shown in FIG. 6A, the first P well region PW1 and the channel stop portion CS2 between the pixels 11a are supplied so that the surface GND (ground) potential can be supplied to the vicinity of the overflow barrier region OFB. The second P well region PW2 is connected by a semiconductor region EPCR_3 having a different impurity concentration and not depleted.

  Similar to the semiconductor regions EPCR_1 and EPCR_2 in the first and second embodiments, the semiconductor region EPCR_3 is around the overflow barrier region OFB, which is a second conductivity type semiconductor region under the sensor unit 11 as a charge storage region. In addition, it functions as a first potential fluctuation suppressing semiconductor region EPCR for suppressing potential barrier fluctuations depending on the amount of signal charge accumulated in the sensor unit 11 as a charge accumulation region.

  In the semiconductor region EPCR_3, the entire channel stop portion CS2 between the pixels 11a is configured. That is, the semiconductor region EPCR_3 has a device structure that also serves as the channel stop portion CS2 between the pixels 11a. This is the same as the semiconductor region EPCR_1 of the first embodiment also serving as the horizontal channel stop portion CS1 between adjacent unit cells.

  The semiconductor region EPCR_3 also serving as the channel stop portion CS2 is a deep region of the sensor unit 11 so as to surround the overflow barrier region OFB, thereby forming the overflow barrier region OFB below the sensor unit 11. Like to do.

  In the sensor structure of the third embodiment, the overflow barrier region OFB is surrounded by the semiconductor region EPCR_3 instead of the entire first P well region PW1 in the lower part of the sensor unit 11 as in the prior art. A major feature is that the overflow barrier region OFB is positively formed in a part of the lower portion of the portion 11.

  In particular, as a difference from the sensor structure of the first embodiment, as shown in FIG. 6C, only the lower part of the sensor unit 11 surrounds the overflow barrier region OFB by the semiconductor region EPCR_3. It is characterized by a point. In this case, as shown in FIG. 6C, the semiconductor region EPCR_3 is formed to a depth not to be depleted up to a deep position between the pixels 11a.

  Even in the sensor structure of the third embodiment, the semiconductor region EPCR_3 also serving as the channel stop portion CS2 between the pixels 11a is set to the ground potential. In this way, in the exposure accumulation state, the potential close to the overflow barrier region OFB can be reliably set to the GND potential, as in the sensor structures of the first and second embodiments.

  Therefore, similarly to the sensor structure of the first and second embodiments, the barrier potential varies due to the influence of the GND potential due to the semiconductor region EPCR_3 around the overflow barrier region OFB. It is suppressed. As a result, the knee characteristic resulting from the accumulation of signal charges exceeding the saturation level can be greatly suppressed, and the saturation signal level can be made substantially constant with respect to the amount of light.

  Since the entire periphery of the first P well region PW1 is surrounded by the semiconductor region EPCR_3 in the deep region of the sensor unit 11, it is possible to enjoy the same barrier potential fluctuation suppressing effect as that of the sensor structure of the first embodiment.

  In addition, unlike the sensor structure of the first embodiment, since the semiconductor region EPCR_2 is not provided below the read gate portion ROG adjacent to the vertical transfer register 13, the sensor structure of the second example of the second embodiment is provided. Similarly to the sensor structure of the first example of the first embodiment or the second embodiment, since the modulation of the GND potential to the vertical transfer register 13 can be reduced, the vertical transfer register 13 can be easily depleted. There is an advantage.

  Note that the mechanism of the first to third embodiments described above has a potential distribution from the side of the element structure in which the GND potential is extended from the sensor surface to the vicinity of the overflow barrier region OFB by the non-depleted P-type semiconductor layer. By forming, when the signal charge is to be accumulated at the saturation level or higher, the knee characteristic that the potential in the vicinity of the overflow barrier region OFB self-rises and the signal charge is excessively accumulated is suppressed.

  On the other hand, as another method, the above-described potential distribution is formed in the charge accumulation period while using the same device structure as the conventional device structure, and in the subsequent readout period and transfer period, It is also conceivable to control the drive voltage and drive timing so that the potential distribution is suitable for each operation.

  However, by controlling the drive voltage and drive timing with the conventional device structure, the potential distribution as described above during the charge accumulation period, or the potential distribution suitable for each operation during the subsequent readout period and transfer period In other words, there is a difficulty in reducing the reading efficiency and the transfer efficiency, and it is necessary to consider a new mechanism for solving this problem.

  Compared to this, from the aspect of the device structure, it is difficult to achieve the structure in which the above-described potential distribution is formed during the charge accumulation period within a range that does not have a large adverse effect on the reading efficiency and the transfer efficiency. There is nothing.

It is a block diagram which shows one Embodiment of the imaging device (camera system) which is an example of an electronic device. It is a figure which shows an example of the arrangement structure of four types of vertical transfer electrodes of the CCD solid-state image sensor shown in FIG. It is a figure explaining the structure of the unit cell of 1st Embodiment. It is a figure explaining improvement of knee characteristics by applying the device structure shown in FIG. It is a figure explaining the structure of the unit cell of 2nd Embodiment. It is a figure explaining the structure of the unit cell of 3rd Embodiment. It is a figure explaining the conventional solid-state image sensor which has a vertical overflow barrier structure.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Imaging device, 10 ... CCD solid-state image sensor, 10a ... Imaging part, 11 ... Sensor part, 118 ... Sensor opening part, 11a ... Between pixels, 12 ... Vertical transfer electrode, 12A ... Dedicated transfer electrode, 12B ... Read transfer electrode , 13 ... Vertical transfer register, 15 ... Horizontal transfer register, 17 ... Output amplifier unit, 50 ... Drive control unit, 52 ... Timing signal generation unit, 54 ... Driver, 56 ... Drive power supply, BC ... Embedded channel, CS1, CS2 ... channel stop part, ROG ... read gate part, PW1 ... first P well region, PW2 ... second P well region, EPCR ... potential fluctuation suppressing semiconductor region, EPCR_1, EPCR_2, EPCR_3 ... semiconductor region, OFB ... overflow barrier region, NSUB ... Semiconductor substrate

Claims (7)

Between the charge accumulation region of the first conductivity type that accumulates signal electrons generated in each unit cell and the semiconductor region below the charge accumulation region, the flow of signal charges in the depth direction from the charge accumulation region A solid-state imaging device having a vertical overflow barrier structure having a semiconductor region of a second conductivity type forming a potential barrier,
A potential fluctuation suppressing semiconductor region is formed around the second conductivity type semiconductor region below the charge storage region to suppress potential barrier fluctuations depending on the amount of signal charge stored in the charge storage region. And
The solid state imaging device , wherein the potential fluctuation suppressing semiconductor region is formed of a second conductivity type having a higher concentration than the second conductivity type semiconductor region . 2. The solid-state imaging device according to claim 1, wherein the first potential variation suppressing semiconductor region is also used as an element isolation region for isolation from an adjacent unit cell. A signal charge reading unit for reading the signal charge stored in the charge storage region; and a charge transfer unit for transferring the signal charge read by the signal charge reading unit,
A second potential fluctuation suppressing semiconductor region is formed so as to surround a part of the second conductivity type semiconductor region under the signal charge readout portion,
The second potential fluctuation suppressing semiconductor region is connected to the first potential fluctuation suppressing semiconductor region;
The lower part of the charge storage region is characterized in that the first potential fluctuation suppressing semiconductor region and the second potential fluctuation suppressing semiconductor region surround the entire periphery of the second conductivity type semiconductor region. Item 3. The solid-state imaging device according to Item 2. A signal charge reading unit for reading the signal charge stored in the charge storage region; and a charge transfer unit for transferring the signal charge read by the signal charge reading unit,
A second potential fluctuation suppressing semiconductor region is formed so as to surround a part of the second conductivity type semiconductor region under the signal charge readout portion,
The solid-state imaging device according to claim 2, wherein the second potential fluctuation suppressing semiconductor region is separated from the first potential fluctuation suppressing semiconductor region. The first potential fluctuation suppressing semiconductor region that is also used as the element isolation region surrounds the entire periphery of the second conductivity type semiconductor region under the charge storage region. 2. The solid-state imaging device according to 2. The potential fluctuation suppressing semiconductor region is set to a concentration at which the impurity concentration of the second conductivity type is not depleted.
The solid-state imaging device according to claim 1. The potential fluctuation suppressing semiconductor region is set to a ground potential.
The solid-state imaging device according to claim 1.

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