JP4778715B2 - Semiconductor manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor manufacturing method including a step of forming a trench using plasma. The present invention particularly relates to a method for manufacturing a semiconductor including a step of forming roundness (top round) at the upper end of a trench.

  Among the steps of manufacturing a semiconductor chip, there is a step of separating semiconductor elements from each other by an insulating film layer. Recently, Shallow Trench Isolation (STI) has been used for an element isolation region on a semiconductor substrate in this process. In order to form this STI, it is necessary to bury the insulating film after etching the silicon substrate into a trench shape.

  Depending on the shape of the trench and the method of embedding the insulating film, electric field concentration is considered to be caused by crystal defects at the top and bottom ends of the trench and non-uniform thickness of the PAD oxide film. One solution is to round the top and bottom trenches on the silicon substrate.

As a conventional technique, an example in which the upper end of a trench on a silicon substrate is rounded using HBr and CF ₄ as etching gases in a state where a resist is used as a mask (see, for example, Patent Document 1), or on a silicon substrate using a resist as a mask. After etching the insulating film layer composed of the silicon nitride film and the silicon oxide film, the CHF ₃ and the insulating film layer composed of the silicon nitride film and the silicon oxide film having the openings are used as masks. There is an example in which the upper end of a trench on a silicon substrate is rounded using HBr as an etching gas (see, for example, Patent Document 2).
JP 2001-345375 A Japanese Patent Laid-Open No. 2004-63921

  As described above, in order to form the element isolation region, rounding of the upper end portion of the trench opening formed in the silicon substrate has been frequently performed so far. In the case of rounding the upper end of the trench, in order to proceed the etching while attaching the reaction product of the etching gas and the silicon substrate to the insulating film layer constituting the upper layer of the silicon substrate and the side surface of the opening of the silicon substrate, Etching conditions with high chamber pressure are preferred.

  However, with the recent miniaturization of a dense portion (pattern dense portion) in which adjacent patterns on a semiconductor substrate generated due to higher device density are closely arranged, the trench interval has become narrower than ever. . Along with this, the etching atmosphere state between a dense portion (pattern dense portion) where adjacent patterns are arranged close to each other and a sparse portion (pattern sparse portion) where adjacent patterns are arranged apart from each other However, this difference in atmosphere has begun to affect the trench shape on the silicon substrate and the round portion at the upper end of the trench. In particular, when etching for forming a round portion at the upper end portion of the trench is performed under a high pressure condition, a difference in the shape of the top round has begun to occur between the pattern dense portion and the pattern sparse portion.

Even when plasma processing is performed under high-pressure etching conditions of a CHF ₃ and CF ₄ mixed gas to form a round portion at the upper end of the trench, the difference in top round shape between the pattern dense portion and the pattern sparse portion It was difficult to eliminate.

  In order to cope with the above problem, the present invention etches an insulating film layer composed of silicon nitride and silicon oxide through a patterned resist mask, and does not peel off the resist mask and the antireflection film layer. In the case where a top round portion is formed at the upper end of a trench on a silicon substrate using the etched insulating film layer as a mask, a pattern adjacent to a dense portion (pattern dense portion) in which adjacent patterns are arranged close to each other The object is to reduce the shape difference of the top round part formed at the upper end of the trench between the sparse parts (pattern sparse parts) arranged apart from each other.

For this purpose, it is necessary to perform etching for forming a top round portion at the upper end portion of the trench not under high pressure conditions (2.0 Pa or higher) but under low pressure conditions (1 Pa or lower). In order to perform the treatment under a low pressure condition, a high-deposition high-order fluorocarbon gas CxFy, for example, C ₄ F _8, which forms a large amount of reaction products with a silicon substrate even at a low pressure, is used as a main source gas, and an Ar mixed gas is used. Etching is performed.

According to the present invention, after etching a silicon nitride film and a silicon oxide film composed of an insulating film using a patterned resist as a mask, a silicon substrate is formed at a low pressure using the C ₄ F ₈ and Ar mixed gas as an etching gas. Etching using conditions (1 Pa or less) and performing etching using a mixed gas of O ₂ , HBr, and CF ₄ required to remove the reaction product formed under the processing conditions, Difference in shape of the upper end of the trench on the silicon substrate between a dense part (pattern dense part) where adjacent patterns are arranged close to each other and a sparse part (pattern sparse part) where adjacent patterns are arranged apart from each other Is improved.

  As a result, it is possible to cope with further microfabrication of the trench that is predicted in the future, and the density of the insulating film embedded in the trench and the crystal defect in the dense portion and particularly in the dense portion are improved.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining a configuration of a plasma generation unit of a plasma processing apparatus to which a semiconductor manufacturing method according to the present invention is applied. FIG. 2-1 and FIG. 2-2 are diagrams for explaining the processing steps of the semiconductor manufacturing method according to the present invention. FIG. 3 is a diagram for explaining the relationship between the processing pressure and the difference between the top round lengths of the pattern dense part and the pattern sparse part of the trench part on the semiconductor substrate. FIG. 4 is a diagram for explaining the relationship between the processing pressure and the radius of the top round formed at the upper end of the trench portion.

  The details of the semiconductor manufacturing method (dry etching method) according to the present invention will be described. As shown in FIG. 1, a plasma processing apparatus (etching apparatus) to which a semiconductor manufacturing method according to the present invention is applied is an apparatus that uses UHF waves and a magnetic field as means for generating plasma. , UHF transmission plate 102, solenoid coil 103, processing base 107, high-frequency power source 106, and electrostatic adsorption power source 108. A wafer 105 is mounted on the processing table 107, and plasma 104 is generated between the wafer 105 and the UHF transmission plate 102. The UHF wave that enters through the antenna 101 from the UHF power source, which is a plasma source, passes through the UHF transmission plate 102 and reaches the processing chamber, and acts on the magnetic field generated by the solenoid coil 103 disposed so as to surround the processing chamber. As a result, ECR (Electron Cyclotron Resonance) is caused with the process gas, and a high-density plasma 104 is generated in the processing chamber.

  After the high-density plasma is generated in the processing chamber, the wafer 105 is electrostatically attracted to the processing table 107 to which a DC voltage is applied by the electrostatic attraction power source 108. The processing table 107 is also connected to a high-frequency power source 106, and a high-frequency bias voltage is applied to the processing table 107, and an accelerating potential is applied to ions localized in the high-density plasma toward the sample (wafer) direction (downward). Process processing is started.

  During the process, the pressure in the processing chamber can be regulated by an exhaust structure including a vacuum pump, a turbo molecular pump, and a variable valve provided between the turbo molecular pump and the processing chamber.

  Referring to FIGS. 2A and 2B, a wafer processing process when the semiconductor manufacturing method according to the present invention is applied to the etching apparatus shown in FIG. 1 will be described. In FIG. 2A, the wafer 105 is composed of a resist 201, an antireflection film 202, a silicon nitride film 203, a silicon oxide film 204, and a silicon substrate 205 that are already patterned in order from the upper layer by an exposure technique. Is shown.

Using the etching apparatus, the antireflection film 202 is etched with a mixed gas of Cl ₂ and O ₂ using the patterned resist 201 as a mask (FIG. 2-1 (b)), and then the silicon nitride film 203 and the silicon The insulating film composed of the oxide film 204 was etched using SF ₆ , CHF ₃ and Ar mixed gas (FIG. 2-1 (c)).

Next, a top-round step using a mixed gas of C ₄ F ₈ and Ar, which is one of higher-order fluorocarbons (CxFy), is performed under an etching condition of a pressure of 0.2 Pa and a gas flow ratio of C ₄ F ₈ / Ar of about 1/10. As a result, the reaction product 207 was deposited on the side wall of the insulating film and the surface of the silicon substrate 205 (FIG. 2-2 (d)). Thereafter, the high frequency bias voltage applied to the silicon substrate 205 using a mixed gas of O ₂ , HBr, and CF ₄ is set high, and etching is performed to remove the reaction product 207 that adheres to the silicon surface and is cast (FIG. 2). -2 (e)). Next, a trench 206 was formed on the silicon substrate 205 using the same mixed gas of O ₂ , HBr, and CF ₄ (FIG. 2-2 (f)).

When the etching of the silicon nitride film 203 and the silicon oxide film 204 constituting the insulating layer above the silicon substrate 205 is completed (FIG. 2-1 (c)), the opening of the trench 206 formed on the silicon substrate 205 When the pattern dense portion and the pattern sparse portion are compared, as shown in FIG. 2C, the silicon oxide film 204 remains in the pattern dense portion, whereas the silicon oxide film in the pattern sparse portion. 204 hardly remains and the silicon substrate 205 is exposed. Here, when etching is performed with the above C ₄ F ₈ and Ar mixed gas, the etching hardly progresses in the pattern sparse portion where the silicon is exposed, whereas in the pattern dense portion where the silicon oxide film 204 is localized. Etching proceeds. This is because the etching rate of the silicon oxide film is faster (higher selection ratio) than polycrystalline or amorphous silicon.

Further, when the silicon substrate 205 is etched, the reaction product 207 is formed on the side wall of the insulating film composed of the silicon nitride film 203 and the silicon oxide film 204 existing on the side of the opening of the trench 206 and on the side wall of the trench on the silicon substrate. It adheres (FIG. 2-2 (d)). This becomes a sidewall, and when the anisotropic etching gradually proceeds, the trench 206 formed on the silicon substrate 205 has an angle. In this step, the reaction product 207 with the silicon substrate 205 or the low pressure (1.0 Pa or less) compared with the case where the CHF ₃ and CF ₄ mixed gas is etched at a high pressure (2.0 Pa or more). A feature is that a fluorocarbon multimer (CxFy) composed of an etching gas peculiar to a high-order fluorocarbon is easily generated, and it is easy to form the top round portion 208 at the upper end of the trench.

When the etching using the mixed gas of C ₄ F ₈ and Ar is completed, the scraping amount and taper of the silicon substrate 205 appearing on the surface layer on the semiconductor substrate are close to each other in the pattern dense portion and the pattern sparse portion. The shape difference is improved in the pattern dense portion and the pattern sparse portion of the opening of the trench 206 on the substrate 205. As described above, this is because the etching rate of the silicon oxide film with respect to polycrystalline or amorphous silicon is high (selectivity is high) and the effect of anisotropic etching due to the low etching processing pressure.

However, as described above, the etching with the C ₄ F ₈ and Ar mixed gas involves an excessive reaction product 207 with the silicon substrate 205, so that the insulating film composed of the silicon nitride film 203 and the silicon oxide film 204 is etched. The reaction product 207 is deposited on the surface layer of the silicon substrate 205 after completion (FIG. 2-2 (d)), which may cause an etching stop when the trench 206 is processed. In order to prevent this, a mixture of O ₂ , HBr, and CF ₄ is applied at a high frequency bias voltage between the etching of the insulating film composed of the silicon nitride film 203 and the silicon oxide film 204 and the process of processing the trench 206. It is necessary to insert a gas etching step.

  However, if all of the reaction product 207 adhering to the side wall of the insulating film constituted by the silicon nitride film 203 and the silicon oxide film 204 is removed, a sufficient roundness 208 is not formed at the upper end portion of the trench 206. Care must be taken when removing the reaction product 207 deposited on the surface layer.

In the state of FIG. 2-2 (d), a high-frequency bias voltage is applied, and the reaction product on the surface layer of the silicon substrate is removed by etching the mixed gas of O ₂ , HBr, and CF ₄ (FIG. 2-2 (e) Next, by processing the silicon substrate 205 with a mixed gas of O2, HBr, and CF4, a trench 206 having a sufficient roundness 208 in the shoulder portion could be formed (FIG. 2-2 (f)). .

Further, the angle and the degree of protrusion of the upper end portion of the trench 206 can be controlled as desired by the gas flow rate ratio, time, etc., when etching is performed with the C ₄ F ₈ and Ar mixed gas.

In the etching using the C ₄ F ₈ and Ar mixed gas, the etching selectivity of the silicon oxide film to the polycrystalline silicon is preferably 4.0 or more.

  If the etching selectivity of the silicon oxide film to the polycrystalline silicon is too low, the silicon oxide film of the insulating film functions as a mask, and the silicon substrate under the silicon oxide film has a tapered or skirt shape.

  Further, if the shape of the silicon substrate at the upper end of the trench is different between the dense pattern portion and the loose pattern portion, the shape is not improved even if the etching proceeds after the trench processing is completed.

In addition, when etching is performed at a low pressure (1.0 Pa or less) using a mixed gas obtained by adding CF ₄ gas to a C ₄ F ₈ and Ar mixed gas, it is difficult to form a top round at the upper end of the trench. I want to be. By adding CF ₄ gas, the selectivity of the silicon oxide film to the polycrystalline or amorphous silicon is lowered, the etching rate of the polycrystalline or amorphous silicon to the silicon oxide film is increased, and the pattern dense portion and the pattern sparse portion are increased. Since the amount of shaving and taper on the silicon substrate are different at the end of etching, the shape difference is likely to occur.

When a mixed gas composed of CHF ₃ and CF ₄ is used, a sufficiently large top round portion 208 is formed at the upper end portion of the trench 206 at low pressure to medium pressure (1.5 Pa or less). I can't.

With reference to FIG. 3, the difference in length between the pattern round portion and the top round portion of the pattern dense portion when using the C ₄ F ₈ and Ar mixed gas and the CHF ₃ and CF ₄ mixed gas used in the present invention (dense density). The results of measuring the relationship between the difference and the processing pressure using the wafer center and wafer edge as parameters will be described. Curves A and B are obtained when a mixed gas of C ₄ F ₈ and C ₅ F ₈ and Ar is used. Curve A is the measurement result at the wafer center and curve B is the measurement result at the wafer edge. Curve C and curve D are obtained when a mixed gas of CHF ₃ and CF ₄ is used. Curve C is the measurement result at the wafer center and curve D is the measurement result at the wafer edge. In the CHF ₃ and CF ₄ mixed gas system, a better result than the mixed gas meter of C ₄ F ₈ , C ₅ F ₈ and Ar can be obtained in terms of density difference. However, as shown in FIG. 4 showing the relationship between the processing pressure and the radius of the top round portion formed on the upper portion of the trench 206, in the CHF ₃ and CF ₄ mixed gas system, the radius of the top round portion 208 on the upper portion of the trench 206 is The absolute amount is insufficient and is not suitable as a condition.

The present invention is not limited to the mixed gas of C ₄ F ₈ and Ar, but other high-order fluorocarbon gas CxFy gas (for example, C ₃ F ₆ , C ₄ F ₁₀ , C ₅ F ₈ , C ₅ F _10, etc.) ) And other inert gases (for example, He, Ne, Xe, etc.) are also effective. In the present invention, a plasma etching apparatus using an interaction with a magnetic field using a UHF wave as a plasma source is taken as an example, but the effect of the present invention is not limited to this. The present invention can also be applied to a plasma etching apparatus using an inductive coupling type or capacitive coupling type plasma source such as microwave ECR or helicon wave.

  According to the present invention, a trench for forming element isolation corresponding to future fine processing can be processed.

The schematic sectional drawing of the UHF plasma etching apparatus with which the manufacturing method of the semiconductor of this invention is applied. Sectional drawing explaining the processing process of the semiconductor substrate by the manufacturing method of the semiconductor of this invention. Sectional drawing explaining the processing process of the semiconductor substrate by the manufacturing method of the semiconductor of this invention. The figure explaining the relationship between a process pressure and the difference of the top round amount of the pattern dense part of a trench part on a semiconductor substrate, and a pattern sparse part. The figure explaining the relationship between a process pressure and the top round on a semiconductor substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Antenna, 102 ... UHF transmission plate, 103 ... Solenoid coil, 104 ... Plasma, 105 ... Processed wafer, 106 ... Sample stand, 107 ... Electrostatic adsorption power supply, 108 ... High frequency power supply, 201 ... Patterned resist, 202 ... Antireflection film layer, 203 ... Silicon nitride film, 204 ... Silicon oxide film, 205 ... Silicon substrate, 206 ... Trench, 207 ... Reaction product, 208 ... Top round

Claims (1)

Using a plasma processing apparatus, a multilayer film composed of a resist and an insulating film layer is dry etched on a silicon substrate to form a mask, and the silicon substrate is dry etched using the mask to form a trench. A manufacturing method comprising:
The insulating film layer is dry- etched using a mixed gas of SF ₆ , CHF ₃ and Ar to form a mask, the mixed gas of C ₄ F ₈ and Ar is used, and the low pressure condition is 1.0 Pa or less. the silicon substrate is dry etched, further dry etch processing the silicon substrate using a mixed gas of _O 2, HBr and CF _4,
The dry etching process of the silicon substrate using the mixed gas of O ₂ , HBr, and CF ₄ applies a first etching process that applies a higher high-frequency voltage and a lower high-frequency voltage than the first etching process. With the second etching process
A method for producing a semiconductor, comprising:

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