JP4768292B2 - パッケージ用基板 - Google Patents
パッケージ用基板 Download PDFInfo
- Publication number
- JP4768292B2 JP4768292B2 JP2005079752A JP2005079752A JP4768292B2 JP 4768292 B2 JP4768292 B2 JP 4768292B2 JP 2005079752 A JP2005079752 A JP 2005079752A JP 2005079752 A JP2005079752 A JP 2005079752A JP 4768292 B2 JP4768292 B2 JP 4768292B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- package substrate
- coaxial cable
- package
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
(1)
導電性金属からなるコア基板1を用意し、コア基板1には、絶縁外被を除去してシールド被覆2Aを表出した同軸ケーブル2を挿通可能な径をもつ孔1Aを形成する。尚、記号2Bは同軸ケーブル2の中心導体を指示している。
(2)
コア基板1の孔1Aに同軸ケーブル2の先端を挿通し、孔1Aの周縁と同軸ケーブル2のシールド被覆2Aとをはんだ付けし、コア基板1とシールド被覆2Aとを電気的な接地接続と機械的な固着を行う。
(3)
同軸ケーブル2からなる配線を取り付けたコア基板1の裏面及び表面を絶縁性樹脂3で埋め込んで一体化する。尚、絶縁性樹脂3としては、エポキシ樹脂など熱硬化性の樹脂材料を用いることができる。
(4)
表面側の絶縁性樹脂3の研磨を行い、同軸ケーブル2の中心導体2B、シールド被覆2Aをコア基板1の表面と同一平面とする。
(5)
表出された同軸ケーブル2の端面に於ける中心導体2B上にめっき法を適用してAu、Ag、Cuなどから選択された材料からなる電極パッド4を形成する。尚、電極パッド4を形成するには、めっき法に代えて導電性ぺーストの印刷法を用いても良い。
(6)
半導体チップ5をフリップチップして、そのバンプを電極パッド4に対向させ、ボンディングを行って実装する。尚、半導体チップ5のバンプとしては、はんだバンプや金バンプを用いる。
(1)
表出された同軸ケーブル2の端面に於ける中心導体2B上にめっき法を適用してAu、Ag、Cuなどから選択された材料からなる電極パッド4を形成すると共にシールド被覆2Aと接続された電極パッド4Aを形成する。尚、電極パッド4並びに4Aを形成するには、めっき法に代えて導電性ぺーストの印刷法を用いても良い。
(2)
半導体チップ5をフリップチップして、そのバンプを電極パッド4に対向させ、また、電極パッド4及び電極パッド4Aに同軸ケーブル−導波管変換器6を介して導波管アンテナ7を対向させてボンディングを行って実装する。尚、ここで用いるバンプもはんだバンプや金バンプを用いて良い。
1A 孔
2 同軸ケーブル
2A シールド被覆
3 絶縁性樹脂
4 電極パッド
Claims (3)
- 複数の半導体チップどうし或いは半導体チップとアンテナを接続するパッケージ用基板であって、
複数の貫通孔が設けられた導電性金属コア基板と、
シールド被覆が表出されており、先端がそれぞれ前記貫通孔のいずれかに嵌挿され、且つ、シールド被覆が前記貫通孔の周縁に電気接続されてなる同軸ケーブルと、
前記金属コア基板から露出する同軸ケーブルを埋め込む絶縁性樹脂と、
前記金属コア基板に表出された同軸ケーブル先端に於ける中心導体の端面に形成された電極パッドと
を備えてなることを特徴とするパッケージ用基板。 - 前記半導体チップは、バンプを備えており、
前記バンプは、前記金属コア基板に表出された同軸ケーブル先端に於ける中心導体の端面に形成された電極パッドに電気接続されること
を特徴とする請求項1記載のパッケージ用基板。 - 前記アンテナは、導波管の接合部を備えており、前記接合部は、前記金属コア基板に表出された同軸ケーブル先端に於ける中心導体の端面に形成された電極パッドに同軸−導波管変換器を介して結合されること
を特徴とする請求項1または2記載のパッケージ用基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005079752A JP4768292B2 (ja) | 2005-03-18 | 2005-03-18 | パッケージ用基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005079752A JP4768292B2 (ja) | 2005-03-18 | 2005-03-18 | パッケージ用基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006261557A JP2006261557A (ja) | 2006-09-28 |
JP4768292B2 true JP4768292B2 (ja) | 2011-09-07 |
Family
ID=37100424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005079752A Active JP4768292B2 (ja) | 2005-03-18 | 2005-03-18 | パッケージ用基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4768292B2 (ja) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0537211A (ja) * | 1991-07-26 | 1993-02-12 | Nec Corp | 同軸導波管変換回路 |
US5949383A (en) * | 1997-10-20 | 1999-09-07 | Ericsson Inc. | Compact antenna structures including baluns |
JP4106592B2 (ja) * | 2002-03-20 | 2008-06-25 | 富士通株式会社 | 配線基板及びその製造方法 |
JP2004007176A (ja) * | 2002-05-31 | 2004-01-08 | Toko Inc | 導波管アンテナ |
-
2005
- 2005-03-18 JP JP2005079752A patent/JP4768292B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2006261557A (ja) | 2006-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6842093B2 (en) | Radio frequency circuit module on multi-layer substrate | |
EP1307078B1 (en) | High frequency circuit module | |
KR100723635B1 (ko) | 고주파 신호를 전달하기 위한 변환 회로 및 이를 구비한송수신 모듈 | |
EP3358670A1 (en) | Multilayer dielectric substrate and semiconductor package | |
US9647313B2 (en) | Surface mount microwave system including a transition between a multilayer arrangement and a hollow waveguide | |
JP6643714B2 (ja) | 電子装置及び電子機器 | |
JPWO2011118544A1 (ja) | 無線モジュール及びその製造方法 | |
US20060082422A1 (en) | Connection structure of high frequency lines and optical transmission module using the connection structure | |
EP1081989A2 (en) | High frequency wiring board and its connecting structure | |
US6998292B2 (en) | Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier | |
JP3631667B2 (ja) | 配線基板およびその導波管との接続構造 | |
JP3420913B2 (ja) | 半導体チップ実装用回路基板、半導体チップ収納用パッケージ、及び半導体デバイス | |
JP4883010B2 (ja) | 電子部品パッケージ | |
JP3217677B2 (ja) | 高周波用半導体装置 | |
JP4448461B2 (ja) | 半導体パッケージの作製方法 | |
JP4768292B2 (ja) | パッケージ用基板 | |
JP3619396B2 (ja) | 高周波用配線基板および接続構造 | |
JP3140385B2 (ja) | 高周波用半導体装置 | |
JP3998562B2 (ja) | 半導体装置 | |
JP3462062B2 (ja) | 高周波用伝送線路の接続構造および配線基板 | |
US7105924B2 (en) | Integrated circuit housing | |
JP2007235149A (ja) | 半導体装置および電子装置 | |
US11658374B2 (en) | Quasi-coaxial transmission line, semiconductor package including the same, and method of manufacturing the same | |
JP4186166B2 (ja) | 高周波回路モジュールおよび通信機 | |
JP2000040771A (ja) | 高周波パッケージ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080121 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100311 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100427 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100615 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110329 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110525 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110614 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110616 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4768292 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140624 Year of fee payment: 3 |