JP4761906B2 - 半導体集積回路の設計方法 - Google Patents

半導体集積回路の設計方法 Download PDF

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Publication number
JP4761906B2
JP4761906B2 JP2005279917A JP2005279917A JP4761906B2 JP 4761906 B2 JP4761906 B2 JP 4761906B2 JP 2005279917 A JP2005279917 A JP 2005279917A JP 2005279917 A JP2005279917 A JP 2005279917A JP 4761906 B2 JP4761906 B2 JP 4761906B2
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JP
Japan
Prior art keywords
path
delay
variation
component
integrated circuit
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Expired - Fee Related
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JP2005279917A
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English (en)
Japanese (ja)
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JP2007094512A5 (enExample
JP2007094512A (ja
Inventor
篤志 吉川
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005279917A priority Critical patent/JP4761906B2/ja
Priority to US11/516,552 priority patent/US7512920B2/en
Publication of JP2007094512A publication Critical patent/JP2007094512A/ja
Publication of JP2007094512A5 publication Critical patent/JP2007094512A5/ja
Priority to US12/379,361 priority patent/US7707531B2/en
Application granted granted Critical
Publication of JP4761906B2 publication Critical patent/JP4761906B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2005279917A 2005-09-27 2005-09-27 半導体集積回路の設計方法 Expired - Fee Related JP4761906B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005279917A JP4761906B2 (ja) 2005-09-27 2005-09-27 半導体集積回路の設計方法
US11/516,552 US7512920B2 (en) 2005-09-27 2006-09-07 Method and program for designing semiconductor integrated circuits, and semiconductor integrated circuit designing apparatus
US12/379,361 US7707531B2 (en) 2005-09-27 2009-02-19 Method and program for designing semiconductor integrated circuits, and semiconductor integrated circuit designing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005279917A JP4761906B2 (ja) 2005-09-27 2005-09-27 半導体集積回路の設計方法

Publications (3)

Publication Number Publication Date
JP2007094512A JP2007094512A (ja) 2007-04-12
JP2007094512A5 JP2007094512A5 (enExample) 2008-07-31
JP4761906B2 true JP4761906B2 (ja) 2011-08-31

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Family Applications (1)

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JP2005279917A Expired - Fee Related JP4761906B2 (ja) 2005-09-27 2005-09-27 半導体集積回路の設計方法

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US (2) US7512920B2 (enExample)
JP (1) JP4761906B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4761906B2 (ja) * 2005-09-27 2011-08-31 ルネサスエレクトロニクス株式会社 半導体集積回路の設計方法
US8341575B2 (en) 2007-04-24 2012-12-25 Nec Corporation Circuit design device, circuit design method, and circuit design program
US7861200B2 (en) * 2008-03-24 2010-12-28 Freescale Semiconductor, Inc. Setup and hold time characterization device and method
JP5304088B2 (ja) * 2008-07-31 2013-10-02 富士通株式会社 遅延時間分布を解析する解析方法および解析装置
US8762908B1 (en) 2009-12-04 2014-06-24 Cadence Design Systems, Inc. Static timing analysis with design-specific on chip variation de-rating factors
US8407640B2 (en) * 2010-08-25 2013-03-26 Synopsys, Inc. Sensitivity-based complex statistical modeling for random on-chip variation
JP5785725B2 (ja) * 2010-10-15 2015-09-30 富士通株式会社 電力見積装置、電力見積方法及びプログラム
US9898565B2 (en) 2015-11-25 2018-02-20 Synopsys, Inc. Clock jitter emulation
US10255395B2 (en) * 2016-03-11 2019-04-09 Synopsys, Inc. Analyzing delay variations and transition time variations for electronic circuits

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005122298A (ja) * 2003-10-14 2005-05-12 Fujitsu Ltd タイミング解析装置、タイミング解析方法及びプログラム
US7266474B2 (en) * 2005-08-31 2007-09-04 International Business Machines Corporation Ring oscillator structure and method of separating random and systematic tolerance values
JP4761906B2 (ja) * 2005-09-27 2011-08-31 ルネサスエレクトロニクス株式会社 半導体集積回路の設計方法

Also Published As

Publication number Publication date
US7512920B2 (en) 2009-03-31
US7707531B2 (en) 2010-04-27
JP2007094512A (ja) 2007-04-12
US20090164958A1 (en) 2009-06-25
US20070073500A1 (en) 2007-03-29

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