JP4752586B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component which allows a reliable electric connection via a projection electrode with an underfill material applied. <P>SOLUTION: This electronic component comprises a projection electrode 5 composed of conductive materials and a dummy projection 6 taller than the projection electrode 5 on a substrate 2. A number of dummy projections 6 are created outside of an area having the projection electrode 5, each having a height nearly equal to that of the projection electrode. The melting point of each projection 6 lies in a temperature range except the melting point of the projection electrode 5. In addition, when the projection electrode 5 is connected to the outside, electronic component position information can be detected via the projection 6. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to an electronic component and a mounting method thereof, and more particularly, to an electronic component that allows a highly reliable electrical connection through a protruding electrode by applying an underfill material in advance, a semiconductor device using the electronic component, and a method for manufacturing the semiconductor device .

  Electronic devices typified by mobile products such as mobile phones have very high demands for higher density, smaller size, and higher performance. Various mounting techniques have been studied in order to realize these requirements.

  SiP (System in Package) is a chip stack type by wire bonding that supports high-density mounting, but it is currently the mainstream, but in order to realize high-speed signal transmission and high density, direct connection between semiconductor chips Development of a chip-on-chip (CoC) mounting technology for connecting to the substrate has started. The advantage of CoC implementation is that the data transfer density can be improved by realizing a wide bus by increasing the number of pins.

  The development point of CoC mounting technology is high-precision mounting technology that supports multiple pins and fine pitches, and mounting on the circuit surface. Therefore, the fragile low dielectric constant film (Low−) applied to the interlayer insulating film low damage flip chip mounting technology corresponding to (k film).

  In CoC mounting technology, fusion bonding using solder bumps or the like is employed as a low-damage mounting technology for flip chip bonding of upper and lower semiconductor chips.

  FIG. 14 is a cross-sectional view for explaining a conventional technique for injecting an underfill material after melt bonding of upper and lower semiconductor chips using solder bumps by flip chip bonding.

  As shown in FIG. 14A, solder bumps 54 and 55 are formed on the wiring conductor 53 in the upper chip 51 and the lower chip 52, respectively. When connecting the upper chip 51 and the lower chip 52 via the solder bumps 54 and 55, first, the upper chip 51 and the lower chip 52 are aligned, and the solder bumps 54 and 55 are made to face each other. Next, a predetermined pressure is applied to the solder bumps 54 and 55 so that all the solder bumps of the upper chip 51 and the lower chip 52 are in contact with each other. In order to detect the contact state, a load detection device is provided in the bonder, and the load at the time of contact is detected. In the case of low-damage mounting, the contact load itself may damage the interlayer insulating film of the semiconductor chip and the like, so that the contact is detected by a very small load change. Thereafter, in order to bond the solder bumps 54 and 55 sufficiently with each other and to form a target gap (gap) between the upper chip 51 and the lower chip 52, the upper chip 51 is set to a predetermined value. The solder bumps 54 and 55 are heated to the melting temperature and the upper and lower solder bumps 54 and 55 are connected to each other by pushing in the amount of pressure. In this way, flip chip bonding is completed.

  With only this flip chip bonding, stress concentrates on the small solder bumps 54 and 55, and connection failure occurs due to cracks or the like. To prevent this, underfill has been performed for a long time.

  As shown in FIG. 14B, a liquid sealing material called an underfill material 58 is dropped onto the surface of the lower chip 52 in the vicinity of the side surface of the upper chip 51 using a needle (discharge nozzle) 56, and the upper chip 51. A narrow gap (gap) g between the lower chip 52 and the lower chip 52 is permeated using capillary action (hereinafter referred to as side fill underfill). Next, by heating and curing, the reliability of the connection between the upper chip 51 and the lower chip 52 is improved, and at the same time, the surface of the semiconductor chip is protected from external stress such as humidity.

A predetermined amount of underfill material is discharged onto the surface of the lower chip 52 in the vicinity of the side edge of the upper chip 51 using the discharge nozzle 56, and the discharged underfill material is separated between the upper chip 51 and the lower chip 52 by capillary action. At this time, if there is uneven flow of the underfill material in the gap, for example, air existing in the gap is not pushed out of the gap by the underfill material and remains in the gap as bubbles 57. If the discharge amount of the underfill material from the discharge nozzle 56 is small, the unfilled portion 59 of the underfill material 58 is used.
Remains, and the fillet portion is not formed. The state in which such bubbles 57 and unfilled portions 59 are formed is easily affected by the external environment, and becomes a major cause of reducing reliability.

  Further, in the side fill underfill, since the osmotic pressure due to the capillary action of the underfill material is injected into the gap between the upper chip 51 and the lower chip 52, the surface condition (dirt etc.) of the upper chip 51 and the lower chip 52 and the gap The underfill material injectability varies depending on the area and the density of the solder bumps 54 and 55 depending on the location, etc., so that a portion where the underfill material is not injected is generated and voids (bubbles) are generated. This causes a problem of deteriorating long-term reliability. In addition, it takes time to complete the injection of the underfill material, and there is a problem that productivity is low and a dedicated device is required for sidefill underfill, resulting in an increase in capital investment.

  Side fill underfill has many problems, such as poor workability, easy voids, and the area where dripping underfill material is required, and there are restrictions on the chip size to be joined. A fill process has been proposed.

  FIG. 15 is a cross-sectional view for explaining the prior art in which the upper and lower semiconductor chips are joined by flip chip bonding after applying an underfill material to the surface of the lower semiconductor chip.

  As shown in FIG. 15, the underfill material 58 (liquid resin) is first supplied onto the lower chip 52, the gap between the upper chip 51 and the lower chip 52 is held at a predetermined value, and solder bumps 54, 55 are provided. At the same time as flip-chip connection, underfill sealing is completed (hereinafter referred to as no-flow underfill or no-flow type underfill).

  Non-patent document 1 entitled “Technological trend of semiconductor encapsulating material” includes a method of infiltrating liquid encapsulating resin from the periphery of the chip into a narrow gap between the chip and the substrate using a capillary phenomenon, and heat-curing. NCP (Non Conductive), a no-flow type underfill system that first supplies underfill resin (which also has a flux function) onto the substrate and completes underfill sealing at the same time as flip chip connection in the reflow process after chip mounting. a method called an NCP process in which a chip is mounted after applying a liquid resin called a paste) material on a substrate, and a mechanical metal-to-metal bond is fixed by pressurization and heating for a short time (several seconds to 10 seconds), and There is a description regarding the characteristics of lead-free solder materials.

  Non-Patent Document 2 entitled “LSI Assembly Technology for Consumer Products Realizing High-Density Mounting” includes a description of flip chip mounting technology and bump forming technology, pressure contact flip chip mounting technology, and multi-pin ultrasonic flip chip mounting technology. In addition, there is a description that mounting stress reduction such as low load and low vibration amplitude is required by adopting fine pitch of LSI terminals and adopting fragile low-k material (low dielectric constant material).

  Patent Document 1 below entitled “Semiconductor Device and Manufacturing Method Thereof” has the following description.

  A semiconductor device according to the invention of Patent Document 1 has a semiconductor element having a first terminal on a main surface and a second terminal disposed on the surface corresponding to the first terminal, A wiring board on which the semiconductor element is placed as an opposing surface; and a conductive bump that is bonded to the first terminal and the second terminal by melting and electrically connects the semiconductor element and the wiring board; A gap adjusting member that is interposed between the semiconductor element and the substrate and adjusts a distance between these gaps; and a resin sealing body that is formed in the gap and includes a resin that activates a metal surface; And at least a part of the gap adjusting member is in contact with both the gap adjusting member and the semiconductor element.

  The gap adjusting member has a height less than a total value of the height of the first terminal, the height of the conductive bump before melting, and the height of the second terminal, and the height is more specific. Specifically, it is preferably 20 μm or more and 200 μm.

  The gap adjusting member included in the semiconductor measure may be a spherical particle.

  The gap adjusting member may be a protrusion formed on either the circuit wiring board or the facing surface of the semiconductor chip.

  In Patent Document 1, particles for maintaining the gap size at a constant value are contained in the resin for no-flow underfill, and the gap is maintained at a constant size without being crushed below the particle size. In order to advance the curing of the resin, or to provide a plurality of protrusions on the chip side or the substrate side for maintaining the gap size at a constant value, the curing of the resin for no-flow underfill is advanced in the gap of a certain size. . Accordingly, the material of the particles and protrusions is selected so that the shape is not significantly changed due to damage caused by the load and heat during heating.

  Patent Document 2 below entitled “Flip Chip Mounting Method” has the following description.

  The flip chip mounting method of the invention of Patent Document 2 is a method of flip chip mounting a semiconductor component chip on the surface of a substrate, and a connection pad provided on the substrate and an electrode pad formed on the back surface of the semiconductor component chip When using a bump-shaped solder, the area of the connection pad is made smaller than the area of the corresponding electrode pad, and a bump-shaped solder used on the surface of the connection pad is produced, Surrounding the connection pads provided with bump-shaped solder, a solder resist layer is provided on the substrate surface, and a substrate surface region surrounded by the solder resist layer is formed as a recess, and at that time, the layer thickness of the solder resist layer, Comparing the height of the bump-shaped solder top formed on the surface of the connection pad from the substrate surface, the height of the bump-shaped solder top is the thickness of the solder resist layer. The semiconductor component corresponding to the connection pad provided on the substrate is filled with a liquid thermosetting resin composition containing a flux agent to a depth exceeding the bump-shaped solder top. The semiconductor component chip is aligned and overlapped in an arrangement where the electrode pad formed on the back surface of the chip is positioned, and the liquid thermosetting containing the flux agent on the electrode pad surface formed on the back surface of the semiconductor component chip The temperature at which melting of the bump-shaped solder and the thermosetting of the liquid thermosetting resin composition occur in a state in which a load is applied to the semiconductor component chip while maintaining the arrangement and maintaining the arrangement The substrate surface and the semiconductor by the flux treatment by the action of the flux agent, the subsequent solder bonding by the melted solder material, and the thermosetting of the thermosetting resin composition A flip chip mounting method which is characterized in that the sealing and adhesive fixing by thermosetting material into the gap between the component chips. In this flip chip mounting method, tin alloy solder can be used as a solder material constituting the bump-shaped solder.

  In the flip-chip mounting method of the invention of Patent Document 2, the height from the substrate surface of the bump-shaped solder top formed on the connection pad and the thickness of the electrode pad formed on the back surface of the semiconductor component chip The total value is obtained by subtracting the electrode pad thickness and the connection pad thickness from the layer thickness of the solder resist layer, and multiplying the electrode pad area by the volume value. It is preferable that the volume is selected to be larger than the volume of the solder portion of the solder.

  In Patent Document 2, the solder resist layer functions as a spacer that defines a gap between a semiconductor component chip to be mounted and a wiring board. The underfill agent contains a flux agent.

  Patent Document 3 described later entitled “Electronic Component Mounting Method” includes the following description.

  In the electronic component mounting method according to claim 1 of the invention of Patent Document 3, a solder portion is formed on at least one of the electrode of the substrate or the electrode of the electronic component, and the solder portion forms an electrode on the substrate. An electronic component joining method for solder-joining an electrode of an electronic component, wherein a thermosetting resin containing a curing agent having a melting point temperature lower than a solder melting point temperature is applied to the substrate and applied to the electrode or electrode of the substrate A step of covering the formed solder part, a step of aligning the solder part with the solder part formed on the electrode or the electrode, and a solder part formed on the electrode or the electrode. Heating the electronic component in a pressed state to cure the thermosetting resin, and in the step of heating the electronic component, the solder portion is melted before the thermosetting resin is completely cured. temperature It was to raise the temperature to above.

  The electronic component mounting method according to claim 2 of the invention of Patent Document 3 is the electronic component mounting method according to claim 1, wherein the thermosetting resin is the electronic component mounting method according to claim 1. In addition, at least a first curing agent having a melting point lower than the melting point of the solder and a second curing agent having a melting point higher than the melting point of the solder are included.

  According to the invention of Patent Document 3, in the step of heating the electronic component, the temperature of the solder portion is raised to the melting point temperature of the solder or higher before the thermosetting resin is completely cured, so Wetting and spreading of the molten solder is not hindered, a highly reliable joint with a good shape can be obtained, and the mounting time can be shortened by promoting the curing of the thermosetting resin.

  In the flip chip bonding apparatus, the head part is lowered, the chip is pressed against the substrate, and the chip and the substrate are bonded by pressurization and heating, but various control of the mounting load when the chip is mounted on the substrate. Methods are known (see, for example, Patent Documents 4, 5, and 6 described later).

  Japanese Patent Application Laid-Open No. 2004-228561 describes a “component mounting apparatus and method” that performs component mounting by load control and component mounting by pushing amount control.

  Patent Document 5 describes a “flip chip bonding apparatus” that bonds all the bumps of a flip chip against the electrodes of the substrate with a uniform force while maintaining the posture of the pressing head correctly.

  Patent Document 6 entitled “Bonding Tool and Bonding of Semiconductor Chip Using the Tool” includes the following description.

  The invention of Patent Document 6 ensures parallelism between the face surface of the semiconductor chip and the surface of the mounting substrate even when the mounting substrate is flip-chip connected to the mounting substrate, even if the mounting substrate is deformed by heat warp or the like. It is an object of the present invention to provide a simple bonding tool that can be used and a semiconductor chip bonding method using the same.

  A bonding tool according to claim 1 of the invention of Patent Document 6 is a suction head unit for holding a semiconductor chip face down, and driving the suction head unit to place the semiconductor chip held by the suction head unit on a mounting substrate. A semiconductor chip face having a drive unit that is transported and mounted and a head surface adjustment unit that adjusts the inclination of the head surface of the suction head unit, and is held by the suction head unit using the head surface adjustment unit After the surface is made parallel to the surface of the mounting substrate, the semiconductor chip and the mounting substrate are flip-chip connected.

  Further, in the bonding tool according to claim 1 of the invention of Patent Document 6, a plurality of pressure sensors for detecting pressures at a plurality of locations when the semiconductor chip held by the suction head portion contacts the mounting substrate surface are provided. And adjusting the inclination of the head surface of the suction head unit by the head surface adjustment unit based on the pressure values at a plurality of locations detected by the plurality of pressure sensors.

  When deformation such as warpage due to heat has occurred on the mounting board, the pressure sensor closest to the first contact portion of the semiconductor chip to the mounting board surface detects the largest pressure value, and the farthest pressure sensor has the smallest. The pressure value is not detected, and the pressure values at a plurality of locations on the semiconductor chip vary depending on the deformation of the mounting substrate. For this reason, when the head surface adjustment unit adjusts the inclination of the head surface of the suction head unit, it corrects the variation in the pressure values detected by the plurality of pressure sensors, thereby correcting the pressure at the plurality of points on the semiconductor chip. Since the values may be adjusted to be uniform, the face surface of the semiconductor chip can be easily made parallel to the mounting substrate surface.

  Further, in the bonding tool according to claim 1 of the invention of Patent Document 6, a plurality of portions between the face surface of the semiconductor chip and the surface of the mounting substrate when the semiconductor chip held by the suction head portion approaches the mounting substrate. It has an interval measuring device for detecting the interval between the points, and the head surface adjusting unit adjusts the inclination of the head surface of the suction head unit based on the intervals of the plurality of points detected by the interval measuring device. To do.

  When the mounting substrate is deformed such as warpage due to heat, it is detected that variations occur at intervals between a plurality of adjacent locations between the semiconductor chip face surface and the mounting substrate surface. For this reason, when the head surface adjustment unit adjusts the inclination of the head surface of the suction head unit, the variation in the intervals detected by the interval measuring device is corrected, and the face surface of the semiconductor chip and the mounting substrate surface are corrected. Therefore, the face surface of the semiconductor chip can be easily made parallel to the mounting substrate surface.

  In Patent Document 6, the adjustment of the inclination of the head surface of the suction head unit can be automated.

JP 2001-53109 A (FIG. 1, FIG. 2, paragraphs 0010 to 0013, paragraphs 0019 to 0026, paragraphs 0029 to 0036, paragraphs 0045 to 0046, paragraph 0053) JP-A-2003-100809 (FIGS. 1, 2, and 3, paragraphs 0011 to 0012, paragraph 0018, paragraph 0027, and paragraph 0026).

Japanese Patent Laid-Open No. 11-214440 (paragraphs 0007 to 0009, FIGS. 1 and 2) JP-A-9-199545 (paragraphs 0011 to 0013, paragraph 0018, FIG. 1) JP 2002-93856 (paragraphs 0006 to 0008, paragraph 0021, FIGS. 1 and 2) Japanese Patent Laid-Open No. 11-297664 (paragraphs 0011, 0012, paragraphs 0014 to 0017, first embodiment, second embodiment) Fukui, Matsushita Electric Engineering Technical Report, Feb. 2004, p. 9-15 (p.10, p.13-14) Kira et al., FUJITSU, 56, 6, p. 539-544 (11, 2005) (p. 540-544)

  As shown in FIG. 14A, in CoC mounting of a semiconductor chip using a low dielectric constant film (Low-k), low damage flip chip bonding with low load is required, and the upper chip 51 and the lower chip 52 are The load for detecting the contact of the solder bumps 54 and 55 is very small. When the side fill underfill is employed, the underfill material 58 has no influence on the contact between the solder bumps 54 and 55 of the upper chip 51 and the lower chip 52.

  However, as shown in FIG. 15, when no-flow underfill is adopted, the load for detecting the contact between the solder bumps 54 and 55 of the upper chip 51 and the lower chip 52 is very small. The presence of the underfill material 58 applied to the solder bumps 55 of the lower chip 52 greatly affects the load detection at the time of contact of 55. In order to realize low-damage flip chip bonding, the underfill material applied to the surfaces of the solder bumps 54 of the upper chip 51 and the lower chip 52 in order to detect contact between the solder bumps 54 and 55 with a very small load. The load is detected at the time of contact with 58, and there is a problem that the contact of the solder bumps 54 and 55 cannot be detected accurately. That is, the contact between the solder bump 54 of the upper chip 51 and the underfill material 58 is erroneously detected as the contact between the solder bump 54 of the upper chip 51 and the solder bump 55 of the lower chip 52.

  Since the contact between the solder bumps 54 and 55 cannot be detected accurately, the gap (g) between the upper chip 51 and the lower chip 52 cannot be accurately maintained at a predetermined value, and the solder bumps 54 of the upper chip 51 There is a problem that contact between the lower chip 52 and the solder bump 55 is not sufficiently ensured, resulting in poor bonding.

  In order to avoid the contact between the solder bump 54 and the underfill material 58 prior to the contact between the solder bump 54 and the solder bump 55, the load is detected first by the contact between the solder bump 54 and the solder bump 55. Therefore, when the amount of the underfill material (precoat resin) 58 is adjusted and applied to the lower chip 52, the amount of the underfill material 58 for filling the gap between the upper chip 51 and the lower chip 52 is insufficient. As a result, bubbles (voids) are generated, resulting in a problem of poor reliability.

  As described above, there are many problems in adopting no-flow underfill for CoC mounting by low damage flip chip bonding. At present, no-flow underfill cannot be adopted, and side fill using capillary phenomenon is used. Underfill is adopted, voids are likely to remain, and reliability is likely to be deteriorated. The area where the underfill material is dropped is required for the lower chip, and the size of the lower chip is increased, so there is a limit to the miniaturization of CoC mounted products. There is a problem that there is.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to make it possible to apply an underfill material in advance to enable reliable electrical connection via protruding electrodes. An object is to provide a component, a semiconductor device using the component, and a method for manufacturing the semiconductor device.

  That is, the present invention relates to an electronic component having a protruding electrode made of a conductive material and a dummy protruding portion having a height larger than that of the protruding electrode on a substrate.

  The present invention is also a semiconductor device in which a semiconductor chip is electrically connected to the electronic component via the protruding electrode, and the electric insulation adhered to the surface of the electronic component in the inner region of the protruding portion The semiconductor chip is fixed to the electronic component by a material.

  The present invention also provides a semiconductor device in which a protruding electrode is formed on at least one surface of the first and second electronic components, and the first and second electronic components are electrically connected via the protruding electrode. In the manufacturing method, a first step of forming a dummy protrusion having a height greater than the protrusion electrode on the surface of the first electronic component, and a surface of the first electronic component from the protrusion electrode A second step of attaching an electrical insulating material that is higher and lower than the protrusion, the first electronic component and the second electronic component are brought close to each other, and the second electronic component and the protrusion A third step of detecting a contact of the first electronic component and the first electronic component until the distance between the first electronic component and the second electronic component reaches a predetermined value after the contact is detected. A fourth step of bringing the second electronic component closer to each other Those relating to the manufacturing process.

  According to the electronic component of the present invention, since the dummy projecting portion having a height larger than the projecting electrode is provided, the projecting electrode is covered with an electrical insulating material when the projecting electrode is externally connected, and the projecting electrode By applying the electrical insulating material in advance on the surface of the electronic component so as to be lower than the portion, it is possible to prevent air bubbles from being mixed into the electrical insulating material and to make highly reliable electrical connection. it can. That is, it is possible to provide an electronic component suitable for flip chip bonding with high reliability by applying the electrical insulating material in advance.

  According to the semiconductor device of the present invention, a gap is set using the protrusion, and the semiconductor chip is formed by the electrical insulating material attached to the surface of the electronic component in the inner region of the protrusion. Since it is fixed to the electronic component, the semiconductor chip and the electronic component can be electrically connected with high reliability through the protruding electrode while accurately maintaining a predetermined gap.

  According to the method for manufacturing a semiconductor device of the present invention, a protrusion having a height larger than that of the protrusion electrode is formed on the surface of the first electronic component, and the surface of the first electronic component is An electrical insulating material that is higher than the protruding electrode and lower than the protruding portion is attached, and the first electronic component and the second electronic component are brought close to each other, and the second electronic component and the protruding portion are After the contact is detected, the first electronic component and the second electronic component are brought closer to each other until the distance between the first electronic component and the second electronic component reaches a predetermined value. Contact between the first electronic component and the second electronic component can be accurately detected without being affected by the presence of the electrical insulating material. Accordingly, the distance between the first electronic component and the second electronic component can be accurately maintained at a predetermined value, and bubbles can be prevented from being generated due to an insufficient amount of adhesion of the electrical insulating material. . As a result, it is possible to provide a method for manufacturing a highly reliable semiconductor device that enables low-damage flip-chip bonding with low load.

  In the electronic component of the present invention, it is preferable that the protruding portion is formed outside the region where the protruding electrode is formed. Since the protruding portion is formed so as to surround the protruding electrode, it is only necessary to add the protruding electrode to a conventional electronic component. When the protruding electrode is externally connected, the position information of the electronic component is displayed as the protruding portion. It can be detected by the part.

  Further, it is preferable that a plurality of the protruding electrodes are provided, and these have substantially the same height. The protruding electrode can be externally connected with high reliability.

  Also, it is preferable that a plurality of the protrusions are provided and these have substantially the same height. When the protruding electrode is externally connected, position information of the electronic component can be accurately detected by the plurality of protruding portions, and the protruding electrode can be externally connected with high reliability.

  Further, it is preferable that a melting point of the protruding portion is in a temperature range equal to or lower than a melting point of the protruding electrode. Furthermore, it is preferable that the protrusion has a melting point of 180 ° C. or higher and a predetermined temperature range equal to or higher than the melting point of the protruding electrode. When the protruding electrode is externally connected, the position information of the electronic component can be accurately detected by the protruding portion without being affected by the presence of the protruding electrode, and the presence of the protruding portion is determined by the protrusion. It does not affect the external connection of the electrode.

  Moreover, it is preferable that the protrusion is formed of a conductive material or a thermoplastic resin. When a conductive material is used for the protruding portion, for example, the same conductive material as the material constituting the protruding electrode can be used, and no special material is required for the protruding portion. Further, when a thermoplastic resin is used as the protrusion, the protrusion can be easily formed by using a film-like material and thermally fusing (heat sealing) the surface of the electronic component with a predetermined thickness. Can be formed.

  The electronic component may constitute a semiconductor chip. By bonding semiconductor chips having the same area, a small and reliable CoC mounted product can be provided.

  The electronic component may constitute a mounting board. A module in which a semiconductor chip is electrically connected to an interposer substrate with high reliability can be provided.

  In the semiconductor device of the present invention, it is preferable that the electrical insulating material is an underfill material and has a thermosetting temperature lower than the melting point of the protrusion. Since the protruding electrode and the protruding portion are not remelted, the semiconductor chip and the electronic component are electrically connected with high reliability in a state where the protruding electrode is protected by the underfill material. Goods can be provided.

  In the method of manufacturing a semiconductor device according to the present invention, it is configured to detect contact between the protrusion formed on the first electronic component and the second protrusion formed on the second electronic component. Good. Since the first and second electronic components are respectively formed with protrusions to detect the positional relationship between the first and second electronic components, the heights of the first and second protrusions are respectively The first and second protrusions may be smaller than the height of the protrusion electrode, and the height of the first and second protrusions may be lower than when the protrusion is formed only on one of the first and second electronic components. May be formed.

  In addition, prior to the third step, there is a step of heating the first and second electronic components such that the temperature of the protruding portion falls within a predetermined temperature range below the melting point of the protruding electrode, It is preferable that the first and second electronic components are heated to the predetermined temperature range before the electrical insulating material is completely cured. The first electronic component and the second electronic component via the protrusion in a state where the protrusion is held at a temperature not lower than the predetermined temperature range (for example, the melting point of the protrusion) and not higher than the melting point of the protrusion electrode. Will be detected. The protrusion is usually kept at 180 ° C. or higher. While the temperature of the first and second electronic components is rapidly increased to the predetermined temperature range in a short time, the thermosetting of the electrical insulating material proceeds very little, so the viscosity of the electrical insulating material is The small value is kept and does not affect the subsequent fourth step.

  In addition, prior to the fourth step, there is a step of heating the first and second electronic components such that the temperature of the protruding electrode is in a predetermined temperature range equal to or higher than the melting point thereof, and the electrical insulation Before the material is completely cured, the first and second electronic components are heated to the predetermined temperature range, and after the fourth step, the thermosetting temperature is lower than the melting point of the protrusion. In order to cure the electrical insulating material, it is preferable to include a step of holding the first and second electronic components at the predetermined temperature range or a temperature lower than the predetermined temperature range for a predetermined time. While the temperature of the first and second electronic components is rapidly increased to the predetermined temperature range in a short time, the thermosetting of the electrical insulating material proceeds very little, so the viscosity of the electrical insulating material is A small value (for example, at 100 ° C. to 200 ° C., the viscosity of the electrical insulating material is a small value in the range of 0.05 Pa · s to 1 Pa · s) is maintained. The electrical connection between the first and second electronic components is not affected by the viscosity of the electrical insulating material. Further, as the electrical insulating material, a thermosetting resin having a relatively low thermosetting temperature (temperature at which heat curing proceeds) lower than the melting point of the protruding portion and the protruding electrode is used. By maintaining the first and second electronic components in the predetermined temperature range, the time required for complete curing can be shortened. Further, the electrical insulating material can be thermoset while being held at a temperature lower than the predetermined temperature range and the protruding electrodes are solidified.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment FIG. 1 shows an upper semiconductor chip (hereinafter simply referred to as an upper chip) 1 and a lower semiconductor chip (hereinafter simply referred to as a lower chip) bonded by flip chip bonding in the first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along a ZZ portion.

  As shown in FIG. 1, in the bonding region 9 of the upper chip 1, the solder bump (projection electrode) 4 has a predetermined height (h1) on the wiring conductor 3, and the upper projection 7 has a predetermined height (H1). Are formed respectively. Note that H1 ≧ h1. Further, in the bonding region 9 of the lower chip 2, the solder bump (projection electrode) 5 is formed on the wiring conductor 3 with a predetermined height (h2), and the lower protrusion 6 is formed with a predetermined height (H2). Yes. Note that H2 ≧ h2. In this embodiment, the solder bumps 4 and 5, the upper protrusion 7 and the lower protrusion 6 are each formed in a spherical crown shape. The solder bumps 4 and 5, the upper protrusion 7 and the lower protrusion 6 are each formed of the same solder material.

  The protruding electrodes formed by the solder bumps 4 shown in FIG. 1 are used for electrically connecting the upper chip 1 and the lower chip 2. The upper protrusion 7 and the lower protrusion 6 are used to accurately define the distance of the gap after the upper chip 1 and the lower chip 2 are joined. It is used to prevent air bubbles from entering due to a shortage of underfill material filling the gap at the same time as joining. The upper protrusion 7 and the lower protrusion 6 are dummy protrusions that are essentially irrelevant to the electrical connection between the upper chip 1 and the lower chip 2 and are formed at a height greater than the protrusion electrodes. It may be formed of any one of a conductive material and an insulating material.

  In FIG. 1, 20 solder bumps 4 and 5 are shown, but this is for the sake of simplicity. Actually, a large number of solder bumps 4 and 5 are formed (the same applies to the following drawings). .) Further, although four upper protrusions 7 and lower protrusions 6 are illustrated, any number of three or more may be formed (the same applies to the respective drawings described below).

  As shown in FIG. 1 (B), when the upper chip 1 and the lower chip 2 are joined by flip chip bonding via the solder bumps 4 and 5, the surface of the lower chip 2 is preliminarily provided as a precoat resin. A filling material (electrical insulating material) 8 is applied by a predetermined amount so as to cover the solder bumps 5 so that the maximum height (d) does not exceed the height of the lower protrusions 6. d <H2. The underfill material 8 preferably has a temperature of 100 to 200 ° C. and a viscosity of 0.05 Pa · s to 1 Pa · s, and is easier to apply than the height of the lower protrusion 6.

  Normally, an under bump metal (UBM) is formed between the wiring conductor 3 and the solder bumps 4 and 5 as a barrier metal for preventing metal diffusion. The upper protrusion 7 and the lower protrusion 6 are formed on an under bump metal formed as a base metal layer (seed layer) formed on the upper chip 1 and the lower chip 2, respectively. In FIG. 1, the under bump metal is not shown (the same applies to FIGS. 2 to 15).

  In FIG. 1, the upper protrusion 7 may be formed in the same manner as the solder bump 4. In this case, H1 = h1. Further, the upper protrusion 7 may not be formed. In this case, H1 = 0.

  FIG. 2 is a cross-sectional view taken along the line ZZ (see FIG. 1) for explaining the process of joining the upper semiconductor chip 1 and the lower semiconductor chip 2 in this embodiment, and FIG. Before, FIG. 2 (B) is a figure which shows the state in each time of the time of the time of contact after the upper protrusion part 7 and the lower protrusion part 6 and FIG. 2 (C).

  2 (A) is the same view as FIG. 1 (B), and shows a state before the upper protrusion 7 and the lower protrusion 6 are in contact, and FIG. 2 (B) lowers the upper chip 1. The upper chip 1 and the lower chip 2 approach each other, the upper protrusion 7 and the lower protrusion 6 come into contact with each other, and the state when this contact is detected is shown in FIG. From the point in time when contact between 7 and the lower projection 6 is detected, the upper chip 1 is further lowered until the gap between the upper chip 1 and the lower chip 2 reaches a predetermined value g.

  When the upper protrusion 7 and the lower protrusion 6 are not formed, the load is detected when the underfill material 8 applied higher than the solder bump 5 and the solder bump 4 come into contact with each other. In this embodiment, the contact between the upper protrusion 7 and the lower protrusion 6 formed higher than the solder bumps 4 and 5 is detected first, and from the time of detection of this contact, the defect occurs. If the upper chip 1 is pushed down by a predetermined pushing amount so as to obtain the target gap (gap) g, normal joining with the target gap g can be realized.

  For example, when the height of the solder bumps 4 and 5 is h1 = h2 = 17 μm, the height of the upper protrusion is H1 = 17 μm, the height of the lower protrusion is H2 = 25 μm, and the target gap is g = 29 μm In the state where the upper protrusion 7 and the lower protrusion 6 are in contact with each other as shown in FIG. 2B, the interval between the bonding surfaces of the upper chip 1 and the lower chip 2 is (H1 + H2) = 42 μm. If the upper chip 1 is lowered and pushed in by (H1 + H2−g) = 13 μm, a normal joining state having a target gap can be realized.

  As described above, in this embodiment, a semiconductor chip suitable for flip chip bonding with high reliability can be provided by applying an underfill material in advance.

  Before reaching the state shown in FIG. 2B, the upper chip 1 and the lower chip 2 have a predetermined temperature range in which the temperature of the upper protrusion 7 and the lower protrusion 6 is lower than the melting point of the solder bumps 4 and 5. And heated to a temperature equal to or higher than the melting point of the upper protrusion 7 and the lower protrusion 6. In addition, before reaching the state shown in FIG. 2C, the upper chip 1 and the lower chip 2 have the solder bumps 4 and 5 at a temperature in a predetermined temperature range equal to or higher than the melting point of the solder bumps 4 and 5. So that it is heated.

  The state in which the gap between the upper chip 1 and the lower chip 2 is maintained at a predetermined value g is continued for a predetermined time in a predetermined temperature range equal to or higher than the melting point of the solder bumps 4 and 5, and the underfill material is shortened in a short time. 8 can be heat cured. Further, the temperature of the upper chip 1 and the lower chip 2 is held for a predetermined time as a temperature not higher than the melting point of the solder bumps 4, 5, and the solder bumps 4, 5, the upper protrusion 7, the lower protrusion 6. The underfill material 8 can also be thermally cured in a state where is solidified.

  FIG. 2C is a conceptual diagram for explaining a state after the upper chip 1 and the lower chip 2 are joined (described later, FIG. 6C, FIG. 7C, FIG. 8D, FIG. 11C). The same applies to FIGS. 12C and 13C.) In consideration of the volume of the under bump metal (not shown), the total volume of the fused solder bumps 4 and 5 is fused. The total volume of the fused upper projection 7 and lower projection 6 is the sum of the respective volumes of the previous solder bumps 4 and 5, and the total volume of the fused upper projection 7 and lower projection 6 is the upper projection 7 and lower projection 6 before melting. It shows that the fused state is solidified as a cylinder having a height g so as to be the sum of the respective volumes.

  The size of the upper protrusion 7 and the lower protrusion 6 is the same as that of the melted upper protrusion 7 and lower protrusion 6 after the upper chip 1 and the lower chip 2 are joined at the target gap g. It is determined in advance so as to give a state in which it does not come into contact with the adjacent merged solder bumps 4 and 5. It is preferable to design the sizes of the upper protrusions 7 and the lower protrusions 6 so that the above two combined products are formed apart from the arrangement interval of the solder bumps 4 and 5. When the upper protrusion 7 is not formed, the volume of the upper protrusion 7 may be zero and the design may be performed in the same manner as described above. Furthermore, it is preferable to consider the variation in the setting of the gap (g) caused by the apparatus error of the flip chip bonding apparatus in the above design.

  3A and 3B are diagrams illustrating a configuration example of the lower semiconductor chip 2 in the present embodiment. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along the line ZZ.

  As shown in FIG. 3, the lower chip 2 is formed with solder bumps 5 that are externally connected and a lower protrusion 6 that is higher than the height of the solder bumps 5. The solder bump 5 is formed on the wiring conductor 3 by electrolytic plating. The lower protrusions 6 can be formed higher than the solder bumps 5 by printing solder on the protrusion bumps formed simultaneously with the solder bumps 5 using a printing method, and then applying flux and performing reflow. . Further, before the solder bumps 5 are formed by electrolytic plating, the lower protrusions 6 may be formed in advance only at predetermined locations by electrolytic plating or printing.

  The upper protrusion 7 and the lower protrusion 6 can be formed by an electrolytic plating method or a dispenser discharge (injection) method in which molten metal (for example, solder) is discharged (injected) from a nozzle. In the discharge (injection) method, protrusions (bumps) of different sizes can be created by controlling the discharge (injection) amount, so that externally connected bumps and lower protrusions can be formed simultaneously. The discharge method can be formed with a diameter of 70 μm or more, and the electrolytic plating method with a diameter of 10 μm.

  For example, in order to form the solder bumps 4 and 5 and the upper protrusion 7 with a diameter of 30 μm and a height of 17 μm and the lower protrusion 6 with a diameter of 75 μm and a height of 25 μm, the electrolytic plating method requires two lithography steps. Steps are performed to form solder bumps 5 and lower protrusions 6. In the discharge method, the shape of the protrusion and the solder bump is expressed by a spherical crown having the above-mentioned diameter as the lower diameter and the height described above, and the volume of the protrusion and the solder bump is set in consideration of the presence of the under bump. The volume to be discharged is calculated, and the molten metal is discharged by this volume so that the target height is obtained. When the connecting solder bumps 4, 5, 7 are of a size that can be produced by the discharge (injection) method, the discharge (injection) amount of the solder bumps 4, 5, 7 and the lower protrusion 6 is changed to 1 Can be produced in a single time.

  FIG. 4 is a diagram for explaining an outline of a configuration example of the flip chip bonding apparatus in the present embodiment.

  As shown in FIG. 4, the flip chip bonding apparatus holds a lower holder 21 that holds the lower chip 2, a horizontally placed base 20 that holds the lower holder 21, an upper chip 1, and is fixed to the bonding head 23. The upper holder 22, the bonding head holding part 25 for holding the bonding head 23, the movement of the bonding head holding part 25 in the x, y and z directions, and the surface of the bonding head 23 to which the upper holder 22 is fixed A bonding head drive unit 26 for changing the tilt angle of the bonding head, a bonding head drive control unit 27 for controlling the driving of the bonding head drive unit 26, and a monitor for observing the positional relationship between the upper chip 1 and the lower chip 2. Heating / cooling unit (not shown) for heating and cooling the unit 31, the upper chip 1 and the lower chip 2. One or more pressure detectors such as a load cell for detecting a load at the time of contact between the upper protrusion 7 and the lower protrusion 6, disposed on the lower surface of the lower holder 24, a main control unit 30 that performs control for the entire apparatus and computation for controlling the apparatus is included.

  In the configuration shown in FIG. 4, the upper chip 1 is lowered in the z direction while the bonding surface of the lower chip 2 is held horizontally and fixed, and the bonding surface of the upper chip 1 is held horizontally. The lower chip 2 with the underfill material 8 previously applied to the bonding surface is bonded to the upper chip 1. The position coordinates in the z direction of the upper chip 1 are detected in synchronization with the movement of the upper chip 1.

  It should be noted that the pressure detector 24 or the plurality of pressure detectors 24 can be disposed at any position as long as the load at the time of contact between the upper protrusion 7 and the lower protrusion 6 can be detected. Not too long.

  FIG. 5 is a flowchart for explaining an outline of the flip-chip bonding procedure in the present embodiment.

  Hereafter, each process shown in FIG. 5 is demonstrated, referring FIGS. 1-4.

S1: Mounting the lower chip on the preheated lower holder The lower chip 2 is mounted and fixed on the lower holder 21 preheated to a predetermined temperature so that the joint surface is horizontal. Needless to say, the position of the joint surface of the lower chip 2 in the z direction is known.

S2: Application of underfill resin to the surface of the lower chip The underfill material 8 (resin) is applied to the bonding surface of the lower chip 2. The application height of the underfill material 8 may exceed the height of the solder bump 5, but does not exceed the height of the lower protrusion 6.

S3: Holding the upper chip in the preheated upper holder The upper chip 1 is mounted and fixed on the upper holder 22 preheated to a predetermined temperature so that the joint surface thereof is horizontal.

S4: Alignment of the upper chip and the lower chip in the x and y directions By driving the bonding head drive unit 26, the position of the upper chip 1 is lowered to a predetermined position in the z direction, and the solder bump 4 and the solder bump 5, The main control unit 30 controls each part of the apparatus based on the detection result of the monitor unit 31 so that the upper projecting part 7 and the lower projecting part 6 face each other at the position of the respective central axes, and the upper chip 1 And the lower chip 2 are aligned in the x and y directions. Needless to say, the position of the bonding surface of the upper chip 1 in the z direction is detected in synchronization with the movement of the upper chip 1.

  In addition, you may perform the process of S2 after the process of S3 and S4.

S5: Heating of the upper holder (upper chip) and the lower holder (lower chip) so that the temperature of the upper protrusion 7 and the lower protrusion 6 is within a predetermined temperature range of 180 ° C. or higher and below the melting point of the solder bumps 4 and 5. Then, the upper holder 22 and the part holder 21 are heated to raise the temperatures of the upper chip 1 and the lower chip 2. In this temperature range, the upper protrusion 7 and the lower protrusion 6 have a melting point and are in a molten state. This temperature rise by heating is performed before the underfill material 8 is completely cured.

S6: Start of descent of bonding head The descent of the bonding head 23 is started while detecting the position of the bonding surface of the lower chip 2 in the z direction.

S7: Detection of contact between the upper chip and the lower chip via the protrusion by the pressure detector. The upper protrusion 7 and the lower protrusion 6 which are generated when the upper chip 1 and the lower chip 2 approach while the bonding head 23 is lowered. The position in the z direction (contact position) at the time of contact is stored in the main control unit 31. This contact detection is performed using one or a plurality of (three or more) pressure detectors 24. When using a plurality of pressure detectors arranged at different locations, the main controller 31 stores the contact position in the z direction at the point of contact detected by each pressure detector.

  When the contact between the upper chip 1 and the lower chip 2 via the protrusions (upper protrusion 7 and lower protrusion 6) is detected by all the pressure detectors, the descent of the bonding head 23 is temporarily stopped.

S8: Correction drive for holding the joint surfaces of the upper chip and the lower chip in parallel In S7, when a single pressure detector 24 is used, the process of S8 is omitted. Alternatively, the distance between the bonding surfaces of the upper chip 1 and the lower chip 2 is optically detected by the monitor unit 31 or the like at a plurality of three or more locations. From the data of the distance between the joint surfaces detected at a plurality of locations, the angle of inclination of the joint surface of the upper chip 1 with respect to the horizontal plane can be obtained using the least square method.

  In S7, when a plurality of pressure detectors are used, the contact position between the upper protrusion 7 and the lower protrusion 6 is formed based on the contact position data in the z direction at the time of contact detected by each pressure detector. The inclination angle of the average surface to the horizontal plane of the joint surface of the upper chip 1 can be obtained using the least square method.

  Even when a plurality of pressure detectors are not used, the contact of the solder bumps 4 and 5 can be optically detected by the monitor unit 31 or the like at three or more locations. From the contact position data in the z direction at the time of contact of the solder bumps 4 and 5 generated at each of a plurality of locations, the average formed by the contact positions of the upper protrusion 7 and the lower protrusion 6 in the same manner as described above. The angle of inclination of the flat surface of the joint surface of the upper chip 1 with respect to the horizontal plane can be obtained using the method of least squares.

  When the inclination angle obtained as described above is outside the allowable range, the upper chip 1 and the lower chip are corrected by a correction drive that rotates the joint surface of the upper chip 1 so that the inclination is zero. The two joint surfaces are held in parallel. This correction driving is executed under the control of the main control unit 30. As a result, the upper chip 1 and the lower chip 2 are joined in consideration of the influence of the warp existing in them.

  If the inclination angle is within the allowable range, it can be considered that the two joint surfaces are parallel, and this S8 can be omitted.

  S9: The bonding head is lowered and the interval between the bonding surfaces of the upper chip and the lower chip is maintained as a predetermined value and maintained for a predetermined time.

  Prior to S9, the upper chip 1 and the lower chip 2 are heated so that the temperature of the solder bumps 4 and 5 is within a predetermined temperature range equal to or higher than the melting point thereof, and the temperature of the solder bumps 4 and 5 is increased. Before the under bump material 8 is completely cured, the temperature is raised to the predetermined temperature range.

  Next, in order to thermally cure the underfill material 8 having a thermosetting temperature lower than the melting point of the upper protrusion 7 and the lower protrusion 6, the upper chip 1 and the lower chip 2 are held at the predetermined temperature for a predetermined time. Keep temperature at or below range.

  The underfill material 8 includes, for example, an epoxy resin as a main component, an acid anhydride as a curing agent, and a solder flux agent.

S10: Cooling of upper chip and lower chip After the thermosetting of the underfill material 8 is completed, the upper chip 1 and the lower chip 2 are cooled. Through the above steps, the upper chip 1 and the lower chip 2 are solder bumps. It is possible to obtain a joined product that is electrically joined by the members 4 and 5 and the joint is protected by the underfill material 8.

S11: To join the next part The joined product of the upper chip 1 and the lower chip 2 is unloaded from the apparatus and stored in the storage unit (not shown in FIG. 4), and the process proceeds to the next part joining operation.

  The main controller 30 controls the mounting of the lower chip 2 on the lower holder 21, the mounting of the upper chip 1 on the upper holder 22, the unloading of the joined product of the upper chip 1 and the lower chip 2, and the like. It is executed by an automatic transfer unit (robot unit) (not shown in FIG. 4).

  According to the present embodiment described above, no-flow underfill is employed to maintain the gap between the bonding surfaces of the upper chip and the lower chip at a target value, thereby suppressing the generation of bubbles and high reliability. Bonding can be realized with low damage. In addition, it is possible to join the semiconductor chips having the same size electrically connected and perform underfill sealing with a voidless, which is difficult in the prior art, and the degree of freedom in mounting design can be improved.

Second Embodiment FIG. 6 is a diagram for explaining a configuration example of an upper semiconductor chip 1 and a lower semiconductor chip 2 bonded by flip chip bonding and a bonding process in the second embodiment of the present invention. 6A is a plan view showing a state before joining, FIG. 6B is a cross-sectional view of the ZZ portion showing the state before joining, and FIG. 6C is a Z- showing the state after joining. It is sectional drawing in a Z section.

  Hereinafter, differences from the first embodiment will be described, and description of the same points as those of the first embodiment will not be repeated. The same applies to third to eighth embodiments to be described later.

  In the present embodiment, the upper protrusion 7 is formed on the wiring conductor 3 with the same configuration as the solder bump 4. That is, the height and volume of the upper protrusion 7 are the same as the height and volume of the solder bump 4.

  FIGS. 7A and 7B are diagrams for explaining a modification of FIG. 6. FIG. 7A is a plan view showing a state before joining, and FIG. FIG. 7C is a cross-sectional view taken along the line ZZ showing the state after bonding.

  The modification shown in FIG. 7 is an example in which the number of the upper protrusions 7 and the lower protrusions 6 in the configuration shown in FIG. When the parallelism of the upper chip 1 and the lower chip 2 is within an allowable range, there is little influence on the bonding of the warps of the two chips, so in order to detect the inclination of the bonding surface of the upper chip 1 and the lower chip 2 The configuration shown in FIG.

  6 and 7, for example, the upper protrusion 7 and the solder bumps 4 and 5 are formed in a spherical crown shape having a lower diameter of 30 μm and a height of 12 μm on an unillustrated under bump metal having a diameter of 30 μm and a thickness of 5 μm. Then, the lower protrusion 6 is formed in a spherical crown shape having a lower diameter of 30 μm and a height of 20 μm on an unillustrated under bump metal having a diameter of 30 μm and a thickness of 5 μm.

  When the target gap is g = 23.5 μm, the diameter of the cylindrical combined product of the upper projection 7 and the lower projection 6 melted after joining is the same as that of the upper projection 7 and the lower projection 6 before joining. Since it is smaller than the lower diameter, it is sufficient that the distance between the upper protrusion 7 and the solder bump 4 and the distance between the lower protrusion 6 and the solder bump 5 are 30 μm.

  Here, when the gap is set to, for example, g = 18.5 μm due to the setting variation (for example, ± 5 μm) of the gap (g) caused by the apparatus error of the flip chip bonding apparatus, the melted after bonding. Since the diameter of the cylindrical combination of the upper protrusion 7 and the lower protrusion 6 is about 15 μm larger than the lower diameter of the upper protrusion 7 and the lower protrusion 6 before bonding, the reliability and yield of bonding are taken into consideration. Then, it is preferable that the distance between the upper protrusion 7 and the solder bump 4 and the distance between the lower protrusion 6 and the solder bump 5 are {30+ (15-20)} μm = 50 μm or more.

  The values of the distance between the upper protrusion 7 and the solder bump 4 and the distance between the lower protrusion 6 and the solder bump 5 are designed as follows: upper protrusion 7, lower protrusion 6, solder bumps 4, 5 Since it depends on the lower diameter and height, it is basically preferable to design as described in the first embodiment.

Third Embodiment FIG. 8 is a diagram for explaining a configuration example of the upper semiconductor chip 1 and the lower semiconductor chip 2 bonded by flip chip bonding and the bonding process in the third embodiment of the present invention. 8A is a plan view showing a state before joining, FIG. 8B is a cross-sectional view taken along the line ZZ showing the state before joining, and FIG. 8C is a diagram showing the lower protrusion 6 and the upper semiconductor chip. Sectional drawing in the ZZ part which shows the state at the time of 1 contact, FIG.8 (D) is sectional drawing in the ZZ part which shows the state after joining.

  In the present embodiment, the upper protrusion 7 is not formed in the first embodiment. As described above, in the first embodiment, it may be understood that the volume of the upper protrusion 7 is zero. In the present embodiment, it is necessary to make the height of the lower protrusion 6 larger than the height of the lower protrusion 6 in the first character intention form and the second embodiment.

  In FIG. 8, for example, when the solder bumps 4 and 5 are formed in a spherical crown shape having a lower diameter of 30 μm and a height of 12 μm on an unillustrated under bump metal having a diameter of 30 μm and a thickness of 5 μm, the height is 34 μm or more. It is necessary to form a certain lower protrusion 6.

  The lower protrusion 6 is formed in a spherical crown shape having a lower diameter of 75 μm and a height of 35 μm on an unillustrated under bump metal having a diameter of 75 μm and a thickness of 5 μm. When the target gap is g = 23.5 μm, the diameter of the cylindrical united product of the lower protrusions 6 melted after joining is about 100 μm, which is about 25 μm larger than the lower diameter 75 μm before joining. The distance between the protrusion 6 and the solder bump 5 is preferably {30+ (25-30)} μm = 60 μm or more.

  Further, considering the case where the gap is set to, for example, g = 18.5 μm due to the setting variation (for example, ± 5 μm) of the gap (g) caused by the apparatus error of the flip chip bonding apparatus, Since the diameter of the cylindrical combined body of the protrusions 6 is about 125 μm, which is about 50 μm larger than the lower diameter 75 μm before bonding, considering the reliability and yield of bonding, the lower protrusions 6 and the solder bumps 5 The interval is preferably (30 + 50) μm = 80 μm or more.

  Since what kind of value the interval between the lower protrusion 6 and the solder bump 5 is designed depends on the lower diameter and height of the lower protrusion 6 and the solder bump 5, basically the first implementation It is preferable to design as described above.

Fourth Embodiment FIG. 9 illustrates a configuration example of an upper semiconductor chip 1 and a lower semiconductor chip 2 bonded by flip chip bonding in the fourth embodiment of the present invention (FIG. 9). 8 is a cross-sectional view.

  In the first to third embodiments, the solder bumps are formed on both the upper chip 1 and the lower chip 2, but in this embodiment, the solder bumps 4 are formed on the upper chip 1 and the lower chip 1 is formed. The chip 2 is configured not to form solder bumps. A pad electrode (not shown) is formed on the wiring conductor 3 of the lower chip 2 with a predetermined diameter and thickness. The upper protrusion 7 and the lower protrusion 6 are formed higher than the solder bump 4. The underfill material 8 is applied so as to be higher than the solder bumps 4 and not to exceed the height of the lower protrusions 6.

Fifth Embodiment FIG. 10 illustrates a configuration example of an upper semiconductor chip 1 and a lower semiconductor chip 2 bonded by flip chip bonding in a fifth embodiment of the present invention. 8 is a cross-sectional view.

  In the present embodiment, the solder bumps 5 are formed on the lower chip 2 and the solder bumps are not formed on the upper chip 1. A pad electrode (not shown) is formed on the wiring conductor 3 of the upper chip 1 with a predetermined diameter and thickness. The lower protrusion 6 is formed higher than the solder bump 5. The underfill material 8 is applied so as to be higher than the solder bump 5 and not to exceed the height of the lower protrusion 6. The upper protrusion 7 is formed to be higher than the thickness of the pad electrode (not shown).

  In the sixth to eighth embodiments described below, the upper protrusion formed with the same configuration as the solder bump 4 in the first to fifth embodiments described above. Except for the portion 7, the upper protrusion 7 may be read as the upper resin film 11, and the lower protrusion 6 may be read as the lower resin film 10. That is, the upper resin film 11 is used as the upper protrusion 7 and the lower resin film 10 is used as the lower protrusion 6.

  The resin films 11 and 10 are thermoplastic resins having a melting point of 180 ° C. or higher and a predetermined temperature range higher than the melting point of the solder bumps 4 and 5 (that is, a temperature range during bonding). A thermoplastic resin has flexibility when heated to its melting point or higher than its glass transition temperature, and its glass transition temperature is lower than its melting point. A thermoplastic resin having a melting point lower than that of the solder bumps 4 and 5 and higher than 180 ° C. is used as the resin films 11 and 10, and before the upper chip 1 and the lower chip 2 are brought close to each other, The upper chip 1 and the lower chip 2 are heated so that the temperature is below the melting point of the solder bumps 4 and 5 and above 180 ° C. As a result, when the upper chip 1 and the lower chip 2 are brought close to each other and the lower resin film 10 comes into contact with the upper resin film 11 or the upper chip 1, the resin film is in a softened state.

  In the sixth embodiment to the eighth embodiment described below, the upper and lower protrusions are formed of a film-like resin, and this film-like resin can be laminated with a tape-like resin, A liquid material can be applied and used.

  The volume before melting of the upper resin film 11 and the lower resin film 10 is calculated by the thickness and area of the film, respectively.

Sixth Embodiment FIG. 11 is a diagram for explaining a configuration example of an upper semiconductor chip 1 and a lower semiconductor chip 2 bonded by flip chip bonding and a bonding process in the sixth embodiment of the present invention. 11A is a plan view showing a state before joining, FIG. 11B is a cross-sectional view taken along the line ZZ showing the state before joining, and FIG. 11C is a Z- showing the state after joining. It is sectional drawing in a Z section.

  In the second embodiment, the lower protrusion 6 is replaced with the lower resin film 10 in the second embodiment. Due to the temperature rise at the time of joining, the upper protrusion 7 and the lower resin film 10 are each in a molten state to form a combined product, which is then solidified.

  When the gap (g) setting variation caused by the apparatus error of the flip chip bonding apparatus exemplified in the second embodiment can be ignored, the under bump metal having a diameter of 30 μm and a thickness of 5 μm not shown in FIGS. On the top, a lower resin film 10 having a thickness of 25 μm is provided in place of the spherical crown-shaped lower protrusion 6 formed to have a lower diameter of 30 μm and a height of 20 μm. Furthermore, in place of the lower resin film 10, the melting point is 180 ° C. or higher and the bonding temperature range (predetermined temperature range higher than or equal to the melting point of the solder bumps 4 and 5). A metal protrusion having a height of 25 μm may be provided.

Seventh Embodiment FIG. 12 is a diagram for explaining a configuration example of the upper semiconductor chip 1 and the lower semiconductor chip 2 bonded by flip chip bonding and the bonding process in the seventh embodiment of the present invention. 12A is a plan view showing a state before joining, FIG. 12B is a cross-sectional view of the ZZ portion showing the state before joining, and FIG. 12C is a Z- showing the state after joining. It is sectional drawing in a Z section.

  In the third embodiment, the lower protrusion 6 is replaced with the lower resin film 10 in the third embodiment. The upper chip 1 and the lower resin film 10 are respectively heated by the temperature rise at the time of bonding, and the lower resin film 10 is in a molten state and is heat-sealed to the surface of the upper chip 1 and then solidified.

  When the setting variation of the gap (g) caused by the apparatus error of the flip chip bonding apparatus exemplified in the third embodiment can be ignored, on the under bump metal having a diameter of 75 μm and a thickness of 5 μm not shown in FIG. A lower resin film 10 having a thickness of 40 μm is provided in place of the spherical crown-shaped lower protrusion 6 formed to have a lower diameter of 75 μm and a height of 35 μm. Further, in place of the lower resin film 10, a metal protrusion having a melting point of 180 ° C. or more and having a melting point below the bonding temperature range and formed of a metal other than solder and having a height of 40 μm may be provided. Good.

Eighth Embodiment FIG. 13 is a diagram for explaining a configuration example of the upper semiconductor chip 1 and the lower semiconductor chip 2 bonded by flip chip bonding and the bonding process in the eighth embodiment of the present invention. FIG. 13A is a plan view showing a state before joining, FIG. 13B is a cross-sectional view of a ZZ portion showing a state before joining, and FIG. 13C is a Z- showing a state after joining. It is sectional drawing in a Z section.

  In this embodiment, the upper protrusion 7 is replaced with the upper resin film 11 and the lower protrusion 6 is replaced with the lower resin film 10 in the first embodiment. An upper resin film 11 and a lower resin film 10 having the heights of the upper protrusion 7 and the lower protrusion 6 in the first embodiment are provided. The upper resin film 11 and the lower resin film 10 are each in a molten state due to the temperature rise at the time of joining, forming a combined product, and then solidified. In addition, instead of the upper resin film 11 and the lower resin film 10, a metal protrusion having a height of 40 μm formed of a metal other than solder having a melting point of 180 ° C. or higher and below the temperature range during bonding. A part may be provided.

  In the fourth and fifth embodiments, the upper resin film 11 can be used as the upper protrusion 7 and the lower resin film 10 can be used as the lower protrusion 6, and the upper resin film can be used. 11. Instead of the lower resin film 10, a metal protrusion having a melting point of 180 ° C. or higher and having a melting point below the bonding temperature range and formed of a metal other than solder and having a height of 40 μm may be provided.

  In each of the embodiments described above, Sn / Pb alloys (melting point: 180 ° C. to 200 ° C.) of various compositions are used as solder alloys constituting the solder bumps 4 and 5, and 89Sn / 8Zn / 3Bi (melting point) is used as a lead-free solder alloy. 187 ° C to 197 ° C), 91Sn / 9Zn (melting point: 199 ° C), 96.2Sn / 2.5Ag / 0.8Cu / 0.5Sb (melting point: 215 ° C to 217 ° C), 95.5Sn / 3.9Ag /0.6Cu (melting point: 217 ° C.) or the like can be used. In place of the solder bumps 4 and 5, metal bumps formed of Sn (melting point: 232 ° C.) or the like can also be used.

  Further, the upper protrusion 7 and the lower protrusion 6 may be made of the same material as the solder bump or metal bump, or may be made of different materials. For example, metal bumps formed of Sn can be used instead of solder bumps, and the protrusions formed of Sn can be used as the upper protrusions 7 and the lower protrusions 6. That is, the bonding bump for electrically connecting the upper chip and the lower chip, the upper protrusion 7 and the lower protrusion 6 can be formed of the same metal or alloy. The melting points of the upper protrusion 7 and the lower protrusion 6 are 180 ° C. or higher, and the upper and lower chips are bonded to bring the bonding bumps formed on the upper and / or lower chips into a molten state. It may be below the temperature set at the time of (bonding). The temperature set at the time of bonding may be any temperature that can hold the bonding bump in a stable molten state, and is set to a temperature that is about 20 ° C. to 30 ° C. higher than the melting point of the bonding bump, for example. The

  Moreover, although the example which each forms the solder bumps 4 and 5, the upper projection part 7, and the lower projection part 6 in the shape of a spherical crown was demonstrated, you may form these in a column shape and a polygonal column shape.

  Further, as a usable thermoplastic resin in place of the upper protrusion 7 and the lower protrusion 6, PC (polycarbonate) (glass transition temperature: 150 ° C., melting point: 220 ° C.), PBT (polybutylene terephthalate) (glass transition) There are various resins such as a temperature of 53 ° C. and a melting point of about 225 ° C. For example, instead of solder bumps, metal bumps formed of Sn (melting point: 232 ° C.) can be used, and PC and PBT can be used as the upper protrusions 7 and the lower protrusions 6. The melting point of the thermoplastic resin may be 180 ° C. or higher, and may be equal to or lower than the temperature set at the time of joining.

  In each of the embodiments described above, the lower chip can be replaced with a mounting substrate, and a highly reliable module can be manufactured.

  In the above description, the lower chip or the mounting substrate is fixed and the upper chip is lowered to replace the bonding device configured to join the lower chip or the mounting substrate and the upper chip. A bonding apparatus having a configuration in which the chip or the mounting substrate is raised and the lower chip or the mounting substrate and the upper chip are bonded to each other can be obtained.

  As described above, by applying an underfill material in advance, an electronic component such as a semiconductor chip or a mounting substrate suitable for highly reliable flip chip bonding can be realized, and the electronic component and the semiconductor chip are bonded to each other. Thus, a highly reliable semiconductor device can be realized.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to the above-mentioned embodiment, Various deformation | transformation based on the technical idea of this invention is possible.

  For example, the present invention can be applied to the NCP process described in Non-Patent Document 1, the pressure-contact flip chip mounting technology described in Non-Patent Document 2, and the ultrasonic flip chip mounting technology.

  As described above, the present invention can provide an electronic component suitable for flip-chip bonding with high reliability by applying an underfill material in advance, a semiconductor device using the electronic component, and a method for manufacturing the semiconductor device.

In the first embodiment of the present invention, (A) a plan view and (B) a cross-sectional view at a ZZ portion for explaining a configuration example of an upper semiconductor chip and a lower semiconductor chip to be joined. FIG. 4 is a cross-sectional view at each point of time, (A) before joining, (B) at the time of contact, and (C) after the joining, illustrating the process of joining the upper semiconductor chip and the lower semiconductor chip. FIG. 4A is a plan view illustrating a configuration example of a lower semiconductor chip, and FIG. 5B is a cross-sectional view taken along the line ZZ. It is a figure explaining the outline | summary of the structural example of a flip-chip bonding apparatus same as the above. It is a flowchart explaining the outline of the procedure of flip chip bonding same as the above. In the second embodiment of the present invention, (A) a plan view showing a configuration example of an upper semiconductor chip and a lower semiconductor chip to be joined and a joining process, illustrating a state before joining, and (B) ZZ. It is sectional drawing in a part, (C) It is sectional drawing in the ZZ part which shows the state after joining. It is a figure explaining the modification of FIG. 6 same as the above. In the third embodiment of the present invention, (A) a plan view and (B) ZZ showing a state before bonding, explaining a configuration example of an upper semiconductor chip and a lower semiconductor chip to be bonded and a process of bonding. It is sectional drawing in a part, (C) It is sectional drawing in the ZZ part which shows the state after joining. In the 4th Embodiment of this invention, it is the (A) top view and (B) sectional drawing in the ZZ part explaining the structural example of the upper semiconductor chip and lower semiconductor chip which are joined. In the 5th Embodiment of this invention, it is the (A) top view and (B) sectional drawing in the ZZ part explaining the structural example of the upper semiconductor chip and lower semiconductor chip which are joined. In the sixth embodiment of the present invention, (A) a plan view illustrating a configuration example of an upper semiconductor chip and a lower semiconductor chip to be bonded and a bonding process, illustrating a state before bonding, and (B) ZZ. It is sectional drawing in a part, (C) It is sectional drawing in the ZZ part which shows the state after joining. In the seventh embodiment of the present invention, (A) a plan view and (B) ZZ showing a state before bonding, explaining a configuration example of an upper semiconductor chip and a lower semiconductor chip to be bonded and a bonding process. It is sectional drawing in a part, (C) It is sectional drawing in the ZZ part which shows the state after joining. In the eighth embodiment of the present invention, (A) a plan view showing a configuration example of an upper semiconductor chip and a lower semiconductor chip to be bonded and a bonding process, illustrating a state before bonding, and (B) ZZ. It is sectional drawing in a part, (C) It is sectional drawing in the ZZ part which shows the state after joining. It is sectional drawing explaining joining of the upper and lower semiconductor chip in a prior art. It is sectional drawing explaining joining of the upper and lower semiconductor chip in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Upper chip, 2 ... Lower chip, 3 ... Wiring conductor, 4 ... Solder bump, 5 ... Solder bump,
6 ... Lower projection, 7 ... Upper projection, 8 ... Underfill material, 9 ... Joining region,
DESCRIPTION OF SYMBOLS 10 ... Lower resin film, 11 ... Upper resin film, 20 ... Base, 21 ... Lower holder,
22 ... Upper holder, 23 ... Bonding head, 24 ... Pressure detector,
25: Bonding head holding unit, 26 ... Bonding head driving unit,
27 ... Bonding head drive control unit, 30 ... Main control unit, 31 ... Monitor unit,
32 ... Temperature controller

Claims (7)

In the method for manufacturing a semiconductor device, a protruding electrode is formed on at least one surface of the first and second electronic components, and the first and second electronic components are electrically connected via the protruding electrode.
Forming a dummy protrusion having a height greater than that of the protrusion electrode on the surface of the first electronic component;
A second step of attaching an electrical insulating material higher than the protruding electrode and lower than the protruding portion to the surface of the first electronic component;
A third step of bringing the first electronic component and the second electronic component close to each other and detecting contact between the second electronic component and the protrusion;
After the contact is detected, the first electronic component and the second electronic component are further brought closer to each other until the distance between the first electronic component and the second electronic component reaches a predetermined value. 4. A method for manufacturing a semiconductor device, comprising the step of 4. 2. The contact according to claim 1 , wherein in the third step, contact between the protrusion formed on the first electronic component and a second protrusion formed on the second electronic component is detected. A method for manufacturing a semiconductor device. Prior to the third step, the step of heating the first and second electronic components such that the temperature of the protruding portion falls within a predetermined temperature range below the melting point of the protruding electrode, 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the temperature of the first and second electronic components is raised to the predetermined temperature range before the insulating material is completely cured. Prior to the fourth step, the step of heating the first and second electronic components such that the temperature of the protruding electrode is within a predetermined temperature range equal to or higher than its melting point, Before the complete curing, the first and second electronic components are heated to the predetermined temperature range, and after the fourth step, the electrical insulation having a thermosetting temperature lower than the melting point of the protrusion. 2. The semiconductor according to claim 1 , further comprising a step of holding the first and second electronic components at the predetermined temperature range or at a temperature lower than the predetermined temperature range for a predetermined time in order to cure the material. Device manufacturing method. The method for manufacturing a semiconductor device according to claim 1, wherein the protrusion is formed of a resin film. Higher than the protruding electrode formed on at least one surface of the first and second electronic components On the surface of the first electronic component on which a dummy protrusion having a thickness is formed, Attaching an electrical insulating material that is higher and lower than the protrusion; and
The first electronic component and the second electronic component are brought close to each other, and the first electronic component is inserted through the protrusion. Detecting a contact between one electronic component and the second electronic component;
After detecting the contact, a distance between the first electronic component and the second electronic component is predetermined. The first electronic component and the second electronic component are brought closer to each other until the value of Electrically connecting the first electronic component and the second electronic component via an electromotive electrode;
A method for manufacturing a semiconductor device, comprising: The first electronic component and the second electronic component through contact between the protrusion formed on the first electronic component and the second protrusion formed on the second electronic component The method for manufacturing a semiconductor device according to claim 6, wherein contact with the semiconductor device is detected.

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