JP4751380B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4751380B2 JP4751380B2 JP2007312544A JP2007312544A JP4751380B2 JP 4751380 B2 JP4751380 B2 JP 4751380B2 JP 2007312544 A JP2007312544 A JP 2007312544A JP 2007312544 A JP2007312544 A JP 2007312544A JP 4751380 B2 JP4751380 B2 JP 4751380B2
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- JP
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- Prior art keywords
- sic
- diode
- heat sink
- capacitor
- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
- Power Conversion In General (AREA)
Description
ヒートシンク上に設けられた、所定の面積を有する誘電体と、前記誘電体を挟んで対向する2つの導電体を有するコンデンサと、前記コンデンサの上に設けられ、前記コンデンサに直列に接続されたダイオード素子と、前記ダイオード素子に並列に接続された抵抗器とを有するスナバ回路と、
上記スナバ回路に並列に接続された半導体スイッチング素子と
を有することを特徴とする。
本発明の第1参考例の半導体装置である半導体パッケージ1を図1及び図2を参照して説明する。図1の(a)は第1参考例の半導体パッケージ1の断面図であり、同(b)は半導体パッケージ1内に収納されている複数の半導体素子を含む半導体モジュールの回路図である。図2の(a)及び(b)は、図1の(a)の半導体パッケージ1に含まれる半導体素子を構成する各半導体層を図の上下に拡大して示した断面図である。
本発明の第2参考例の半導体装置を図3の(a)及び(b)を参照して説明する。図3の(a)は本第2参考例の半導体装置の断面図であり、同(b)はその回路図である。
本発明の第3参考例の半導体装置を図4及び図5を参照して説明する。図4は本第3参考例の半導体装置の断面図である。本第3参考例の半導体装置においては、半導体スイッチング素子として絶縁ゲートバイポーラトランジスタ(以下、IGBTと略記する。)39を用い、フリーホイールダイオードとしてショットキーダイオード40を用いているが、半導体装置としての機能は前記第1及び第2参考例のものと実質的に変わりはない。
本発明の第1実施例の半導体装置を図6の(a)及び(b)を参照して説明する。本実施例の半導体装置はSiCダイオード10、コンデンサ15及び抵抗器52を組み合わせたスナバ回路50である。このスナバ回路50は他の半導体回路と組み合わせて使うものである。図6の(a)はスナバ回路50の断面図であり、同(b)はその回路図である。
本発明の第4参考例の半導体装置を図7及び図8を参照して説明する。図7は本第4参考例の半導体装置である半導体パッケージ60断面図であり、図8は半導体パッケージ60の回路図である。
3 金属板
4 絶縁板
5a、5b、5c 導電板
6 ゲート端子
7 カソード端子
8 アノード端子
9、69、79 SiC−GTO
10、70、80 SiCダイオード
11、12 金属板
13 誘電体板
15 コンデンサ
19 キャップ
38、48 熱膨張緩和板
39 IGBT
40 ショットキーダイオード
Claims (1)
- ヒートシンク上に設けられた、所定の面積を有する誘電体と、前記誘電体を挟んで対向する2つの導電体を有するコンデンサと、前記コンデンサの上に設けられ、前記コンデンサに直列に接続されたダイオード素子と、前記ダイオード素子に並列に接続された抵抗器とを有するスナバ回路と、
上記スナバ回路に並列に接続された半導体スイッチング素子と
を有することを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007312544A JP4751380B2 (ja) | 2007-12-03 | 2007-12-03 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007312544A JP4751380B2 (ja) | 2007-12-03 | 2007-12-03 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004021738A Division JP4195398B2 (ja) | 2004-01-29 | 2004-01-29 | 半導体装置及びそれを用いた電力装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008072149A JP2008072149A (ja) | 2008-03-27 |
JP4751380B2 true JP4751380B2 (ja) | 2011-08-17 |
Family
ID=39293403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007312544A Expired - Fee Related JP4751380B2 (ja) | 2007-12-03 | 2007-12-03 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4751380B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010206012A (ja) * | 2009-03-04 | 2010-09-16 | Nissan Motor Co Ltd | 半導体装置 |
JP5577607B2 (ja) * | 2009-03-05 | 2014-08-27 | 日産自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2023188000A1 (ja) * | 2022-03-29 | 2023-10-05 | 三菱電機株式会社 | 半導体装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273276A (ja) * | 1994-03-28 | 1995-10-20 | Nissan Motor Co Ltd | パワー素子とスナバ素子の接続構造及びその実装構造 |
JPH1079471A (ja) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | 半導体装置、その製造方法及びフレキシブルカード |
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2007
- 2007-12-03 JP JP2007312544A patent/JP4751380B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2008072149A (ja) | 2008-03-27 |
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