JP4740559B2 - Pulse power supply - Google Patents

Description

  The present invention relates to a pulse power source that continuously outputs a positive pulse and a negative pulse.

  Recently, techniques for performing deodorization, sterilization, film formation, decomposition of harmful gases, and the like have been applied by plasma generated by discharge of a high-voltage pulse (see, for example, Patent Document 1 and Non-Patent Document 1). It has been found that it is necessary to supply a high voltage and a very narrow pulse in order to efficiently perform plasma processing (see, for example, Non-Patent Document 2).

  For example, a pulse power supply as shown in Patent Document 2 has been proposed. As shown in FIG. 5, the pulse power supply 100 includes an inductor 104, a first semiconductor switch 106, and a second semiconductor switch 108 connected in series to both ends of a DC power supply unit 102, and an anode of the first semiconductor switch 106. This is a very simple circuit in which a diode 110 is connected so that a cathode is connected to the other end of the inductor 104 whose one end is connected to a terminal and an anode is connected to a gate terminal of the first semiconductor switch 106.

  When the second semiconductor switch 108 is turned on, the first semiconductor switch 106 is also turned on, the voltage of the DC power supply unit 102 is applied to the inductor 104, and inductive energy is accumulated in the inductor 104. After that, when the second semiconductor switch 108 is turned off, the first semiconductor switch 106 is also turned off rapidly, so that a very narrow high voltage pulse Po that rises very steeply is generated in the inductor 104, and the output terminal 112 and The high voltage pulse Po can be extracted from 114.

  According to this pulse power supply 100, a high voltage pulse Po having a steep rise time and an extremely narrow pulse width can be supplied with a simple circuit configuration without using a plurality of semiconductor switches to which a high voltage is applied. it can.

Japanese Patent No. 2649340 (column 8, line 3 to line 41) Japanese Patent Laid-Open No. 2002-359979 Applied Physics, Vol. 61, No. 10, 1992, p. 1039-1043, "Preparation of amorphous silicon thin film by high voltage pulsed discharge chemical vapor deposition" IEEE TRANSACTION ON PLASMIC SCIENCE, VOL.28, NO.2, APRIL 2000, p.434-442, “Improvement of NOx Removal Efficiency Using Short-Width Pulsed Power”

  By the way, in the pulse power supply used to generate plasma by changing the electric field and accelerating the electrons, in order to generate a high potential difference by a low voltage, a pulse with a reverse polarity, that is, a positive pulse A system in which negative pulses are continuously output is employed.

  For example, as shown in FIG. 6, a conventional pulse power supply 200 according to this method includes a DC power supply 202, a first switch 204 and a second switch 206 connected in series to both ends of the DC power supply 202, and the DC power supply. 202, the third switch 208 and the fourth switch 210 connected in series to both ends of the 202, the contact a1 between the first switch 204 and the second switch 206, and the third switch 208 and the fourth switch 210. A transformer 214 is connected to the primary winding 212 between the contact a2. That is, it has a bridge configuration. The output voltage Vout is taken out from both ends of the secondary winding 216 of the transformer 214.

  Then, for example, when the second switch 206 and the third switch 208 are turned on, a negative voltage is output from both ends of the secondary winding 216 as shown in FIG. When the switch 206 and the third switch 208 are turned off, the negative pulse 218 is generated. Further, by turning on the first switch 204 and the fourth switch 210, a positive voltage is output from both ends of the secondary winding 216. After a predetermined time, the first switch 204 and the fourth switch By turning off 210, a negative polarity pulse 220 is output.

  However, since the pulse power supply 200 according to this conventional example forms a bridge, it is necessary to use four switches 204, 206, 208, and 210, which disadvantageously increases the number of parts. This leads to an increase in size and cost.

  As a small and inexpensive pulse power source, there is a pulse power source 100 (see FIG. 5) described in Patent Document 2 described above, but there is a problem that only a unipolar pulse can be generated.

  The present invention has been made in view of such problems, and can be reduced in size and cost, and can continuously generate a positive pulse and a negative pulse. An object is to provide a pulsed power supply.

The pulse power supply according to the present invention includes accumulation of first inductive energy for a transformer, generation of a first pulse accompanying release of the first inductive energy from the transformer, and the first inductive energy for the transformer. In a pulse power source for storing second induced energy having a polarity opposite to that of the first pulse and generating a second pulse having a polarity opposite to that of the first pulse accompanying the release of the second induced energy from the transformer A direct current power source, a tap connection point provided in the primary winding of the transformer, and a negative terminal of the direct current power source and the tap connection point. A first switching element drawn into the first power source, a first diode connected in a forward direction between a positive terminal of the DC power source and one terminal of the primary winding, and a positive end of the DC power source And a second diode connected in the forward direction between the first terminal and the other terminal of the primary winding, and a positive diode connected to the positive terminal of the DC power source and the first diode. A current is passed from the DC power source to the tap connection point via the first diode and the one terminal of the primary winding, and the voltage between the tap connection point and the one terminal is negative. A second switching element that sets the voltage of the secondary winding of the transformer to a negative polarity voltage and turns off the voltage of the secondary winding of the transformer to a positive polarity voltage, and the direct current The tap connection point is connected between the positive terminal of the power source and the second diode, and is turned on so that the direct current power source passes through the second diode and the other terminal of the primary winding. Current flows toward the front The voltage between the tap connection point and the other terminal is set to a positive voltage, the voltage of the secondary winding of the transformer is set to a positive voltage, and the voltage of the secondary winding of the transformer is set to a negative polarity by performing an off operation. have a third switching element to sexual voltage, the first switching element is constituted by a bipolar transistor, its between the anode terminal of the gate terminal and the first diode, said from the gate terminal A first parallel circuit of a third diode and a first resistor whose forward direction is the direction of the anode terminal of the first diode is connected, and between the gate terminal and the anode terminal of the second diode the fourth diode and wherein Rukoto second parallel circuit of the second resistor is connected to the direction of the anode terminal of the second diode from the gate terminal and the forward And

The pulse power source according to the present invention can reduce the size and cost of a pulse power source that continuously outputs a positive pulse and a negative pulse.

  As described above, according to the pulse power supply of the present invention, it is possible to reduce the size and the cost, and it is possible to continuously generate a positive pulse and a negative pulse.

  Embodiments of a pulse power source according to the present invention will be described below with reference to FIGS.

  First, as shown in FIG. 1, the pulse power supply 10A according to the first embodiment includes a DC power supply 12 (power supply voltage = E) and a transformer 14, and both ends of the secondary winding 16 of the transformer 14. The output is taken out from. The primary winding 18 of the transformer 14 has a tap connection point 20, and a load 22 is connected to both ends of the secondary winding 16. As the load 22, for example, a resistance load or a capacitive load (discharge gap or the like) is used.

  The pulse power supply 10A according to the first embodiment includes a first diode D1 connected in the forward direction between the positive terminal of the DC power supply 12 and the tap connection point 20 of the primary winding 18, and 1 A first semiconductor switch that is connected between one terminal 26 of the next winding 18 and the negative terminal of the DC power supply 12 and that allows a current from the DC power supply 12 to flow from the tap connection point 20 toward the one terminal 26. S1 is connected between the second semiconductor switch S2 for controlling on / off of the first semiconductor switch S1, the other terminal 28 of the primary winding 18 and the negative terminal of the DC power source 12, and A third semiconductor switch S3 for passing a current from the DC power supply 12 from the tap connection point 20 toward the other terminal 28, and a fourth semiconductor switch S4 for controlling on / off of the third semiconductor switch S3; Have

  The first semiconductor switch S1 and the third semiconductor switch S3 can use self-extinguishing type or commutation-extinguishing type devices, respectively. In the first embodiment, an example using a bipolar transistor is shown. Of course, GTO, SI thyristor, or the like may be used.

  In the first semiconductor switch S1, a second diode D2 is connected between the collector terminal and the emitter terminal, and a third diode D3 is connected between the base terminal and the anode terminal of the first diode D1. And a parallel circuit 30 of the first resistor R1 are connected. The cathode terminal of the second diode D2 is connected to the collector terminal of the first semiconductor switch S1, and the anode terminal is connected to the emitter terminal of the first semiconductor switch S1. The third diode D3 has an anode terminal connected to the base terminal of the first semiconductor switch S1, and a cathode terminal connected to the anode terminal of the first diode D1.

  Similarly, in the third semiconductor switch S3, the fourth diode D4 is connected between the collector terminal and the emitter terminal, and the fifth diode D4 is connected between the base terminal and the anode terminal of the first diode D1. A parallel circuit 32 of the diode D5 and the second resistor R2 is connected. The cathode terminal of the fourth diode D4 is connected to the collector terminal of the third semiconductor switch S3, and the anode terminal is connected to the emitter terminal of the third semiconductor switch S3. The fifth diode D5 has an anode terminal connected to the base terminal of the fifth semiconductor switch S5 and a cathode terminal connected to the anode terminal of the first diode D1.

  As the second semiconductor switch S2 and the fourth semiconductor switch S4, self-extinguishing type or commutation-extinguishing type devices can be used, respectively. In the first embodiment, for example, an n-channel power metal oxide semiconductor field effect transistor in which an avalanche diode is built in antiparallel is used.

  The second semiconductor switch S2 has a source terminal connected to the negative terminal of the DC power supply 12, and a drain terminal connected to the emitter terminal of the first semiconductor switch S1. The fourth semiconductor switch S4 has a source terminal connected to the negative terminal of the DC power supply 12, and a drain terminal connected to the emitter terminal of the third semiconductor switch S3.

  The gate terminal of the second semiconductor switch S2 is connected to a first gate drive circuit 34 for controlling on / off of the second semiconductor switch S2 via a resistor R3. Similarly, the gate terminal of the fourth semiconductor switch S4 is connected to the second gate drive circuit 36 for controlling on / off of the fourth semiconductor switch S4 via the resistor R4. As the first and second gate drive circuits 34 and 36, various amplifiers and inverters for amplifying an input signal can be used.

  Here, the circuit operation of the pulse power supply 10A according to the first embodiment, in particular, the circuit operation when the discharge gap is used as the load 22 connected to both ends of the secondary winding 16, is a circuit diagram of FIG. 2A to 2H and the waveform diagrams.

  Note that the voltage of the DC power source 12 is E (V), the number of turns from the tap connection point 20 of the primary winding 18 in the transformer 14 to one terminal 26 is n1, and the number of turns from the tap connection point 20 to the other terminal 28. n2, the number of turns of the secondary winding 16 is n3. Of the primary inductance of the transformer 14, the primary inductance from the tap connection point 20 to one terminal 26 is Lex1, and the primary inductance from the tap connection point 20 to the other terminal 28 is Lex2.

  First, at a time point t0, for example, a high-level switching control signal Sc1 (see FIG. 2G) is supplied from the first gate drive circuit 34 between the gate and the source of the second semiconductor switch S2, and the second semiconductor switch S2 is turned on. From off to on.

  When the second semiconductor switch S2 is turned on at time t0, V1 = −E (V) is applied between the tap connection point 20 of the primary winding 18 and one terminal 26 in the transformer 14 (see FIG. 2A). V2 = − (n2 / n1) E (V) is induced between the tap connection point 20 and the other terminal 28 (see FIG. 2C), and the current I1 flowing between the tap connection point 20 and one terminal 26 is The gradient (E / Lex1) increases in a straight line in the positive direction with time (see FIG. 2B).

  In the period tw1 during which the second semiconductor switch S2 is on, a constant negative voltage (negative pulse P3a) is output to both ends of the secondary winding 16. The level of the output voltage V3 appearing at both ends of the secondary winding 16 is-(n3 / n1) E (V) (see FIG. 2E). Since the discharge gap is used as the load 22, the current I3 hardly flows through the secondary winding 16 during the period tw1, and 0 (A) is maintained (see FIG. 2F).

Current I1 flowing between one terminal 26 and the tap connection point 20 of the primary winding 18, at time t1 Ip1 (= E · tw1 / Lex1) , and the desired electromagnetic energy ^{(= Lex1 · Ip1 2/2} ) is When obtained, a low-level switching control signal Sc1 (see FIG. 2G) is supplied through the first gate drive circuit 34, whereby the second semiconductor switch S2 is turned off.

  At time t1, when the second semiconductor switch S2 is turned off, the first semiconductor switch S1 is opened, so that the current I1 flowing in the primary winding 18 of the transformer 14 is cut off and generated in the transformer 14. The output voltage V3 sharply rises due to the induced electromotive force, and a pulse P3b having a narrow pulse width having a positive voltage value (V3p1) as a peak is output (see FIG. 2E).

  That is, the output voltage V3 sharply increases due to the induced electromotive force generated in the transformer 14, and a positive voltage (positive pulse P3b) having a positive voltage value (V3p1) as a peak is output. Ideally, the output voltage V3 becomes a peak value (V3p1) when the second semiconductor switch S2 is turned off. However, the rise of the current I3 flowing through the secondary winding 16 is caused by the leakage inductance of the transformer 14. Accordingly, the peak value (V3p1) of the output voltage V3 also occurs at a time point t2 slightly later than the off time point t1 of the second semiconductor switch S2. However, during a short period Tm from the time t1 when the second semiconductor switch S2 is turned off to the time t2 when the output voltage V3 reaches the peak value (V3p1), the output voltage V3 has a negative voltage value (− ( n3 / n1) Since the voltage rises sharply from E) toward the positive voltage value (V3p1), the above-described time lag (period Tm) is almost negligible.

  Note that the voltage V2 = (n2 / n3) V3 (V) (see FIG. 2C) induced between the tap connection point 20 of the primary winding 18 and the other terminal 28 in the transformer 14 in the period from the time point t1 to the time point t2. When the voltage is higher than the voltage (E) of the DC power supply 12, the difference voltage (V2-E) is applied to the first diode D1 in the reverse direction. As a result, current inflow to the DC power supply 12 is blocked, and all the energy stored in the transformer 14 is consumed by the load 22 without being regenerated to the DC power supply 12.

  The peak value of the output voltage V3, that is, the peak value (V3p1) of the positive pulse P3b is a value determined by the discharge start voltage of the load 22. It should be noted that the output voltage V3 is gradually attenuated after the peak time point t2, and gradually attenuates, so that the reference at the time point t3 of the period td during which the second semiconductor switch S2 is off. It becomes level (0V). Further, the current I3 flowing through the secondary winding 16 also becomes the reference level (0 A) at time t3. At this time, the output voltage V3 is attenuated so that the integral value of the negative pulse P3a and the integral value of the positive pulse P3b are substantially the same.

  When the voltage E of the DC power supply 12 is 100 V, the excitation inductances Lex1 and Lex2 are both 10 (μH), and the transformer winding ratio n1: n2: n3 is 1: 1: 5-10, the primary winding 18 The peak value Ip1 of the current I1 flowing between the tap connection point 20 and one terminal 26 is approximately 100 (A), the peak value (V3p1) of the output voltage V3 is several to 30 (kV), and flows through the secondary winding 16. The peak value (I3p1) of the current I3 is several to several tens (A). Further, the time during which the second semiconductor switch S2 is on (the time from the time point t0 to the time point t1) is about 10 μsec.

  Thereafter, at time t4, for example, a high-level switching control signal Sc2 (see FIG. 2H) is supplied from the second gate drive circuit 36 to the gate-source of the fourth semiconductor switch S4, and the fourth semiconductor switch S4 is turned on. From off to on.

  When the fourth semiconductor switch S4 is turned on at time t4, V2 = E (V) is applied between the tap connection point 20 of the primary winding 18 and the other terminal 28 in the transformer 14 (see FIG. 2C). V1 = (n1 / n2) E (V) is induced between the tap connection point 20 and one terminal 26 (see FIG. 2A), and the current I2 flowing between the tap connection point 20 and the other terminal 28 has a gradient. -(E / Lex2) linearly increases in the negative direction over time (see FIG. 2D).

  In the period tw2 during which the fourth semiconductor switch S4 is on, a constant positive voltage (positive pulse P3c) is output to both ends of the secondary winding 16. The level of the output voltage V3 appearing at both ends of the secondary winding 16 is (n3 / n2) E (V) (see FIG. 2E). In this period tw2, the current I3 hardly flows through the secondary winding 16, and 0 (A) is maintained (see FIG. 2F).

Current I2 flowing between the tap connection point 20 and the other terminal 28 of the primary winding 18, at time t5 Ip2 (= E · tw2 / Lex2) , and the desired electromagnetic energy ^{(= Lex2 · Ip2 2/2} ) is When obtained, a low-level switching control signal Sc2 (see FIG. 2H) is supplied through the second gate drive circuit 36, whereby the fourth semiconductor switch S4 is turned off.

  At time t5, when the fourth semiconductor switch S4 is turned off, the third semiconductor switch S3 is opened, so that the current I2 flowing in the primary winding 18 of the transformer 14 is cut off and generated in the transformer 14. The output voltage V3 sharply drops due to the induced electromotive force, and a pulse P3d having a narrow pulse width having a negative voltage value (V3p2) as a peak is output (see FIG. 2E).

  That is, the output voltage V3 sharply drops due to the induced electromotive force generated in the transformer 14, and a negative voltage (negative pulse P3d) having a negative voltage value (V3p2) as a peak is output. Also in this case, the trailing edge of the current I3 flowing through the secondary winding 16 is slightly loosened due to the leakage inductance of the transformer 14, and accordingly, the peak value (V3p2) of the output voltage V3 is also the fourth semiconductor switch. Occurs at a time point t6 slightly later than the off time point t5. However, during a short period Tn from the time t5 when the fourth semiconductor switch is turned off to the time t6 when the output voltage V3 reaches the peak value (V3p2), the output voltage V3 has a positive voltage value (− (n3 / N2) Since the voltage falls sharply from E) toward the negative voltage value (V3p2), the above-described time lag (period Tn) is almost negligible.

  It should be noted that the voltage V1 = − (n1 / n3) V3 (V) induced between the tap connection point 20 of the primary winding 18 and the one terminal 26 in the transformer 14 in the period from time t5 to t6 (see FIG. 2A). Becomes smaller than the voltage (−E) of the DC power supply 12, the difference voltage (V 1 −E) is applied to the first diode D 1 in the reverse direction. As a result, current inflow to the DC power supply 12 is blocked, and all the energy stored in the transformer 14 is consumed by the load 22 without being regenerated to the DC power supply 12.

  The peak value of the output voltage V3, that is, the peak value (V3p2) of the negative polarity pulse P3d is a value determined by the discharge start voltage of the load 22.

  It should be noted that the output voltage V3 is gradually attenuated after the peak time point t6 and is gradually attenuated, and the reference voltage is obtained at the time point t7 of the period tf in which the fourth semiconductor switch S4 is off. It becomes level (0V). Further, the current I3 flowing through the secondary winding 16 also becomes the reference level (0 A) at time t7. At this time, the output voltage V3 is attenuated so that the integral value of the positive pulse P3c and the integral value of the negative pulse P3d are substantially the same.

  As a specific value, the peak value Ip2 of the current I2 flowing between the tap connection point 20 of the primary winding 18 and the other terminal 28 is approximately −100 (A) under the same conditions as described above, and the output The peak value (V3p2) of the voltage V3 is −number to −30 (kV), and the peak value (I3p2) of the current I3 flowing through the secondary winding 16 is −number to −several 10 (A).

  The fourth semiconductor switch S4 is preferably turned on after the discharge at the load 22 is completely stopped, so that the fourth semiconductor switch S4 is turned on from the time t1 when the second semiconductor switch S2 is turned off. The period td until the turn-on time t4 was several to several hundred μsec. Further, the period tw2 (the period from the time point t4 to the time point t5) during which the fourth semiconductor switch S4 is on was set to about 10 μsec.

  Thus, in the pulse power supply 10A according to the first embodiment, while following the advantages of the pulse power supply disclosed in Japanese Patent Laid-Open No. 2002-359979 (Patent Document 2), the positive pulse P3b and The pulse power supply 10A that continuously outputs the negative pulse P3d can be reduced in size and cost.

  Next, a pulse power supply 10B according to a second embodiment will be described with reference to FIGS. 3 and 4A to 4H. In addition, about the thing corresponding to 1st Embodiment, the same code | symbol is attached | subjected and the duplication description is abbreviate | omitted.

  The pulse power supply 10B according to the second embodiment has substantially the same configuration as the pulse power supply 10A according to the first embodiment described above, but differs in the following points.

  That is, the fifth semiconductor switch S5 connected between the negative terminal of the DC power supply 12 and the tap connection point 20 of the transformer 14 and drawing the current flowing through the primary winding 18 of the transformer 14 to the DC power supply 12 side. The sixth diode D6 forward-connected between one terminal 26 of the primary winding 18 and the second semiconductor switch S2, the other terminal 28 of the primary winding 18, and the fourth semiconductor switch And a seventh diode D7 forward-connected to S4.

  For the fifth semiconductor switch S5, a self-extinguishing type or commutation-extinguishing type device can be used. In the second embodiment, an example using a bipolar transistor is shown. Of course, GTO, SI thyristor, or the like may be used.

  The fifth semiconductor switch S5 has an eighth diode D8 connected between its collector terminal and emitter terminal, and a parallel circuit 30 (between the base terminal and the anode terminal of the sixth diode D6). The third diode D3 and the first resistor R1) are connected, and a parallel circuit (the fifth diode D5 and the second resistor R2) is connected between the base terminal and the anode terminal of the seventh diode D7. ing. The third diode D3 of the parallel circuit 30 has an anode terminal connected to the base terminal of the fifth semiconductor switch S5 and a cathode terminal connected to the anode terminal of the sixth diode D6. Similarly, the fifth diode D5 of the parallel circuit 32 has an anode terminal connected to the base terminal of the fifth semiconductor switch S5 and a cathode terminal connected to the anode terminal of the seventh diode D7.

  The second semiconductor switch S2 has a source terminal connected to the anode terminal of the sixth diode D6 and a drain terminal connected to the + terminal of the DC power supply 12. The fourth semiconductor switch S4 has a source terminal connected to the anode terminal of the seventh diode D7 and a drain terminal connected to the + terminal of the DC power supply 12.

  Here, the circuit operation of the pulse power supply 10B according to the second embodiment will be described with reference to the circuit diagram of FIG. 3 and the waveform diagrams of FIGS. 4A to 4H.

  First, at time t10, for example, a high-level switching control signal Sc1 (see FIG. 4G) is supplied from the first gate drive circuit 34 between the gate and the source of the second semiconductor switch S2, and the second semiconductor switch S2 is turned on. From off to on.

  When the second semiconductor switch S2 is turned on at time t10, V1 = −E (V) is applied between the tap connection point 20 of the primary winding 18 and one terminal 26 in the transformer 14 (see FIG. 4A). V2 = − (n2 / n1) E (V) is induced between the tap connection point 20 and the other terminal 28 (see FIG. 4C), and the current I1 flowing between the tap connection point 20 and one terminal 26 is In the gradient (E / Lex1), the voltage increases linearly in the positive direction with time (see FIG. 4B).

  In the period tw1 during which the second semiconductor switch S2 is on, a constant negative voltage (negative pulse P3a) is output to both ends of the secondary winding 16. The level of the output voltage V3 appearing at both ends of the secondary winding 16 is-(n3 / n1) E (V) (see FIG. 4E). In this period tw1, the current I3 hardly flows through the secondary winding 16, and 0 (A) is maintained (see FIG. 4F).

Current I1 flowing between one terminal 26 and the tap connection point 20 of the primary winding 18, at the time t11 Ip1 (= E · tw1 / Lex1) , and the desired electromagnetic energy ^{(= Lex1 · Ip1 2/2} ) is When obtained, a low-level switching control signal Sc1 (see FIG. 4G) is supplied through the first gate drive circuit 34, thereby turning off the second semiconductor switch S2.

  When the second semiconductor switch S2 is turned off at the time t11, the fifth semiconductor switch S5 is opened, so that the current I1 flowing in the primary winding 18 of the transformer 14 is cut off and generated in the transformer 14. The output voltage V3 rises sharply by the induced electromotive force, and a pulse P3b having a narrow pulse width with a positive voltage value (V3p1) as a peak is output. Also in this case, the trailing edge of the current I3 flowing through the secondary winding 16 is slightly loosened due to the leakage inductance of the transformer 14, and accordingly, the peak value (V3p1) of the output voltage V3 is also corresponding to the second semiconductor switch. This occurs at a time t12 slightly later than the off time t11 of S2.

  Note that the voltage V2 = (n2 / n3) V3 (V) (see FIG. 4C) induced between the tap connection point 20 of the primary winding 18 and the other terminal 28 in the transformer 14 in the period from time t11 to t12. When the voltage is higher than the voltage (E) of the DC power supply 12, the difference voltage (V2-E) is applied to the seventh diode D7 in the reverse direction. As a result, current inflow to the DC power supply 12 is blocked, and all the energy stored in the transformer 14 is consumed by the load 22 without being regenerated to the DC power supply 12.

  The peak value (V3p1) of the output voltage V3 is a value determined by the discharge start voltage of the load 22. The output voltage V3 is gradually attenuated after the peak time t12, and gradually attenuates, so that the reference voltage is obtained at the time td of the period td during which the second semiconductor switch S2 is off. It becomes level (0V).

  Thereafter, at time t14, for example, a high-level switching control signal Sc2 (see FIG. 4H) is supplied from the second gate drive circuit 36 to the gate-source of the fourth semiconductor switch S4, and the fourth semiconductor switch S4 is turned on. From off to on.

  When the fourth semiconductor switch S4 is turned on at time t14, V2 = E (V) is applied between the tap connection point 20 of the primary winding 18 and the other terminal 28 in the transformer 14 (see FIG. 4C). V1 = (n1 / n2) E (V) is induced between the tap connection point 20 and one terminal 26 (see FIG. 4A), and the current I2 flowing between the tap connection point 20 and the other terminal 28 has a gradient. -(E / Lex2) linearly increases in the negative direction over time.

  In the period tw2 during which the fourth semiconductor switch S4 is on, a constant positive voltage (positive pulse P3c) is output to both ends of the secondary winding 16. The level of the output voltage V3 appearing at both ends of the secondary winding 16 is (n3 / n2) E (V) (see FIG. 4E). In this period tw2, the current I3 hardly flows through the secondary winding 16, and 0 (A) is maintained (see FIG. 4F).

Current I2 flowing between the tap connection point 20 and the other terminal 28 of the primary winding 18, at the time t15 Ip2 (= E · tw2 / Lex2) , and the desired electromagnetic energy ^{(= Lex2 · Ip2 2/2} ) is When obtained, a low-level switching control signal Sc2 (see FIG. 4H) is supplied through the second gate drive circuit 36, whereby the fourth semiconductor switch S4 is turned off.

  When the fourth semiconductor switch S4 is turned off at the time t15, the fifth semiconductor switch S5 is opened, so that the current I2 flowing in the primary winding 18 of the transformer 14 is cut off and generated in the transformer 14. The output voltage V3 drops sharply by the induced electromotive force, and a pulse P3d having a narrow pulse width with a negative voltage value (V3p2) as a peak is output. Also in this case, the trailing edge of the current I3 flowing through the secondary winding 16 is slightly loosened due to the leakage inductance of the transformer 14, and accordingly, the peak value (V3p2) of the output voltage V3 is also the fourth semiconductor switch. This occurs at a time point t16 slightly later than the off time point t15 of S4.

  It should be noted that voltage V1 = − (n1 / n3) V3 (V) induced between the tap connection point 20 of the primary winding 18 and one terminal 26 in the transformer 14 in the period from time t15 to time t16 (see FIG. 4A). Becomes smaller than the voltage (−E) of the DC power supply 12, the difference voltage (V 1 −E) is applied to the sixth diode D 6 in the reverse direction. As a result, current inflow to the DC power supply 12 is blocked, and all the energy stored in the transformer 14 is consumed by the load 22 without being regenerated to the DC power supply 12.

  The peak value (V3p2) of the output voltage V3 is a value determined by the discharge start voltage of the load 22. Note that, after the peak time t16, the output voltage V3 is gradually attenuated because energy is consumed in the load 22, and the output voltage V3 becomes the reference at the time t17 of the period tf in which the fourth semiconductor switch S4 is off. It becomes level (0V).

  As described above, in the pulse power supply 10B according to the second embodiment, the positive pulse P3b and the pulse power supply 10B according to Japanese Patent Application Laid-Open No. 2002-359979 (patent document 2) are also used. The pulse power supply 10B that continuously outputs the negative pulse P3d can be reduced in size and cost. In particular, in the second embodiment, since only one semiconductor switch for interrupting the current flowing through the primary winding 18 is required, control is facilitated and it is advantageous for downsizing.

  The pulse power supply according to the present invention is not limited to the above-described embodiment, and various configurations can be adopted without departing from the gist of the present invention.

It is a circuit diagram which shows the structure of the pulse power supply which concerns on 1st Embodiment. 2A to 2H are waveform diagrams showing the operation of the pulse power supply according to the first embodiment. It is a circuit diagram which shows the structure of the pulse power supply which concerns on 2nd Embodiment. 4A to 4H are waveform diagrams showing the operation of the pulse power supply according to the first embodiment. It is a circuit diagram which shows the pulse power supply which concerns on a prior art example. It is a circuit diagram which shows the pulse power supply which concerns on another prior art example. It is a figure which shows the pulse waveform output from the pulse power supply which concerns on another prior art example.

Explanation of symbols

10A, 10B ... Pulse power supply 12 ... DC power supply 14 ... Transformer 16 ... Secondary winding 18 ... Primary winding D1-D8 ... Diodes S1-S5 ... Semiconductor switch

Claims (1)

Accumulation of first induced energy in the transformer, generation of a first pulse associated with the release of the first induced energy from the transformer, and a second polarity opposite to the first induced energy in the transformer In a pulse power source that performs accumulation of inductive energy and generation of a second pulse having a polarity opposite to that of the first pulse accompanying release of the second inductive energy from the transformer,
DC power supply,
A tap connection point provided in the primary winding of the transformer;
A first switching element connected between the negative terminal of the DC power supply and the tap connection point, and drawing current flowing through the primary winding to the DC power supply side;
A first diode connected in a forward direction between a positive terminal of the DC power source and one terminal of the primary winding;
A second diode connected in a forward direction between the positive terminal of the DC power source and the other terminal of the primary winding;
The tap is connected between the positive terminal of the DC power source and the first diode, and is turned on so that the tap from the DC power source passes through the first diode and the one terminal of the primary winding. By flowing a current toward the connection point, the voltage between the tap connection point and the one terminal is a negative voltage, the voltage of the secondary winding of the transformer is a negative voltage, A second switching element in which the voltage of the secondary winding of the transformer is a positive voltage;
The tap is connected between the + terminal of the DC power supply and the second diode, and is turned on, so that the tap from the DC power supply passes through the second diode and the other terminal of the primary winding. By flowing current toward the connection point, the voltage between the tap connection point and the other terminal is a positive voltage, the voltage of the secondary winding of the transformer is a positive voltage, have a third switching element for the voltage of the transformer secondary winding and a negative polarity voltage,
The first switching element is composed of a bipolar transistor, and a forward direction is defined between the gate terminal and the anode terminal of the first diode between the gate terminal and the anode terminal of the first diode. A first parallel circuit of a third diode and a first resistor is connected, and between the gate terminal and the anode terminal of the second diode, the gate terminal to the anode terminal of the second diode fourth diode and pulse power source second parallel circuit of a second resistor is characterized that it is connected to the direction forward.

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